KR102586974B1 - Display device - Google Patents

Abstract

The present invention relates to a display device. A display device according to an embodiment of the present invention includes a pixel unit disposed in an active area where an image is displayed, a detection unit that detects whether the threshold voltage of the pixel unit changes, and an output value detected from the detection unit. It includes a compensation unit that receives input and compares the output value with a preset reference value to generate and output a compensation voltage that compensates for the threshold voltage change, and the detection unit may be configured as an inverter. Accordingly, the display device according to an embodiment of the present invention can easily detect a change in the threshold voltage of the active area with a simple circuit configuration.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more specifically, to a display device for improving problems caused by changes in threshold voltage characteristics of a thin film transistor made of an oxide semiconductor material.

Recently, as we have entered the information age, the field of displays that visually express electrical information signals has developed rapidly, and in response to this, various display devices with excellent performance such as thinner, lighter, and lower power consumption have been developed. is being developed.

Specific examples of such display devices include a Liquid Crystal Display device (LCD), a Plasma Display Panel device (PDP), a Field Emission Display device (FED), and an organic light emitting display device ( Organic Light Emitting Display device (OLED), etc. may be mentioned.

Such a display device consists of a display panel in which a plurality of pixels are arranged and a driver that drives the display panel, and a light emitting element, a switching thin film transistor, and a driving thin film transistor are formed in each of the plurality of pixels.

Recently, as display devices have been implemented with large areas and high resolution, thin film transistors with faster signal processing speeds, stable operation, and durability are required.

Accordingly, in order to improve the mobility of thin film transistors constituting each of a plurality of pixels, research is being actively conducted to form the active layer of the thin film transistor using an oxide semiconductor material with excellent mobility characteristics.

However, while thin film transistors made of oxide semiconductor materials have excellent mobility characteristics, there is a problem in that the reliability is reduced due to severe changes in threshold voltage (Vth) and transfer characteristics due to severe changes in bias stress. .

Accordingly, the inventors of the present invention proposed a method of detecting whether the threshold voltage of a thin film transistor made of an oxide semiconductor material shifts and applying a compensation voltage to compensate for the change in the threshold voltage.

The problem to be solved by the present invention is to provide a display device that can minimize degradation of image quality of the display device due to changes in the threshold voltage of a thin film transistor made of an oxide semiconductor material.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment of the present invention includes a pixel unit disposed in an active area where an image is displayed, a detection unit that detects whether the threshold voltage of the pixel unit changes, and an output detected from the detection unit. It includes a compensation unit that receives an input value and compares the output value with a preset reference value to generate and output a compensation voltage that compensates for the change in threshold voltage. The detection unit may be configured as an inverter. Accordingly, the display device according to an embodiment of the present invention can easily detect a change in the threshold voltage of the active area with a simple circuit configuration.

Specific details of other embodiments are included in the detailed description and drawings.

The present invention detects changes in the threshold voltage of a thin film transistor made of an oxide semiconductor material and compensates for the threshold voltage according to the detected result, thereby minimizing the decrease in brightness and image quality of the display device.

The present invention detects changes in the threshold voltage of a thin film transistor made of an oxide semiconductor material in the active area by placing a detection unit consisting of only an inverter in a dummy pixel, so that the change in threshold voltage in the active area can be easily detected with a simple circuit configuration.

The present invention can be more advantageous in securing the area of a display device by forming the gate electrode of a thin film transistor made of an oxide semiconductor material into a double gate structure and configuring it so that different signals are applied to each double gate electrode.

In the present invention, the gate electrode of a thin film transistor made of an oxide semiconductor material is formed in a double gate structure, and a compensation voltage according to a change in threshold voltage is applied to the lower gate electrode, thereby directly compensating for pixel deterioration.

The present invention can further improve device characteristics by forming thin film transistors made of two different types of semiconductor materials on the same substrate, so that the shortcomings of one thin film transistor are compensated for by the other thin film transistor.

The effects according to the present invention are not limited to the details exemplified above, and further various effects are included within the present invention.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention.
Figure 2 is a circuit diagram for explaining the pixel circuit of a general display device.
FIG. 3 is a waveform diagram showing a signal input to the pixel circuit of the general display device shown in FIG. 2.
FIG. 4 is a circuit diagram schematically showing the configuration of a pixel in an active area and a dummy pixel in an inactive area of a display device according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view schematically showing the structure of a portion of a pixel circuit in an active area of a display device according to an embodiment of the present invention.
6A and 6B are circuit diagrams showing another example of a detection unit disposed in a dummy pixel of an inactive area according to an embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

When an element or layer is referred to as “on” another element or layer, it includes instances where the other layer or other element is directly on top of or interposed between the other elements.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the components shown.

Each feature of the various embodiments of the present invention can be partially or fully combined or combined with each other, and as can be fully understood by those skilled in the art, various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other. It may be possible to conduct them together due to a related relationship.

In the present invention, the thin film transistor (TFT) may be configured as a PMOS type or NMOS type, and in the following embodiments, the thin film transistor will be described as configured as an NMOS type for convenience of explanation. Additionally, when describing a pulse-type signal, the gate high voltage (VGH) state is defined as a “high state” and the gate low voltage (VGL) state is defined as a “low state.”

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention.

Referring to FIG. 1 , a display device 100 according to an embodiment of the present invention includes a display panel 110, a gate driver 120, a data driver 130, and a timing controller 140.

The display panel 110 includes n gate lines (GL1,..., GLn) arranged in a first direction, m data lines (DL1,..., DLm) arranged in a direction different from the first direction, and n gate lines. It includes a plurality of pixels (P) electrically connected to (GL1, ..., GLn) and m data lines (DL1, ..., DLm). Accordingly, the plurality of pixels (P) display images by driving signals or driving voltages applied through the gate lines (GL1, ..., GLn) and data lines (DL1, ..., DLm).

The display panel 110 includes an active area (Active Area: A/A) and a non-active area (N/A) adjacent to the active area (A/A).

A plurality of pixels (P) capable of displaying an image are arranged in the active area (A/A). Each of the plurality of pixels P is disposed in a light emitting unit that emits light by a light emitting element and a pixel driver in which a plurality of driving elements for driving the light emitting element are disposed.

The light emitting device of the pixel P disposed in the active area A/A may be an organic light emitting device. In one embodiment of the present invention, the description is made on the assumption that the light-emitting device of the pixel P of the display device 100 is an organic light-emitting device, but the present invention is not limited thereto. That is, the present invention can be applied not only to organic light emitting display devices but also to quantum dot light emitting display devices (QLED) or various other display devices (eg, liquid crystal display devices). More specifically, one embodiment of the present invention is an invention to compensate for the shift of the threshold voltage (Vth) characteristics of a thin film transistor made of an oxide semiconductor to a negative polarity, and therefore, an oxide semiconductor is used in the pixel circuit configuration of the pixel P. It can be applied to any display device including a transistor.

The driver of the pixel P disposed in the active area A/A includes one or more switching thin film transistors, a driving thin film transistor, and a capacitor. At this time, one or more switching thin film transistors and one driving thin film transistor may be formed of different semiconductor materials. For example, the active layer of the switching thin film transistor may be formed of a semiconductor material made of oxide, and the driving thin film transistor may be formed of a semiconductor material made of low temperature polysilicon material. At this time, at least one thin film transistor among the one or more switching thin film transistors may have a double gate structure. More specifically, the switching thin film transistor having a double gate structure may be a thin film transistor whose threshold voltage characteristics are shifted to negative polarity while the display device 100 is driven. Different signals may be applied to each gate of a switching thin film transistor having a double gate structure. The pixel driver of the pixel P disposed in the active area A/A according to an embodiment of the present invention will be examined in more detail with reference to FIGS. 4 to 7B.

The non-active area (N/A) is an area arranged around the active area (A/A). More specifically, the non-active area (N/A) is an area adjacent to the active area (A/A) and surrounding the active area (A/A). The non-active area (N/A) is an area where no image is displayed, including dummy pixels, signal lines that transmit signals to pixels placed in the active area (A/A), and driving pixels in the active area (A/A). A circuit part, etc. may be disposed for this purpose. For example, an anti-static element, a signal pad, a signal link line, etc. may be disposed in the non-active area (N/A).

A dummy pixel (DP) will be further arranged in an area where a plurality of rows arranged in the first direction (X) of the pixel (P) arranged in the active area (A/A) of the non-active area (N/A) are extended. You can. More specifically, a dummy pixel (DP) may be disposed in an area of the non-active area (N/A) closest to the active area (A/A). That is, the dummy pixel DP is placed in the same row as the pixel P placed in the active area A/A, but is placed in an area adjacent to the active area A/A. Accordingly, if n rows of pixels P in the active area A/A are arranged in the first direction, n dummy pixels DP may also be arranged. Meanwhile, in FIG. 1, dummy pixels (DP) are shown to be disposed on both sides of the active area (A/A) among the non-active areas (N/A), but this is not limited to this, and the active area (A/A) and It may be placed only on one side of the active area (A/A) in the adjacent non-active area (N/A), and may be placed on the upper and lower sides of the active area (A/A) corresponding to the pixel row of the active area (A/A). It may be placed in .

Since the dummy pixel (DP) is placed in the non-active area (A/A), it is not used for image display and detects the change in threshold voltage of any one switching thin film transistor made of an oxide semiconductor material in the active area (A/A). A detection unit may be disposed. This detection unit may be formed to have an inverter structure, and the detection unit of the dummy pixel DP will be examined in more detail with reference to FIGS. 4, 6A, and 6B below.

The timing controller 140 processes image data (RGB) input from the outside to suit the size and resolution of the display panel 110 and supplies it to the data driver 130. The timing controller 140 receives synchronization signals (SYNC) input from the outside, for example, a dot clock signal (DCLK), a data enable signal (DE), a horizontal synchronization signal (Hsync), and a vertical synchronization signal (Vsync). It generates multiple gate control signals (GCS) and data control signals (DCS). The timing controller 140 supplies the generated gate control signal (GCS) and data control signal (DCS) to the gate driver 120 and the data driver 130, respectively, to operate the gate driver 120 and the data driver 130. Control.

The timing controller 140 may compare the detection value input from the sensing driving element included in the dummy pixel DP with a preset reference value and then control to apply a compensation voltage to the pixel P according to the comparison result. Meanwhile, in one embodiment of the present invention, a compensation unit that compares the value detected in the dummy pixel DP with a preset reference value has been described as being included in the timing controller 140, but the present invention is not limited thereto and generates a compensation voltage. The compensation unit may be included in the gate driver 120.

The gate driver 120 supplies gate signals to n gate lines GL1, ..., GLn according to the gate control signal GCS supplied from the timing controller 140. Here, the gate signal includes at least one scan signal (SCAN) and an emission control signal (EM).

The gate driver 120 applies a compensation voltage according to the deterioration of the pixel P to the lower gate of the thin film transistor having a double gate structure according to the detection signal that detects the degree of deterioration of the pixel P supplied from the timing controller 140. It can be approved.

The data driver 130 converts image data (RGB) into a data voltage according to the data control signal (DCS) supplied from the timing controller 140, and transmits the converted data voltage to m data lines DL1, ..., DLm. It is supplied to the pixel (P) through .

Each pixel P of the display device 100 according to an embodiment of the present invention includes an organic light emitting element and a pixel circuit that controls driving of the organic light emitting element. An organic light emitting device consists of an anode, a cathode, and a light emitting layer between the anode and the cathode. The pixel circuit includes a switching transistor, a driving transistor, and a capacitor. More specifically, the driving transistor controls the amount of light emitted from the organic light-emitting device by controlling the amount of current supplied to the organic light-emitting device according to the data voltage charged in the capacitor, and the switching transistor controls the amount of light emitted from the organic light-emitting device (SCAN signal) supplied through the gate line (GL). ) is received and the data voltage (Vdata) is charged to the capacitor.

As described above, the display device 100 according to an embodiment of the present invention has a threshold voltage of a thin film transistor made of an oxide semiconductor material among the pixel circuits constituting the pixel P disposed in the active area A/A. Since the image quality of the display device deteriorates when the characteristic is shifted to a negative polarity, the invention is intended to compensate for the threshold voltage characteristic shifted to the negative polarity. Therefore, before looking at the present invention in more detail, a pixel circuit arranged in a general active area is as follows.

Figure 2 is a circuit diagram for explaining the pixel circuit of a general display device.

Referring to FIG. 2, the pixel circuit of a typical display device includes a driving thin film transistor (DT), one or more switching thin film transistors (T1, T2, T3, T4, and T5), and a capacitor (Cst). At this time, one or more switching thin film transistors (T1, T2, T3, T4, T5) and the driving thin film transistor (DT) may be made of different semiconductor materials. For example, at least one switching thin film transistor (T1, T2, T3, T4, T5) among the one or more switching thin film transistors (T1, T2, T3, T4, T5) may be made of an oxide semiconductor material, an example of which is 2 It may be a switching thin film transistor (T2).

The driving thin film transistor (DT) controls the light emission current applied to the light emitting device (OD) by the gate-source voltage (Vgs). The driving thin film transistor DT includes a gate connected to the second node N2, a source connected to the third node N3, and a drain connected to the first node N1. Specifically, the gate of the driving thin film transistor (DT) stores the high potential voltage (VDD) when the second switching thin film transistor (T2) and the third switching thin film transistor (T3) are turned on. When the data voltage is supplied while the second switching thin film transistor (T2) is turned on, the data voltage is written to the gate of the driving thin film transistor (DT) using a diode connection method. The driving thin film transistor (DT) supplies driving current to the light emitting device (OD) by the light emission control signal (EM) and controls light emission of the light emitting device (OD) according to the amount of current.

The first switching thin film transistor T1 is turned on in response to the second scan signal SCAN2 applied to the second gate line, and the data voltage provided through the data line Data is applied to the driving thin film transistor DT. It is structured so that The first switching thin film transistor T1 includes a gate connected to the second gate line, a drain connected to the data line, and a source connected to the third node N3. Specifically, when the second scan signal SCAN2 is supplied to the gate in a high state, the data voltage is supplied from the drain of the first switching thin film transistor T1 to the driving thin film transistor DT. ) is supplied to the third node (N3), which is the source node of ).

The second switching thin film transistor T2 is connected between the gate and drain of the driving thin film transistor DT, that is, between the first node N1 and the second node N2. The second switching thin film transistor T2 includes a gate connected to the first gate line, a source connected to the second node N2, and a drain connected to the first node N1. Specifically, when the first scan signal SCAN1 applied through the first gate line is in a high state, the second switching thin film transistor T2 is turned on. In this way, when the second switching thin film transistor T2 is turned on, the second switching thin film transistor T2 generates the high potential voltage VDD of the first node N1 or the sampled voltage of the driving thin film transistor DT. 2 It is supplied to the node N2 to initialize the data voltage written to the light emitting device OD, or the data voltage is written and the threshold voltage of the driving thin film transistor DT is sampled. This second switching thin film transistor T2 may be made of an oxide semiconductor material.

The third switching thin film transistor T3 controls the current path between the high potential voltage VDD and the driving transistor DT in response to the second emission control signal EM2 applied through the second emission control line. The third switching thin film transistor T3 includes a gate connected to the second light emission control line, a drain of the driving transistor DT, that is, a source connected to the first node N1, and a drain connected to the high potential voltage VDD. Specifically, when the second light emission control signal EM2 is in a high state, the third switching thin film transistor T3 is turned on and drives the high potential voltage VDD from the source. It is supplied to the first node (N1), which is the drain node of the transistor (DT).

The fourth switching thin film transistor T4 controls the current path between the light emitting device OD and the driving transistor DT in response to the first light emission control signal EM1 applied through the first light emission control line. The fourth switching thin film transistor T4 includes a gate connected to the first light emission control line, a source connected to the light emitting device OD, and a drain connected to the third node N3. Specifically, when the first light emission control signal EM1 is in a high state, the fourth switching thin film transistor T4 is turned on, and the third switching thin film transistor T4 is the source of the driving thin film transistor DT. The node N3 and the fourth node N4, which is the source node of the fourth switching TFT T4, are electrically connected. Accordingly, when the fourth switching thin film transistor T4 is turned on by the first emission control signal EM1, the voltage of the third node N3 is supplied to the fourth node N4. When the fourth switching thin film transistor (T4), the driving thin film transistor (DT), and the third switching thin film transistor (T3) are turned on, the high potential voltage (VDD) is supplied to the driving thin film transistor (DT), and the light emitting device (OD) ), a driving current is supplied to the light emitting element (OD) to emit light.

The fifth switching thin film transistor T5 is turned on in response to the first scan signal SCAN1 applied through the first gate line, and accordingly, the initialization voltage VINI is set to the fourth node N4 and the fifth node ( N5) can be approved. The fifth switching thin film transistor T5 includes a gate connected to the first gate line, a drain connected to the initialization voltage line, and a source connected to the fourth node N4 and the fifth node N5, which is the anode of the light emitting device OD. do. Specifically, when the first scan signal SCAN1 is in a high state, the fifth switching thin film transistor T5 is turned on and sets the initialization voltage VINI to the fourth node N4 and It is supplied to the fifth node (N5). Accordingly, when the fifth switching thin film transistor (T5) is turned on by the first scan signal (SCAN1), the initialization voltage (VINI) is supplied to the fourth node (N4) and the fifth node (N5) to turn on the light emitting device (OD). ) can be initialized.

The capacitor Cst may be a storage capacitor Cst that stores the gate voltage and threshold voltage Vth of the driving thin film transistor DT until the next refresh frame. Here, the capacitor Cst is disposed between the second node N2, which is the gate of the driving thin film transistor DT, and the fourth node N4, which is electrically connected to the anode of the light emitting device OD. That is, the capacitor Cst is electrically connected to the second node N2 and the fourth node N4 to adjust the difference between the voltage of the gate of the driving thin film transistor DT and the voltage supplied to the anode of the light emitting device OD. Save.

The light-emitting device OD emits light by the light-emitting current supplied from the driving transistor DT. The anode of this light emitting device (OD) is connected to the fifth node (N5), and the cathode is connected to the low potential voltage (VSS).

The operation of the pixel circuit of a typical display device configured in this way is shown in FIG. 3.

FIG. 3 is a waveform diagram showing a signal input to the pixel circuit of the general display device shown in FIG. 2.

Referring to FIG. 3, a data voltage is written to each pixel arranged in one horizontal line through an initialization section (P1), a sampling and programming section (P2), a holding section (P3), and an emission section (P4), and each pixel It glows.

In the initialization period P1, the first scan signal SCAN1 rises to a high state, and the second scan signal SCAN2 maintains a low state. At the same time, the first emission control signal EM1 falls to a low state, and the second emission control signal EM2 maintains a high state. Accordingly, in the initialization period P1, in the pixel circuit shown in FIG. 2, the second switching thin film transistor T2, the third switching thin film transistor T3, and the fifth switching thin film transistor T5 are turned on, and the first switching thin film transistor T5 is turned on. The thin film transistor T1 and the fourth switching thin film transistor T4 are turned off. Accordingly. In the initialization period (P1), the initialization voltage (VINI) is supplied to the fourth node (N4) through the fifth switching thin film transistor (T5), and is applied to the first node (N1) through the third switching thin film transistor (T3). The high potential voltage (VDD) is supplied to the second node (N2) through the second switching thin film transistor (T2). That is, as the initialization voltage VINI is supplied to the fifth node N5, which is the anode of the light emitting device OD, the data voltage written to the light emitting device OD is initialized, and the data voltage written to the light emitting device OD is initialized, and the data voltage written to the light emitting device OD is reset. The above voltage (VDD) is supplied.

During the sampling and programming period P2, the first scan signal SCAN1 rises from a low state to a high state, and the second scan signal SCAN2 also rises to a high state. During the sampling and programming period P2, the second emission control signal EM2 is polled to a low state, and the first emission control signal EM1 is also maintained in a low state. Accordingly, in the sampling and programming period P2, the first switching thin film transistor T1, the second switching thin film transistor T2, and the fifth switching thin film transistor T5 are turned on, and the third switching thin film transistor T3 and The fourth switching thin film transistor T4 is turned off. Accordingly, the data voltage is supplied to the third node N3 through the first switching thin film transistor T1. In addition, as the second switching thin film transistor T2 is turned on, the first node N1, which is the drain node of the driving thin film transistor DT, and the second node N2, which is the gate node of the driving thin film transistor DT, are turned on. By being connected, the gate-source voltage (Vgs) of the driving thin film transistor (DT) is sampled as the threshold voltage (Vth) of the driving thin film transistor (DT) by a diode-connection method. In addition, as the fifth switching thin film transistor (T5) is turned on, the initialization voltage (VINI) is supplied to the fourth node (N4), and the data voltage (Vdata) + threshold voltage (Vth) - initialization is supplied to the capacitor (Cst). The voltage (VINI) value is stored. Accordingly, during the sampling and programming period (P2), the first node (N1) and the second node (N2) have a data voltage (Vdata) + a threshold voltage (Vth) value, and the third node (N3) has a data voltage (Vdata) ) value, and the fourth node (N4) may have an initialization voltage (VINI) value.

The holding section P3 may include a first holding section (P3-1) and a second holding section (P3-2).

In the first holding period (P3-1), the first scan signal (SCAN1) and the second scan signal (SCAN2) poll to be in a low state, and the first emission control signal (EM1) and the second emission control signal (EM2) remains low. Accordingly, in the first holding period (P3-1), all switching thin film transistors (T1, T2, T3, T4, and T5) are turned off. Accordingly, each of the first node (N1), the second node (N2), the third node (N3), and the fourth node (N4) to which the data voltage is sampled or written during the sampling and programming period (P2) is floated, The voltage at each node remains the same.

In the second holding period (P3-2), the first scan signal (SCAN1) and the second scan signal (SCAN2) poll to the low state, and the first emission control signal (EM1) rises from the low state to the high state. , the second emission control signal EM2 remains low. Accordingly, in the second holding period (P3-2), only the fourth switching thin film transistor (T4) is turned on, and the first switching thin film transistor (T1), the second switching thin film transistor (T2), and the third switching thin film transistor (T3) are turned on. ) and the fifth switching thin film transistor (T5) are all turned off. Accordingly, the fourth switching thin film transistor T4 is turned on to connect the third node N3 and the fifth node N5, and the data voltage Vdata held at the third node N3 is connected to the fifth node It is supplied to (N5).

In the emission period P4, the first scan signal SCAN1 and the second scan signal SCAN2 are maintained in a low state, and the second emission control signal EM2 rises and remains in a high state. Additionally, the first emission control signal EM1 also maintains a high state. Accordingly, in the light emission period P4, the first switching thin film transistor T1, the second switching thin film transistor T2, and the fifth switching thin film transistor T5 are turned off, and the third switching thin film transistor T3 and the fourth switching thin film transistor T5 are turned off. The switching thin film transistor T4 is turned on. In addition, the driving transistor (DT) is also turned on by the data voltage (Vdata) + threshold voltage (Vth) stored in the second node (N2) until the second holding period (P3-2), and the high potential voltage (VDD) is turned on. A path through which the driving current can flow from the line to the light emitting device OD is formed. That is, in the light emission section P4, the light emission current Ioled flows to the light emitting device OD through the turned-on driving thin film transistor DT, the third switching thin film transistor T3, and the fourth switching thin film transistor T4.

The active layer of the second switching thin film transistor (T2) of the pixel circuit of a general display device driven in this way may be made of an oxide semiconductor material. Depending on the characteristics of the oxide semiconductor material, there is a significant change in bias stress, so the threshold The voltage (Vth) shifts to negative polarity. At this time, the second node N2, which is the source of the second switching thin film transistor T2, has a data voltage (Vdata) + threshold voltage from the sampling and programming period (P2) to the holding period (P3), as described in FIG. It is a node where (Vth) is stored and is a node that affects the light emission of the light emitting device (OD) in the light emission section (P4). However, if the characteristics of the threshold voltage (Vth) are shifted to negative polarity according to the characteristics of the second switching thin film transistor (T2), this causes a decrease in luminance of the display device and thus deteriorates the image quality of the display device. . In particular, as shown in FIG. 3, it can be seen that the voltage supplied to the second node N2 in the sampling and programming period P2 is shifted to negative polarity as the second scan signal SCAN2 is turned on. .

Accordingly, in the present invention, a configuration capable of sensing a change in the threshold voltage of the second switching thin film transistor (T2) in the active area (A/A) is performed using a dummy pixel in the non-active area (N/A) or a dummy pixel in the active area (A). By adding to the pixel circuit configuration of /A), we would like to propose a method to minimize the degradation of image quality of the display device by detecting changes in threshold voltage and then compensating for them according to the detection result. Accordingly, first, with reference to FIG. 4 below, a method for detecting pixel deterioration using a dummy pixel and a method for compensating for the same will be examined in detail.

FIG. 4 is a circuit diagram schematically showing the configuration of a pixel in an active area and a dummy pixel in an inactive area of a display device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view schematically showing the structure of a portion of a pixel circuit in an active area of a display device according to an embodiment of the present invention. 6A and 6B are circuit diagrams showing another example of a detection unit disposed in a dummy pixel of an inactive area according to an embodiment of the present invention.

First, referring to FIG. 4, the display device 100 according to an embodiment of the present invention includes a pixel (P) disposed in the active area (A/A), a non-active area ( It may include a dummy pixel (DP) and a compensation unit 430 disposed in N/A).

The pixel P disposed in the active area A/A includes a pixel driver 410 and a light emitting unit 420. The pixel driver 410 disposed in the active area (A/A) includes one or more switching thin film transistors (T1-T5), a driving thin film transistor (DT), and a capacitor (Cst) for driving the light emitting device (OD). . At this time, the active thin film transistor (DT) constituting the pixel (P) disposed in the active area (A/A) and the second switching thin film transistor (T2) among one or more switching thin film transistors (T1-T5), respectively. The layers may be composed of different semiconductor materials. As such, a transistor configuration in which at least one of the driving thin film transistor (DT) and one or more switching thin film transistors (T1-T5) in one pixel circuit is made of different semiconductor materials may be referred to as a multi-type transistor configuration.

The structures of the driving thin film transistor (DT) and the second switching thin film transistor (T2) will be examined in more detail with reference to FIG. 5 below.

Referring to FIG. 5, the pixel P disposed in the active area A/A may include a substrate SUB, a buffer layer 111, a driving thin film transistor DT, and a second thin film transistor T2. .

The substrate SUB supports various components of the display panel 100. The substrate (SUB) may be made of glass or a plastic material with flexibility. If the substrate (SUB) is made of a plastic material, for example, it may be made of polyimide (PI).

The buffer layer 111 may be formed on the entire surface of the substrate SUB. The buffer layer 111 may be made of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The buffer layer 111 may serve to improve adhesion between the layers formed on the buffer layer 111 and the substrate SUB and to block alkaline components leaking from the substrate SUB. The buffer layer 111 is not an essential component and may be omitted depending on the type and material of the substrate (SUB), the structure and type of the thin film transistor, etc.

The driving thin film transistor (DT) may be disposed on the buffer layer 111. The driving thin film transistor DT may include a first active layer 121, a first gate electrode 124, a first source electrode 122, and a first drain electrode 123.

The first active layer 121 of the driving thin film transistor (DT) may be disposed on the buffer layer 111. The first active layer 121 may include low temperature poly-silicon (LTPS). Polysilicon materials have high mobility, low energy consumption, and excellent reliability, so they can be applied to gate drivers and/or multiplexers (MUX) for driving devices that drive thin film transistors for display devices. The first active layer 121 includes a first channel region 121a where a channel is formed when the driving thin film transistor DT is driven, a first source region 121b on both sides of the first channel region 121a, and a first drain. It may include an area 121c.

A gate insulating layer 112 may be disposed on the first active layer 121 of the driving thin film transistor DT. The first gate insulating layer 112 may be made of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The first gate insulating layer 112 includes the first source electrode 122 and the first drain electrode 123 of the driving thin film transistor DT, respectively, and the first active layer 121 of the driving thin film transistor DT. It may include a contact hole to be connected to each of the source region 121b and the first drain region 121c.

The first gate electrode 124 of the driving thin film transistor DT may be disposed on the first gate insulating layer 112. The first gate electrode 124 is made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), or neodymium (Nd). Alternatively, it may be formed as a single layer or multiple layers made of alloys thereof. The first gate electrode 124 may be formed on the first gate insulating layer 112 to overlap the first channel region 121a of the first active layer 121 of the driving thin film transistor DT.

An interlayer insulating layer 113 may be disposed on the first gate insulating layer 112 and the first gate electrode 124. The interlayer insulating layer 113 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. A contact hole may be formed in the interlayer insulating layer 113 to expose the first source region 121b and the first drain region 121c of the first active layer 121 of the driving thin film transistor DT.

A first source electrode 122 and a first drain electrode 123 may be formed on the interlayer insulating layer 113. The first source electrode 122 and the first drain electrode 123 may be connected to the first active layer 121 through contact holes formed in the interlayer insulating layer 113 and the first gate insulating layer 112. The first source electrode 122 and the first drain electrode 123 may have a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti) made of a conductive metal material, but are not limited thereto. For example, the first source electrode 122 and the first drain electrode 123 are made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), It may be formed as a single layer or multiple layers made of either nickel (Ni), neodymium (Nd), or an alloy thereof.

A second switching thin film transistor T2 may be disposed on the interlayer insulating layer 113. The second switching thin film transistor T2 may have a double gate structure. More specifically, the second switching thin film transistor T2 includes a lower second gate electrode 134B, a second active layer 131, a second source electrode 132, a second drain electrode 133, and an upper second gate. It may include an electrode 134T. Meanwhile, in FIG. 5, it has been described that the second switching thin film transistor T2 is disposed on the interlayer insulating layer 113, but the present invention is not limited thereto. For example, the second switching thin film transistor T2 may be disposed on the isolation insulating layer 114.

The lower second gate electrode 134B of the second switching thin film transistor T2 is disposed on the interlayer insulating layer 113. The lower second gate electrode 134B of the second switching thin film transistor T2 is electrically connected to the external compensation unit 430 and provides a compensation voltage for compensating for changes in the threshold voltage characteristics of the second switching thin film transistor T2. This can be approved. The lower second gate electrode 134B of the second switching thin film transistor T2 may have a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti) made of a conductive metal material, but is not limited to this. No. For example, the lower second gate electrode 134B is made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium ( It may be formed as a single layer or multiple layers made of any one of Nd) or an alloy thereof. The lower second gate electrode 134B of the second switching thin film transistor T2 may be formed through the same process as the first source electrode 122 and the first drain electrode 123 of the driving thin film transistor DT.

A separation insulating layer 114 will be disposed on the interlayer insulating layer 113, the first source electrode 122, the first drain electrode 123, and the lower second gate electrode 134B of the second switching thin film transistor T2. You can. The isolation insulating layer 114 may be disposed between the driving thin film transistor (DT) and the second switching thin film transistor (T2) to separate the driving thin film transistor (DT) and the second switching thin film transistor (T2). The isolation insulating layer 114 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

The second active layer 131 of the second switching thin film transistor T2 may be disposed on the isolation insulating layer 114. The second active layer 131 may be made of an oxide semiconductor material. Oxide semiconductor materials have a larger bandgap compared to polysilicon materials. Accordingly, since the oxide semiconductor material does not allow electrons to cross the bandgap in the off state, the second active layer 131 made of the oxide semiconductor material has a low off current. Therefore, the second switching thin film transistor T2 including an active layer made of an oxide semiconductor material may be suitable as a switching transistor that maintains a short on time and a long off time, but is not limited thereto. . That is, depending on the characteristics of the display device, a transistor made of an oxide semiconductor material may be used as a driving transistor. Meanwhile, the second active layer 131 may be made of a metal oxide, for example, IGZO (Indium-Gallium-Zinc-Oxide), IZO (Indium-Zinc-Oxide), or IGO (Indium-Gallium-Oxide).

A second gate insulating layer 116 may be disposed on the second active layer 131. The second gate insulating layer 116 may be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

A second upper gate electrode 134T may be disposed on the second gate insulating layer 116. The upper second gate electrode 134T is made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), or neodymium (Nd). It may be formed as a single layer or multiple layers made of one or an alloy thereof. The upper second gate electrode 134T may be patterned to overlap the second active layer 131 and the second gate insulating layer 114. A first scan signal SCAN1 that controls whether the second switching thin film transistor T2 is switched may be applied to the second upper second gate electrode 134T.

A protective layer 115 may be disposed on the isolation insulating layer 114, the second active layer 131, and the upper second gate electrode 134T. The protective layer 115 may be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

A second source electrode 132 and a second drain electrode 133 may be disposed on the protective layer 115. The second source electrode 132 and the second drain electrode 133 may be connected to the second active layer 131 through a contact hole formed in the protective layer 115.

A planarization layer 117 may be disposed on the second source electrode 132, the second drain electrode 133, and the protective layer 115. The planarization layer 117 may be made of an organic material for planarizing the top of the driving thin film transistor (DT) and the second switching thin film transistor (T2). Although not shown, a contact hole may be formed in the planarization layer 117 to expose the second drain electrode 133 for electrical connection with the anode electrode of the light emitting device disposed on the planarization layer 117.

As such, the second switching thin film transistor T2 disposed in the active area A/A of the display device 100 according to an embodiment of the present invention has a double gate structure, and the lower second gate electrode 134B By configuring to apply a compensation voltage according to a change in the threshold voltage of the second switching thin film transistor T2, degradation of image quality of the display device 100 according to an embodiment of the present invention can be minimized.

Meanwhile, referring to FIG. 4 , the dummy pixel DP in the non-active area N/A may include a detection unit 430 configured in the form of an inverter. In one embodiment of the present invention, as shown in FIG. 4, the dummy pixel DP is shown as consisting of only an inverter, but the present invention is not limited thereto. For example, the dummy pixel DP may be configured to have a structure similar to the pixel P disposed in the active area A/A, but in this case, the dummy pixel DP may have a structure in which no light emitting unit is disposed. You can.

The detection unit 430 may detect whether the threshold voltage of the second switching thin film transistor (T2) disposed in the pixel (P) of the active area (A/A) changes. The detection unit 430 may be configured in the form of an inverter. At this time, the detection unit 430 may be equipped with an inverter of a different type depending on the type of the driving thin film transistor (DT) disposed in the pixel (P) of the active area (A/A). More specifically, when the driving thin film transistor (DT) disposed in the pixel (P) of the active area (A/A) has an NMOS type, the inverter disposed in the detection unit 430 is shown in FIGS. 4 and 6A. As shown, it may have a D inverter form consisting of a combination of two NMOS transistors. Meanwhile, if the driving thin film transistor (DT) disposed in the pixel (P) of the active area (A/A) has a PMOS type, the inverter disposed in the detection unit 430 is a combination of PMOS transistor and NMOS transistor. It may take the form of a CMOS inverter. This is to more accurately detect changes in threshold voltage by having a shape similar to that of the driving transistor (DT) and the second switching thin film transistor (T2) of the pixel (P) disposed in the active area (A/A).

First, referring to FIG. 4, the detection unit 430 may have a de-inverter form because the driving transistor DT in the active area A/A has an NMOS form. More specifically, the detection unit 430 may have a first NMOS transistor (M1) and a second NMOS transistor (M2) electrically connected to each other. At this time, the first NMOS transistor (M1) can be said to be a depletion type load transistor, and the second NMOS transistor (M2) can be said to be a driving transistor.

The drain of the first NMOS transistor M1 may be connected to a high potential voltage (VDD), and the gate and source may be commonly connected to the output terminal (Vout).

The gate of the second NMOS transistor M2 may be connected to the input terminal (Vin), the drain may be connected to the output terminal (Vout), and the source may be connected to the low potential voltage (VSS). At this time, a swept voltage may be applied to the input terminal Vin, and the swept voltage may be from the gate low voltage VGL to the gate high voltage VGH.

The detection unit 430 having this structure generates a high potential voltage (VDD) in a state in which a voltage of 0V is applied to the input terminal (Vin), that is, in a state in which the second NMOS transistor (M2) is turned off. When a high level high potential voltage is applied to the drain of the first NMOS transistor M1, a high level voltage is detected at the output terminal Vout. With the high potential voltage (VDD) continuously applied to the drain of the first NMOS transistor (M1), a sweep voltage signal for detecting the threshold voltage characteristics of the second switching thin film transistor (T2) is applied to the input terminal (Vin). When the second NMOS transistor (M2) is turned on by applying, most of the current flows through the second NMOS transistor (M2) at the low potential voltage (VSS). Accordingly, a low level voltage is detected at the output terminal (Vout). That is, while the high potential voltage (VDD) is fixed, the output value output to the output terminal (Vout) may vary depending on the sweep voltage applied to the input terminal (Vin). The output value output in this way is input to the external compensation unit 440.

The compensation unit 440 compares the output value output from the detection unit 430 with a preset reference value to determine a change in the threshold voltage of the second switching thin film transistor T2 and generates a compensation voltage Vc according to the determination result. A compensation voltage is applied to the lower second gate electrode 134B of the second switching thin film transistor T2 in the active area A/A. One end of the compensation unit 440 may be connected to the detection unit 430 of the dummy pixel DP, and the other end may be electrically connected to the second switching thin film transistor T2 of the active area A/A. This compensation unit 440 may also be referred to as a comparison unit and may be composed of, for example, an operational amplifier (OP AMP).

The detection unit 430 and the compensation unit 440 are periodically driven every frame to detect changes in the threshold voltage of the corresponding pixel row in the active area (A/A) and generate a compensation voltage according to the detection result to generate a compensation voltage in the active area (A/A). It can be driven to be applied to the pixel (P) of A/A). However, as previously seen in FIG. 3, when the second scan signal (SCAN2) is turned on in the sampling and programming section, the threshold voltage of the second switching thin film transistor (T2) is shifted to negative polarity, so the timing controller ( 140) may control the compensation voltage to be applied to the lower second gate electrode 134B of the second switching thin film transistor T2 in the active area A/A in response to the application of the second scan signal SCAN2. there is. Meanwhile, in one embodiment of the present invention, it has been described that the compensation unit 440 may be placed in the timing controller 140, but the present invention is not limited thereto and may also be placed in the gate driver 120.

In addition, when the driving thin film transistor (DT) of the active area (A/A) has an NMOS form, as shown in FIG. 4, the detection unit 430 has a de-inverter form, but as shown in FIG. 6A, The first NMOS transistor M11 of the detection unit 430 may have a double gate structure. In this way, when the first NMOS transistor (M11), which is a depletion type transistor, has a double gate structure, a high potential voltage (VDD) is input to the lower gate, so that the second NMOS transistor (M12) is output faster than when it is turned off. A high level voltage can be output from the terminal (Vout).

Meanwhile, when the driving transistor DT of the active area A/A has a PMOS form, the detection unit 430 may have a CMOS inverter form, as shown in FIG. 6B. More specifically, when the driving transistor DT has a PMOS type, the detection unit 430 may have a structure in which the PMOS transistor M21 and the NMOS transistor M22 are connected to each other.

The PMOS transistor M21 may have a drain connected to a high potential voltage (VDD), a gate connected to an input terminal, and a source connected to an output terminal (Vout).

The gate of the NMOS transistor M22 may be connected to the input terminal (Vin), the drain may be connected to the output terminal (Vout), and the source may be connected to the low potential voltage (VSS). At this time, a swept voltage may be applied to the input terminal Vin, and the swept voltage may be from the gate low voltage VGL to the gate high voltage VGH.

The detector 430 having this structure turns on the PMOS transistor (M21) to output a high-level voltage when a low-level signal is input to the input terminal (Vin), and outputs a high-level voltage to the input terminal (Vin). When the signal is input, the NMOS transistor (M22) is turned on so that a low level voltage is output. The output value output in this way is input to the external compensation unit 440, and the setting value preset in the compensation unit 440 is compared with the output value output from the detection unit 430 to determine the second value of the active area (A/A). By allowing the compensation voltage generated in the compensation unit 440 to be applied to the switching thin film transistor T2, a decrease in luminance and image quality of the display device 100 due to a change in threshold voltage can be minimized.

A display device according to various embodiments of the present invention may be described as follows.

A display device according to an embodiment of the present invention includes a pixel unit disposed in an active area where an image is displayed, a detection unit that detects whether the threshold voltage of the pixel unit changes, and an output value detected from the detection unit, and sets the output value and a preset reference value. It includes a compensation unit that compares to generate and output a compensation voltage that compensates for the threshold voltage change, and the detection unit may be configured as an inverter.

According to another feature of the present invention, the pixel unit includes a light-emitting device that emits light, a capacitor that stores a data voltage supplied through a data line, a driving thin film transistor that controls the light-emitting current flowing through the light-emitting device, and a light-emitting device that is supplied through a gate line. It may include one or more switching thin film transistors that receive the scan signal and charge the data voltage to the capacitor.

According to another feature of the present invention, the detector may have a different type of inverter structure depending on the type of the driving thin film transistor.

According to another feature of the present invention, if the driving thin film transistor is an NMOS type, the detector may have a de-inverter structure in which two NMOS transistors are electrically connected.

According to another feature of the present invention, one of the two NMOS transistors may be a depletion type transistor.

According to another feature of the present invention, the voltage input to the inverter may be a swept gate voltage.

According to another feature of the present invention, if the driving thin film transistor is a PMOS type, the detector may have a CMOS inverter structure in which the PMOS transistor and the NMOS transistor are electrically connected.

According to another feature of the present invention, the detection unit may be included in a dummy pixel disposed in an inactive area located in a peripheral area of the active area.

According to another feature of the present invention, the detector may be disposed in an inactive area where an image is not displayed and is located in a peripheral area of the active area, but may be disposed on an extension of the same row in which the pixel unit is disposed.

According to another feature of the present invention, the active layers of at least one of the driving thin film transistor and one or more switching thin film transistors may be made of different semiconductor materials.

According to another feature of the present invention, a compensation voltage applied from the compensation unit is applied to any one switching thin film transistor among one or more switching thin film transistors, and the active layer of any one switching thin film transistor may be made of an oxide semiconductor material. there is.

According to another feature of the present invention, any one switching thin film transistor has a double gate structure having an upper gate electrode and a lower gate electrode, and different signals can be applied to the upper gate electrode and the lower gate electrode.

According to another feature of the present invention, a switching signal for turning on or off one switching thin film transistor is applied to the upper gate electrode, and a switching signal is applied to the lower gate electrode from the compensation unit. A compensation voltage may be applied.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100: display device
110: display panel
120: Gate driver
130: data driving unit
140: Timing controller
410: Pixel driver
420: light emitting unit
430: detection unit
440: Compensation unit
P: Pixel
DP: dummy pixel
A/A: Active area
N/A: Inactive area

Claims (13)

A pixel unit disposed in an active area where an image is displayed;
a detection unit that detects whether the threshold voltage of the pixel unit changes; and
A compensation unit that receives the detected output value from the detection unit and compares the output value with a preset reference value to generate and output a compensation voltage that compensates for the change in the threshold voltage.
A display device wherein the detection unit is comprised of an inverter. The method of claim 1, wherein the pixel unit,
A light emitting device that emits light;
A capacitor that stores the data voltage supplied through the data line;
a driving thin film transistor that controls light emission current flowing through the light emitting device;
A display device comprising: one or more switching thin film transistors that receive a scan signal supplied through a gate line and charge the capacitor with the data voltage. According to paragraph 2,
The display device wherein the detection unit has an inverter structure of a different type depending on the type of the driving thin film transistor. According to paragraph 3,
If the driving thin film transistor is an NMOS type, the detection unit is comprised of a de-inverter in which two NMOS transistors are electrically connected. According to paragraph 4,
A display device, wherein one of the two NMOS transistors is a depletion type transistor. According to paragraph 4,
A display device wherein the voltage input to the inverter is a swept gate voltage. According to paragraph 3,
If the driving thin film transistor is a PMOS type, the detection unit is composed of a CMOS inverter to which a PMOS transistor and an NMOS transistor are electrically connected. According to paragraph 1,
The display device wherein the detection unit is included in a dummy pixel disposed in a non-active area located in a peripheral area of the active area. According to paragraph 1,
The detection unit is disposed in an inactive area in which an image is not displayed and is located in a peripheral area of the active area, and is disposed on an extension line of the same row in which the pixel unit is disposed. According to paragraph 2,
A display device, wherein each active layer of at least one of the driving thin film transistor and the one or more switching thin film transistors is made of a different semiconductor material. According to clause 10,
A compensation voltage applied from the compensation unit is applied to any one of the one or more switching thin film transistors,
A display device, wherein the active layer of any one of the switching thin film transistors is made of an oxide semiconductor material. According to clause 11,
One of the switching thin film transistors has a double gate structure having an upper gate electrode and a lower gate electrode,
A display device in which different signals are applied to the upper gate electrode and the lower gate electrode. According to clause 12,
A switching signal for turning on or off the one switching thin film transistor is applied to the upper gate electrode, and a compensation voltage applied from the compensation unit is applied to the lower gate electrode. , display device.

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