KR20200071603A - Display device - Google Patents

Abstract

The present invention relates to a display device, wherein the display device according to one embodiment of the present invention includes: a pixel portion disposed in an active area in which an image is displayed; a detection unit which detects whether or not a threshold voltage of a pixel unit changes; and a compensation unit which receives a detected output value from the detection unit and compares the output value with a preset reference value to generate and output a compensation voltage which compensates for the change in the threshold voltage, wherein the detection unit may be composed of an inverter. Accordingly, the display device according to one exemplary embodiment of the present invention can easily detect a change in the threshold voltage of the active area with a simple circuit configuration.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device for improving a problem caused by a change in threshold voltage characteristics of a thin film transistor made of an oxide semiconductor material.

With the recent advent of the information age, the display field for visually expressing electrical information signals has rapidly developed, and in response to this, various display devices having excellent performance of thinning, lightening, and low power consumption have been developed. Is being developed.

Specific examples of the display device include a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an organic light emitting display device ( Organic Light Emitting Display device (OLED).

The display device includes a display panel in which a plurality of pixels are arranged, and a driving unit for driving the display panel, and a light emitting element, a switching thin film transistor, and a driving thin film transistor are formed in each of the plurality of pixels.

Recently, as the display device is implemented in a large area and a high resolution, a thin film transistor is required that secures stable operation and durability along with a faster signal processing speed.

Accordingly, studies have been actively conducted to form an active layer of a thin film transistor with an oxide semiconductor material having excellent mobility characteristics in order to improve the mobility of the thin film transistors constituting each of the plurality of pixels.

However, a thin film transistor made of an oxide semiconductor material has excellent mobility characteristics and has a problem in that its reliability is deteriorated due to a large change in bias stress and a large change in threshold voltage (Vth) and a change in transmission characteristics. .

Accordingly, the inventors of the present invention have proposed a method of detecting a shift of a threshold voltage of a thin film transistor made of an oxide semiconductor material and applying a compensation voltage to compensate for a change in the threshold voltage.

The problem to be solved by the present invention is to provide a display device capable of minimizing image quality degradation of a display device due to a threshold voltage variation of a thin film transistor made of an oxide semiconductor material.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment of the present invention includes a pixel unit disposed in an active area in which an image is displayed, a detection unit for detecting whether a threshold voltage of a pixel unit is changed, and output detected from the detection unit It includes a compensation unit for receiving a value and comparing the output value with a preset reference value to generate and output a compensation voltage to compensate for a threshold voltage change, but the detection unit may be configured as an inverter. Accordingly, the display device according to the exemplary embodiment of the present invention can easily detect a change in the threshold voltage of the active region with a simple circuit configuration.

Details of other embodiments are included in the detailed description and drawings.

According to the present invention, a threshold voltage change of a thin film transistor made of an oxide semiconductor material is detected, and a threshold voltage is compensated according to the detected result, thereby reducing luminance and image quality degradation of the display device.

According to the present invention, the threshold voltage change of the thin film transistor made of the oxide semiconductor material of the active region can be easily detected by a simple circuit configuration by detecting the threshold voltage variation of the inverter only in the dummy pixel.

The present invention can be more advantageous in securing an area of a display device by forming a gate electrode of a thin film transistor made of an oxide semiconductor material in a double gate structure and applying different signals to each of the double gate electrodes.

In the present invention, the pixel electrode compensation may be directly performed by forming a gate electrode of a thin film transistor made of an oxide semiconductor material in a double gate structure, but applying a compensation voltage according to a threshold voltage change to the lower gate electrode.

The present invention can further improve device characteristics by forming a thin film transistor made of two different types of semiconductor materials on the same substrate, and having a feature that another thin film transistor complements the disadvantages of one thin film transistor.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram for describing a pixel circuit of a general display device.
3 is a waveform diagram showing a signal input to a pixel circuit of the general display device shown in FIG. 2.
4 is a circuit diagram schematically showing a configuration of a pixel in an active area and a dummy pixel in an inactive area of a display device according to an exemplary embodiment of the present invention.
5 is a cross-sectional view schematically showing a structure of a portion of a pixel circuit in an active area of a display device according to an exemplary embodiment of the present invention.
6A and 6B are circuit diagrams showing still another embodiment of the detection unit disposed in the dummy pixel in the inactive area according to an embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and the ordinary knowledge in the technical field to which the present invention pertains. It is provided to fully inform the holder of the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. When'include','have','consist of', etc. mentioned in this specification are used, other parts may be added unless'~man' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship of two parts is described as'~top','~upper','~bottom','~side', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

An element or layer being referred to as being "on" another element or layer includes all instances of another layer or other element immediately above or in between.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The same reference numerals refer to the same components throughout the specification.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each of the features of the various embodiments of the present invention may be partially or totally combined or combined with each other, and technically various interlocking and driving may be possible as those skilled in the art can fully understand, and each of the embodiments may be implemented independently of each other. It can also be implemented together in an associative relationship.

In the present invention, the thin film transistor TFT may be configured as a PMOS (PMOS) type or an NMOS (NMOS) type, and in the following embodiments, the thin film transistor is configured as an NMOS type for convenience of description. In addition, in describing a pulse type signal, a gate high voltage (VGH) state is defined as a "high state", and a gate low voltage (VGL) state is defined as a "low state."

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display device 100 according to an exemplary embodiment of the present invention includes a display panel 110, a gate driver 120, a data driver 130, and a timing controller 140.

The display panel 110 includes n gate lines GL1, …, and GLn arranged in a first direction, m data lines DL1, …, DLm arranged in a direction different from the first direction, and n gate lines. It includes (GL1, ..., GLn) and a plurality of pixels (P) electrically connected to the m data lines (DL1, ..., DLm). Accordingly, the plurality of pixels P displays an image by a driving signal or a driving voltage applied through the gate lines GL1, …, GLn and the data lines DL1, …, DLm.

The display panel 110 includes an active area (A/A) and a non-active area (N/A) adjacent to the active area (A/A).

A plurality of pixels P capable of displaying an image is disposed in the active area A/A. Each of the plurality of pixels P is provided with a light emitting unit through which light is emitted by the light emitting element and a pixel driving unit in which a plurality of driving elements for driving the light emitting element are disposed.

The light emitting device of the pixel P disposed in the active area A/A may be an organic light emitting device. In an exemplary embodiment of the present invention, it is assumed that the light emitting element of the pixel P of the display device 100 is an organic light emitting element, but is not limited thereto. That is, the present invention can be applied not only to an organic light emitting display device, but also to a quantum dot light emitting display device (QLED) or various other display devices (for example, a liquid crystal display device). More specifically, an embodiment of the present invention is an invention for compensating for a shift in the negative polarity of a threshold voltage (Vth) characteristic of a thin film transistor made of an oxide semiconductor, and thus, as an oxide semiconductor in a pixel circuit constituting the pixel P It can be applied to all of the display device including the transistor made.

The driver of the pixel P disposed in the active area A/A includes one or more switching thin film transistors, driving thin film transistors, and capacitors. At this time, one or more switching thin film transistors and driving thin film transistors may be formed of different semiconductor materials. For example, the active layer of the switching thin film transistor may be formed of a semiconductor material made of oxide, and the driving thin film transistor may be made of a semiconductor material made of low temperature polysilicon material. At this time, at least one of the one or more switching thin film transistors may have a double gate structure. In more detail, the switching thin film transistor having a double gate structure may be a thin film transistor in which threshold voltage characteristics are shifted to a negative polarity while driving the display device 100. A different signal may be applied to each gate of the switching thin film transistor having a double gate structure. The pixel driver of the pixel P disposed in the active area A/A according to an embodiment of the present invention will be described in more detail with reference to FIGS. 4 to 7B below.

The inactive area N/A is an area disposed around the active area A/A. More specifically, the inactive area N/A is an area surrounding the active area A/A adjacent to the active area A/A. The inactive area (N/A) is an area in which an image is not displayed, driving dummy pixels, signal lines for transmitting signals to pixels disposed in the active area (A/A), and pixels in the active area (A/A). A circuit portion or the like may be disposed. For example, an anti-static element, a signal pad, and a signal link line may be disposed in the non-active area N/A.

A dummy pixel DP may be further disposed in an area in which a plurality of rows in which the pixels P disposed in the active area A/A of the inactive areas N/A are arranged in the first direction X, are extended. Can be. More specifically, a dummy pixel DP may be disposed in an area of the inactive area N/A closest to the active area A/A. That is, the dummy pixel DP is disposed in the same row as the pixel P disposed in the active area A/A, but is disposed in an area adjacent to the active area A/A. Accordingly, if n rows of pixels P of the active area A/A are arranged in the first direction, n dummy pixels DP may also be disposed. Meanwhile, in FIG. 1, dummy pixels DP are disposed on both sides of the active area A/A among the inactive areas N/A, but the present invention is not limited thereto, and the active area A/A The adjacent inactive area N/A may be disposed only on one side of the active area A/A, and the upper and lower sides of the active area A/A correspond to pixel columns of the active area A/A. It can also be placed on.

Since the dummy pixel DP is disposed in the inactive area A/A, it is not used for image display, and a threshold voltage change of any one switching thin film transistor made of an oxide semiconductor material in the active area A/A is detected. The detection unit may be arranged. The detector may be formed to have an inverter structure, and the detector of the dummy pixel DP will be described in more detail with reference to FIGS. 4, 6A and 6B.

The timing controller 140 processes image data (RGB) input from the outside to be suitable for the size and resolution of the display panel 110 and supplies it to the data driver 130. The timing controller 140 receives synchronization signals SYNC input from the outside, for example, a dot clock signal DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. Use to generate a number of gate control signal (GCS) and data control signal (DCS). The timing controller 140 supplies the generated gate control signal GCS and data control signal DCS to the gate driver 120 and the data driver 130, respectively, thereby providing the gate driver 120 and the data driver 130. Control.

The timing controller 140 may compare the detection value input from the sensing driving element included in the dummy pixel DP with a preset reference value, and then control to apply a compensation voltage to the pixel P according to the comparison result. On the other hand, in an embodiment of the present invention, it has been described that the compensation unit comparing the value detected in the dummy pixel DP with a preset reference value is included in the timing controller 140, but is not limited thereto, and generates a compensation voltage. The compensation unit may be included in the gate driving unit 120.

The gate driver 120 supplies gate signals to the n gate lines GL1,..., GLn according to the gate control signal GCS supplied from the timing controller 140. Here, the gate signal includes at least one scan signal SCAN and a light emission control signal EM.

The gate driver 120 applies a compensation voltage according to the degradation of the pixel P to the lower gate of the thin film transistor having a double gate structure according to the detection signal detecting the degree of degradation of the pixel P supplied from the timing controller 140. Can apply.

The data driver 130 converts the image data RGB into a data voltage according to the data control signal DCS supplied from the timing controller 140, and converts the converted data voltage into m data lines DL1, …, DLm. Is supplied to the pixel P through.

Each pixel P of the display device 100 according to an exemplary embodiment of the present invention includes an organic light emitting element and a pixel circuit that controls driving of the organic light emitting element. The organic light emitting device is composed of an anode, a cathode, and a light emitting layer between the anode and the cathode. The pixel circuit includes a switching transistor, a driving transistor and a capacitor. More specifically, the driving transistor controls the amount of current supplied to the organic light emitting device according to the data voltage charged in the capacitor to control the amount of light emitted from the organic light emitting device, and the switching transistor scan signal SCAN supplied through the gate line GL ) To charge the data voltage (Vdata) to the capacitor.

As described above, the display device 100 according to an exemplary embodiment of the present invention has a threshold voltage of a thin film transistor made of an oxide semiconductor material among pixel circuits constituting the pixel P disposed in the active area A/A. It is an invention for compensating the threshold voltage characteristic shifted by the negative characteristic because the image quality of the display device is deteriorated by the characteristic being shifted by the negative polarity. Accordingly, before looking at the present invention in more detail, a pixel circuit disposed in a general active region is as follows.

2 is a circuit diagram for describing a pixel circuit of a general display device.

Referring to FIG. 2, a pixel circuit of a typical display device includes a driving thin film transistor DT, one or more switching thin film transistors T1, T2, T3, T4, and T5, and a capacitor Cst. At this time, the one or more switching thin film transistors T1, T2, T3, T4, and T5 and the driving thin film transistor DT may be made of different semiconductor materials. For example, at least one of the switching thin film transistors T1, T2, T3, T4, and T5 of the one or more switching thin film transistors T1, T2, T3, T4, and T5 may be made of an oxide semiconductor material. 2 may be a switching thin film transistor T2.

The driving thin film transistor DT controls the light emission current applied to the light emitting device OD by the gate-source voltage Vgs. The driving thin film transistor DT includes a gate connected to the second node N2, a source connected to the third node N3, and a drain connected to the first node N1. Specifically, the gate of the driving thin film transistor DT stores the high potential voltage VDD when the second switching thin film transistor T2 and the third switching thin film transistor T3 are turned on. When the data voltage is supplied while the second switching thin film transistor T2 is turned on, the data voltage is written to the gate of the driving thin film transistor DT by a diode-connetion method. The driving thin film transistor DT supplies driving current to the light emitting device OD by the light emission control signal EM to control light emission of the light emitting device OD according to the amount of current.

The first switching thin film transistor T1 is turned on in response to the second scan signal SCAN2 applied to the second gate line, and the data voltage provided through the data line Data is applied to the driving thin film transistor DT. It is configured to be. The first switching thin film transistor T1 includes a gate connected to the second gate line, a drain connected to the data line, and a source connected to the third node N3. Specifically, when the second scan signal SCAN2 is supplied as a high state to the gate of the first switching thin film transistor T1, the data voltage is driven from the drain of the first switching thin film transistor T1 to the driving thin film transistor DT ) Is supplied to the third node N3 which is a source node.

The second switching thin film transistor T2 is connected between the gate and the drain of the driving thin film transistor DT, that is, between the first node N1 and the second node N2. The second switching thin film transistor T2 includes a gate connected to the first gate line, a source connected to the second node N2, and a drain connected to the first node N1. Specifically, when the first scan signal SCAN1 applied through the first gate line of the second switching thin film transistor T2 is in a high state, the second switching thin film transistor T2 is turned on. As described above, when the second switching thin film transistor T2 is turned on, the second switching thin film transistor T2 removes the high potential voltage VDD of the first node N1 or the sampled voltage of the driving thin film transistor DT. It is supplied to the two nodes N2 to initialize the data voltage written to the light emitting element OD, or to write the data voltage and sample the threshold voltage of the driving thin film transistor DT. The second switching thin film transistor T2 may be made of an oxide semiconductor material.

The third switching thin film transistor T3 controls the current path between the high potential voltage VDD and the driving transistor DT in response to the second emission control signal EM2 applied through the second emission control line. The third switching thin film transistor T3 includes a gate connected to the second emission control line, a drain of the driving transistor DT, that is, a source connected to the first node N1 and a drain connected to the high potential voltage VDD. Specifically, in the third switching thin film transistor T3, when the second emission control signal EM2 is in a high state, the third switching thin film transistor T3 is turned on, and the thin film driving the high potential voltage VDD from the source It is supplied to the first node N1 which is the drain node of the transistor DT.

The fourth switching thin film transistor T4 controls the current path between the light emitting device OD and the driving transistor DT in response to the first light emission control signal EM1 applied through the first light emission control line. The fourth switching thin film transistor T4 includes a gate connected to the first emission control line, a source connected to the light emitting device OD, and a drain connected to the third node N3. Specifically, in the fourth switching thin film transistor T4, when the first emission control signal EM1 is in a high state, the fourth switching thin film transistor T4 is turned on, and the third that is the source of the driving thin film transistor DT The node N3 and the fourth node N4, which is a source node of the fourth switching TFT T4, are electrically connected. Accordingly, when the fourth switching thin film transistor T4 is turned on by the first emission control signal EM1, the voltage of the third node N3 is supplied to the fourth node N4. When the fourth switching thin film transistor T4, the driving thin film transistor DT, and the third switching thin film transistor T3 are turned on, a high potential voltage VDD is supplied to the driving thin film transistor DT, and the light emitting device OD ), the driving current is supplied, and the light emitting element OD emits light.

The fifth switching thin film transistor T5 is turned on in response to the first scan signal SCAN1 applied through the first gate line, so that the initialization voltage VINI is the fourth node N4 and the fifth node ( N5). The fifth switching thin film transistor T5 includes a gate connected to the first gate line, a drain connected to the initialization voltage line, and a source connected to the fourth node N4 and the fifth node N5 which is an anode of the light emitting device OD. do. Specifically, when the first scan signal SCAN1 is in a high state, the fifth switching thin film transistor T5 is turned on to turn on the initialization voltage VINI to the fourth node N4 and It supplies to the fifth node N5. Accordingly, when the fifth switching thin film transistor T5 is turned on by the first scan signal SCAN1, the initialization voltage VINI is supplied to the fourth node N4 and the fifth node N5 to supply the light emitting device OD. ) Can initialize the data voltage.

The capacitor Cst may be a storage capacitor Cst that stores the gate voltage and the threshold voltage Vth of the driving thin film transistor DT until the next refresh frame. Here, the capacitor Cst is disposed between the second node N2 which is the gate of the driving thin film transistor DT and the fourth node N4 that is electrically connected to the anode of the light emitting element OD. That is, the capacitor Cst is electrically connected to the second node N2 and the fourth node N4 to determine the difference between the voltage of the gate of the driving thin film transistor DT and the voltage supplied to the anode of the light emitting device OD. To save.

The light emitting element OD emits light by the light emission current supplied from the driving transistor DT. The anode of the light emitting element OD is connected to the fifth node N5, and the cathode is connected to the low potential voltage VSS.

The operation of the pixel circuit of the general display device configured as described above is as follows.

3 is a waveform diagram showing a signal input to a pixel circuit of the general display device shown in FIG. 2.

Referring to FIG. 3, data voltages are written to each pixel disposed on one horizontal line through the initialization section P1, the sampling and programming section P2, the holding section P3, and the emission section P4, and each pixel It emits light.

In the initialization period P1, the first scan signal SCAN1 rises to a high state, and the second scan signal SCAN2 maintains a low state. At the same time, the first emission control signal EM1 falls to a low state, and the second emission control signal EM2 maintains a high state. Accordingly, in the initialization period P1, the second switching thin film transistor T2, the third switching thin film transistor T3, and the fifth switching thin film transistor T5 are turned on in the pixel circuit illustrated in FIG. 2, and the first switching The thin film transistor T1 and the fourth switching thin film transistor T4 are turned off. Accordingly. In the initialization period P1, the initialization voltage VINI is supplied to the fourth node N4 through the fifth switching thin film transistor T5, and is applied to the first node N1 through the third switching thin film transistor T3. The high potential voltage VDD is supplied to the second node N2 through the second switching thin film transistor T2. That is, as the initialization voltage VINI is supplied to the fifth node N5 that is the anode of the light emitting device OD, the data voltage written to the light emitting device OD is initialized, and the gate of the driving thin film transistor DT is damaged. The above voltage (VDD) is supplied.

In the sampling and programming period P2, the first scan signal SCAN1 rises from a low state to a high state, and the second scan signal SCAN2 also rises from a high state. In the sampling and programming period P2, the second emission control signal EM2 is polled to go low, and the first emission control signal EM1 is also kept low. Accordingly, in the sampling and programming period P2, the first switching thin film transistor T1, the second switching thin film transistor T2, and the fifth switching thin film transistor T5 are turned on, and the third switching thin film transistor T3 and The fourth switching thin film transistor T4 is turned off. Accordingly, the data voltage is supplied to the third node N3 through the first switching thin film transistor T1. Further, as the second switching thin film transistor T2 is turned on, the first node N1 which is a drain node of the driving thin film transistor DT and the second node N2 that is a gate node of the driving thin film transistor DT are By being connected, the gate-source voltage Vgs of the driving thin film transistor DT is sampled as a threshold voltage Vth of the driving thin film transistor DT by a diode-connection method. In addition, as the fifth switching thin film transistor T5 is turned on, the initialization voltage VINI is supplied to the fourth node N4, and the data voltage Vdata+threshold voltage Vth-initialization is applied to the capacitor Cst. The voltage (VINI) value is stored. Accordingly, during the sampling and programming period P2, the first node N1 and the second node N2 have a data voltage Vdata+threshold voltage Vth, and the third node N3 has a data voltage Vdata. ) Value, and the fourth node N4 may have an initialization voltage VINI value.

The holding period P3 may include a first holding period P3-1 and a second holding period P3-2.

In the first holding period P3-1, the first scan signal SCAN1 and the second scan signal SCAN2 are polled to become low, and the first emission control signal EM1 and the second emission control signal EM2 are generated. Remains low. Accordingly, in the first holding period P3-1, all the switching thin film transistors T1, T2, T3, T4, and T5 are turned off. Accordingly, each of the first node N1, the second node N2, the third node N3, and the fourth node N4, which is sampled or data voltage is written during the sampling and programming period P2, is floating, The voltage at each node is maintained.

In the second holding period P3-2, the first scan signal SCAN1 and the second scan signal SCAN2 are polled to go low, and the first emission control signal EM1 rises from a low state to a high state. The second emission control signal EM2 maintains a low state. Accordingly, only the fourth switching thin film transistor T4 is turned on in the second holding period P3-2, the first switching thin film transistor T1, the second switching thin film transistor T2, and the third switching thin film transistor T3. ) And the fifth switching thin film transistor T5 are both turned off. Accordingly, the fourth switching thin film transistor T4 is turned on to connect the third node N3 and the fifth node N5, and the data voltage Vdata held at the third node N3 is the fifth node. (N5).

In the emission period P4, the first scan signal SCAN1 and the second scan signal SCAN2 are maintained in a low state, and the second emission control signal EM2 is raised to maintain a high state. In addition, the first emission control signal EM1 also maintains a high state. Accordingly, in the emission period P4, the first switching thin film transistor T1, the second switching thin film transistor T2, and the fifth switching thin film transistor T5 are turned off, and the third switching thin film transistor T3 and the fourth The switching thin film transistor T4 is turned on. In addition, the driving transistor DT is also turned on by the data voltage Vdata+threshold voltage Vth stored in the second node N2 until the second holding period P3-2 to turn on the high potential voltage VDD. A path through which the driving current flows from the line to the light emitting element OD is formed. That is, a light emission current (Ioled) flows to the light emitting device OD through the turned-on driving thin film transistor DT, the third switching thin film transistor T3 and the fourth switching thin film transistor T4 in the emission period P4.

The active layer of the second switching thin film transistor T2 of the pixel circuit of the general display device driven as described above may be made of an oxide semiconductor material, and a threshold due to a change in bias stress according to characteristics of the oxide semiconductor material is severe. The voltage Vth is shifted to the negative polarity. At this time, the second node N2, which is the source of the second switching thin film transistor T2, as described in FIG. 3, data voltage (Vdata) + threshold voltage from the sampling and programming period P2 to the holding period P3 (Vth) is a node that stores and is a node that affects the light emission of the light emitting element OD in the light emission section P4. However, when the characteristic of the threshold voltage Vth is shifted to the negative polarity according to the characteristic of the second switching thin film transistor T2, this causes a decrease in luminance of the display device, which degrades the image quality of the display device. . In particular, as illustrated in FIG. 3, it can be seen that the voltage supplied to the second node N2 in the sampling and programming period P2 is shifted to the negative polarity as the second scan signal SCAN2 is turned on. .

Accordingly, in the present invention, a configuration capable of sensing whether the threshold voltage of the second switching thin film transistor T2 of the active area A/A is changed is a dummy pixel of the inactive area N/A or the active area A By adding to the pixel circuit configuration of /A), a method of detecting a change in the threshold voltage and compensating it according to the detection result is proposed to minimize the image quality degradation of the display device. Accordingly, first, a method for detecting pixel degradation using dummy pixels and a compensation method thereof will be described in detail with reference to FIG. 4.

4 is a circuit diagram schematically showing a configuration of a pixel in an active area and a dummy pixel in an inactive area of a display device according to an exemplary embodiment of the present invention. 5 is a cross-sectional view schematically showing a structure of a portion of a pixel circuit in an active area of a display device according to an exemplary embodiment of the present invention. 6A and 6B are circuit diagrams showing still another embodiment of a detection unit disposed in a dummy pixel in an inactive area according to an embodiment of the present invention.

First, referring to FIG. 4, the display device 100 according to an exemplary embodiment of the present invention includes a pixel P disposed in the active area A/A and an inactive area adjacent to the active area A/A ( N/A) and a dummy pixel DP and a compensation unit 430.

The pixel P disposed in the active area A/A includes a pixel driver 410 and a light emitting unit 420. The pixel driver 410 disposed in the active area A/A includes one or more switching thin film transistors T1-T5, a driving thin film transistor DT, and a capacitor Cst for driving the light emitting device OD. . At this time, the active thin film transistor DT constituting the pixel P disposed in the active area A/A and the second switching thin film transistor T2 among the one or more switching thin film transistors T1-T5 The layers can be made of different semiconductor materials. In this way, in one pixel circuit, at least one of the driving thin film transistor DT and the one or more switching thin film transistors T1-T5 may be referred to as a multi-type transistor configuration.

The structures of the driving thin film transistor DT and the second switching thin film transistor T2 will be described in more detail with reference to FIG. 5 below.

Referring to FIG. 5, the pixel P disposed in the active area A/A may include a substrate SUB, a buffer layer 111, a driving thin film transistor DT, and a second thin film transistor T2. .

The substrate SUB supports various components of the display panel 100. The substrate SUB may be made of glass or a plastic material having flexibility. When the substrate SUB is made of a plastic material, it may be made of, for example, polyimide (PI).

The buffer layer 111 may be formed on the entire surface of the substrate SUB. The buffer layer 111 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. The buffer layer 111 may improve adhesion between the layers formed on the buffer layer 111 and the substrate SUB, and may serve to block alkali components, etc., from the substrate SUB. The buffer layer 111 is not an essential component, and may be omitted depending on the type and material of the substrate SUB and the structure and type of the thin film transistor.

The driving thin film transistor DT may be disposed on the buffer layer 111. The driving thin film transistor DT may include a first active layer 121, a first gate electrode 124, a first source electrode 122 and a first drain electrode 123.

The first active layer 121 of the driving thin film transistor DT may be disposed on the buffer layer 111. The first active layer 121 may include low temperature poly-silicon (LTPS). Since the polysilicon material has high mobility, low energy consumption, and high reliability, it can be applied to a gate driver and/or multiplexer (MUX) for driving thin film transistors for display elements. The first active layer 121 includes a first channel region 121a in which a channel is formed when driving the driving thin film transistor DT, a first source region 121b on both sides of the first channel region 121a, and a first drain. The region 121c may be included.

A gate insulating layer 112 may be disposed on the first active layer 121 of the driving thin film transistor DT. The first gate insulating layer 112 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. In the first gate insulating layer 112, each of the first source electrode 122 and the first drain electrode 123 of the driving thin film transistor DT is the first of the first active layer 121 of the driving thin film transistor DT. A contact hole for connecting to the source region 121b and the first drain region 121c may be included.

The first gate electrode 124 of the driving thin film transistor DT may be disposed on the first gate insulating layer 112. The first gate electrode 124 is any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) Or it may be formed of a single layer or multiple layers of these alloys. The first gate electrode 124 may be formed on the first gate insulating layer 112 to overlap the first channel region 121a of the first active layer 121 of the driving thin film transistor DT.

An interlayer insulating layer 113 may be disposed on the first gate insulating layer 112 and the first gate electrode 124. The interlayer insulating layer 113 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. A contact hole for exposing the first source region 121b and the first drain region 121c of the first active layer 121 of the driving thin film transistor DT may be formed in the interlayer insulating layer 113.

The first source electrode 122 and the first drain electrode 123 may be formed on the interlayer insulating layer 113. The first source electrode 122 and the first drain electrode 123 may be connected to the first active layer 121 through contact holes formed in the interlayer insulating layer 113 and the first gate insulating layer 112. The first source electrode 122 and the first drain electrode 123 may be formed of a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti) made of a conductive metal material, but are not limited thereto. For example, the first source electrode 122 and the first drain electrode 123 are molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), Nickel (Ni), neodymium (Nd) may be formed of a single layer or multiple layers of any one or alloys thereof.

The second switching thin film transistor T2 may be disposed on the interlayer insulating layer 113. The second switching thin film transistor T2 may have a double gate structure. More specifically, the second switching thin film transistor T2 includes a lower second gate electrode 134B, a second active layer 131, a second source electrode 132, a second drain electrode 133, and an upper second gate. An electrode 134T may be included. Meanwhile, in FIG. 5, the second switching thin film transistor T2 is described as being disposed on the interlayer insulating layer 113, but is not limited thereto. For example, the second switching thin film transistor T2 may be disposed on the isolation insulating layer 114.

The lower second gate electrode 134B of the second switching thin film transistor T2 is disposed on the interlayer insulating layer 113. The lower second gate electrode 134B of the second switching thin film transistor T2 is electrically connected to an external compensator 430 to compensate for a change in the threshold voltage characteristic of the second switching thin film transistor T2. This can be applied. The lower second gate electrode 134B of the second switching thin film transistor T2 may be formed of a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti) made of a conductive metal material, but is not limited thereto. Does not. For example, the lower second gate electrode 134B includes molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium ( Nd), or a single layer or a multi-layer made of an alloy thereof. The lower second gate electrode 134B of the second switching thin film transistor T2 may be formed in the same process as the first source electrode 122 and the first drain electrode 123 of the driving thin film transistor DT.

The separation insulating layer 114 is disposed on the lower second gate electrode 134B of the interlayer insulating layer 113, the first source electrode 122, the first drain electrode 123, and the second switching thin film transistor T2. Can be. The isolation insulating layer 114 may be disposed between the driving thin film transistor DT and the second switching thin film transistor T2 to separate the driving thin film transistor DT and the second switching thin film transistor T2. The separation insulating layer 114 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

The second active layer 131 of the second switching thin film transistor T2 may be disposed on the isolation insulating layer 114. The second active layer 131 may be made of an oxide semiconductor material. The oxide semiconductor material is a material having a larger band gap compared to the polysilicon material. Accordingly, the second active layer 131 made of the oxide semiconductor material has a low off current because the electron does not cross the band gap in the off state of the oxide semiconductor material. Accordingly, the second switching thin film transistor T2 including the active layer made of an oxide semiconductor material may be suitable for a switching transistor having a short on time and a long off time, but is not limited thereto. . That is, a transistor made of an oxide semiconductor material may be applied as a driving transistor according to the characteristics of the display device. Meanwhile, the second active layer 131 may be formed of a metal oxide, for example, Indium-Gallium-Zinc-Oxide (IGZO), Indium-Zinc-Oxide (IZO), or Indium-Gallium-Oxide (IGO).

The second gate insulating layer 116 may be disposed on the second active layer 131. The second gate insulating layer 116 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

The upper second gate electrode 134T may be disposed on the second gate insulating layer 116. The upper second gate electrode 134T includes any of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) It may be formed of a single layer or multiple layers of one or alloys thereof. The upper second gate electrode 134T may be patterned to overlap the second active layer 131 and the second gate insulating layer 114. A first scan signal SCAN1 that controls whether to switch the second switching thin film transistor T2 may be applied to the second upper second gate electrode 134T.

A protective layer 115 may be disposed on the isolation insulating layer 114, the second active layer 131, and the upper second gate electrode 134T. The protective layer 115 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

The second source electrode 132 and the second drain electrode 133 may be disposed on the protective layer 115. The second source electrode 132 and the second drain electrode 133 may be connected to the second active layer 131 through a contact hole formed in the protective layer 115.

The planarization layer 117 may be disposed on the second source electrode 132, the second drain electrode 133, and the protective layer 115. The planarization layer 117 may be made of an organic material for planarizing the upper portions of the driving thin film transistor DT and the second switching thin film transistor T2. Although not illustrated, a contact hole for exposing the second drain electrode 133 may be formed in the planarization layer 117 for electrical connection with the anode electrode of the light emitting device disposed on the planarization layer 117.

As described above, the second switching thin film transistor T2 disposed in the active area A/A of the display device 100 according to an exemplary embodiment of the present invention has a double gate structure and the lower second gate electrode 134B. By configuring the compensation voltage according to the threshold voltage change of the second switching thin film transistor T2 to be applied, the degradation of the image quality of the display device 100 according to an exemplary embodiment of the present invention can be minimized.

Meanwhile, referring to FIG. 4, the dummy pixel DP of the inactive area N/A may include a detection unit 430 configured in an inverter form. In an embodiment of the present invention, as illustrated in FIG. 4, the dummy pixel DP is shown to be composed of only an inverter, but is not limited thereto. For example, the dummy pixel DP may be configured to have a structure similar to the pixel P disposed in the active area A/A, but the dummy pixel DP may have a structure in which a light emitting unit is not disposed. Can be.

The detector 430 may detect whether the threshold voltage of the second switching thin film transistor T2 disposed in the pixel P of the active area A/A is changed. The detector 430 may be configured in the form of an inverter. In this case, the detector 430 may be provided with other types of inverters according to the shape of the driving thin film transistor DT disposed in the pixel P of the active area A/A. More specifically, when the driving thin film transistor DT disposed in the pixel P of the active area A/A has an NMOS shape, the inverter disposed in the detection unit 430 is shown in FIGS. 4 and 6A. As illustrated, it may have a form of a D inverter consisting of a combination of two NMOS transistors. On the other hand, if the driving thin film transistor DT disposed in the pixel P of the active area A/A has a PMOS shape, the inverter disposed in the detection unit 430 uses a combination of the PMOS transistor and the NMOS transistor. It may take the form of a CMOS inverter made (CMOS inverter). This is to detect a more accurate change in the threshold voltage by having a shape similar to that of the driving transistor DT and the second switching thin film transistor T2 of the pixel P disposed in the active area A/A.

First, referring to FIG. 4, since the driving transistor DT of the active area A/A has an NMOS shape, the detector 430 may have a de-inverter shape. More specifically, the detector 430 may have a form in which the first NMOS transistor M1 and the second NMOS transistor M2 are electrically connected to each other. In this case, the first NMOS transistor M1 may be referred to as a depletion type load transistor, and the second NMOS transistor M2 may be referred to as a driving transistor.

The drain of the first NMOS transistor M1 may be connected to the high potential voltage VDD, and the gate and the source may be commonly connected to the output terminal Vout.

The gate of the second NMOS transistor M2 is connected to the input terminal Vin, the drain is connected to the output terminal Vout, and the source can be connected to the low potential voltage VSS. In this case, a sweeped voltage may be applied to the input terminal Vin, and the sweeped voltage may be a gate high voltage VGH from a gate low voltage VGL.

The detector 430 having such a structure applies the high potential voltage VDD in a state in which a voltage of 0 V is applied to the input terminal Vin, that is, the second NMOS transistor M2 is turned off. When a high level high voltage is applied to the drain of the first NMOS transistor M1, a high level voltage is detected at the output terminal Vout. Sweep voltage signal for detecting the threshold voltage characteristic of the second switching thin film transistor T2 to the input terminal Vin while the high potential voltage VDD is continuously applied to the drain of the first NMOS transistor M1. When is applied to turn on the second NMOS transistor M2, most of the current flows to the low potential voltage VSS through the second NMOS transistor M2. Therefore, a voltage at a low level is detected at the output terminal Vout. That is, the output value output to the output terminal Vout may be changed according to the sweep voltage applied to the input terminal Vin while the high potential voltage VDD is fixed. The output value thus output is input to the external compensation unit 440.

The compensation unit 440 determines a threshold voltage change of the second switching thin film transistor T2 by comparing an output value output from the detection unit 430 with a preset reference value, and generates a compensation voltage Vc according to the determination result The compensation voltage is applied to the lower second gate electrode 134B of the second switching thin film transistor T2 of the active area A/A. One end of the compensation unit 440 may be connected to the detection unit 430 of the dummy pixel DP, and the other end may be electrically connected to the second switching thin film transistor T2 of the active area A/A. The compensator 440 may be referred to as a comparator, and may be, for example, an op amp.

The detection unit 430 and the compensation unit 440 are periodically driven every frame to detect a change in the threshold voltage of a corresponding pixel row in the active area A/A and generate a compensation voltage according to the detection result to generate an active area ( It may be driven to be applied to the pixel P of A/A). However, as shown in FIG. 3, when the second scan signal SCAN2 is turned on in the sampling and programming period, the threshold controller of the second switching thin film transistor T2 is shifted to the negative polarity, and thus the timing controller ( 140 may control the compensation voltage to be applied to the lower second gate electrode 134B of the second switching thin film transistor T2 of the active area A/A in response to the second scan signal SCAN2 being applied. have. On the other hand, in one embodiment of the present invention has been described that the compensation unit 440 may be disposed on the timing controller 140, but is not limited thereto and may be disposed on the gate driver 120.

In addition, when the driving thin film transistor DT of the active region A/A has an NMOS shape, the detector 430 has a de-inverter shape as illustrated in FIG. 4, but as illustrated in FIG. 6A, The first NMOS transistor M11 of the detector 430 may have a double gate structure. As described above, when the first NMOS transistor M11, which is a depletion-type transistor, has a double gate structure, a high potential voltage VDD is input to the lower gate to output faster than when the second NMOS transistor M12 is turned off. A high level voltage may be output from the terminal Vout.

Meanwhile, when the driving transistor DT of the active area A/A has a PMOS form, the detector 430 may have a CMOS inverter form, as illustrated in FIG. 6B. More specifically, when the driving transistor DT has a PMOS form, the detector 430 may have a structure in which the PMOS transistor M21 and the NMOS transistor M22 are connected to each other.

The PMOS transistor M21 has a drain connected to a high potential voltage VDD, a gate connected to an input terminal, and a source connected to an output terminal Vout.

The gate of the NMOS transistor M22 is connected to the input terminal Vin, the drain is connected to the output terminal Vout, and the source can be connected to the low potential voltage VSS. In this case, a sweeped voltage may be applied to the input terminal Vin, and the sweeped voltage may be a gate high voltage VGH from a gate low voltage VGL.

When the low level signal is input to the input terminal Vin, the detector 430 having such a structure turns on the PMOS transistor M21 so that a high level voltage is output, and the high level is input to the input terminal Vin. When the signal of is input, the NMOS transistor M22 is turned on to output a low-level voltage. The output value output as described above is input to the external compensation unit 440, and compares the preset value set in the compensation unit 440 with the output value output from the detection unit 430, and the second value of the active area A/A. By applying the compensation voltage generated by the compensation unit 440 to the switching thin film transistor T2, luminance degradation and image quality degradation of the display device 100 due to a threshold voltage change can be minimized.

A display device according to various embodiments of the present invention may be described as follows.

The display device according to an exemplary embodiment of the present invention receives an output value and a preset reference value by receiving an output value detected by a pixel unit disposed in an active area where an image is displayed, a detection unit detecting whether a pixel unit has a threshold voltage change, and an output value detected by the detection unit And a compensating unit that generates and outputs a compensating voltage compensating for a threshold voltage change, and the detector can be configured as an inverter.

According to another aspect of the present invention, the pixel unit is a light emitting device that emits light, a capacitor that stores a data voltage supplied through a data line, a driving thin film transistor that controls a light emitting current flowing through the light emitting device, and a gate line. And one or more switching thin film transistors to receive the scan signal and charge the data voltage to the capacitor.

According to another feature of the present invention, the detection unit may have a different type of inverter structure according to the shape of the driving thin film transistor.

According to another feature of the present invention, when the driving thin film transistor is an NMOS type, the detection unit may have a de-inverter structure in which two NMOS transistors are electrically connected.

According to another feature of the present invention, one of the two NMOS transistors may be a depletion type transistor.

According to another feature of the present invention, the voltage input to the inverter may be a swept gate voltage.

According to another feature of the invention, if the driving thin film transistor is a PMOS type (PMOS), the detector may have a CMOS inverter structure in which the PMOS transistor and the NMOS transistor are electrically connected.

According to another feature of the present invention, the detection unit may be included in a dummy pixel disposed in an inactive area disposed in a peripheral area of the active area.

According to another feature of the present invention, the detection unit is not displayed and is disposed in an inactive region disposed in the peripheral region of the active region, but may be disposed on an extension line of the same row in which the pixel portion is disposed.

According to another feature of the present invention, at least one of the driving thin film transistor and the one or more switching thin film transistors may have respective active layers made of different semiconductor materials.

According to another feature of the present invention, a compensation voltage applied from the compensation unit is applied to any one of the one or more switching thin film transistors, and the active layer of any one of the switching thin film transistors may be made of an oxide semiconductor material. have.

According to another feature of the present invention, any one of the switching thin film transistors has a double gate structure having an upper gate electrode and a lower gate electrode, and different signals may be applied to the upper gate electrode and the lower gate electrode.

According to another feature of the present invention, a switching signal for turning on or turning off any one of the switching thin film transistors is applied to the upper gate electrode, and the compensation unit is applied to the lower gate electrode. The compensation voltage can be applied.

The embodiments of the present invention have been described in more detail with reference to the accompanying drawings, but the present invention is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and not restrictive. The scope of protection of the present invention should be interpreted by the claims below, and all technical spirits within the equivalent range should be interpreted as being included in the scope of the present invention.

100: display device
110: display panel
120: gate driver
130: data driver
140: timing controller
410: pixel driver
420: light emitting unit
430: detection unit
440: compensation unit
P: Pixel
DP: dummy pixel
A/A: Active area
N/A: inactive area

Claims (13)

A pixel portion disposed in the active area where the image is displayed;
A detection unit detecting whether a threshold voltage of the pixel unit is changed; And
It includes; a compensation unit for receiving the output value detected by the detection unit and comparing the output value with a preset reference value to generate and output a compensation voltage compensating for the threshold voltage change.
The detection unit is composed of an inverter, a display device. The method of claim 1, wherein the pixel unit,
A light emitting element that emits light;
A capacitor that stores the data voltage supplied through the data line;
A driving thin film transistor for controlling a light emission current flowing through the light emitting element;
And one or more switching thin film transistors configured to receive the scan signal supplied through the gate line and charge the data voltage to the capacitor. According to claim 2,
The detection unit has a different type of inverter structure according to the type of the driving thin film transistor, the display device. According to claim 3,
When the driving thin film transistor is an NMOS type, the detection unit comprises a de-inverter in which two NMOS transistors are electrically connected. The method of claim 4,
The display device of one of the two NMOS transistors is a depletion type transistor. The method of claim 4,
The voltage input to the inverter is a sweeped (sweep) gate voltage, the display device. According to claim 3,
If the driving thin film transistor is a PMOS (PMOS) type, the detection unit comprises a PMOS transistor and an NMOS transistor electrically connected to a CMOS inverter. According to claim 1,
The detection unit is included in a dummy pixel disposed in an inactive area disposed in a peripheral area of the active area. According to claim 1,
The detection unit is an image not displayed and is disposed in an inactive area disposed in a peripheral area of the active area, and is disposed on an extension line of the same row in which the pixel unit is disposed. According to claim 2,
At least one of the driving thin film transistor and the one or more switching thin film transistors, wherein each active layer is made of a different semiconductor material. The method of claim 10,
A compensation voltage applied from the compensation unit is applied to any one of the one or more switching thin film transistors,
The display device of any one of the switching thin film transistors is made of an oxide semiconductor material. The method of claim 11,
Any one of the switching thin film transistors has a double gate structure having an upper gate electrode and a lower gate electrode,
A display device having different signals applied to the upper gate electrode and the lower gate electrode. The method of claim 12,
A switching signal for turning on or turning off any one of the switching thin film transistors is applied to the upper gate electrode, and a compensation voltage applied from the compensation unit is applied to the lower gate electrode. , Display device.

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