CN113366562A

CN113366562A - Pixel unit, array substrate and display terminal

Info

Publication number: CN113366562A
Application number: CN201980090107.0A
Authority: CN
Inventors: 袁泽; 王劭文; 康佳昊; 王煜闵
Original assignee: Shenzhen Royole Technologies Co Ltd
Current assignee: Shenzhen Royole Technologies Co Ltd
Priority date: 2019-07-12
Filing date: 2019-07-12
Publication date: 2021-09-07
Also published as: WO2021007694A1

Abstract

The application discloses a pixel unit (100) which comprises a driving unit (102), a compensation unit (104), a data writing unit (101) and a display unit (103). The data writing unit (101) writes image data into the driving unit (102) in accordance with a first scan signal in a data writing period (H2). The driving unit (102) supplies a driving current to the display unit (103) according to the received light emission signal and the image data in the display period (H3) to drive the display unit (103) to perform image display. The compensation unit (104) provides a compensation voltage to the driving unit (102) in advance when the image data is written into the driving unit (102) so as to compensate the voltage drift generated by the driving unit (102). The driving unit (102) comprises at least one P-type transistor, and the data writing unit (101) and the compensation unit (104) comprise at least one N-type transistor. The application further discloses an array substrate (11c) and a display terminal (10) comprising the pixel unit.

Description

Pixel unit, array substrate and display terminal

Technical Field

The invention relates to the field of display driving, in particular to a pixel unit, an array substrate and a display terminal.

Background

In the image display process of the self-luminous display panel, the scanning driving circuit is required to provide a grid scanning signal and a luminous scanning signal, and the data driving circuit is required to provide an image data signal to drive the pixel unit array arranged in the image display area to perform image display.

Each pixel unit includes therein a display unit that performs image display and a plurality of driving elements for driving the display unit, the plurality of driving elements including a thin film transistor and a capacitor. Currently, the types of the thin film transistors in the pixel units are all the same, that is, the types of the thin film transistors performing light emission of the display unit and the types of the thin film transistors performing image data writing are all the same, for example, the thin film transistors in the pixel units are all of N type or all of P type. However, when the tfts in the pixel units are all of P-type, the leakage current is large, which results in that the refresh rate cannot be reduced and the overall power consumption of the display panel is large when the pixel units perform image display, and when the tfts in the pixel units are all of N-type, the drift is likely to occur, which results in that the display luminance of the plurality of display units for the same image data is not completely the same, and thus the image data cannot be uniformly displayed.

Disclosure of Invention

To solve the foregoing problems, a pixel unit with better display effect is provided.

In an embodiment of the present application, a pixel unit is provided, which includes a driving unit, a compensation unit, a data writing unit, and a display unit. The data writing unit is electrically connected with the driving unit and used for writing image data into the driving unit according to a first scanning signal in a data writing time period. The driving unit is electrically connected with the display unit and used for providing driving current to the display unit according to the received light-emitting signal and the image data in a display time period so as to drive the display unit to execute image display, and the display time period is not completely overlapped after the data writing time period. The compensation unit is electrically connected with the driving unit and used for providing compensation voltage to the driving unit in advance when image data are written into the driving unit, and the compensation voltage is used for compensating voltage drift generated by the driving unit when the driving unit provides driving current to the display unit. Wherein the driving unit comprises at least one P-type transistor, and the data writing unit or the compensating unit comprises at least one N-type transistor.

In an embodiment of the present application, an array substrate is provided, which includes a plurality of pixel units located in a display area for performing image display.

In an embodiment of the present application, a display terminal is provided, which includes the array substrate.

Compared with the prior art, the transistors in the driving unit are all P-type thin film transistors, and one of the data writing unit or the compensating unit adopts an N-type thin film transistor instead of only adopting an N-type or P-type thin film transistor. Therefore, the whole leakage current of the pixel unit is small, the drift of the pixel unit and the drift of the display unit can be accurately inhibited, the power consumption is effectively reduced, a better display effect is achieved, and the refresh rate of different high-speed and low-speed image data can be quickly adapted to when the image data is displayed.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic side view of a display terminal according to an embodiment of the present application;

FIG. 2 is a schematic plan view of an array substrate of the display panel shown in FIG. 1;

FIG. 3 is a block diagram of a circuit of any one of the pixel units shown in FIG. 2 according to the first embodiment of the present application;

FIG. 4 is a schematic diagram of a specific circuit structure of the pixel unit shown in FIG. 3;

FIG. 5 is a timing diagram of the pixel unit shown in FIG. 4 during a frame of image display;

fig. 6 is a schematic diagram of a circuit operation state of the pixel unit shown in fig. 4 in a reset period;

FIG. 7 is a schematic diagram of the circuit operation state of the pixel unit shown in FIG. 4 during a data writing period;

FIG. 8 is a schematic diagram of a circuit operation state of the pixel unit shown in FIG. 4 during a display period;

FIG. 9 is a block circuit diagram of the pixel cell shown in FIG. 2 according to a second embodiment of the present application;

FIG. 10 is a block circuit diagram of the pixel cell shown in FIG. 2 according to a third embodiment of the present application;

FIG. 11 is a block circuit diagram of a pixel cell shown in FIG. 2 according to a fourth embodiment of the present application;

FIG. 12 is a block circuit diagram of a pixel cell shown in FIG. 2 according to a fifth embodiment of the present application;

fig. 13 is a circuit block diagram of a pixel unit shown in fig. 2 according to a sixth embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The circuit structure of the pixel unit in the display terminal and the operation process thereof are specifically described below with reference to the accompanying drawings.

Fig. 1 is a schematic side view of a display terminal 10 according to an embodiment of the present application. As shown in fig. 1, the display terminal 10 includes a display panel 11 and other components (not shown), wherein the other components include a power module, a signal processor module, a signal sensing module, and the like.

The display panel 11 includes an image display area 11a and a non-display area 11 b. The display area 11a is used for displaying images, and the non-display area 11b is disposed around the display area 11a to dispose other auxiliary components or modules, and specifically, the display panel 11 includes an array substrate 11c and an opposite substrate 11d, and a display medium layer 11e disposed between the array substrate 11c and the opposite substrate 11 d. In this embodiment, the display medium in the display medium layer is an Organic light emitting semiconductor (OLED).

Please refer to fig. 2, which is a schematic plan view of an array substrate 11c of the display panel 11 shown in fig. 1. As shown in fig. 2, the corresponding image display area 11a of the array substrate 11c includes a plurality of m × n Pixel units (pixels) P, m Data lines (Data lines) 120, n Scan driving lines (Scan lines) 130, and n light emitting driving lines (Emission lines) 140 arranged in a matrix, where m and n are natural numbers greater than 1.

The data lines 120 are insulated and arranged in parallel at intervals of a first predetermined distance along a second direction Y, the scanning driving lines 130 are insulated and arranged in parallel at intervals of a second predetermined distance along a first direction X, the light-emitting driving lines 140 are insulated and arranged in parallel at intervals of a second predetermined distance along the first direction X, the scanning lines 130, the light-emitting driving lines 140 and the data lines 120 are insulated from each other, and the first direction X is perpendicular to the second direction Y.

For convenience of description, the m data lines 120 are respectively defined as D1, D2, … …, Dm-1, Dm; the n scan driving lines 130 are respectively defined as G1, G2, … …, Gn in positional order; the n scanning light-emitting lines 140 are respectively defined as E1, E2, … …, En in order of position. Each pixel unit P is electrically connected to a scan driving line 130 extending along the first direction X, a light-emitting driving line 140 and a data line 120 extending along the second direction Y.

The display terminal 10 further includes a timing control circuit 101, a Data Driver circuit (Data Driver)102, a Scan Driver circuit (Scan Driver)103, and a light Emission Driver circuit (Emission Driver)104 for driving the pixel units to display an image, which are disposed on the array substrate 11c corresponding to the non-display region 11b of the display panel 11.

The Data driving circuit 102 is electrically connected to the Data lines 120, and is configured to transmit image Data (Data) to be displayed to the pixel units P through the Data lines 120 in the form of Data voltages.

The scan driving circuit 103 is electrically connected to the plurality of scan driving lines 130, and is configured to output a scan signal Gn through the plurality of scan driving lines 130 for controlling when the pixel unit P receives image data. The scanning drive circuit 103 sequentially outputs scanning signals G1, G2, G … …, Gn from the plurality of scanning drive lines 130 in the order of position arrangement in a scanning period from the scanning drive lines G1, G2, … ….

The light-emitting driving circuit 104 is electrically connected to the light-emitting driving lines 140, and is configured to output a light-emitting signal En through the light-emitting driving lines 140 for controlling when the pixel unit P emits light according to the received image data. The light-emitting driving circuit 104 sequentially outputs scanning signals E1, E2, … …, En from the plurality of light-emitting driving lines 140 in the order of position arrangement in a scanning period from the light-emitting driving lines E1, E2, … ….

The timing control circuit 101 is electrically connected to the Data driving circuit 102, the scan driving circuit 103 and the light emitting driving circuit 104, and is configured to control the working timings of the Data driving circuit 102, the scan driving circuit 103 and the light emitting driving circuit 104, that is, output corresponding timing control signals to the Data driving circuit 102, the scan driving circuit 103 and the light emitting driving circuit 104, so as to control when to output corresponding scan signals Gn, light emitting signals En and image Data.

In this embodiment, the circuit elements in the scan driving circuit 103 and the pixel units P in the display panel 11 are manufactured in the display panel 11 in the same process, that is, the goa (gate Driver on array) technology, and the circuit elements in the scan driving circuit 104 and the pixel units P in the display panel 11 are manufactured in the same process, that is, the eoa (emitter on array) technology.

It can be understood that the display terminal 10 further includes other auxiliary circuits for jointly completing the display of the image, such as an image receiving Processing circuit (GPU), a power circuit, and the like, which are not described in detail in this embodiment.

Please refer to fig. 3, which is a circuit block diagram of any one pixel unit 100 of the pixel units P shown in fig. 2 according to the first embodiment of the present application. As shown in fig. 3, the pixel unit 100 includes: a data writing unit 101, a driving unit 102, a display unit 103, a compensation unit 104, an auxiliary unit 105, a first reset unit 106, and a second reset unit 107. The pixel unit 100 performs a display process of one frame of image, and includes three sequential and continuous periods H1-H3, where H1 is a reset period, H2 is a data write period, and H3 is a display period.

As shown in fig. 3-4, the Data writing unit 101 is electrically connected to the driving unit 102, and is used for writing the image Data into the driving unit 102 according to the first scan signal Gn during the Data writing period H2.

The driving unit 102 is electrically connected to the display unit 103, and is configured to provide a driving current to the display unit 103 according to the received light-emitting signal En and the image data in the display time period H3, so as to drive the display unit 103 to emit light and perform image display. The display period H3 follows the data writing period H2 and does not completely overlap.

The compensation unit 104 is electrically connected to the driving unit 102, and is used for providing a compensation voltage to the driving unit 102 in advance when the image Data is written into the driving unit 102 during the Data writing period H2. The compensation voltage is used to compensate for a voltage drift generated by the driving unit 102 itself when the driving unit 102 supplies the driving current to the display unit 103.

The auxiliary unit 105 is electrically connected between the display unit 103 and the driving unit 102, and is configured to be in an electrically off state in the Data writing time period H2 under the control of the first scan signal Gn, so that the display unit 103 is electrically disconnected from the driving unit 102, and the image Data is prevented from being transmitted to the display unit 103 in the non-display stage to affect the correct image display. Meanwhile, the auxiliary unit 105 is in a conducting state in the display time period H3 under the control of the first scan signal Gn, such that the display unit 103 is electrically conducted with the driving unit 102, and the driving current is transmitted to the display unit 103.

The first reset unit 106 is electrically connected to the display unit 103, and configured to write a reset voltage into the display unit 103 in a reset time period T1 according to a reset signal, so that the display unit is in an initial display voltage state. The first reset unit 106 is used to eliminate the current and voltage remaining in the display unit 103 in the previous display stage, so as to ensure that each pixel unit 100 can accurately perform the display of the image data in each frame of image display stage.

The second reset unit 107 is electrically connected to the driving unit 102, and configured to write a reset voltage Vint into the driving unit 102 in a reset time period T1 according to a reset signal, so that the driving unit 102 is in an initial driving voltage state, and the current and the voltage remaining in the driving unit 102 in a previous display stage are eliminated, thereby ensuring that each pixel unit 100 can accurately perform display of image data in each frame of image display stage. Here, the reset period T3 precedes and does not completely overlap the data write period H2.

Specifically, please refer to fig. 4, which is a schematic circuit diagram of the pixel unit 100 shown in fig. 3. As shown in fig. 4, it should be noted that the pixel unit 100 is any one of the plurality of pixel units P in the nth row that is turned on by scanning signals output by the scanning lines Gn.

The data writing unit 101 includes a writing transistor T1, a gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, a drain of the writing transistor T1 is electrically connected to one of the data lines Dm, and a source of the writing transistor T1 is electrically connected to the first node Ns of the driving unit 102. In this embodiment, the writing Transistor T1 is a Thin Film Transistor (TFT) of an N-type Oxide, and specifically, the Thin Film Transistor of the N-type Oxide may be a zinc Oxide (ZnO) TFT, a GaZnO TFT, an InZnO TFT, an AlZnO TFT, or an indium gallium zinc Oxide TFT (InGaZnO TFT, IGZO TFT).

In other embodiments of the present application, the write Transistor T1 may also be a Thin Film Transistor (TFT) of Low Temperature Poly-silicon (LTPS) P-type.

The driving unit 102 includes a first driving transistor T2, a second driving transistor T4, and a driving capacitor Cs. The gate of the first driving transistor T2 is electrically connected to the driving node Nn, the source of the first driving transistor T2 is electrically connected to the first node Ns, and the drain of the first driving transistor T2 is electrically connected to the second node Nd. The driving capacitor Cs is electrically connected to the driving voltage terminal Vdd and the driving node Nn, respectively. The driving voltage terminal Vdd is used for providing the light emitting driving voltage ELVDD for the display unit 103, and is, for example, 4.5-7V.

The gate of the second driving transistor T4 is electrically connected to the light-emitting driving line En, the source of the second driving transistor T4 is electrically connected to the driving voltage terminal Vdd, and the drain of the second driving transistor T4 is electrically connected to the first node Ns.

In this embodiment, the first driving transistor T2 and the second driving transistor T4 are thin film transistors TFT of P-type low temperature polysilicon LTPS.

In other modified embodiment modes of the present application, the driving unit 102 includes only the first driving transistor T2 and does not include the second driving transistor T4.

The display unit 103 is an organic light emitting diode OLED, wherein an anode of the organic light emitting diode OLED is electrically connected to the display node Na, and a cathode of the organic light emitting diode OLED is electrically connected to the low reference voltage terminal ELVSS.

The compensation unit 104 includes a compensation transistor T3, wherein a gate of the compensation transistor T3 is electrically connected to the light-emitting driving line En, a source of the compensation transistor T3 is electrically connected to the driving node Nn, and a drain of the compensation transistor T3 is electrically connected to the second node Nd. In this embodiment, the compensation transistor T3 is a TFT of N-type Oxide.

The auxiliary unit 105 includes an auxiliary transistor T5, wherein a gate of the auxiliary transistor T5 is electrically connected to the first scan line Gn, a source of the auxiliary transistor T5 is electrically connected to the second node Nd, and a drain of the auxiliary transistor T5 is electrically connected to the display node Na. In this embodiment, the auxiliary transistor T5 is a P-type LTPS TFT.

The first reset unit 106 includes a first reset transistor T6, wherein a gate of the first reset transistor T6 is electrically connected to the second scan line Gn-1, a source of the first reset transistor T6 is electrically connected to the light emitting node Na, and a drain of the first reset transistor T6 is electrically connected to the reset voltage terminal Vint. The reset voltage terminal Vint provides the low reference voltage ELVSS as the reset voltage. In this embodiment, the low reference voltage ELVSS may be-1.5V-0V.

The second reset unit 107 includes a second reset transistor T7, wherein a gate of the second reset transistor T7 is electrically connected to the second scan line Gn-1, a source of the second reset transistor T7 is electrically connected to the driving node Nn, and a drain of the second reset transistor T4 is electrically connected to the reset voltage terminal Vint. The reset voltage terminal Vint provides the low reference voltage ELVSS as the reset voltage.

The second scanning line Gn-1 and the first scanning line Gn are two adjacent scanning lines, and the two scanning lines output scanning signals in two adjacent scanning periods.

In this embodiment, the first reset transistor T6 and the second reset transistor T7 are TFTs of N-type Oxide.

The transistors in the driving unit 102 and the auxiliary unit 105 are P-type TFTs, wherein the sources of the P-type TFTs can accurately receive the light emitting driving voltage ELVDD with a fixed value, so that the voltage of the sources is not affected by the display unit 103 with the electrically connected drain terminal, and meanwhile, the turn-on and turn-off of the P-type TFTs are determined by the voltage difference between the gate and the source, and when the voltage of the sources is determined and is not affected by the display unit 103, the P-type TFTs in the driving unit 102 and the auxiliary unit 105 can accurately ensure that the source-drain current is not affected by the display unit 103 by the gate voltage. Therefore, the drift of the light emitting diode OLED in the display unit 103 will not directly affect the source node voltages and the driving currents of the first and second driving transistors T2 and T4 in the driving unit 102, so that the driving current provided to the display unit 103 can be accurately and effectively prevented from being affected by the display unit 103 to generate the drift, and a better compensation effect is achieved.

The data writing unit 101, the compensation unit 104, the first reset unit 106 and the second reset unit 107 all employ N-type TFTs, and thus, the leakage current of the TFTs in the data writing unit 101, the compensation unit 104, the first reset unit 106 and the second reset unit 107 is small, which can effectively prevent the voltage and current of the first node Ns, the second node Nd, the driving node Nn and the light emitting node Na from being interfered, and obtain better protection. Meanwhile, the voltage and current protection of the node is better, so that the accurate writing and display of the image Data can be quickly dealt with, that is, the Refresh Rate (Refresh Rate) during the display of different image Data at high and low speeds can be quickly adapted, and the pixel unit 100 can be completely matched and adapted to the low power consumption mode driving mode due to the small leakage current.

Please refer to fig. 5, which is a timing diagram of the pixel unit 100 shown in fig. 4 during one frame of image display, as shown in fig. 5, a graph corresponding to En is a voltage waveform diagram of the light emitting signal En output by the light emitting driving line En, and Gn-1 and Gn are respectively waveforms of the scanning line signals output by the second scanning line Gn-1 and the first scanning line Gn; data is a waveform diagram of image Data received by the pixel unit 100 in the frame image and required to perform image display; VNn is a graph of the voltage waveform of the drive node.

Referring to fig. 5-6, fig. 6 is a schematic diagram illustrating the circuit operation state of the pixel unit 100 shown in fig. 4 during the reset period H1.

In the reset period H1, the light emission signal En is at a high level, the scan signal Gn-1 is at a high level, and the scan signal Gn is at a low level, whereby the write transistor T1 in the data write unit 101 is in an off state under the control of the scan signal Gn at the low level, the first and second drive transistors T2 and T4 in the drive unit 102 are in an off state under the control of the light emission signal En at the high level, the compensation transistor T3 in the compensation unit 104 is in an on state under the control of the light emission signal En at the high level, the auxiliary transistor T5 in the auxiliary unit 105 is in an on state under the control of the scan signal Gn at the low level, and the first and second reset transistors T6 and T7 in the first and

second reset units

106 and 107 are in an on state under the control of the scan signal Gn-1 at the high level.

Therefore, since the compensation transistor T3 is in a conducting state, the second node Nd and the driving node Nn have the same potential, and the auxiliary transistor T5 is in a conducting state, the driving capacitor Cs forms a discharging loop through the driving node Nn, the compensation transistor T3, the second node Nd, the auxiliary transistor T5 and the light emitting diode OLED, and a current flows from the driving electrical contact Nn to the low reference voltage terminal ELVSS through the compensation transistor T3, the second node Nd, the auxiliary transistor T5 and the light emitting diode OLED along with the discharging loop, during which the voltage VNn of the driving node Nn continuously decreases from the previous time along with the discharging process until the low reference voltage ELVSS is reached. Meanwhile, the first reset transistor T6 is also in a conducting state, the reset voltage provided by the reset voltage terminal Vint is output to the display node Na, a discharge loop is formed for the driving capacitor Cs through the driving node Nn, the compensation transistor T3, the second node Nd, the auxiliary transistor T5 and the light emitting diode OLED, and the voltage VNs of the display node Ns is reduced from the previous voltage retained along with the discharge process until the low reference voltage ELVSS is reached.

It is obvious that, in the reset period H1, the voltages of the driving node Nn and the display node Na in the driving unit 102 are both the reference voltage ELVSS, so that the voltages remaining on the driving node Nn and the display node Na during the image display process of the previous frame are effectively eliminated, and it is ensured that the driving node Nn and the display node Na are both at the initial low reference voltage ELVSS.

Referring to fig. 5 and 7, fig. 7 is a schematic diagram illustrating a circuit operation state of the pixel unit 100 shown in fig. 4 during a data writing period H2.

In the Data writing period H2, the light emission signal En continues to be at the high level, the scan signal Gn-1 is at the low level, the scan signal Gn jumps from the low level to the high level, and the image Data supplies the Data voltage Vdata.

Thus, the write transistor T1 in the data write unit 101 is in a turned-on state under the control of the scan signal Gn of a high level, and the data voltage Vdata is transmitted to the first node Ns through the write transistor T1.

Since the voltage VNn of the driving node Nn is the low reference voltage ELVSS, the gate of the first driving transistor T2 in the driving unit 102 is loaded with the low reference voltage ELVSS which is necessarily smaller than the source of the data voltage Vdata, so that the first driving transistor T2 is in a conducting state.

The compensation transistor T3 in the compensation unit 104 is turned on under the control of the high-level light-emitting signal En, that is, the source and the drain of the compensation transistor T3 are electrically connected, so that the gate and the drain of the first driving transistor T2 are directly electrically connected to form a diode connection, and then, at this time, the voltage VNn of the driving node Nn has a data voltage Vdata charged through the first driving transistor T2, and when the voltage VNn of the driving node Nn is charged to Vata-Vth, the first driving transistor T2 is in a cut-off state, where Vth is a threshold voltage when the second transistor T2 is turned on, the data voltage Vdata stops charging the driving node Nn, and the voltage VNn of the driving node Nn is maintained at Vata-Vth due to the non-abrupt change characteristic of the driving capacitor Cs. As can be seen, the threshold voltage Vth of the first driving transistor T2 is written to the driving node Nn together with the data voltage Vdata.

The second driving transistor T4 in the driving unit 102 is in an off state under the control of the light emission signal En of a high level, the auxiliary transistor T5 in the auxiliary unit 105 is in an off state under the control of the scan signal Gn of a high level, and the first reset transistor T6 in the first reset unit 106 and the second reset transistor T7 in the second reset unit 107 are in an off state under the control of a low level of the scan signal Gn-1.

Referring to fig. 5 and 8, fig. 8 is a schematic diagram illustrating a circuit operation state of the pixel unit 100 shown in fig. 4 during a display time period H3.

In the display period H3, the light-emitting signal En jumps from the high level to the low level, the scanning signal Gn-1 continues to be positioned at the low level, the scanning signal Gn jumps from the high level to the low level, and the image Data jumps from the Data voltage Vdata to the low level, that is, the Data signal stops being written.

Thereby, the write transistor T1 in the data write unit 101 is in an off state under the control of the scan signal Gn of a low level.

The second transistor T4 in the driving unit 102 is in a turn-on state under the control of the light emitting signal En of a low level, and thus, the voltage of the light emitting driving voltage ELVDD of the driving voltage terminal Vdd is transmitted to the first node Ns.

The gate voltage Vdata-Vth in the second transistor T2 is obviously smaller than the light emitting driving voltage ELVDD, so the second transistor T2 is in an on state.

The compensation transistor T3 in the compensation unit 104 is in an off state under the control of the light emission signal En of a low level, and the auxiliary transistor T5 in the auxiliary unit 105 is in an on state under the control of the scan signal Gn of a low level.

Thereby, the light emitting driving voltage ELVDD is further transmitted to the light emitting diode OLED in the display unit 103 through the second driving transistor T2 and the auxiliary transistor T5.

Meanwhile, the driving current transmitted to the display unit 103 through the second driving transistor T2 is: ids 1/2K (Vgs-Vth) ^2, where K μ Cox W/L, W is the width of the conduction channel of the second transistor T2, and L is the length of the conduction channel, i.e., K is a parameter related to the conduction channel size, electron mobility, etc. of the second driving transistor.

Further, Vgs is VNs-VNn ═ ELVDD- (Vdata-Vth), then Vgs-Vth ═ ELVDD- (Vdata-Vth) -Vth ═ ELVDD-Vdata + Vth-Vth ═ ELVDD-Vdata.

It is obvious that the driving current Ids for the light emitting diode OLED in the display unit 103 has no relation with the threshold voltage Vth of the first driving transistor T2, that is, the threshold voltage Vth of the first driving transistor T2 is written into the driving node Nn in advance at the data writing node, so that the threshold voltage Vth of the first driving transistor T2 is cancelled in the light emitting display phase, and then the threshold voltage Vth shift for the first driving transistor T2 is compensated and eliminated, thereby preventing the light emitting luminance of the light emitting diode OLED in the display unit 103 from being affected by the threshold voltage shift of the first driving transistor T2 and failing to reach the correct luminance.

Meanwhile, it can be ensured that the display of the display units 103 in all the pixel units P in all the display regions is not caused by the curves with inconsistent luminance generated by the different threshold voltages Vth of the first driving transistors T2 at different positions in the manufacturing process and the using process, that is, the display luminance of all the pixel units P in the display regions is ensured to be uniform and consistent without being influenced by the parameters of the first driving transistors T2.

The first reset transistor T6 in the first reset unit 106 and the second reset transistor T7 in the second reset unit 107 are in an off state under the low level control of the scan signal Gn-1.

Please refer to fig. 9, which is a circuit block diagram of the pixel unit 200 shown in fig. 2 according to a second embodiment of the present application. As shown in fig. 9, the circuit structure and the operation principle of the pixel unit 200 in this embodiment are substantially the same as those of the pixel 100 in the first embodiment, except that the pixel unit 200 does not include the first reset unit 106, that is, the pixel unit 200 only includes the data writing unit 101, the driving unit 102, the display unit 103, the compensation unit 104, the auxiliary unit 105, and the second reset unit 107.

The Data writing unit 103 is electrically connected to the driving unit 101, and is configured to write the image Data into the driving unit 101 according to the first scan signal Gn in the Data writing period H2.

The auxiliary unit 105 is electrically connected between the display units 103, and is configured to be in an electrically off state in the Data writing time period H2 under the control of the first scan signal Gn, so that the display units 103 are electrically disconnected from the driving unit 102, and the image Data is prevented from being transmitted to the display units 103 in the non-display stage to affect the correct image display. Meanwhile, the auxiliary unit 105 is in a conducting state in the display time period H3 under the control of the first scan signal Gn, such that the display unit 103 is electrically conducted with the driving unit 102, and the driving current is transmitted to the display unit 103.

The second reset unit 107 is electrically connected to the driving unit 102, and configured to write a reset voltage Vint into the driving unit 102 in a reset time period H1 according to a reset signal, so that the driving unit 102 is in an initial driving voltage state, and the current and the voltage remaining in the driving unit 102 in a previous display stage are eliminated, thereby ensuring that each pixel unit 100 can accurately perform display of image data in each frame of image display stage.

Specifically, as shown in fig. 9, the data writing unit 101 includes a writing transistor T1, a gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, a drain of the writing transistor T1 is electrically connected to one of the data lines Dm, and a source of the writing transistor T1 is electrically connected to the first node Ns of the driving unit 102. In this embodiment, the writing transistor T1 is a thin film transistor TFT of N-type Oxide.

The driving unit 102 includes a first driving transistor T2, a second driving transistor T4, and a driving capacitor Cs. The gate of the first driving transistor T2 is electrically connected to the driving node Nn, the source of the first driving transistor T2 is electrically connected to the first node Ns, and the drain of the first driving transistor T2 is electrically connected to the second node Nd. The driving capacitor Cs is electrically connected to the driving voltage terminal Vdd and the driving node Nn, respectively. The driving voltage terminal Vdd is used for providing a light emitting driving voltage ELVDD for the display unit 103, for example, 4.5-5V.

In this embodiment, the first driving Transistor T2 and the second driving Transistor T4 are Thin Film Transistors (TFTs) of Low Temperature Poly-silicon (LTPS) P-type.

The display unit 103 is an organic light emitting diode OLED, wherein an anode of the organic light emitting diode OLED is electrically connected to the display node Na, and a cathode of the organic light emitting diode OLED is electrically connected to the low reference voltage terminal Vss.

In this embodiment, the second reset transistor T7 is a TFT of N-type Oxide.

The transistors in the driving unit 102 and the auxiliary unit 105 are both P-type TFTs, so that the drift of the light emitting diode OLED in the display unit 103 does not directly affect the source node voltages of the first and second driving transistors T2 and T4 in the driving unit 102, and the driving current provided to the display unit 103 can be effectively prevented from drifting, thereby having a better compensation effect.

The data writing unit 101, the compensation unit 104, and the second reset unit 107 all use N-type TFTs, so that the leakage current of the TFTs in the data writing unit 101, the compensation unit 104, and the second reset unit 107 is small, and the voltage and current of the first node Ns, the second node Nd, and the light emitting node Na can be effectively prevented from being disturbed, thereby obtaining better protection. Meanwhile, the voltage and current protection of the node is better, so that the accurate writing and display of the image Data can be quickly dealt with, that is, the Refresh Rate (Refresh Rate) during the display of different image Data at high and low speeds can be quickly adapted, and the pixel unit 100 can be completely matched and adapted to the low power consumption mode driving mode due to the small leakage current.

The specific working timing and working process of the pixel unit 200 are substantially the same as the working timing of the pixel unit 100, except that in the reset time period H1 (fig. 5), the first reset unit 106 does not reset the display node Na to the preset voltage, and the working principle and working timing of other thin film transistors TFT in the corresponding working time period are the same, which is not described in detail in this embodiment.

In the reset period H1 (fig. 5), only the second reset unit 107 performs resetting on the drive node Nn. Specifically, the compensation transistor T3 is in a conducting state, the second node Nd and the driving node Nn have the same potential, and the auxiliary transistor T5 is in a conducting state, so the driving capacitor Cs forms a discharging loop through the driving node Nn, the compensation transistor T3, the second node Nd, the auxiliary transistor T5 and the light emitting diode OLED, and a current flows from the driving electrical contact Nn to the low reference voltage terminal ELVSS through the compensation transistor T3, the second node Nd, the auxiliary transistor T5 and the light emitting diode OLED along with the discharging loop, and during the discharging process, the voltage VNn retained from the previous time of the driving node Nn continuously decreases along with the discharging process until the low reference voltage ELVSS identical to the reset voltage is reached.

Meanwhile, for the driving capacitor Cs forming a discharge loop through the driving node Nn, the compensation transistor T3, the second node Nd, the auxiliary transistor T5, and the light emitting diode OLED, the voltage VNs of the display node Ns decreases with the discharge process from the previous retained voltage until the reset period H1 ends.

Please refer to fig. 10, which is a circuit block diagram of the pixel unit 300 shown in fig. 2 according to a third embodiment of the present application. As shown in fig. 10, the pixel unit 300 in this embodiment is substantially the same as the pixel 100 in the first embodiment in terms of circuit structure and operation principle, except that the pixel unit 300 does not include the second reset unit 107, that is, the pixel unit 200 only includes the data writing unit 101, the driving unit 102, the display unit 103, the compensation unit 104, the auxiliary unit 105, and the first reset unit 106.

The first reset unit 106 is electrically connected to the display unit 103, and configured to write a reset voltage into the display unit 103 according to a reset signal in a reset time period H1, so that the display unit is in an initial display voltage state.

Specifically, as shown in fig. 10, the data writing unit 101 includes a writing transistor T1, a gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, a drain of the writing transistor T1 is electrically connected to one of the data lines Dm, and a source of the writing transistor T1 is electrically connected to the first node Ns of the driving unit 102. In this embodiment, the writing Transistor T1 is a Thin Film Transistor (TFT) of an N-type Oxide, and specifically, the Thin Film Transistor of the N-type Oxide may be a zinc Oxide (ZnO) TFT, a GaZnO TFT, an InZnO TFT, an AlZnO TFT, or an indium gallium zinc Oxide TFT (InGaZnO TFT, IGZO TFT).

The data writing unit 101, the compensation unit 104, and the first reset unit 106 all use N-type TFTs, so that the leakage currents of the TFTs in the data writing unit 101, the compensation unit 104, and the first reset unit 106 are small, and the voltage and current of the first node Ns, the second node Nd, the driving node Nn, and the light emitting node Na can be effectively prevented from being disturbed, thereby obtaining better protection. Meanwhile, the voltage and current protection of the node is better, so that the accurate writing and display of the image Data can be quickly dealt with, that is, the Refresh Rate (Refresh Rate) during the display of different image Data at high and low speeds can be quickly adapted, and the pixel unit 100 can be completely matched and adapted to the low power consumption mode driving mode due to the small leakage current.

The specific working timing and working process of the pixel unit 300 are substantially the same as the working timing of the pixel unit 100, except that in the reset period H1 (fig. 5), the second reset unit 107 does not reset the driving node Na to the preset voltage, and the working principle and working timing of other thin film transistors TFT in the corresponding working period are the same, which is not described again in this embodiment.

In the reset period H1 (fig. 5), only the first reset unit 106 performs reset on the display node Na. Specifically, the compensation transistor T3 is turned on, the second node Nd and the driving node Nn have the same potential, and the auxiliary transistor T5 is turned on, so that the driving capacitor Cs forms a discharging loop through the driving node Nn, the compensation transistor T3, the second node Nd, the auxiliary transistor T5 and the light emitting diode OLED, and a current flows from the driving electrical contact Nn to the low reference voltage terminal ELVSS through the compensation transistor T3, the second node Nd, the auxiliary transistor T5 and the light emitting diode OLED along with the discharging loop, and during the discharging process, the voltage VNn remaining from the previous time at the driving node Nn decreases along with the discharging process until the reset period H1 ends.

Meanwhile, the first reset transistor T6 is in a conducting state, the reset voltage provided by the reset voltage terminal Vint is output to the display node Na, and for a discharge loop formed by the driving capacitor Cs through the driving node Nn, the compensation transistor T3, the second node Nd, the auxiliary transistor T5 and the light emitting diode OLED, the voltage VNs at the display node Ns is continuously reduced from the previous voltage along with the discharge process until reaching the low reference voltage ELVSS with the same reset voltage.

Please refer to fig. 11, which is a circuit block diagram of the pixel unit 400 shown in fig. 2 according to a fourth embodiment of the present application. As shown in fig. 11, the circuit structure and the operation principle of the pixel unit 400 in this embodiment are substantially the same as those of the pixel 100 in the first embodiment, except that the pixel unit 400 does not include the auxiliary unit 105, that is, the pixel unit 200 only includes the data writing unit 101, the driving unit 102, the display unit 103, the compensation unit 104, the first reset unit 106, and the second reset unit 107.

The first reset unit 106 is electrically connected to the display unit 103, and configured to write a reset voltage into the display unit 103 according to a reset signal in a reset time period H1, so that the display unit is in an initial display voltage state. The first reset unit 106 is used to eliminate the current and voltage remaining in the display unit 103 in the previous display stage, so as to ensure that each pixel unit 100 can accurately perform the display of the image data in each frame of image display stage.

The second reset unit 107 is electrically connected to the driving unit 102, and configured to write a reset voltage Vint into the driving unit 102 in a reset time period H1 according to a reset signal, so that the driving unit 102 is in an initial driving voltage state, and the current and the voltage remaining in the driving unit 102 in a previous display stage are eliminated, thereby ensuring that each pixel unit 100 can accurately perform display of image data in each frame of image display stage. Here, the reset period T3 precedes and does not completely overlap the data write period H2.

Specifically, the data writing unit 101 includes a writing transistor T1, a gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, a drain of the writing transistor T1 is electrically connected to one of the data lines Dm, and a source of the writing transistor T1 is electrically connected to the first node Ns of the driving unit 102. In this embodiment, the writing Transistor T1 is a Thin Film Transistor (TFT) of an N-type Oxide, and specifically, the Thin Film Transistor of the N-type Oxide may be a zinc Oxide (ZnO) TFT, a GaZnO TFT, an InZnO TFT, an AlZnO TFT, or an indium gallium zinc Oxide TFT (InGaZnO TFT, IGZO TFT).

The first reset unit 106 includes a first reset transistor T6, wherein a gate of the first reset transistor T6 is electrically connected to the second scan line Gn-1, a source of the first reset transistor T6 is electrically connected to the light emitting node Na, and a drain of the first reset transistor T6 is electrically connected to the reset voltage terminal Vint. The reset voltage terminal Vint provides the low reference voltage ELVSS as the reset voltage. In this embodiment, the low reference voltage ELVSS may be-1.5V-0V. In this embodiment, the light emitting node Na overlaps the second node Nd.

The transistors of the driving unit 102 are all P-type TFTs, so that the drift of the light emitting diode OLED in the display unit 103 does not directly affect the source node voltages of the first and second driving transistors T2 and T4 in the driving unit 102, and the driving current provided to the display unit 103 can be effectively prevented from drifting, thereby having a better compensation effect.

Please refer to fig. 12, which is a circuit block diagram of a pixel unit 500 shown in fig. 2 according to a fifth embodiment of the present application. As shown in fig. 12, the pixel unit 400 in this example is basically the same as the pixel 100 in the first embodiment in terms of circuit structure and operation principle, and the pixel unit 500 includes only the data writing unit 101, the driving unit 102, the display unit 103, the compensation unit 104, the auxiliary unit 105, the first reset unit 106, and the second reset unit 107. The pixel unit 100 performs a display process of one frame of image, and includes three sequential and continuous periods H1-H3, where H1 is a reset period, H2 is a data write period, and H3 is a display period. The pixel unit 500 in this embodiment is different from the pixel unit 100 in the first embodiment in that the data writing unit 101, the compensation unit 104, the first reset unit 106, and the second reset unit 107 may employ thin film transistors TFT of P-type low temperature polysilicon LTPS.

The second reset unit 107 is electrically connected to the driving unit 102, and configured to write a reset voltage into the driving unit 102 in a reset time period H1 according to a reset signal, so that the driving unit 102 is in an initial driving voltage state, and the current and the voltage remaining in the driving unit 102 in a previous display stage are eliminated, thereby ensuring that each pixel unit 100 can accurately perform display of image data in each frame of image display stage. Here, the reset period T3 precedes and does not completely overlap the data write period H2.

Specifically, the data writing unit 101 includes a writing transistor T1, a gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, a drain of the writing transistor T1 is electrically connected to one of the data lines Dm, and a source of the writing transistor T1 is electrically connected to the first node Ns of the driving unit 102.

In this embodiment, the write transistor T1 is a TFT of P-type oxide LTPS. Correspondingly, the write transistor T1 needs a low-level start signal in the data write period H2, that is, the low-level scan signal Gn which the start signal needs to be output to the scan drive line Gn.

The compensation unit 104 includes a compensation transistor T3, wherein a gate of the compensation transistor T3 is electrically connected to the light-emitting driving line En, a source of the compensation transistor T3 is electrically connected to the driving node Nn, and a drain of the compensation transistor T3 is electrically connected to the second node Nd.

In this embodiment, the compensating transistor T3 is an N-type oxide TFT, but the gate of the supplementary transistor T3 is connected to the scanning light emitting line En alone, and is not connected in parallel with the gate of the second driving transistor T4 and then connected to the scanning light emitting line En together. Thereby, the supplementary transistor T3 can control only the transition of the corresponding light emission signal En in the data writing period H2 without conflicting with the control of the second driving transistor T4.

In a modified embodiment of the present application, please refer to fig. 13, wherein fig. 13 is a circuit block diagram of the pixel unit shown in fig. 2 in the sixth embodiment of the present application, and as shown in fig. 13, the compensation transistor T3 is a P-LTPS TFT, which is used to effectively reduce the leakage current and receives a low-level enable signal, which may be a low-level light-emitting signal En, in the data writing period H2. In other embodiments of the present application, the compensation transistor T3 is two serially connected P-type LTPS TFTs (not shown) for effectively reducing the leakage current, and receives a low-level enable signal, which may be a low-level light emission signal En, in the data writing period H2.

In this embodiment, the first reset transistor T6 and the second reset transistor T7 may also be P-LTPS TFTs or N-oxide TFTs. Correspondingly, when the first reset transistor T6 and the second reset transistor T7 are TFTs of P-LTPS, the first reset transistor T6 and the second reset transistor T7 need to adopt a low-level start signal in the reset period H1, that is, the start signal needs to be a low-level scan signal Gn output by the scan driving line Gn-1.

When the TFTs in the first reset unit 106 and the second reset unit 107 are N-type oxide TFTs, the leakage current is small, so that the voltage and current of the first node Ns, the second node Nd, the driving node Nn, and the light emitting node Na can be effectively prevented from being interfered, and better protection can be obtained. Meanwhile, the voltage and current protection of the node is better, so that the accurate writing and display of the image Data can be quickly dealt with, that is, the Refresh Rate (Refresh Rate) during the display of different image Data at high and low speeds can be quickly adapted, and the pixel unit 100 can be completely matched and adapted to the low power consumption mode driving mode due to the small leakage current.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to assist in understanding the core concepts of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

A pixel cell, comprising: drive unit, compensation unit, data write unit and display element, wherein:

the data writing unit is electrically connected with the driving unit and used for writing image data into the driving unit according to a first scanning signal in a data writing time period;

the driving unit is electrically connected with the display unit and used for providing driving current to the display unit according to the received light-emitting signal and the image data in a display time period so as to drive the display unit to execute image display,

the compensation unit is electrically connected with the driving unit and is used for providing compensation voltage to the driving unit in advance when image data are written into the driving unit, and the compensation voltage is used for compensating voltage drift generated by the driving unit when the driving unit provides driving current to the display unit;

the driving unit comprises at least one P-type transistor, and the data writing unit and the compensation unit at least comprise one N-type transistor.
The pixel cell of claim 1, wherein the display periods follow the data write period and do not completely overlap.
The pixel cell of claim 2, wherein the drive cell comprises a first drive transistor, a second drive transistor, and a drive capacitor, wherein,

the grid electrode of the first driving transistor is electrically connected with a driving node, the source electrode of the first driving transistor is electrically connected with a first node, and the drain electrode of the first driving transistor is electrically connected with a second node;

the driving capacitor is respectively and electrically connected with a driving voltage end and the driving node, and the driving voltage end is used for providing a light-emitting driving voltage required by the display unit for displaying;

the gate of the second driving transistor is electrically connected to the light-emitting driving line to receive a light-emitting signal, the source of the second driving transistor is electrically connected to the driving voltage terminal, and the drain of the second driving transistor is electrically connected to the first node.
The pixel cell of claim 3, wherein the first and second driving transistors are P-type low temperature poly-Si TFTs.
The pixel unit according to claim 4, wherein the compensation unit comprises a compensation transistor, a gate of the compensation transistor is electrically connected to the light-emitting driving line, a source of the compensation transistor is electrically connected to the driving node, a drain of the compensation transistor is electrically connected to the second node, and the compensation transistor is configured to be in a conducting state under the control of the light-emitting signal during a data writing period to store the compensation voltage to the driving node.
The pixel unit according to claim 5, wherein the compensation transistor is an N-type oxide thin film transistor, and the compensation transistor receives a light emission signal of a high level output from the light emission driving line in a data writing period and is in an on state.
The pixel unit according to claim 5, wherein the compensation transistor comprises a thin film transistor of P-type low temperature polysilicon, and the compensation transistor receives a low level light emission signal output from the light emission driving line to be in an on state in a data writing period.
The pixel cell of claim 5, wherein the compensation cell comprises two series-connected P-type low temperature polysilicon thin film transistors.
The pixel unit according to claim 5, wherein the data writing unit comprises a writing transistor, a gate of the writing transistor is electrically connected to a first scan driving line, a drain of the writing transistor is electrically connected to one of the data lines for receiving image data, a source of the writing transistor is electrically connected to the first node, and the writing transistor is turned on by a scan signal output by the first scan driving line during the data writing period to write the image data into the driving node.
The pixel unit according to claim 9, wherein the writing transistor is an N-type oxide thin film transistor, and the writing transistor receives a high-level scan signal output from the first scan line and is in a turned-on state in a data writing period.
The pixel unit according to claim 9, wherein the writing transistor is a P-type low temperature polysilicon thin film transistor, and the writing transistor receives a low level scan signal output from the first scan line and is in a turned-on state during a data writing period.
The pixel unit according to claim 9, further comprising an auxiliary unit electrically connected between the driving unit and the display unit, for being in an electrically off state during the data writing period under the control of the first scan signal, so that the display unit is electrically disconnected from the driving unit; and the display unit is in a conducting state in the display time period under the control of a first scanning signal, so that the display unit is electrically conducted with the driving unit, and the driving current and the image data are transmitted to the display unit to execute image display.
The pixel unit according to claim 12, wherein the auxiliary unit comprises an auxiliary transistor, the auxiliary transistor T gate is electrically connected to the first scan line, the auxiliary transistor T source is electrically connected to the second node, the auxiliary transistor T drain is electrically connected to a display node, and the auxiliary transistor T is in a conducting state under a scan signal output from the first scan line during the display period.
The pixel unit according to claim 13, wherein the auxiliary transistor is a P-type low temperature polysilicon thin film transistor, and the auxiliary transistor receives a low level scan signal output from the first scan line and is in an on state in a display period, and receives a high level scan signal output from the first scan line and is in an off state in a data writing period.
The pixel unit according to claim 13, further comprising a first reset unit electrically connected to the display unit for writing a reset voltage to the display unit according to the reset period, so that the display unit is in an initial display voltage state, wherein the reset periods are before and not completely overlapped with the display period.
The pixel unit according to claim 13, wherein the pixel driving circuit comprises a second reset unit electrically connected to the driving unit for writing a reset voltage into the driving unit during a reset period, so that the driving unit is in an initial driving voltage state, and the reset periods are before the display period and do not completely overlap.
The pixel cell of claim 13, wherein the pixel driving circuit comprises a first reset unit and a second reset unit, wherein,

the first reset unit is electrically connected with the display unit and used for writing a reset voltage into the display unit according to the reset time period so that the display unit is in an initial display voltage state;

the second reset unit is electrically connected to the driving unit and used for writing a reset voltage into the driving unit in a reset time period so that the driving unit is in an initial driving voltage state;

the reset periods precede the display periods and do not completely overlap.
The pixel cell of claim 9, wherein the pixel drive circuit comprises a first reset unit and a second reset unit, wherein,

the first reset unit is electrically connected with the display unit and used for writing a reset voltage into the display unit in a reset time period so that the display unit is in an initial display voltage state;

the second reset unit is electrically connected to the driving unit and used for writing a reset voltage into the driving unit in a reset time period so that the driving unit is in an initial driving voltage state;

the reset periods precede the display periods and do not completely overlap.
The pixel cell of any one of claims 15-18,

the first reset unit comprises a first reset transistor, a grid electrode of the first reset transistor is electrically connected with the second scanning line, a source electrode of the first reset transistor is electrically connected with the light emitting node, a drain electrode of the first reset transistor is electrically connected with a reset voltage end, and the reset voltage provided by the reset voltage end is transmitted to the display unit when the first reset unit is in a conducting state according to the control of the scanning signal output by the second scanning line in the reset time period.
The pixel cell of claim 19, wherein the reset voltage terminal provides a low reference voltage as the reset voltage, the low reference voltage ranging from-1.5V to 0V.
The pixel unit according to claim 19, wherein the first reset transistor is a thin film transistor of an N-type oxide, and wherein a high-level scan signal output from the second scan line is on in the reset period, and a low-level scan signal output from the second scan line is off in the data write period and the display period.
The pixel unit according to claim 19, wherein the first reset transistor is a P-type low temperature polysilicon thin film transistor, and wherein a low level scan signal output from the second scan line is on during the reset period, and a high level scan signal output from the second scan line is off during the data write period and the display period.
The pixel unit according to any one of claims 15 to 18, wherein the second reset unit comprises a second reset transistor, a gate of the second reset transistor is electrically connected to a second scan line, a source of the second reset transistor is electrically connected to a driving node, a drain of the second reset transistor is electrically connected to a reset voltage terminal, and the reset voltage provided by the reset voltage terminal is transmitted to the display unit when the second reset transistor is controlled to be in a conducting state according to a scan signal output by the second scan line during the reset period.
The pixel cell of claim 23, wherein the reset voltage terminal provides a low reference voltage as the reset voltage, the low reference voltage ranging from-1.5V to 0V.
The pixel unit according to claim 24, wherein the second reset transistor is a thin film transistor of an N-type oxide, and wherein a high-level scan signal output from the second scan line is on in the reset period, and a low-level scan signal output from the second scan line is off in the data write period and the display period.
The pixel unit according to claim 24, wherein the second reset transistor is a P-type low temperature polysilicon thin film transistor, and wherein a low level scan signal output from the second scan line is turned on in the reset period, and a high level scan signal output from the second scan line is turned off in the data writing period and the display period.
An array substrate comprising a plurality of pixel cells according to any one of claims 1 to 25 in a display area for performing image display.
A display terminal comprising the array substrate of claim 27.