JP4915195B2 - Display device - Google Patents

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JP4915195B2
JP4915195B2 JP2006261720A JP2006261720A JP4915195B2 JP 4915195 B2 JP4915195 B2 JP 4915195B2 JP 2006261720 A JP2006261720 A JP 2006261720A JP 2006261720 A JP2006261720 A JP 2006261720A JP 4915195 B2 JP4915195 B2 JP 4915195B2
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signal
circuit
pixel
potential
scanning
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JP2008083272A (en
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貴央 谷亀
幸人 飯田
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ソニー株式会社
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  The present invention relates to a display device, and more particularly to a flat panel display device in which pixels including electro-optical elements are arranged in a matrix (matrix).

  In recent years, in the field of display devices that perform image display, as a light emitting element of a pixel, a so-called current-driven electro-optic element whose emission luminance changes according to a flowing current value, for example, a phenomenon that emits light when an electric field is applied to an organic thin film An organic EL display device in which pixels (pixel circuits) including the organic EL element are arranged in a matrix using the organic EL (electroluminescence) element used has been developed and commercialized.

  This organic EL display device has low power consumption because the organic EL element can be driven with an applied voltage of 10 V or less, and is a self-luminous element. Therefore, light from a light source (backlight) is emitted by a pixel including a liquid crystal cell. Compared with a liquid crystal display device that controls the strength, it has features such as high image visibility, no need for a backlight, and a high element response speed.

  In the organic EL display device, as in the liquid crystal display device, a simple (passive) matrix method and an active matrix method can be adopted as the driving method. However, although a simple matrix display device has a simple structure, there is a problem that it is difficult to realize a large and high-definition display device. Therefore, in recent years, the current flowing through the electro-optical element is controlled by an active element provided in the same pixel circuit as the electro-optical element, for example, an insulated gate field effect transistor (generally, a TFT (Thin Film Transistor)). Active matrix display devices have been actively developed.

  By the way, generally, the current-voltage (IV) characteristic of the organic EL element deteriorates (deteriorates with time) over time. In a pixel circuit using an N-channel TFT as a transistor for driving an organic EL element with current (hereinafter referred to as “driving transistor”), the organic EL element is connected to the source side of the driving transistor. When the IV characteristic of the organic EL element changes with time, the gate-source voltage Vgs of the driving transistor changes, and as a result, the emission luminance of the organic EL element also changes.

  This will be described more specifically. The source potential of the drive transistor is determined by the operating point between the drive transistor and the organic EL element. When the IV characteristic of the organic EL element deteriorates, the operating point of the driving transistor and the organic EL element fluctuates. Therefore, even if the same voltage is applied to the gate of the driving transistor, the source potential of the driving transistor changes. . As a result, the source-gate voltage Vgs of the driving transistor changes and the current value flowing through the driving transistor changes, so that the current value flowing through the organic EL element also changes. As a result, the emission luminance of the organic EL element increases. Change.

  In addition, in a pixel circuit using a polysilicon TFT, in addition to the deterioration of the IV characteristics of the organic EL element over time, the threshold voltage Vth and mobility μ of the driving transistor change over time, or due to manufacturing process variations. The threshold voltage Vth and the mobility μ are different for each pixel (individual transistor characteristics vary). When the threshold voltage Vth and mobility μ of the driving transistor are different, the current value flowing through the driving transistor varies, so even when the same voltage is applied to the gate of the driving transistor, the light emission luminance of the organic EL element changes. The uniformity of the screen is lost.

  Therefore, even if the IV characteristic of the organic EL element deteriorates with time, or the threshold voltage Vth or mobility μ of the driving transistor changes with time, the light emission luminance of the organic EL element is not affected by those effects. In order to keep the pixel circuit constant, each pixel circuit is provided with a compensation function for the characteristic variation of the organic EL element and a correction function for the variation of the threshold voltage Vth and mobility μ of the driving transistor (for example, Patent Document 1).

JP 2006-133542 A

  In the correction processing (hereinafter referred to as “threshold correction” and “mobility correction”) for the variation of the threshold voltage Vth and the mobility μ described above, the threshold correction and the mobility correction are the respective corrections determined by the timing of the pulse signal. The correction period was carried out within the period, and the threshold correction period and the mobility correction period were within the horizontal scanning time (1H).

  On the other hand, as display devices become smaller, graphics such as QVGA (Quarter Video Graphics Array) and VGA (Video Graphics Array) are used as display devices mounted on mobile devices such as mobile phones that display fine maps and characters. The demand for high-definition display devices with display standards is increasing. As the display device becomes higher in definition, the horizontal scanning time is reduced accordingly, so that it is not possible to sufficiently secure each correction time for threshold correction and mobility correction determined by the timing of the pulse signal.

  In particular, since the correction time for threshold correction requires a length of less than 1H, the horizontal scanning time is shortened so that the correction time cannot be sufficiently secured, and accordingly the threshold correction cannot be sufficiently performed. There may be a variation in emission luminance at a low gradation.

  Therefore, an object of the present invention is to provide a display device that can sufficiently perform threshold correction even when the horizontal scanning time is shortened with higher definition.

  The display device according to the present invention includes an electro-optic element, a writing transistor that samples and writes an input signal voltage, a holding capacitor that holds a signal voltage written by the writing transistor, and a signal voltage that is held in the holding capacitor. And a scanning circuit that outputs a scanning signal for selecting each pixel of the pixel array unit in a row unit, the pixel array unit including pixels including driving transistors that drive the electro-optic element based on the matrix And a driving circuit for driving to write an input signal to each pixel in a row selected by the scanning signal output from the scanning circuit, and for a threshold voltage of a drain-source current of the driving transistor A display device capable of threshold correction operation that cancels the dependence, wherein the scanning circuit includes unit circuits connected in cascade. A shift register that sequentially shifts a start pulse having a variable pulse width in synchronization with a clock pulse having a unit of 1H (H is a horizontal scanning time), and sequentially outputs a shift pulse from each of the unit circuits; An OR gate group having two inputs of a control signal that selectively takes one of a low potential and a high potential and each output signal of the unit circuit, and each input signal of the unit circuit and the OR gate group A first NAND gate group that inputs three output signals and a first enable signal that determines a correction period for the threshold correction, an inverted signal of each input signal of each unit circuit, an output signal, and a writing period of the input signal voltage A second NAND gate group that inputs three second enable signals to determine the output of the first NAND gate group and two output signals of the first and second NAND gate groups, and outputs the scanning signal. To the 3NAND and a gate group, wherein the first enable signal and said second enable signal is characterized in that occur at different 1H.

  In a scanning circuit comprising a combination of a shift register and a logic circuit of an OR gate group, first, second and third NAND gate groups, the first enable signal and the second enable signal are generated at different 1H. In addition, by changing the active period (pulse width) of the start pulse, the threshold correction period can be set a plurality of times over a plurality H determined by the active period of the start pulse. Then, by changing the polarity (low potential / high potential) of the control signal which is one input of each gate of the OR gate group, the correction period of the threshold correction is set to an odd number over a plurality of H times or an even number of times. Therefore, the correction period for threshold correction can be set finely for every 1H instead of every 1H.

  According to the present invention, since the correction period of threshold correction can be set a plurality of times over a plurality of H determined by the active period of the start pulse, even if the horizontal scanning time is shortened due to high definition, the threshold value is corrected. Since the correction can be sufficiently performed and the correction period for threshold correction can be set finely for each 1H, the optimum threshold correction time can be set in terms of the characteristics of the pixel circuit, so that the threshold correction can be performed more reliably. It is possible to suppress variations in light emission luminance with low gradation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a system configuration diagram showing an outline of the configuration of an active matrix display device according to an embodiment of the present invention, for example, an organic EL display device.

  As shown in FIG. 1, the organic EL display device 10 according to this embodiment includes a pixel array unit 30 in which pixels (PXLC) 20 are two-dimensionally arranged in a matrix (matrix shape), and the pixel array unit 30. It is arranged in the periphery and has a drive unit that drives each pixel 20, that is, a write scanning circuit 40, a power supply scanning circuit 50, and a horizontal driving circuit 60.

  The pixel array unit 30 is provided with scanning lines 31-1 to 31-m and power supply lines 32-1 to 32-m for each pixel row with respect to a pixel array of m rows and n columns. The signal lines 33-1 to 33-n are wired.

  The pixel array unit 30 is usually formed on a transparent insulating substrate such as a glass substrate, and has a flat (flat) panel structure. Each pixel 20 of the pixel array unit 30 can be formed using an amorphous silicon TFT (Thin Film Transistor) or a low-temperature polysilicon TFT. When the low-temperature polysilicon TFT is used, the scanning circuit 40, the power supply scanning circuit 50, and the horizontal driving circuit 60 can also be mounted on the panel (substrate) on which the pixel array unit 30 is formed.

  The writing scanning circuit 40 is configured by a shift register or the like, and sequentially supplies the scanning signals WSL1 to WSLm to the scanning lines 31-1 to 31-m to scan the pixels 20 line-sequentially in units of rows. The power supply scanning circuit 50 is configured by a shift register or the like, and is synchronized with the line sequential scanning by the write scanning circuit 40 to the power supply lines 32-1 to 32-m at the first potential Vcc_H and a lower second potential Vcc_L. The power supply line potentials DSL1 to DSLm that are switched at are supplied. The horizontal drive circuit 60 appropriately supplies the signal potential Vsig and the reference potential Vo of the video signal corresponding to the luminance information to the signal lines 33-1 to 33-n. Here, the second potential Vcc_L is a potential sufficiently lower than the reference potential Vo.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating a specific configuration example of the pixel (pixel circuit) 20. As shown in FIG. 2, the pixel 20 has a current-driven electro-optical element, for example, an organic EL element 31 whose light emission luminance changes according to a current value flowing through the device, as the light-emitting element. In addition, the driving transistor 22, the writing transistor 23, and the storage capacitor 24 are included.

  Here, N-channel TFTs are used as the drive transistor 22 and the write transistor 23. However, the combination of the conductivity types of the driving transistor 22 and the writing transistor 23 here is only an example, and is not limited to these combinations.

  The organic EL element 21 has a cathode electrode connected to a common power supply line 35 that is wired in common to all the pixels 20. The drive transistor 22 has a source connected to the anode electrode of the organic EL element 21 and a drain connected to the power supply line 32 (32-1 to 32-m). The writing transistor 23 has a gate connected to the scanning line 31 (31-1 to 31-m), a source connected to the signal line 33 (33-1 to 33-n), and a drain connected to the gate of the driving transistor 22. Has been. The storage capacitor 24 has one end connected to the gate of the drive transistor 22 and the other end connected to the source of the drive transistor 22 (the anode electrode of the organic EL element 21).

  In the pixel 20 having such a configuration, the writing transistor 23 is supplied from the horizontal driving circuit 60 through the signal line 33 by being turned on in response to the scanning signal WSL applied to the gate from the writing scanning circuit 40 through the scanning line 31. The signal potential Vsig of the video signal to be sampled is sampled and written into the pixel 20. The written signal potential Vsig is held in the holding capacitor 24.

  When the power supply line potential DSL is at the first potential Vcc_H, the drive transistor 22 is supplied with current from the power supply line 32 and applies a drive current corresponding to the signal potential Vsig held in the holding capacitor 24 to the organic EL element. By supplying to 21, the organic EL element 21 is driven by current.

(Threshold correction function)
Here, the power supply scanning circuit 50 has the power supply line potential while the horizontal driving circuit 60 supplies the reference potential Vo to the signal lines 33 (33-1 to 33-n) after the writing transistor 23 is turned on. DSL is switched between the first potential Vcc_H and the second potential Vcc_L. By switching the power supply line potential DSL, a voltage corresponding to the threshold voltage Vth of the drive transistor 22 is held in the holding capacitor 24.

  The voltage corresponding to the threshold voltage Vth of the driving transistor 22 is held in the holding capacitor 24 for the following reason. Due to variations in the manufacturing process of the drive transistor 22 and changes over time, transistor characteristics such as the threshold voltage Vth and mobility μ of the drive transistor 22 vary for each pixel. Due to this variation in transistor characteristics, even if the same gate potential is applied to the driving transistor 22, the drain-source current (driving current) Ids varies from pixel to pixel, resulting in variations in light emission luminance. In order to cancel (correct) the influence of the variation in threshold voltage Vth for each pixel, a voltage corresponding to the threshold voltage Vth is held in the holding capacitor 24.

  The threshold voltage Vth of the driving transistor 22 is corrected as follows. That is, by holding the threshold voltage Vth in the storage capacitor 24 in advance, the threshold voltage Vth of the drive transistor 22 becomes the threshold voltage Vth held in the storage capacitor 24 when the drive transistor 22 is driven by the signal voltage Vsig. The threshold voltage Vth is corrected, which cancels out the corresponding voltage, in other words.

  This is the threshold correction function. With this threshold correction function, even if the threshold voltage Vth varies or changes with time for each pixel, the light emission luminance of the organic EL element 21 can be kept constant without being influenced by the threshold voltage Vth. The principle of threshold correction will be described in detail later.

(Mobility correction function)
The pixel 20 shown in FIG. 2 has a mobility correction function in addition to the threshold correction function described above. That is, the scanning signal WSL (WSL <b> 1 to WSL <b> 1) output from the writing scanning circuit 40 during the period in which the horizontal driving circuit 60 supplies the signal potential Vsig of the video signal to the signal lines 33 (33-1 to 33-n). Dependence on the mobility μ of the drain-source current Ids of the drive transistor 22 when the signal potential Vsig is held in the storage capacitor 24 in the period in which the write transistor 23 is turned on in response to WSLm), that is, the mobility correction period. Mobility correction is performed to cancel the sex. The specific principle and operation of this mobility correction will be described later.

(Bootstrap function)
The pixel 20 shown in FIG. 2 further has a bootstrap function. That is, the horizontal driving circuit 60 cancels the supply of the scanning signals WSL (WSL1 to WSLm) to the scanning lines 31 (31-1 to 31-m) when the signal potential Vsig is held in the holding capacitor 24, and the writing transistor 23 is made non-conductive, and the gate of the drive transistor 22 is electrically disconnected from the signal line 33 (33-1 to 33-n). Thereby, since the gate potential Vg is interlocked with the fluctuation of the source potential Vs of the drive transistor 22, the gate-source voltage Vgs of the drive transistor 22 can be kept constant.

(Circuit operation)
Next, the circuit operation of the organic EL display device 10 according to the present embodiment will be described with reference to the operation explanatory diagrams of FIGS. 4 and 5 based on the timing chart of FIG. In the operation explanatory diagrams of FIGS. 4 and 5, the write transistor 23 is illustrated by a switch symbol for simplification of the drawing. Further, since the organic EL element 21 has a parasitic capacitance, the parasitic capacitance Cel is also illustrated.

  In the timing chart of FIG. 3, the time axis is shared, and the change of the scanning line potential WSL, the change of the power supply line potential DSL, the change of the gate potential Vg and the source potential Vs of the driving transistor 22 in 1H (horizontal scanning time) are shown. ing.

<Light emission period>
In the timing chart of FIG. 3, before the time t1, the organic EL element 21 is in a light emission state (light emission period). During this light emission period, the potential of the power supply line 32 is at the high potential Vcc_H (first potential), and as shown in FIG. 4A, a drive current (from the power supply line 32 to the organic EL element 21 through the drive transistor 22) Since the drain-source current (Ids) is supplied, the organic EL element 21 emits light with luminance corresponding to the drive current Ids.

<Threshold correction preparation period>
At time t1, a new field of line sequential scanning is entered, and the power supply line potential DSL is sufficiently higher than the reference potential Vo of the signal line 33 from the high potential Vcc_H (first potential) as shown in FIG. When transitioning to the low potential Vcc_L (second potential), the source potential Vs of the drive transistor 22 also starts to decrease toward the low potential Vcc_L.

  Next, at time t2, the scanning signal WSL is output from the writing scanning circuit 40, and the scanning line potential WSL shifts to the high potential side, so that the writing transistor 23 is turned on as illustrated in FIG. . At this time, since the reference potential Vo is supplied from the horizontal drive circuit 60 to the signal line 33, the gate potential Vg of the drive transistor 22 becomes the reference potential Vo. The source potential Vs of the drive transistor 22 is at a potential Vcc_L that is sufficiently lower than the reference potential Vo.

  Here, the low potential Vcc_L (second potential) is set so that the gate-source voltage Vgs of the drive transistor 22 is larger than the threshold voltage Vth of the drive transistor 22. As described above, the gate voltage Vg of the drive transistor 22 is initialized to the reference potential Vo and the source potential Vs is initialized to the low potential Vcc_L, whereby the preparation for the threshold voltage correction operation is completed.

<Threshold correction period>
Next, at time t3, as illustrated in FIG. 4D, when the power supply line potential DSL is switched from the low potential Vcc_L to the high potential Vcc_H, the source potential Vs of the driving transistor 22 starts to increase. Eventually, the gate-source voltage Vgs of the drive transistor 22 becomes the threshold voltage Vth of the drive transistor 22, and a voltage corresponding to the threshold voltage Vth is written into the storage capacitor 24.

  Here, for convenience, a period during which a voltage corresponding to the threshold voltage Vth is written to the storage capacitor 24 is referred to as a threshold correction period. In this threshold correction period, the common power supply line 35 is set so that the organic EL element 21 is cut off in order to prevent the current from flowing exclusively to the storage capacitor 24 and not to the organic EL element 21. The potential of is set in advance.

  Next, at time t4, the scanning line potential WSL shifts to the low potential side, so that the writing transistor 23 is turned off as illustrated in FIG. At this time, the gate of the driving transistor 22 is in a floating state, but the driving transistor 22 is in a cutoff state because the gate-source voltage Vgs is equal to the threshold voltage Vth of the driving transistor 22. Therefore, the drain-source current Ids does not flow.

<Writing period / mobility correction period>
Next, at time t5, as shown in FIG. 5B, the potential of the signal line 33 is switched from the reference potential Vo to the signal potential Vsig of the video signal. Subsequently, at time t6, the scanning line potential WSL transitions to the high potential side, so that the writing transistor 23 is turned on and the signal potential Vsig of the video signal is sampled as illustrated in FIG.

  By sampling the signal potential Vsig by the writing transistor 23, the gate potential Vg of the driving transistor 22 becomes the signal potential Vsig. At this time, since the organic EL element 21 is initially in a cut-off state (high impedance state), the drain-source current Ids of the drive transistor 22 flows into the parasitic capacitance Cel of the organic EL element 21, and thus the parasitic capacitance Cel is charged. Is started.

  As the parasitic capacitance Cel of the organic EL element 21 is charged, the source potential Vs of the drive transistor 22 starts to rise, and the gate-source voltage Vgs of the drive transistor 22 eventually becomes Vsig + Vth−ΔV. That is, the increase ΔV of the source potential Vs is subtracted from the voltage (Vsig + Vth) held in the holding capacitor 24, in other words, acts to discharge the charged charge of the holding capacitor 24, and negative feedback is applied. It will be. Therefore, the increase ΔV of the source potential Vs becomes a feedback amount of negative feedback.

  As described above, the drain-source current Ids flowing through the drive transistor 22 is negatively fed back to the gate input of the drive transistor 22, that is, the gate-source voltage Vgs, so that the drain-source current Ids of the drive transistor 22 is reduced. Mobility correction is performed to cancel the dependence on the mobility μ, that is, to correct the variation of the mobility μ for each pixel.

  More specifically, since the drain-source current Ids increases as the signal potential Vsig of the video signal increases, the absolute value of the feedback amount (correction amount) ΔV of negative feedback also increases. Therefore, mobility correction according to the light emission luminance level can be performed. When the signal potential Vsig of the video signal is constant, the absolute value of the feedback amount ΔV of the negative feedback increases as the mobility μ of the driving transistor 22 increases. Therefore, variation in the mobility μ for each pixel is removed. Can do.

<Light emission period>
Next, at time t7, the scanning line potential WSL shifts to the low potential side, whereby the writing transistor 23 is turned off as illustrated in FIG. As a result, the gate of the drive transistor 22 is disconnected from the signal line 33. At the same time, the drain-source current Ids starts to flow through the organic EL element 21, whereby the anode potential of the organic EL element 21 rises according to the drain-source current Ids.

  The increase in the anode potential of the organic EL element 21 is nothing but the increase in the source potential Vs of the drive transistor 22. When the source potential Vs of the drive transistor 22 rises, the gate potential Vg of the drive transistor 22 also rises in conjunction with the bootstrap operation of the storage capacitor 24. At this time, the increase amount of the gate potential Vg is equal to the increase amount of the source potential Vs. Therefore, the gate-source voltage Vgs of the drive transistor 22 is kept constant at Vin + Vth−ΔV during the light emission period.

(Principle of threshold correction)
Here, the principle of threshold correction of the drive transistor 22 will be described. The drive transistor 22 operates as a constant current source because it is designed to operate in the saturation region. Accordingly, a constant drain-source current (drive current) Ids given by the following equation (2) is supplied from the drive transistor 22 to the organic EL element 21.
Ids = (1/2) · μ (W / L) Cox (Vgs−Vth) 2 (2)
Here, W is the channel width of the drive transistor 22, L is the channel length, and Cox is the gate capacitance per unit area.

  FIG. 6 shows the characteristics of the drain-source current Ids of the drive transistor 22 versus the gate-source voltage Vgs. As shown in this characteristic diagram, if correction for variation in the threshold voltage Vth of the drive transistor 22 is not performed, when the threshold voltage Vth is Vth1, the drain-source current Ids corresponding to the gate-source voltage Vgs becomes Ids1. On the other hand, when the threshold voltage Vth is Vth2 (Vth2> Vth1), the drain-source current Ids corresponding to the same gate-source voltage Vgs is Ids2 (Ids2 <Ids). That is, when the threshold voltage Vth of the drive transistor 22 varies, the drain-source current Ids varies even if the gate-source voltage Vgs is constant.

On the other hand, in the pixel (pixel circuit) 20 having the above configuration, as described above, the gate-source voltage Vgs of the driving transistor 22 at the time of light emission is Vin + Vth−ΔV. When substituted, the drain-source current Ids is
Ids = (1/2) · μ (W / L) Cox (Vin−ΔV) 2 (3)
It is represented by

  That is, the term of the threshold voltage Vth of the drive transistor 22 is canceled, and the drain-source current Ids supplied from the drive transistor 22 to the organic EL element 21 does not depend on the threshold voltage Vth of the drive transistor 22. As a result, the drain-source current Ids does not vary even if the threshold voltage Vth of the drive transistor 22 varies for each pixel due to variations in the manufacturing process of the drive transistor 22 and changes over time. The emission brightness does not change.

(Principle of mobility correction)
Next, the principle of mobility correction of the drive transistor 22 will be described. FIG. 7 shows a characteristic curve in a state where a pixel A having a relatively high mobility μ of the drive transistor 22 and a pixel B having a relatively low mobility μ of the drive transistor 22 are compared. When the driving transistor 22 is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels like the pixel A and the pixel B.

  In a state where the mobility μ varies between the pixel A and the pixel B, for example, when the input signal potential Vsig of the same level is written to both the pixels A and B, the mobility μ is not corrected. A large difference is generated between the drain-source current Ids1 ′ flowing in the pixel A having a large value and the drain-source current Ids2 ′ flowing in the pixel B having the small mobility μ. Thus, if a large difference occurs between the pixels in the drain-source current Ids due to the variation in the mobility μ, the uniformity of the screen is impaired.

  Here, as is clear from the transistor characteristic equation of Equation (1), the drain-source current Ids increases when the mobility μ is large. Therefore, the feedback amount ΔV in the negative feedback increases as the mobility μ increases. As shown in FIG. 7, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel V having a low mobility. Therefore, by negatively feeding back the drain-source current Ids of the drive transistor 22 to the input signal voltage Vsig side by the mobility correction operation, the larger the mobility μ, the more negative feedback is applied. Can be suppressed.

  Specifically, when the feedback amount ΔV1 is corrected in the pixel A having a high mobility μ, the drain-source current Ids greatly decreases from Ids1 ′ to Ids1. On the other hand, since the feedback amount ΔV2 of the pixel B having a low mobility μ is small, the drain-source current Ids decreases from Ids2 ′ to Ids2, and does not decrease that much. As a result, since the drain-source current Ids1 of the pixel A and the drain-source current Ids2 of the pixel 2 are substantially equal, the variation in the mobility μ is corrected.

  In summary, when there are a pixel A and a pixel B having different mobility μ, the feedback amount ΔV1 of the pixel A having a high mobility μ is smaller than the feedback amount ΔV2 of the pixel B having a low mobility μ. That is, the larger the mobility μ, the larger the feedback amount ΔV, and the larger the amount of decrease in the drain-source current Ids. That is, by negatively feeding back the drain-source current Ids of the drive transistor 22 to the input signal voltage Vsig side, the current value of the drain-source current Ids of the pixels having different mobility μ is made uniform. Variation in degree μ can be corrected.

[Write scanning circuit]
Here, consider the scanning line potential (gate potential of the writing transistor 23) WSL and the power supply line potential (drain potential of the driving transistor 22) DSL that determine the threshold correction period. As is apparent from the timing chart of FIG. 3, the threshold correction period is from timing t3 when the power supply line potential DSL transitions from the low potential Vcc_L to the high potential Vcc_H to timing t4 when the scanning line potential WSL transitions from the high potential to the low potential. It becomes the period.

  As shown in the timing chart of FIG. 3, the scanning line potential WSL determines a threshold correction period, and also determines a writing period (also a mobility correction period) in which the signal potential Vsig of the video signal is written.

  Here, as the threshold correction period, it is necessary to set a time sufficiently longer than the writing period in order to reliably hold the voltage corresponding to the threshold voltage Vth of the drive transistor 22 in the storage capacitor 24. In other words, the scanning line potential WSL is a scanning signal (scanning pulse) WSL in which a pulse for determining a threshold correction period and a pulse having a narrower pulse width and a writing period are continuous in a period of 1H, and writing scanning. Output from the circuit 40.

(General circuit example)
FIG. 8 is a block diagram showing a circuit example of a general write scanning circuit 40A. FIG. 9 is a timing chart for explaining the circuit operation of the write scanning circuit 40A.

  The write scanning circuit 40A includes a shift register 41 in which unit circuits (cells) 41-1, 41-2,..., Such as flip-flops, are cascade-connected by the number of stages corresponding to the number of rows m of the pixel array section 30; An OR gate group 42 composed of a number of 2-input OR gates 42-1, 42-2,... Corresponding to a number m, and a number of 3-input NAND gates 43-1, 43-2, corresponding to the number m of rows. .., And an inverter group 44 including a number of inverters 44-1, 44-2,... Corresponding to the number of rows m.

  When the start pulse WSST is input, the shift register 41 sequentially outputs the start pulse WSST in synchronization with the clock pulse WSCK having a duty ratio of 50% (pulse width is 1H) in a 2H cycle in units of 1H. The shift pulse B (B (1), B (2),...) Is sequentially output from each of the unit circuits 41-1, 41-2,. The pulse width of the start pulse WSST is 2H that is a unit of operation of the shift register 41.

  Each of the OR gates 42-1, 42-2,... Of the OR gate group 42 has the same cycle as the clock pulse WSCK, and the same period as the enable pulse WSEN1 that determines the threshold correction period according to its own pulse width, and the clock pulse WSCK. An enable pulse WSEN2 that determines a writing period (mobility correction period) based on its own pulse width is input as two inputs. The enable pulse WSEN2 rises (becomes active) during the inactive (low potential) period of the enable pulse WSEN1.

  The NAND gates 43-1, 43-2,... Of the NAND gate group 43 are connected to the inputs A (A (1), A (2),. ), The outputs B (B (1), B (2),...) Of the unit circuits 41-1, 41-2,... Of the shift register 41, and the OR gates 42-1, 42-2,. The output is 3 inputs. The outputs of the NAND gates 43-1, 43-2,... Are inverted in polarity by the inverters 44-1, 44-2,..., And are scanned as scanning pulses WSL1, WSL2,. Applied to 31-1, 31-2,.

  The write scanning circuit 40A having the above-described configuration has an advantage that the circuit configuration is simple and the circuit area is small, but has the following problems. That is, as apparent from the timing chart of FIG. 9, since the enable pulse WSEN1 that determines the threshold correction period and the enable pulse WSEN2 that determines the write period are active within the same 1H, high definition is achieved. Accordingly, in order to secure the threshold correction period over a plurality of H as the horizontal scanning time becomes shorter, if the pulse width of the start pulse WSST is increased from 2H to 4H, 6H,..., It corresponds to the threshold correction period. Thus, the writing period also occurs over a plurality of H, and a normal writing operation cannot be performed.

(Circuit example according to the present invention)
FIG. 10 is a block diagram showing a circuit example of the write scanning circuit 40B according to the present invention. 11, FIG. 12, FIG. 13 and FIG. 14 are timing charts for explaining the circuit operation of the write scanning circuit 40B.

  In addition to the shift register 41, the write scanning circuit 40B is formed by connecting unit circuits (cells) 41-1, 41-2,..., Such as flip-flops, in cascade corresponding to the number of rows m of the pixel array section 30. , An OR gate group 45 composed of a number of 2-input OR gates 45-1, 45-2,... Corresponding to the number of rows m, and a number of 3-input NAND gates 46-1, 46- corresponding to the number of rows m. 2, a NAND gate group 46 consisting of a number of inverters 47-1, 47-2,... Corresponding to the number of rows m, and a 3-input NAND gate 48 corresponding to the number of rows m. .., 48-2,..., And a NAND gate group 49 composed of two-input NAND gates 49-1, 49-2,. ing.

  When the start pulse WSST is input, the shift register 41 sequentially outputs the start pulse WSST in synchronization with the clock pulse WSCK having a duty ratio of 50% (pulse width is 1H) in a 2H cycle in units of 1H. The shift pulse B (B (1), B (2),...) Is sequentially output from each of the unit circuits 41-1, 41-2,. The start pulse WSST has a variable pulse width and can take a pulse width that is an integral multiple of 2H.

  Each of the OR gates 45-1, 45-2,... Of the OR gate group 45 has outputs B (B (1), B (2),. ) And a control signal VTH that selectively takes one of a high potential (H) and a low potential (L) are two inputs. The operation of the control signal VTH will be described later in detail.

  The NAND gates 46-1, 46-2,... Of the NAND gate group 46 are connected to the inputs A (A (1), A (2),. , And the outputs of the OR gates 45-1, 45-2,... And an enable pulse WSEN1 that determines the threshold correction period according to its own pulse width in the same cycle as the clock pulse WSCK. The inverters 47-1, 47-2,... Of the inverter group 47 are connected to the inputs A (A (1), A (2),...) Of the unit circuits 41-1, 41-2,. Invert the polarity.

  The NAND gates 48-1, 48-2,... Of the NAND gate group 48 are unit circuits 41-1, 41-2,... Of the shift register 41 whose polarity is inverted by inverters 47-1, 47-2,. , And an enable pulse WSEN2 that determines the writing period (mobility correction period) according to its own pulse width in the same cycle as the clock pulse WSCK, and the shift register 41, and the input signal A (A (1), A (2),. The output B (B (1), B (2),...) Of the unit circuits 41-1, 41-2,.

  Here, as is apparent from the timing charts of FIGS. 11 to 14, the enable pulse WSEN <b> 1 and the enable pulse WSEN <b> 2 are timing relationships that become active (high potential) within different 1H, specifically within adjacent 1H. 9 is different from the circuit example shown in FIG. 9 in which the enable pulse WSEN1 and the enable pulse WSEN2 have a timing relationship that becomes active within the same 1H.

  The NAND gates 49-1, 49-2,... Of the NAND gate group 49 have outputs of the NAND gates 46-1, 46-2,... And outputs of the NAND gates 48-1, 48-2,. Are two inputs. The outputs of the NAND gates 49-1, 49-2,... Are applied to the scanning lines 31-1, 31-2,.

  In the write scanning circuit 40B configured as described above, the NAND gates 46-1, 46-2,... Of the NAND gate group 46 are connected to the inputs A (A (A ( 1), A (2),..., The outputs of the OR gates 45-1, 45-2,... And the enable pulse WSEN1 are made into three inputs, whereby NAND gates 45-1, 45-2,. .., When the control signal VTH is at a low potential (L), each input A (A (1), A (2),...) Of the unit circuits 41-1, 41-2,. The enable pulse WSEN1 is inverted in polarity during the period in which the outputs B (B (1), B (2),...) Are both active (high potential) and sequentially output.

  When the pulse width (active period) of the start pulse WSST is 2H, which is the reference for the operation of the shift register 41, as shown in the timing chart of FIG. 11, the unit circuits 41-1 and 41- of the shift register 41 are used. The period during which both the inputs A (A (1), A (2),...) And the outputs B (B (1), B (2),...) Are active is 1H. Then, one enable pulse WSEN1 whose polarity is inverted is output.

  As shown in the timing chart of FIG. 12, when the pulse width of the start pulse WSST is 4H, which is twice 2H, each input A (A (A ( 1), A (2),... And each output B (B (1), B (2),...) Are both active for 3H, so that the polarity-inverted enable pulse WSEN1 is 3H. 3 are output over the period. Thereafter, by expanding the pulse width of the start pulse WSST to 6H, 8H,..., The polarity-inverted enable pulses WSEN1 are output as 5, 7,.

  On the other hand, when the control signal VTH is at a high potential (H), the inputs A (A (1), A (2),...) Of the unit circuits 41-1, 41-2,. In this period, the enable pulse WSEN1 is inverted in polarity and sequentially output. When the pulse width of the start pulse WSST is 2H, the inputs A (A (1), A (2),...) Of the unit circuits 41-1, 41-2,. Since the period is 2H, two enable pulses WSEN1 whose polarity is inverted are output over 2H.

  As shown in the timing chart of FIG. 14, when the pulse width of the start pulse WSST is 4H, which is twice 2H, each input A (A (A ( Since the period during which 1), A (2),...) Is active is 4H, four enable pulses WSEN1 whose polarity is inverted are output over 4H. Thereafter, by expanding the pulse width of the start pulse WSST to 6H, 8H,..., The polarity-inverted enable pulses WSEN1 are output as 6, 8,.

  Further, the NAND gates 48-1, 48-2,... Of the NAND gate group 48 are unit circuits 41-1, 41-2, 41-2 of the shift register 41 in which the polarity is inverted by the inverters 47-1, 47-2,. ..., each input A (A (1), A (2), ...), the enable pulse WSEN2, and each output B (B (1), ...) of the unit circuits 41-1, 41-2, ... of the shift register 41. B (2),..., 3 inputs, the NAND gates 48-1, 48-2,. A (1), A (2),...) Become inactive (low potential), and the polarity of the enable pulse WSEN2 is inverted during the period when each output B (B (1), B (2),...) Is active. Are output sequentially.

  As a result, each of the NAND gates 49-1, 49-2,... Of the NAND gate group 49 has a unit circuit 41-1, 41-2, 41-2 of the shift register 41 when the control signal VTH is at a low potential (L). .., And an enable pulse WSEN1 that becomes active during a period in which both the inputs A (A (1), A (2),...) And the outputs B (B (1), B (2),. When the control signal VTH is at a high potential (H), a period in which each input A (A (1), A (2),...) Of the unit circuits 41-1, 41-2,. .., And the inputs A (A (1), A (2),...) Of the unit circuits 41-1, 41-2,... Of the shift register 41 become inactive, and the outputs B ( B (1), B (2), ...) is active And enable pulse WSEN2 which becomes active in 1H as a I blanking is, the scan pulse WSL1, WSL2, are sequentially outputted as ....

  As described above, the start pulse WSST is sequentially shifted in synchronization with the clock pulse WSCK having a duty ratio of 50% in the 2H cycle, and the shift pulse (unit circuit 41-1 is transmitted from each of the unit circuits 41-1, 41-2,. , 41-2,..., And the output circuit B (1), B (2),...) Are sequentially output as a basic circuit, and the unit circuits 41-1, 41-2,. Scan pulses WSL1, WSL2,... In combination with the input / output of the output and the logic circuit (45 to 49) that logically operates the enable pulse WSEN1 that determines the threshold correction period and the enable pulse WSEN2 that determines the write period (mobility correction period). Relationship between the enable pulse WSEN1 and the enable pulse WSEN2 in the write scanning circuit 40B that generates The threshold correction period can be set a plurality of times over a plurality of Hs determined by the pulse width of the start pulse WSST by controlling the pulse width of the start pulse WSST while setting the signals to be active within different 1H. it can.

  Specifically, the write operation (mobility) determined by the enable pulse WSEN2 is increased by expanding the pulse width (active period) of the start pulse WSST from 2H, which is the reference of the operation of the shift register 41, to 4H, 6H, 8H,. Since the number of threshold correction operations determined by the enable pulse WSEN1 can be increased over a plurality of H according to the pulse width of the start pulse WSST without increasing the number of correction operations), the threshold correction count (within 1H) The threshold correction operation can be increased according to the pulse width of the start pulse WSST. As a result, even if the horizontal scanning time is shortened as the display device becomes higher in definition, the threshold correction time can be secured over a plurality of H, so that the threshold correction can be sufficiently performed.

  In particular, by switching the polarity (low potential / high potential) of the control signal VTH serving as one input of each of the OR gates 45-1, 45-2,. Since it is possible to switch between setting to the number of times and setting to an even number of times, the number of threshold correction operations can be set finely for every 1H instead of every 1H. As described above, since the number of threshold correction operations can be finely set (finely adjusted) every 1H by the action of the control signal VTH, the optimum threshold correction time can be set in terms of the characteristics of the pixel circuit, so that the threshold correction can be performed more reliably. It can be carried out. As a result, variation in light emission luminance at low gradations can be suppressed, so that a display image with good image quality can be obtained.

[Power supply scanning circuit]
The write scanning circuit 40 that generates the scanning pulses WSL1, WSL2,... Has been described above, and the power scanning circuit 50 that generates the power supply line potentials DSL1, DSL2,.

  FIG. 15 is a block diagram illustrating a circuit example of the power supply scanning circuit 50. The power supply scanning circuit 50 according to the present example includes a shift register in which unit circuits (cells) 51-1, 51-2,... Composed of flip-flops or the like are cascade-connected by the number of stages corresponding to the number of rows m of the pixel array unit 30. 51, an inverter group 52 including a number of inverters 52-1, 52-2,... Corresponding to the number of rows m, and a three-input NAND gate 53-1, 53-2,. And a group of inverters 54 including a number of inverters 54-1, 54-2,... Corresponding to the number of rows m.

  As shown in the timing charts of FIGS. 11 to 14, the shift register 51 sequentially shifts the start pulse DSST in synchronization with the clock pulse DSCK having a phase opposite to that of the clock pulse WSCK, and the shift pulse from each transfer stage (unit circuit). Are output in order. The inverters 52-1, 52-2,... Of the inverter group 52 are connected to the outputs B (B (1), B (2),...) Of the unit circuits 51-1, 51-2,. Invert the polarity.

  The NAND gates 53-1, 53-2,... Of the NAND gate group 53 are connected to the inputs A (A (1), A (2),. , And the outputs B (B (1), B (2),...) Of the unit circuits 51-1, 51-2,... Of the shift register 51 whose polarity is inverted by the inverters 52-1, 52-2,. ) And an enable pulse DSEN for determining a threshold correction preparation period are set to three inputs. The outputs of the NAND gates 53-1, 53-2, ... are inverted in polarity by the inverters 54-1, 54-2, ..., and the power supply of the pixel array unit 30 as the power supply line potentials DSL1, DSL2, ... Applied to the supply lines 32-1, 32-2,.

  In this way, in the power supply scanning circuit 50 constituted by the combination of the shift register 51 and the logic circuit such as the NAND gate group 53, the write scanning circuit 40 starts to set the threshold correction period a plurality of times over a plurality of H times. When the pulse width of the pulse WSST is changed, the generation timing of the start pulse DSST of the power supply scanning circuit 50 may be changed corresponding to the generation timing of the start pulse WSST. Specifically, the timing relationship may be such that the start pulse DSST becomes active at 1H next to 1H when the start pulse WSST becomes active. The pulse width of the start pulse DSST is 2H which is a unit of operation of the shift register.

  In the above embodiment, the driving transistor 22 that drives the organic EL element 21, the writing transistor 23 that samples the input signal voltage Vsig and writes it in the pixel, and the gate and source of the driving transistor 22 are connected, The case where the present invention is applied to the organic EL display device 10 having the pixel circuit 20 having the circuit configuration including the storage capacitor 24 that holds the input signal voltage Vsig written by the write transistor 23 has been described as an example. It is not limited to examples.

  That is, a pixel circuit having a switching transistor that is connected between the drive transistor 22 and the power supply line and performs an operation for selectively supplying a drive current from the power supply line to the drive transistor 22, or appropriately conducting By entering the state, it further includes a switching transistor that detects the threshold voltage Vth of the driving transistor 22 prior to current driving of the organic EL element 21 and holds the detected threshold voltage Vth in the holding capacitor 24. Also in the case of an organic EL display device having a pixel circuit or the like, the mobility correction time is determined by the conduction period of the write transistor 22, so that the write transistor 22 is configured by a CMOS transistor, and thus, similar to the above embodiment. The effect of this can be obtained.

  In the above embodiment, the case where the present invention is applied to an organic EL display device using an organic EL element as the electro-optical element of the pixel circuit 20 has been described as an example. However, the present invention is not limited to this application example. In addition, the present invention can be applied to all display devices using current-driven electro-optic elements (light-emitting elements) whose light emission luminance changes according to the value of current flowing through the device.

1 is a system configuration diagram illustrating an outline of a configuration of an organic EL display device according to an embodiment of the present invention. It is a circuit diagram which shows the specific structural example of a pixel (pixel circuit). It is a timing chart with which it uses for operation | movement description of the organic electroluminescence display which concerns on one Embodiment of this invention. It is explanatory drawing (the 1) of circuit operation | movement of the organic electroluminescence display which concerns on one Embodiment of this invention. It is explanatory drawing (the 2) of the circuit operation | movement of the organic electroluminescence display which concerns on one Embodiment of this invention. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the threshold voltage Vth of a drive transistor. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the mobility (mu) of a drive transistor. It is a block diagram which shows the circuit example of a general write scanning circuit. 6 is a timing chart for explaining a circuit operation of a general write scanning circuit. It is a block diagram which shows the circuit example of the write-in scanning circuit based on this invention. It is a timing chart with which it uses for description of operation | movement of the writing scanning circuit in the case of setting a threshold value correction period once. It is a timing chart with which it uses for description of operation | movement of the writing scanning circuit in the case of setting a threshold value correction period 3 times. It is a timing chart with which it uses for description of operation | movement of the writing scanning circuit in the case of setting a threshold value correction period twice. It is a timing chart with which it uses for description of operation | movement of the writing scanning circuit in the case of setting a threshold value correction period 4 times. It is a block diagram which shows the circuit example of a power supply scanning circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Organic EL display device, 20 ... Pixel (pixel circuit), 21 ... Organic EL element, 22 ... Drive transistor, 23 ... Write transistor, 24 ... Retention capacity, 30 ... Pixel array part, 31 (31-1 to 31-31) m) ... Scanning line, 32 (32-1 to 32-m) ... Power supply line, 33 (33-1 to 33-n) ... Signal line, 35 ... Common power supply line, 40, 40A, 40B ... Write scanning Circuit 50 ... Power supply scanning circuit 60 ... Horizontal drive circuit

Claims (1)

  1. An electro-optic element; a writing transistor that samples and writes an input signal voltage; a holding capacitor that holds a signal voltage written by the writing transistor; and the electro-optic element based on the signal voltage held in the holding capacitor. A pixel array unit in which pixels including driving transistors to be driven are arranged in a matrix;
    A scanning circuit that outputs a scanning signal for selecting each pixel of the pixel array unit in a row unit;
    A drive circuit for driving to write an input signal to each pixel in a row selected by the scan signal output from the scan circuit;
    A display device capable of performing a threshold correction operation that cancels the dependence of the drain-source current of the driving transistor on the threshold voltage,
    The scanning circuit includes:
    The unit circuits are connected in cascade, and the start pulse having a variable pulse width is sequentially shifted in synchronization with a clock pulse whose unit is 1H (H is a horizontal scanning time), and the shift pulse is sequentially transmitted from each of the unit circuits. A shift register to output,
    An OR gate group having two inputs, a control signal that selectively takes one of a low potential and a high potential and each output signal of the unit circuit;
    A first NAND gate group that inputs three input signals of each of the unit circuits, each output signal of the OR gate group, and a first enable signal that determines a correction period of the threshold correction;
    A second NAND gate group that receives three inputs of an inverted signal of each input signal of the unit circuit, an output signal, and a second enable signal that determines a writing period of the input signal voltage;
    Each output signal of the first and second NAND gate groups has two inputs, and a third NAND gate group that outputs the scanning signal,
    The display device, wherein the first enable signal and the second enable signal are generated at different 1H.
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