KR20180072440A - Organic Light Emitting Display - Google Patents

Abstract

According to the present invention, an organic light emitting display device comprises: pixels including a driving transistor driving an organic light emitting diode; gate lines respectively connected to the pixels; and initial lines supplying initial voltage initializing voltage of an anode electrode of the organic light emitting diode. Furthermore, a shield pattern is positioned under a gate electrode of the driving transistor, and the initial line is positioned on the same array layer with the shield pattern. Therefore, the organic light emitting display device can reduce a short circuit between the initial lines and lines adjacent thereto.

Description

[0001] The present invention relates to an organic light emitting display,

The present invention relates to an active matrix type organic light emitting display.

The organic light emitting device OLED, which is a self-luminous device, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light. An active matrix type organic light emitting display includes various organic light emitting diodes (OLEDs) that emit light by themselves, and are widely used because of their high response speed, light emitting efficiency, brightness, and viewing angle.

The organic light emitting display device arranges the pixels each including the organic light emitting diode in a matrix form and adjusts the brightness of the pixels according to the gradation of the video data. Each of the pixels includes a driving transistor for controlling the driving current flowing in the organic light emitting diode according to the gate-source voltage, and at least one switch transistor for programming the gate-source voltage of the driving transistor. The driving current is determined by the gate-source voltage of the driving transistor according to the data voltage and the threshold voltage of the driving transistor, and the luminance of the pixel is proportional to the magnitude of the driving current flowing to the organic light emitting diode. The organic light emitting diode of each pixel emits light based on the image data programmed every frame period and the anode electrode of the organic light emitting diode is initialized by using the initializing voltage before programming new image data every frame period. The initialization voltage supplied to the pixel is supplied through the initial line.

In recent years, the resolution of a display device has increased, and the size of a pixel has become larger. Thus, the design of the pixel array including the initial lines is becoming more important.

An object of the present invention is to provide an organic light emitting display capable of improving the short circuit between adjacent lines and the initial line.

In order to achieve the above object, an organic light emitting diode display according to the present invention includes pixels, gate lines, and initial lines. The pixels include driving transistors for driving the organic light emitting diodes. The gate lines are connected to each of the pixels, and the initial line supplies an initialization voltage for initializing the voltage of the anode electrode of the organic light emitting diode. The shield pattern is located under the gate electrode of the driving transistor. The initial line is located in the same array layer as the shield pattern.

According to the present invention, since the initial line is located between the adjacent signal lines and the buffer layer, the short circuit between the initial line and other signal lines is improved. In addition, since the initial line of the present invention overlaps with the scan line, the threshold voltage of the transistors including the gate electrode connected to the scan line can be varied by the initialization voltage supplied as the initial line.

1 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
Fig. 3 is a waveform diagram of driving signals of the pixel shown in Fig. 2 and a voltage change of a main node; Fig.
4A to 4C are equivalent circuit diagrams of pixels according to a driving period.
5 shows a planar array structure of pixels according to the invention;
6 is a cross-sectional view taken along line I-I 'shown in Fig. 5; Fig.
7 is a cross-sectional view taken along the line II-II 'shown in FIG. 5;
8 is a view showing a planar array structure of pixels according to a comparative example;
9 is a cross-sectional view taken along line III-III 'in FIG.
10 is a diagram showing the relationship between an initialization voltage according to the present invention and a threshold voltage of the first transistor.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

In the gate driving circuit of the present invention, the switching elements may be implemented as n-type or p-type metal oxide semiconductor field effect transistor (MOSFET) transistors. Although n-type transistors are exemplified in the following embodiments, it should be noted that the present invention is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the invention should not be limited to the source and drain of the transistor.

In the embodiment of the present invention, only the transistors constituting the pixel are implemented as the P type. However, the technical idea of the present invention is not limited to this and can be applied to the case of the N type.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 to 10. FIG.

FIG. 1 is a diagram illustrating an organic light emitting display according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the pixel shown in FIG.

1 and 2, an OLED display according to an exemplary embodiment of the present invention includes a display panel 10 on which pixels PXL are formed, a data driver (not shown) for driving the data lines DL1 to DLm And a timing controller 11 for controlling the driving timings of the gate driver 13, the data driver 12 and the gate driver 13 for driving the gate lines GL1 to GL (n) .

In the display panel 10, a plurality of pixels PXL are arranged in a matrix form. The pixels PXL arranged on the n-th horizontal line are connected to the n-th gate line GLn. The nth gate line GLn includes the nth scan line SL [n] and the (n-1) th scan line SL [n-1]. The pixels PXL arranged in the respective column lines are connected to one data line DL.

The pixels PXL may be commonly supplied with the high and low potential driving voltages ELVDD and ELVSS and the initializing voltage Vini from a power source not shown. The initialization voltage Vini may be selected within a voltage range sufficiently lower than the operation voltage of the organic light emitting device OLED so that unnecessary light emission of the organic light emitting device OLED is prevented in the initial period and the sampling period. That is, it may be set to be equal to or lower than the low-potential driving voltage VSS. Therefore, by applying a voltage lower than the initialization voltage Vini and the low-potential driving voltage VSS in the initial period, the lifetime of the organic light emitting diode OLED can be improved.

The transistors (TFTs) constituting the pixel PXL may be implemented as a transistor including an oxide semiconductor layer. The oxide semiconductor layer is advantageous for large-sized display panel 10 when considering both electron mobility and process variations. When formed of an oxide semiconductor, it may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or indium gallium zinc oxide (IGZO). However, the present invention is not limited to this, and the semiconductor layer of the transistor may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or organic semiconductor.

The timing controller 11 rearranges the digital video data RGB input from the outside according to the resolution of the display panel 10 and supplies the digital video data RGB to the data driver 12. The timing controller 11 is also connected to the data driver 12 based on timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK and a data enable signal DE. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the gate driver 13. [

The data driver 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DDC.

The gate driver 13 may generate a scan signal and an emission control signal based on the gate control signal GDC. The gate driver 13 may include a scan driver and an emission driver. The scan driver generates first to nth scan signals SCAN1 to SCAN [n], and the emission driver generates first to nth emission control signals EM1 to EMn. The gate driver 13 may be formed directly on the non-display area of the display panel 10 according to a GIP (Gate-Driver In Panel) scheme.

Referring to FIG. 2, a detailed configuration of the pixel will be described below.

Each of the pixels PXL includes an organic light emitting diode (OLED) driving transistor DT, first through sixth transistors T1 through T6, and a capacitor Cst.

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode OLED. The organic compound layer may include at least one hole transporting layer, an electron transporting layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects holes into the light emitting layer or transmits holes, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer blocking layer, EBL). The electron transport layer is a layer for injecting electrons into the light emitting layer or for transporting electrons, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer blocking layer, HBL). The anode electrode of the organic light emitting diode OLED is connected to the fourth node N4 and the cathode electrode of the organic light emitting diode OLED is connected to the input terminal of the low potential driving voltage VSS.

The driving transistor DT controls the driving current applied to the organic light emitting element OLED according to its source-gate voltage Vsg. The source electrode of the driving transistor DT is connected to the first node N1, the gate electrode is connected to the second node N2, and the drain electrode is connected to the third node N3.

The first transistor T1 includes a source electrode connected to the third node N3, a drain electrode connected to the second node N2, and a gate electrode connected to the nth scan line SL [N]. The first transistor T1 is diode-connected to the gate-drain electrode of the driving transistor DT in response to the n-th scan signal SCAN [N].

The second transistor T2 includes a source electrode connected to the data line DL, a drain electrode connected to the first node N1, and a gate electrode connected to the nth scan line SL [n]. As a result, the second transistor T2 applies the data voltage Vdata supplied from the data line DL1 to the first node N1 in response to the n-th scan signal SCAN [N].

The third transistor T3 includes a source electrode connected to the high potential driving voltage line VDD, a drain electrode connected to the first node N1, and a gate electrode connected to the emission line. As a result, the third transistor T3 applies the high potential driving voltage VDD to the first node N1 in response to the emission control signal EM.

The fourth transistor T4 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to the emission line EL. The fourth transistor T4 forms a current path between the third node N3 and the fourth node N4 in response to the emission control signal EM.

The fifth transistor T5 is connected to the drain electrode connected to the second node N2, the source electrode connected to the initializing voltage Vini input terminal and the (n-1) th scan line SL [N-1] Gate electrode. The fifth transistor T5 applies the initialization voltage Vini to the second node N2 in response to the (n-1) th scan signal SCAN [N-1].

The sixth transistor T6 includes a gate electrode connected to a source electrode connected to an input terminal of a drain electrode initialization voltage Vini connected to the fourth node N4 and an nth scan line SL [N]. The fifth transistor T5 applies the initializing voltage Vini to the fourth node N4 in response to the n-th scan signal SCAN [N].

The storage capacitor Cst includes a first electrode coupled to the second node N2 and a second electrode coupled to the high potential drive voltage line VDD.

3 is a waveform diagram showing a gate signal driving a pixel and a diagram showing a main node voltage of the pixels according to the waveform diagram. 4A is an equivalent circuit diagram of a pixel during the initial period, FIG. 4B is an equivalent circuit diagram of the pixel during the sampling period, and FIG. 4C is an equivalent circuit diagram of the pixel during the emission period.

The driving of the organic light emitting display according to the present invention will be described with reference to FIGS. 2 to 4C.

In the OLED display according to the present invention, one frame period may be divided into an initial period (Ti), a sampling period (Ts), and an emission period (Te). The initial period Ti is a period for initializing the voltage of the gate electrode of the driving transistor. The sampling period Ts is a period for initializing the voltage of the anode electrode of the organic light emitting diode OLED and sampling the threshold voltage of the driving transistor DT and storing it in the node B. The emission period Te includes programming the source-gate voltage of the driving transistor DT including the sampled threshold voltage and causing the organic light emitting diode OLED to emit light with the driving current according to the programmed source- Period.

The initial period Pi of the nth pixel line overlaps the sampling period of the (n-1) th pixel line. That is, according to the present invention, the sampling period Ts can be sufficiently secured, so that the compensation of the threshold voltage can be more accurately performed.

During the initial period Pi, the fifth transistor T5 applies the initialization voltage Vini to the second node N2 in response to the (n-1) th scan signal SCAN (n-1). As a result, the gate electrode of the driving transistor DT is initialized to the initializing voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting device OLED and can be set to a voltage equal to or lower than the low potential driving voltage ELVSS. In the initial period Pi, the data voltage Vdata of the previous frame is held in the first node N1.

During the sampling period Ts, the sixth transistor T6 applies the initializing voltage Vini to the fourth node N4 in response to the n-th scan signal SCAN (n). As a result, the anode electrode of the organic light emitting diode OLED is initialized to the initializing voltage Vini.

The second transistor T2 applies a data voltage Vdata supplied from the data line DL1 to the first node N1 in response to the n-th scan signal SCAN [N]. The first transistor T1 is turned on in response to the n-th scan signal SCAN [N], so that the driving transistor DT is diode-connected (the gate electrode and the drain electrode are short- )do.

In the sampling period Ps, a current Ids flows between the source and the drain of the driving transistor DT. Since the gate electrode and the drain electrode of the driving transistor DT are diode-connected, the voltage of the second node N2 gradually rises due to the current Ids flowing from the source electrode to the drain electrode. During the sampling period Ts, the voltage of the second node N2 increases from the data voltage Vdata (n) to the value (Vdata (n) -Vth) obtained by subtracting the threshold voltage Vth of the driving transistor DT.

During the emission period Pe, the third transistor T3 applies the high potential driving voltage VDD to the first node N1 in response to the light emission control signal EM (n). The fourth transistor T4 forms a current path of the third node N3 and the fourth node N4 in response to the nth emission control signal EM (n). As a result, the driving current Ioled passing through the source electrode and the drain electrode of the driving transistor DT is applied to the organic light emitting diode OLED.

During the emission period Pe, a relational expression for the driving current Ioled flowing through the organic light emitting diode OLED is as shown in the following equation (1).

[Equation 1]

_{I OLED = k / 2 (Vgs} + | Vth |) 2 = k / 2 (Vg-Vs + | Vth |) 2 = k / 2 (Vdata- | Vth | -VDD + | Vth |) 2 = k / 2 (Vdata- VDD) ²

In Equation (1), k / 2 represents a proportional constant determined by electron mobility, parasitic capacitance, channel capacity, and the like of the driving transistor DT.

The threshold voltage (Vth) component of the driving transistor DT is erased in the relational expression of the driving current Ioled as shown in the following formula (1). This is because the organic light emitting display according to the present invention has the threshold voltage The drive current Ioled does not change.

As described above, the OLED display according to the present invention can program the data voltage regardless of the variation of the threshold voltage Vth during the sampling period Ts.

However, even if the gate-source voltage of the driving transistor DT is programmed to a desired voltage during the sampling period Ts, the desired luminance can not be displayed when the gate electrode voltage of the driving transistor DT varies. The gate electrode of the driving transistor DT forms a parasitic capacitance with the adjacent electrode or signal wiring and the voltage of the gate electrode can fluctuate due to the coupling effect due to the parasitic capacitance.

5 is a schematic diagram of a plane of a pixel arranged in an n-th pixel line according to the present invention. FIG. 6 is a cross-sectional view taken along the line I-I 'in FIG. 5, and FIG. 7 is a cross-sectional view taken along the line II-II' in FIG.

5 to 7, the pixel PXL arranged in the n-th pixel line includes the nth scan line SL [n], the (n-1) th scan line SL [n-1] an emission line (EML), and an initial line (VIL). The gate electrode GE of the driving transistor DT is connected to the second node N2, the source electrode SE is connected to the first node N1, the drain electrode DE is connected to the third node N3, Lt; / RTI > The capacitor metal layer TM1 overlaps with the gate electrode GE of the driving transistor DT in a plane. The shield pattern BSM is formed so as to cover the gate electrode GE of the driving transistor DT. The initial line VIL overlaps with the nth scan line SL [n] on a plane.

The cross-sectional structure of the driving transistor DT will be described with reference to FIG.

The source electrode of the driving transistor DT is connected to the first node N1, the gate electrode is connected to the second node N2, and the drain electrode is connected to the third node N3.

A polyimide (PI) layer may be located on the base substrate Glass in the display area AA. The first buffer layer BUF1 is located on the polyimide (PI) layer. The first buffer layer BUF1 may be silicon oxide (SiOx), silicon nitride (SiNx) or a multilayer thereof.

A shield pattern BSM is located on the first buffer layer BUF1. The polyimide-based insulating film forms a mobile charge, which affects the semiconductor layer of the transistor and may cause a problem of reducing the driving current. The shield pattern BSM serves to prevent the amount of current of the semiconductor layer ACT from being reduced due to the charge flow of the polyimide (PI) layer. The shield pattern BSM may be in a floating state and may be connected to the drain electrode as shown in the figure. Although the present specification shows an embodiment in which the shield pattern BSM is connected to the drain electrode, the shield pattern may be connected to another constant voltage source having a constant voltage level.

The second buffer layer BUF2 is located on the shield pattern LS. The second buffer layer BUF2 protects the thin film transistor formed in a subsequent process from impurities such as alkali ions or the like that flow out from the shield pattern LS. The second buffer layer BUF2 may be silicon oxide (SiOx), silicon nitride (SiNx) or a multilayer thereof.

The semiconductor layer ACT is located on the second buffer layer BUF2. The semiconductor layer ACT may be formed of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. Here, the polycrystalline silicon has high mobility (100 cm 2 / Vs or more), low energy consumption power and excellent reliability, and can be applied to a gate driver for a driving device and / or a multiplexer (MUX) have. On the other hand, since the oxide semiconductor has low off-current, it is suitable for a switching TFT which has a short ON time and a long OFF time. Further, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low speed driving and / or low power consumption.

A gate insulating film GI is disposed on the semiconductor layer ACT. The gate insulating film GI may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof. The gate electrode GA is located on the gate insulating film GI at a position corresponding to a certain region of the semiconductor layer ACT, that is, a channel when an impurity is implanted. The gate electrode GA is formed of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) Any one of them or an alloy thereof. The gate electrode GA may be formed of a material selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy of any one selected from the above. For example, the gate electrode GA can be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

A first interlayer insulating film ILD for insulating the gate electrode GA is located on the gate electrode GA. The first interlayer insulating film ILD may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

The capacitor metal layer TM1 is located on the first interlayer insulating film ILD1. The capacitor metal layer TM1 faces the gate electrode GE with the gate insulating film GI interposed therebetween and the capacitor metal layer TM1 and the gate electrode GE form the storage capacitor Cst.

The second interlayer insulating film ILD2 is located on the capacitor metal layer TM1. The second interlayer insulating film ILD2 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

The drain electrode DE and the source electrode SE are located on the second interlayer insulating film ILD. The source electrode SE is connected to the semiconductor layer ACT through the first contact hole CN1 and the drain electrode DE is connected to the semiconductor layer ACT through the second contact hole CN2.

The source electrode SE and the drain electrode DE may be formed of a single layer or a multilayer. When the source electrode SE and the drain electrode DE are a single layer, molybdenum (Mo), aluminum (Al) (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). When the source electrode SE and the drain electrode DE are multilayered, a triple layer of molybdenum / aluminum-neodymium, titanium / aluminum / titanium, molybdenum / aluminum / molybdenum or molybdenum / aluminum- neodymium / molybdenum ≪ / RTI >

The semiconductor layer ACT, the gate electrode GE, the drain electrode DE and the source electrode SE constitute a driving transistor DT.

A pixel planarizing film PLN1 is located on the source electrode SE and the drain electrode DE. The pixel planarizing film PLN1 protects the transistors disposed in the driving transistor DT and the display area AA and relaxes the step of the display area AA.

An anode electrode (AND) of the organic light emitting diode (OLED) is located on the pixel planarizing film (PLN1). The anode electrode AND is connected to the drain electrode DE of the driving transistor DT via a via hole Via. The anode electrode ANO may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

On the anode electrode (AND), a bank layer (BSL) for partitioning the pixels is located. The bank layer BSL is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate.

Referring to FIG. 7, the cross-sectional structure of an area where the initial line VIL and the nth scan line SL [n] overlap is as follows.

The gate region GE1 of the first transistor T1 refers to a region where the nth scan line SL [n] and the semiconductor layer ACT1 overlap in a plane. The initial line VIL is disposed in the first buffer layer BUF1 using the same material as the shield pattern BSM. A semiconductor layer ACT1 is disposed on the second buffer layer BUF2 covering the initial line VIL. The gate electrode GE1 of the first transistor T1 is disposed on the gate insulating film GI covering the semiconductor layer ACT1.

FIG. 8 is a view showing a pixel structure according to a comparative example of the present invention, and FIG. 9 is a cross-sectional view taken along the line III-III 'in FIG.

8 and 9, the pixel according to the comparative example includes an initial line VIL arranged side by side with the (n-1) th scan line SL [n-1]. The initial line VIL is located in the same array layer as the capacitor metal layer TM1. Since the initial line VIL is located in a state very close to the (n-1) th scan line SL [n-1], the initial line VIL and the (n-1) 1] may cause a short phenomenon.

7, since the initial line VIL according to the present invention is disposed in the same array layer as the shield pattern BSM, the initial line VIL between the initial line VIL and the nth scan line SL [n] The first buffer layer BUF1 and the second buffer layer BUF2 are located. The present invention is less likely to cause a short circuit between the initial line VIL and the nth scan line SL [n] because the interval between the initial line VIL and the nth scan line SL [n] .

Since the initial line VIL overlaps with the nth scan line SL [n], the initializing voltage Vini supplied to the initial line VIL is set to the gate voltage Lt; / RTI > of the transistors being supplied to the back bias voltage. Therefore, it is a diagram showing the threshold voltages of the transistors supplied with the gate voltage to the nth scan line SL [n] using the initialization voltage Vini supplied to the initial line VIL.

10 is a diagram showing a threshold voltage change of the first transistor shown in FIG. 5 according to the magnitude of the initialization voltage.

Referring to FIG. 10, the higher the potential of the initialization voltage Vini, the lower the threshold voltage Vth of the first transistor T1.

The initialization voltage Vini applied to the initialization line VIL is equal to the initial value of the initialization voltage Vini of the first transistor T1 because the initialization line VIL overlaps the gate electrode GE1 of the first transistor T1 on the plane. bias voltage. The display device of the present invention controls the initialization voltage Vini in the inspection step of the display panel 10 by using the relationship between the initialization voltage Vini and the threshold voltage Vth of the first transistor T1, The deviation of the threshold voltage (Vth) of one transistor (T1) can be improved.

The threshold voltage Vth of the first transistors T1 arranged in each of the pixels P of the display panel 10 may be changed by a process variation. Particularly, if the threshold voltage Vth of the first transistors T1 is shifted from the designed value, there arises a problem that the sampling operation of the driving transistor DT is not smooth.

The display apparatus of the present invention can measure the threshold voltage Vth of the first transistor T1 in the inspection process of the display panel 10 and set the magnitude of the initialization voltage Vini based on the measured threshold voltage Vth. For example, if the design value of the threshold voltage Vth of the first transistor T1 is -1.21 V but the measured value is -1.70 V, the threshold voltage Vini of the first transistor T1 Vth) can be improved.

The present invention has been described with reference to the organic light emitting diode display device having the 7T1C pixel structure shown in FIG. However, it goes without saying that the technical idea of the present invention can be applied to an organic light emitting diode display device having various pixel structures in addition to the pixel structure shown in FIG. That is, the present invention can be applied to a structure in which an initial line for supplying an initialization voltage is connected to a pixel, and the initialization line is disposed in the same array layer as the shield metal. In addition, the gate line overlapping the initial line is not limited to the n-th scan line shown in Fig. The initial line may overlap the (n-1) th scan line SL [n-1] and the emission line shown in Fig. The threshold voltage of the fifth transistor T5 can be adjusted using the initialization voltage when the initialization line overlaps the (n-1) th scan line SL [n-1]. Further, when the initialization line overlaps the emission line EML, the threshold voltage of the fourth transistor T4 can be adjusted using the initialization voltage. Similarly, in another pixel structure, a transistor capable of adjusting a threshold voltage using an initialization voltage in accordance with a scan line overlapping an initial line will be determined.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Data driver 13: Gate driver
DL: data line SL: scan line
EL: Emission line VIL: Initial line
BSM: Shield pattern

Claims (7)

Pixels including a driving transistor for driving an organic light emitting diode;
One or more gate lines connected to each of the pixels; And
And an initial line for supplying an initialization voltage for initializing a voltage of the anode electrode of the organic light emitting diode,
Wherein the pixels further include a shield pattern located under the gate electrode of the driving transistor,
Wherein the initial line is located in the same array layer as the shield pattern. The method according to claim 1,
Wherein the initial line overlaps with any one of the gate lines in a plan view. The method according to claim 1,
The gate lines connected to the pixels arranged in the n-th pixel line include an n-th scan line for supplying an n-th scan signal,
The pixel disposed in the n-th pixel line
A source electrode connected to the drain electrode of the driving transistor, a drain electrode connected to the gate electrode of the driving transistor, and a first transistor receiving the nth scan signal,
Wherein the initial line overlaps with the nth scan line on a plane. The method according to claim 1,
The initial line is located on the first buffer layer,
Wherein the semiconductor layer of the driving transistor is located on the first buffer layer covering the first buffer layer,
And a gate electrode of the driving transistor is located on a second buffer layer covering the first buffer layer. The method according to claim 1,
Wherein the initialization voltage is lower than the operating voltage of the organic light emitting diode. The method according to claim 1,
Wherein the shield pattern is supplied with a constant voltage. The method of claim 3,
Wherein a threshold voltage of the first transistor is varied according to the initialization voltage.

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