KR102595499B1 - Organic Light Emitting Display - Google Patents

Abstract

The organic light emitting display device according to the present invention includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a drain electrode connected to the gate electrode of the driving transistor, a source electrode connected to the drain electrode of the driving transistor, and a gate electrode. A first transistor connected to the n-th first scan line, a bridge pattern that connects the drain electrode of the first transistor and the gate electrode of the driving transistor and intersects the n-th first scan line on a plane, the bridge pattern and the n-th first scan The first and second interlayer insulating films insulate the line and are stacked perpendicularly to each other, and are interposed between the first interlayer insulating film and the second interlayer insulating film, and overlap the area where the bridge pattern and the nth first scan line intersect on the plane. Includes a shielding pattern that is

Description

Organic Light Emitting Display

The present invention relates to an active matrix type organic light emitting display device.

Organic light-emitting devices (OLEDs), which are self-luminous devices, include an anode electrode and a cathode electrode, and an organic compound layer formed between them. The organic compound layer consists of a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode and cathode electrodes, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, and as a result, the emitting layer (EML) Visible light is generated. The active matrix type organic light emitting display device includes an organic light emitting diode (OLED) that emits light on its own, and is used in a variety of ways due to its advantages of fast response speed, luminous efficiency, brightness, and viewing angle.

An organic light emitting display device arranges pixels, each containing an organic light emitting diode, in a matrix form and adjusts the luminance of the pixels according to the gradation of video data. Each of the pixels includes a driving transistor that controls the driving current flowing through the organic light emitting diode according to the gate-source voltage, and at least one switch transistor that programs the gate-source voltage of the driving transistor. The driving current is determined by the gate-source voltage of the driving transistor according to the data voltage and the threshold voltage of the driving transistor, and the luminance of the pixel is proportional to the size of the driving current flowing through the organic light-emitting diode.

Therefore, in order to display the luminance of a pixel at a desired value, the voltages of the gate electrode and source electrode of the driving transistor must be accurately and stably maintained. However, the voltage of each electrode may be unstable or cause unwanted fluctuations for various reasons.

In particular, when the voltage of electrodes or signal lines adjacent to the gate electrode of the driving transistor changes, the voltage of the gate electrode of the driving transistor may change due to a coupling effect. Ultimately, the voltage of the gate electrode of the driving transistor changes, causing a problem in which the pixel cannot display luminance corresponding to the programmed data voltage.

The present invention is intended to provide an organic light emitting display device that can improve changes in the gate electrode voltage of a driving transistor due to parasitic capacitance.

In order to achieve the above object, the organic light emitting display device according to the present invention includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a drain electrode connected to the gate electrode of the driving transistor, and a source electrode connected to the drain electrode of the driving transistor. A first transistor whose gate electrode is connected to the nth first scan line, a bridge pattern that connects the drain electrode of the first transistor and the gate electrode of the driving transistor and intersects the nth first scan line on a plane, bridge The first and second interlayer insulating films insulate the pattern and the nth first scan line and are stacked perpendicularly to each other, and are interposed between the first interlayer insulating film and the second interlayer insulating film, and have a bridge pattern and the nth first scan on a plane. Includes a shielding pattern that overlaps the area where the lines intersect.

According to embodiments of the present specification, since the shielding pattern suppresses parasitic capacitance from occurring between the nth first scan line and the bridge pattern, the voltage of the second node is prevented from changing due to fluctuations in the first scan signal. can do. As a result, the voltage of the second node is maintained stably at the start of the emission period, and the organic light emitting diode can display the desired luminance.

1 is a diagram showing an organic light emitting display device according to an embodiment of the present invention.
Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
FIG. 3 is a diagram showing the waveform of driving signals of the pixel shown in FIG. 2 and the voltage change of the main node.
4A to 4C are equivalent circuit diagrams of pixels according to the driving period.
Figure 5 is a diagram showing a parasitic capacitor connected to the gate electrode of the driving transistor in the light emission period.
6 is a plan view showing a pixel array according to an embodiment of the present invention.
Figure 7 is a cross-sectional view taken along line II' shown in Figure 6.
Figure 8 is a cross-sectional view taken along line II-II' shown in Figure 6.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. These embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or fully combined or combined with each other, various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

In the embodiment of the present invention, only the transistors constituting the pixel are implemented as P type, but the technical idea of the present invention is not limited to this and can be applied even when the transistors constituting the pixel are implemented as N type.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 1 to 8.

FIG. 1 is a diagram showing an organic light emitting display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the pixel shown in FIG. 1.

Referring to FIGS. 1 and 2 , an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 on which pixels PXL are formed, and a data driver for driving data lines DL1 to DLm. 12), a gate driver 13 for driving the gate lines (EL[1], SL1[1], SL2[1] to EL[n], SL1[n], SL2[n]), a data driver ( 12) and a timing controller 11 for controlling the driving timing of the gate driver 13.

A plurality of pixels (PXL) are arranged in a matrix form on the display panel 10. The pixels (PXL) arranged on the n-th horizontal line are the emission line (EL), the n-th first scan line (SL1[N]), the n-th second scan line (SCAN2[N]), and the n-1-th scan line. 2 Connected to scan line (SCAN2[N-1]). Pixels (PXL) arranged in one column are connected to one data line (DL).

The pixels (PXL) may be commonly supplied with high-potential and low-potential driving voltages (ELVDD, ELVSS) and initialization voltage (Vini) from a power generator (not shown). The initialization voltage Vini may be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting device (OLED) to prevent unnecessary light emission of the organic light emitting device (OLED) during the initial period and sampling period. That is, it can be set equal to or lower than the low potential driving voltage (VSS). Therefore, by applying a voltage lower than the low-potential driving voltage (VSS) to the initialization voltage (Vini) during the initial period, the lifespan of the organic light-emitting device (OLED) can be improved.

The transistors (TFTs) that make up the pixel (PXL) may be implemented as transistors including an oxide semiconductor layer. The oxide semiconductor layer is advantageous for increasing the area of the display panel 10 when considering electron mobility, process deviation, etc. When forming an oxide semiconductor, it may be formed of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide), but is not limited thereto. However, the present invention is not limited to this, and the semiconductor layer of the transistor may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an organic semiconductor.

The timing controller 11 rearranges digital video data (RGB) input from the outside to match the resolution of the display panel 10 and supplies it to the data driver 12. In addition, the timing controller 11 operates the data driver 12 based on timing signals such as the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the dot clock signal (DCLK), and the data enable signal (DE). A data control signal (DDC) for controlling the operation timing and a gate control signal (GDC) for controlling the operation timing of the gate driver 13 are generated.

The data driver 12 converts digital video data (RGB) input from the timing controller 11 into an analog data voltage based on the data control signal (DDC).

The gate driver 13 may generate a scan signal and an emission signal based on the gate control signal (GDC). The gate driver 13 may include a scan driver and an emission driver. The scan driver applies the first scan signal (SCAN1) and the second scan signal (SCAN2) to the first scan line (SL1) and the second scan line (SL2), respectively, and the emission driver applies the first scan signal (SCAN1) and the second scan signal (SCAN2) to the emission line (EL). Apply the emission signal (EM). This gate driver 13 may be formed directly on the non-display area of the display panel 10 according to the Gate-Driver In Panel (GIP) method.

With reference to FIG. 2, the detailed configuration of the pixel is as follows.

Each of the pixels (PXL) includes an organic light emitting diode (OLED) driving transistor (DT), first to sixth transistors (T1 to T6), and a capacitor (Cst).

Organic light-emitting diodes (OLEDs) emit light by driving current supplied from a driving transistor (DT). A multi-layer organic compound layer is formed between the anode and cathode electrodes of an organic light emitting device (OLED). The organic compound layer may include at least one hole transport layer, one electron transport layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects or transmits holes to the light emitting layer, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (Electron). blocking layer, EBL), etc. And, the electron transport layer is a layer that injects or transfers electrons to the light emitting layer, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer (Hole). blocking layer, HBL), etc. The anode electrode of the organic light emitting device (OLED) is connected to the fourth node (N4), and the cathode electrode of the organic light emitting device is connected to the input terminal of the low potential driving voltage (VSS).

The driving transistor (DT) controls the driving current applied to the organic light emitting device (OLED) according to its source-gate voltage (Vsg). The source electrode of the driving transistor DT is connected to the first node N1, the gate electrode is connected to the second node N2, and the drain electrode is connected to the third node N3.

The first transistor T1 includes a source electrode connected to the third node N3, a drain electrode connected to the second node N2, and a gate electrode connected to the nth first scan line SL1[N]. do. The first transistor T1 diode connects the gate-drain electrode of the driving transistor DT in response to the nth first scan signal SCAN1[N].

The second transistor T2 includes a source electrode connected to the data line DL, a drain electrode connected to the first node N1, and a gate electrode connected to the first scan line SL1. As a result, the second transistor T2 responds to the first scan signal SCAN1(N) and applies the data voltage Vdata supplied from the data line DL1 to the first node N1.

The third transistor T3 includes a source electrode connected to the high potential driving voltage line VDD, a drain electrode connected to the first node N1, and a gate electrode connected to the emission line EL. As a result, the third transistor T3 applies the high-potential driving voltage VDD to the first node N1 in response to the emission control signal EM.

The fourth transistor T4 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to the emission line EL. The fourth transistor T4 forms a current path between the third node N3 and the fourth node N4 in response to the emission control signal EM.

The fifth transistor (T5) has a drain electrode connected to the second node (N2), a source electrode connected to the initialization voltage (Vini) input terminal, and a n-1th second scan line (SL2[N-1]). Includes a gate electrode. The fifth transistor T5 applies the initialization voltage Vini to the second node N2 in response to the n-1th second scan signal SCAN2[N-1].

The sixth transistor (T6) includes a drain electrode connected to the fourth node (N4), a source electrode connected to the initialization voltage (Vini) input terminal, and a gate electrode connected to the nth second scan line (SL2[N]). . The fifth transistor T5 applies the initialization voltage Vini to the fourth node N4 in response to the nth second scan signal SCAN2[N].

The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the high potential driving voltage line VDD.

FIG. 3 is a waveform diagram showing a gate signal driving a pixel and a corresponding main node voltage of the pixels. FIG. 4A is an equivalent circuit diagram of a pixel during an initial period, FIG. 4B is an equivalent circuit diagram of a pixel during a sampling period, and FIG. 4C is an equivalent circuit diagram of a pixel during an emission period.

With reference to FIGS. 2 to 4C, the operation of the organic light emitting display device according to the present invention is as follows.

In the organic light emitting display device according to the present invention, one frame period can be divided into an initial period (Ti), a sampling period (Ts), and an emission period (Te). The initial period (Ti) is a period for initializing the voltage of the gate electrode of the driving transistor. The sampling period (Ts) is a period during which the voltage of the anode electrode of the organic light emitting diode (OLED) is initialized and the threshold voltage of the driving transistor (DT) is sampled and stored in node B. The emission period (Te) programs the voltage between the source and gate of the driving transistor (DT), including the sampled threshold voltage, and causes the organic light emitting device (OLED) to emit light with a driving current according to the programmed voltage between the source and gate. It's a period.

The initial period (Pi) of the nth pixel line overlaps the sampling period of the n-1th pixel line. That is, the present invention can secure a sufficient sampling period (Ts) and thus compensate for the threshold voltage more accurately.

During the initial period Pi, the fifth transistor T5 applies the initialization voltage Vini to the second node N2 in response to the nth second scan signal SCAN2(n). As a result, the gate electrode of the driving transistor (DT) is initialized to the initialization voltage (Vini). The initialization voltage (Vini) can be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting device (OLED), and can be set to a voltage equal to or lower than the low potential driving voltage (ELVSS). And, in the initial period Pi, the data voltage Vdata of the previous frame is maintained at the first node N1.

During the sampling period Ts, the sixth transistor T6 responds to the nth second scan signal SCAN2(n) and applies the initialization voltage Vini to the fourth node N4. As a result, the anode electrode of the organic light-emitting diode (OLED) is initialized to the initialization voltage (Vini).

The second transistor T2 responds to the nth first scan signal SCAN1[N] and applies the data voltage Vdata supplied from the data line DL1 to the first node N1. And the first transistor (T1) is turned on in response to the n-th first scan signal (SCAN1[N]), so that the driving transistor (DT) is connected to a diode (diode connection). The gate electrode and the drain electrode are short-circuited, causing the transistor to become a diode. behaves like this).

During the sampling period (Ps), a current (Ids) flows between the source and drain of the driving transistor (DT). Since the gate electrode and drain electrode of the driving transistor (DT) are diode-connected, the voltage of the second node (N2) gradually increases due to the current (Ids) flowing from the source electrode to the drain electrode. During the sampling period Ts, the voltage of the second node N2 increases to a value (Vdata(n)-Vth) obtained by subtracting the threshold voltage (Vth) of the driving transistor (DT) from the data voltage (Vdata(n)).

During the emission period Pe, the third transistor T3 responds to the emission signal EM(n) and applies the high potential driving voltage VDD to the first node N1. The fourth transistor T4 forms a current path through the third node N3 and the fourth node N4 in response to the n-th emission signal EM(n). Ultimately, the driving current (Ioled) passing through the source and drain electrodes of the driving transistor (DT) is applied to the organic light emitting diode (OLED).

During the emission period (Pe), the relational expression for the driving current (Ioled) flowing through the organic light emitting device (OLED) is as shown in Equation 1 below.

[Equation 1]

I _OLED =k/2(Vgs+|Vth|) ² = k/2(Vg-Vs+|Vth|) ² = k/2(Vdata-|Vth|-VDD+|Vth|) ² = k/2(Vdata- VDD) ²

In Equation 1, k/2 represents a proportionality constant determined by the electron mobility, parasitic capacitance, and channel capacity of the driving transistor (DT).

As shown in [Equation 1], the threshold voltage (Vth) component of the driving transistor (DT) is canceled in the relational expression of the driving current (Ioled), which means that the organic light emitting display device according to the present invention changes the threshold voltage (Vth). Even if this is done, it means that the driving current (Ioled) does not change.

As discussed, the organic light emitting display device according to the present invention can program the data voltage regardless of the amount of change in the threshold voltage (Vth) during the sampling period (Ts).

However, even if the voltage between the gate and source of the driving transistor DT is programmed to a desired voltage during the sampling period Ts, the desired luminance cannot be displayed if the gate electrode voltage of the driving transistor DT changes. The gate electrode of the driving transistor DT forms parasitic capacitance with adjacent electrodes or signal wires, and the voltage of the gate electrode may vary due to a coupling effect due to the parasitic capacitance.

Looking at the voltage change of the second node to which the gate electrode of the driving transistor is connected due to the parasitic capacitance is as follows.

FIG. 5 is a diagram showing the parasitic capacitance formed by the gate electrode of the driving transistor and other electrodes (or signal wires) at changes in the sampling period and emission period.

Referring to FIG. 5, the first parasitic capacitance (C1) refers to the capacitance between the second node (N2) and the emission line (EL), and the second parasitic capacitance (C2) refers to the capacitance between the second node (N2) and the first emission line (EL). This refers to the capacitance between scan lines (SL1[N]). The third parasitic capacitance C3 refers to the capacitance between the second node N2 and the data line DL.

As seen with reference to FIGS. 4B and 4C, the second node N2 is programmed with the value “Vdata-Vth” during the sampling period Ts, and “Vdata-Vth” in a floating state during the emission period Te. Maintain the value.

However, the voltage of the second node (N2), which is in a floating state, is unstable. Therefore, when the voltage of adjacent signal lines changes at the start of the emission period Te, the voltage of the second node N2 also changes due to the coupling effect of each of the first to third parasitic capacitors C3. It changes.

Specifically, at the start of the sampling period (Ts), the emission signal (EM) is inverted from the high potential voltage to the low potential voltage, and the first scan signal (SCAN1[N]) is inverted from the low potential voltage to the high potential voltage. do. That is, because the voltage of the electrode forming the parasitic capacitance with the second node N2 changes, the voltage of the second node N2 changes due to a coupling effect.

Hereinafter, the pixel array structure for preventing the voltage of the second node from changing due to parasitic capacitance is as follows.

FIG. 6 is a diagram illustrating an array structure for improving the voltage variation of the second node due to the coupling effect. FIG. 7 is a view showing a cross section taken along II-I' in FIG. 6, and FIG. 8 is a view showing a cross section taken along II-II' in FIG. 6.

Referring to FIGS. 6 to 8 , a buffer layer 110 is located on a substrate (SUB) in a pixel of an organic light emitting display device according to an implementation example of the present invention. The buffer layer 110 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

A semiconductor layer (ACT) is located on the buffer layer 110. The semiconductor layer (ACT) forms the source and drain electrodes of the transistors (DT, T1 to T6). The semiconductor layer (ACT) may be made of a silicon semiconductor or an oxide semiconductor. The impurity of the semiconductor layer (ACT) may be at least one p-type impurity selected from boron (B), aluminum (Al), gallium (Ga), and indium (In).

A gate insulating film 120 is located on the semiconductor layer (ACT). The gate insulating film 120 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

Gate metal layers (SL1[N], SL2[N], and SL2[N-1]) are located on the gate insulating film 120. The gate metal layer includes an n-th first scan line (SL1[N]), an n-1 second scan line (SL2[N-1]), an n-th second scan line (SL2[N]), and a driving transistor (DT). ) includes a gate electrode (G11). The nth first scan line SL1[N] may be disposed in a horizontal line direction in an area adjacent to the gate electrode G11 of the driving transistor DT. The area where the semiconductor layer (ACT) and the gate metal layer overlap can be defined as the gate electrode of each transistor (DT, T1 to T6). The gate metal layer is made of one or an alloy of two or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). can be formed.

A first interlayer insulating layer ILD1 is located on the gate metal layer. The first interlayer insulating film ILD1 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

Capacitor metal layers (E1, EB) are located on the first interlayer insulating layer (ILD). The capacitor metal layers (E1, EB) include the first electrode (E1) and the shielding pattern (EB) of the storage capacitor (Cst). The first electrode (E1) of the storage capacitor (Cst) is connected to the high potential voltage line (VDDL) input line to which the high potential voltage (VDD) is applied. The second electrode of the storage capacitor (Cst) corresponds to the gate electrode (G11) of the driving transistor (DT). As shown in FIG. 7 , the first electrode E1 of the storage capacitor Cst is formed to cover the third node semiconductor layer ACT N3 corresponding to the third node N3. The third node semiconductor layer (ACT N3) is connected to the source electrode of the first transistor (T1) and the source electrode of the fourth transistor (T4). The gap between the third node semiconductor layer (ACT N3) and the first electrode (E1) of the storage capacitor (Cst) is closer than the gap between the third node semiconductor layer (ACT N3) and the gate electrode (G11) of the driving transistor (DT). It is set. Therefore, the parasitic capacitance between the third node semiconductor layer (ACT N3) and the first electrode (G11) of the storage capacitor (Cst) is the difference between the third node semiconductor layer (ACT N3) and the gate electrode (G11) of the driving transistor (DT). It becomes large compared to the parasitic capacitance. As a result, the parasitic capacitance between the third node semiconductor layer (ACT N3) and the gate electrode (G11) of the driving transistor (DT) becomes negligible. That is, the voltage of the gate electrode (G11) of the driving transistor (DT) can be maintained at a constant level regardless of the change in voltage of the third node semiconductor layer (ACT N3).

A second interlayer insulating layer ILD2 is located on the capacitor metal layers E1 and EB. The second interlayer insulating film ILD2 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

After the second interlayer insulating film ILD2 is formed, the gate insulating film GI and the first and second interlayer insulating films ILD1 and ILD2 are selectively etched to form contact holes. The semiconductor layer at the location where the source and drain electrodes of each transistor are formed is exposed through the contact holes.

A source metal layer is located on the second interlayer insulating layer ILD2. The source metal layer includes a high potential voltage line (VDDL), a data line (DL), and the source and drain electrodes of each transistor (DT, T1 to T6). The source electrode is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. It can be done.

The drain electrode (D1) of the first transistor (T1) is located below the nth first scan line (SL1[N]) in a plane view. The drain electrode (D1) of the first transistor (T1) is connected to the gate electrode (G11) of the driving transistor (DT) through the bridge pattern (BR). The bridge pattern (BR) and the gate electrode (G11) of the driving transistor (DT) may be connected through a contact hole (CNT).

The bridge pattern (BR) intersects the nth first scan line (SL1[N]). As shown in FIG. 8, the shielding pattern EB is positioned to overlap the area where the bridge pattern BR and the nth first scan line SL1[N] intersect. The shielding pattern EB prevents parasitic capacitance from occurring between the nth first scan line SL1[N] and the bridge pattern BR.

If there is no shielding pattern (EB), parasitic capacitance occurs between the n-th first scan line (SL1[N]) and the bridge pattern (BR), so the n-th first scan line (SL1[N]) When the voltage of changes, the voltage of the bridge pattern (BR) also changes due to the coupling effect. In particular, the voltage of the second node N2 is unstable during the emission period Te because it is in a floating state. And at the moment when the sampling period (Ts) changes from the emission period (Te), the first scan signal (SCAN1[N]) applied to the nth first scan line (SL1[N]) changes from a low potential voltage to a high potential. converted to voltage. As such, when the voltage of the nth first scan line SL1[N] changes, the voltage of the floating second node N2 changes due to a coupling effect. That is, as the voltage of the second node N2, which determines the size of the driving current Ioled, changes, the organic light emitting diode (OLED) displays unwanted luminance.

On the other hand, in the organic light emitting display device according to the present invention, since the shielding pattern (EB) suppresses parasitic capacitance from occurring between the nth first scan line (SL1[N]) and the bridge pattern (BR), the first It is possible to prevent the voltage of the second node (N2) from changing due to changes in the scan signal (SCAN1[N]). As a result, the voltage of the second node N2 is maintained stably at the start of the emission period Te, and the organic light emitting diode (OLED) can display the desired luminance.

In addition, since the shielding pattern EB is branched from the first electrode E1 of the storage capacitor Cst, a high potential driving voltage VDD, which is a constant voltage, is applied to the shielding pattern EB. That is, the bridge pattern (BR) does not experience voltage fluctuations due to parasitic capacitance with the shielding pattern (EB).

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

10: display panel 11: timing controller
12: data driver 13: gate driver
DL: data line SL1, SL2: scan line
EL: Emission line BR: Bridge pattern
EB: Shielding pattern

Claims (12)

organic light emitting diode;
A driving transistor for driving the organic light emitting diode;
a first transistor whose drain electrode is connected to the gate electrode of the driving transistor, whose source electrode is connected to the drain electrode of the driving transistor, and whose gate electrode is connected to a scan line;
a bridge pattern connecting the drain electrode of the first transistor and the gate electrode of the driving transistor and intersecting the scan line in a plane;
a first interlayer insulating film and a second interlayer insulating film that insulate the bridge pattern and the scan line and are stacked perpendicularly to each other; and
An organic light emitting display device comprising a shielding pattern interposed between the first interlayer insulating film and the second interlayer insulating film and overlapping an area where the bridge pattern and the scan line intersect in a plan view. According to claim 1,
The scan line is located on the gate insulating film,
The shielding pattern is located on the first interlayer insulating film covering the scan line,
The bridge pattern is formed of the same metal layer as the drain electrode of the first transistor on the second interlayer insulating film covering the shielding pattern. According to claim 2,
The first electrode is connected to a high potential driving voltage line and the second electrode corresponds to the gate electrode of the driving transistor, and further includes a storage capacitor that stores the gate-source voltage of the driving transistor,
The shielding pattern is branched from the first electrode of the storage capacitor. According to claim 3,
It further includes a second transistor whose drain electrode is connected to the source electrode of the driving transistor, the source electrode is connected to the data line, and the gate electrode is connected to the scan line,
During the sampling period,
The first and second transistors charge the source electrode of the driving transistor with a data voltage in response to the scan signal applied to the scan line, and apply a threshold voltage of the driving transistor from the data voltage to the gate electrode of the driving transistor. An organic light emitting display device that charges the subtracted value. According to claim 4,
a third transistor including a source electrode connected to the high potential driving voltage input terminal and a drain electrode connected to the source electrode of the driving transistor; and
It further includes a fourth transistor including a source electrode connected to the drain electrode of the driving transistor and a drain electrode connected to the anode electrode of the organic light emitting diode,
The gate electrodes of the third and fourth transistors are connected to an emission line, and the emission signal applied to the emission line maintains a turn-off voltage during the sampling period. According to claim 5,
During the emission period following the above sampling period,
The scan signal is inverted to a turn-off voltage, so that the gate electrode of the driving transistor is in a floating state. According to claim 6,
An organic light emitting display device in which the scan signal is inverted to a turn-off voltage at the start of the emission period. According to claim 3,
An organic light emitting display device wherein a gap between a third node semiconductor layer connected to the drain electrode of the first transistor and the first electrode of the storage capacitor is smaller than a gap between the third node semiconductor layer and the driving transistor. According to claim 8,
The third node semiconductor layer is located in an area adjacent to the gate electrode of the driving transistor in a plane view,
The first electrode of the storage capacitor is formed to cover the third node semiconductor layer. According to claim 1,
The scan signal applied to the scan line is
Maintain the turn-on voltage during the sampling period of pixels placed on the nth horizontal line,
An organic light emitting display device maintaining a turn-off voltage during an emission period of pixels disposed on the nth horizontal line. organic light emitting diode;
A driving transistor for driving the organic light emitting diode;
a storage capacitor whose first electrode is connected to a high-potential driving voltage line and whose second electrode corresponds to a gate electrode of the driving transistor and stores the gate-source voltage of the driving transistor;
a gate insulating layer for insulating between the gate electrode of the driving transistor and a third node semiconductor layer connected to the drain electrode of the driving transistor;
A first insulating layer disposed on the gate insulating layer and insulating between the gate electrode of the driving transistor and the first electrode of the storage capacitor,
The first electrode of the storage capacitor is located on the first insulating layer, and the distance between the first electrode of the storage capacitor and the third node semiconductor layer is the distance between the third node semiconductor layer and the gate electrode of the driving transistor. Smaller organic light emitting display device. According to claim 11,
The third node semiconductor layer is located in an area adjacent to the gate electrode of the driving transistor in a plane view,
The first electrode of the storage capacitor is formed to cover the third node semiconductor layer.

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