KR20180023112A - Organic Light Emitting Display - Google Patents

Abstract

In an organic light emitting display device according to the present invention, a plurality of sub pixels including an organic light emitting diode and a driving transistor for driving the organic light emitting diode are arranged. The plurality of sub pixels include sub pixels of a first column including a first voltage supply line, sub pixels of a second column sharing the first voltage supply line with the sub pixels of the first column, sub pixels of a third column including a second voltage supply line, and sub pixels of a fourth column sharing the second voltage supply line with the sub pixels of the third column. The sub pixels of the first and fourth columns display a first color and the sub pixels of the second and third columns display a second color or a third color. Accordingly, the present invention can reduce the whole size of the sub pixels and improve brightness of a display panel.

Description

[0001] The present invention relates to an organic light emitting display,

The present invention relates to an active matrix type organic light emitting display.

The organic light emitting device OLED, which is a self-luminous device, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

An active matrix type organic light emitting display includes various organic light emitting diodes (OLEDs) that emit light by themselves, and are widely used because of their high response speed, light emitting efficiency, brightness, and viewing angle.

As the resolution of the display device gradually increases, the size of each subpixel of the organic light emitting display device becomes smaller. Therefore, an organic light emitting display suitable for high resolution is required.

The present invention is to provide an organic light emitting display suitable for high resolution.

According to an aspect of the present invention, an organic light emitting display includes a plurality of subpixels including an organic light emitting diode and a driving transistor for driving the organic light emitting diode. The plurality of subpixels includes a first column of subpixels including a first voltage supply line, a second column of subpixels sharing a first voltage supply line with a first column of subpixels, and a second voltage supply line Pixels in the third column and subpixels in the fourth column sharing the second voltage supply line with the subpixels in the third column. The subpixels in the first and fourth columns represent a first color and the subpixels in the second and third columns represent a second color or a third color.

According to the embodiments of the present invention, since the pair of subpixels adjacent in the row direction share the high potential voltage line, the overall size of the subpixels can be reduced, and the signal lines can be easily designed.

The organic light emitting display according to an embodiment of the present invention includes subpixels of three primary colors of R, G, and B in one pixel, and particularly includes two G subpixels of high luminance weight, .

Particularly, in an organic light emitting display according to an embodiment of the present invention, subpixels are arranged in both lateral directions around a high-potential voltage line, and subpixels of the same color are dispersed to the left and right of a high-potential voltage line. Accordingly, even when the patterns are shifted and formed by the process variations, the color defects can be improved because the subpixels of the same color do not have the same luminance deviation.

FIG. 1 is a view illustrating an organic light emitting display according to an embodiment of the present invention. FIG.
2 is a view showing a display panel according to a first embodiment of the present invention.
FIG. 3 is a schematic diagram of first and second subpixels in FIG. 2; FIG.
4 is a diagram schematically illustrating a shift phenomenon of a pattern due to a process deviation.
5 is a view showing a display panel according to a second embodiment;
6 is an equivalent conception of first and second subpixels according to an embodiment.
FIG. 7 is a waveform diagram of drive signals of the subpixel shown in FIG. 6 and a voltage change of a main node; FIG.
8 is a plan view showing a pixel array of the first and second sub-pixels shown in Fig. 7; Fig.
FIG. 9 is a cross-sectional view taken along line I-I 'shown in FIG. 8; FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, and technically various interlocking and driving, and that the embodiments may be practiced independently of each other,

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In the exemplary embodiment of the present invention, only the transistors constituting the subpixel are implemented as P-type transistors. However, the technical idea of the present invention is not limited to this and can be applied to the case of N-type transistors.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 to 9. FIG.

1 is a view illustrating an organic light emitting display according to an embodiment of the present invention.

1, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 10 having subpixels PXL, a data driving circuit 12 for driving data lines DL, A gate driving circuit 13 for driving the gate lines 15 and a timing controller 11 for controlling the driving timing of the data driving circuit 12 and the gate driving circuit 13. [

In the display panel 10, a plurality of data lines DL and a plurality of gate lines 15 are crossed, and sub-pixels PXL are arranged in a matrix form for each of the intersection regions. The subpixels PXL arranged in one row are connected to one gate line 15 and one gate line 15 may include at least one scan line and at least one emission line. That is, each sub-pixel PXL may be connected to one data line DL and at least one scan line and an emission line. The subpixels PXL can be commonly supplied with the high potential and low potential driving voltages ELVDD and ELVSS and the initial voltage Vini from a power source not shown. The initial voltage Vini may be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting device OLED so that unnecessary light emission of the organic light emitting device OLED is prevented in the initial period and the sampling period. That is, it may be set to be equal to or lower than the low-potential driving voltage ELVSS. Therefore, a voltage lower than the low potential driving voltage ELVSS is applied to the initial voltage Vini during the initial period, so that the lifetime of the organic light emitting device OLED can be improved.

The transistors (TFTs) constituting the subpixel PXL may be implemented by transistors including an oxide semiconductor layer. The oxide semiconductor layer is advantageous for large-area display panel 10 when considering both electron mobility and process variations. When formed of an oxide semiconductor, it may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or indium gallium zinc oxide (IGZO). However, the present invention is not limited to this, and the semiconductor layer of the transistor may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or organic semiconductor.

The timing controller 11 rearranges the digital video data RGB input from the outside in accordance with the resolution of the display panel 10 and supplies the digital video data RGB to the data driving circuit 12. The timing controller 11 is also connected to the data driving circuit 12 based on timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK and a data enable signal DE, A data control signal DDC for controlling the operation timing of the gate driving circuit 13 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13. [

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DDC.

The gate driving circuit 13 may generate a scan signal and an emission signal based on the gate control signal GDC. The gate drive circuit 13 may include a scan driver and an emission driver. The scan driver may generate a scan signal in a row sequential manner to supply at least one scan line connected to each subpixel row to the scan lines. The emission driver may generate an emission signal in a row sequential manner to supply at least one emission line connected to each subpixel row to the emission lines.

The gate drive circuit 13 may be formed directly on the non-display area of the display panel 10 in accordance with a GIP (Gate-Driver In Panel) method.

≪ Display panel according to the first embodiment &

FIG. 2 is a view showing a subpixel arrangement of a display panel according to a first embodiment of the present invention, and FIG. 3 is a view showing first and second subpixels in FIG.

Referring to FIGS. 2 and 3, a pair of adjacent subpixels in the display panel 10 share a high-potential voltage line VDD.

The first subpixel P1 and the second subpixel P2 disposed in the first row share the first high potential voltage line VDD1 and the third subpixel P3 and the fourth subpixel P4 share the first high- Share a second high potential voltage line VDD2. Similarly, the fifth subpixel P5 and the sixth subpixel P6 disposed in the second row share the first high potential voltage line VDD1 and the seventh subpixel P7 and the eighth subpixel P6 share the first high- P8 share a second high potential voltage line VDD2. The organic light emitting display according to the present invention can reduce the number of high potential voltage lines by half because adjacent subpixels share a high potential voltage. As a result, the organic light emitting diode display according to the present invention can reduce the size of the subpixel, thereby realizing high resolution.

To implement color, four subpixels constitute one pixel. The first subpixel P1, the second subpixel P2, the fifth subpixel P5 and the sixth subpixel constitute one pixel and the third subpixel P3, the fourth subpixel P4 ), The seventh sub-pixel P7 and the eighth sub-pixel P8 constitute one pixel.

As described above, one pixel includes two G subpixels and one B subpixel and one R subpixel, respectively. The G subpixel has the highest luminance weight among R, G, and B ternary colors. Accordingly, since the display device according to the present invention includes two G subpixels in one pixel, the luminance of the display panel can be increased.

≪ Problems due to process variations >

As described above, the display device according to the first embodiment of the present invention can realize a high resolution of a pixel by sharing a high potential voltage line with adjacent subpixels, and includes two G subpixels in one pixel, . However, as adjacent subpixels share a high potential voltage line, image quality defects may be caused by process variations.

The display device according to the first embodiment shown in Figs. 2 and 3 has a structure in which a pair of adjacent subpixels arranged in the same row share a data line and are symmetrical with respect to a common data line. As a result, when the process deviation occurs, the electrical characteristic deviation occurs inversely.

FIG. 4 is a diagram illustrating a characteristic change of the first subpixel P1 and the second subpixel P2 by the process variation. In FIG. 4, the pattern regions PT1 and PT2 denote regions where patterns arranged in the metal layer different from the high potential voltage line VDD are to be located, and the error regions PT1 'and PT2' The position of the patterns deviating from the region to be formed. The high-potential voltage line VDD can be formed using the same metal layer (hereinafter, a source-drain metal layer) as the source electrode, the drain electrode, and the data line of the transistor. Thus, the pattern regions PT1 and PT2 include array patterns, such as semiconductor layers or gate electrodes, located in a metal layer different from the source-drain metal layer.

The first sub-pixel P1 and the second sub-pixel P2 include patterns arranged in a plurality of metal layers to form transistors in addition to the high-potential voltage line VDD. If an array deviation occurs between the respective metal layers in the process of manufacturing subpixels, the electrical characteristics such as parasitic capacitances may change. There are many reasons why the electrical characteristics change due to process variations. For example, when the size of the overlapping region of the semiconductor layer and the data line of the source-drain metal layer is changed, the parasitic capacitance changes, and the luminance displayed by the subpixel may change due to the change of the parasitic capacitance.

Since the first and second subpixels P1 and P2 are symmetrical with respect to each other with respect to the high potential voltage line VDD, if the pattern is shifted by the process variation, The characteristic deviation of the pixel P2 is reversed.

For example, if the error regions PT1 'and PT2' are shifted to the left as shown in FIG. 4, the first error region PT1 'of the first subpixel P1 is a source region including the high potential voltage line VDD -Drain metal layer and the second pattern region PT2 'is shifted in the negative (-) direction from the source-drain metal layer including the high-potential voltage line VDD. If the brightness of the first subpixel P1 is increased by shifting the first error area PT1 'in the positive direction, the second error area PT2' is shifted in the negative direction, The luminance of the sub-pixel P2 decreases.

As a result, if all of the G subpixels P1, P3, P5 and P7 located in the odd-numbered columns of the display panel shown in FIG. 2 have increased luminance, the R subpixels P4 and P6 located in the even- The subpixels P2 and P8 all have a reduced luminance. If all the G subpixels P1, P3, P5 and P7 located in the odd-numbered columns have decreased in luminance, the R subpixels P4 and P6 and the B subpixels P2 and P8 located in the even column are both The luminance increases.

Thus, in the display panel shown in Fig. 2, the same luminance deviation occurs in subpixels displaying the same color. As a result, the color displayed by the pixels is distorted, resulting in poor image quality.

A second embodiment for improving the image quality defect is as follows.

≪ Display panel according to the second embodiment &

5 is a view showing a display panel according to a second embodiment of the present invention.

Referring to FIG. 5, in the display panel according to the second embodiment, the first sub-pixel P1 and the second sub-pixel P2 disposed in the first row share the first high-potential voltage line VDD1, The third subpixel P3 and the fourth subpixel P4 share a second high potential voltage line VDD2. Similarly, the fifth subpixel P5 and the sixth subpixel P6 disposed in the second row share the first high potential voltage line VDD1 and the seventh subpixel P7 and the eighth subpixel P6 share the first high- P8 share a second high potential voltage line VDD2. The display panel according to the second embodiment can reduce the number of the high-potential voltage lines by half because the adjacent sub-pixels share the high-potential voltage. As a result, the organic light emitting diode display according to the present invention can reduce the size of the subpixel, thereby realizing high resolution.

To implement color, four subpixels constitute one pixel. One pixel includes two pairs of subpixels sharing a high potential voltage line (VDD). For example, the first subpixel P1 and the second subpixel P2, and the fifth subpixel P5 and the sixth subpixel sharing the first high potential voltage line VDD1 constitute one pixel . The third subpixel P3 and the fourth subpixel P4 sharing the second high potential voltage line VDD2 and the seventh subpixel P7 and the eighth subpixel P8 are connected to one pixel .

The first subpixel P1 and the fifth subpixel P5 located in the odd-numbered column in the odd-numbered pixel denote the first color, and the second subpixel P2 and the sixth subpixel P2 in the odd- Pixel P6 represents the second color and the third color. The first color may be G color, and the second color and the third color may be R color and B color, respectively. Thus, one pixel can include two G subpixels and one B subpixel and one R subpixel, thereby increasing the brightness.

The third subpixel P3 and the seventh subpixel P7 located in the odd-numbered column in the odd-numbered pixel indicate the second color and the third color, respectively, and the fourth subpixel P4 And the eighth sub-pixel P8 represent the first color. The first color may be G color, and the second color and the third color may be R color and B color, respectively. The even pixel may include two G subpixels and one B subpixel and one R subpixel, thereby increasing the brightness.

Further, in the display panel according to the second embodiment, subpixels of the same color arranged in adjacent pixels are arranged on the other side with respect to the high-potential voltage line. For example, the G subpixel of the odd-numbered pixel is arranged in the odd-numbered column and the G subpixel of the even-numbered pixel is arranged in the even-numbered column. Accordingly, when the G subpixels P1 and P5 of the odd-numbered pixel are shifted in the + direction by the process deviation, the G subpixels P4 and P8 of the even-numbered pixel are shifted in the negative direction. As a result, the G subpixels of the pixels adjacent in the row direction have opposite brightness variations. Therefore, when the luminance of the G subpixels P1 and P5 of the odd-numbered pixel increases due to the process variation, the luminance of the G subpixels P4 and P8 of the even-numbered pixel decreases, The luminance variation of the G subpixels is compensated.

Likewise, when the luminance of the R-subpixel P2 of the odd-numbered pixel decreases due to the process variation, the luminance of the R-subpixel P3 of the even-numbered pixel increases. Further, when the luminance of the B sub-pixel P6 of the odd-numbered pixel decreases, the luminance of the B sub-pixel P7 of the even-numbered pixel increases.

As described above, in the display panel according to the second embodiment, since the same-color subpixels between pixels adjacent in the row direction are located on the opposite sides with respect to the high-potential voltage line, even if a process deviation occurs, (Increase or decrease in luminance). As a result, the display panel according to the second embodiment can improve the color quality and improve the display quality.

≪ Implementation Example of Sub-Pixel Structure According to the Present Invention &

6 is an equivalent circuit diagram illustrating sub-pixel structures of first and second sub-pixels according to the present invention.

6, the first and second subpixels P1 and P2 share a high potential voltage line VDD1 and are connected to the driving transistor DT, the first transistor T1, the second transistor T2 A third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a capacitor Cst. Hereinafter, the sub-pixel structure will be described with the first sub-pixel P1 as a center.

The organic light emitting element OLED emits light by a driving current supplied from the driving transistor DT. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode OLED. The organic compound layer may include at least one hole transporting layer, an electron transporting layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects holes into the light emitting layer or transmits holes, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer blocking layer, EBL). The electron transport layer is a layer for injecting electrons into the light emitting layer or for transporting electrons, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer blocking layer, HBL). The anode electrode of the organic light emitting element OLED is connected to the node C, and the cathode electrode of the organic light emitting element is connected to the input terminal of the low potential driving voltage ELVSS.

The driving transistor DT controls the driving current applied to the organic light emitting element OLED according to its source-gate voltage Vsg. The gate electrode of the driving transistor DT is connected to the node A, the source electrode is connected to the node D, and the drain electrode is connected to the node B.

The first transistor T1 includes a source electrode connected to the node A, a drain electrode connected to the node D, and a gate electrode connected to the node B.

The second transistor T2 includes a source electrode connected to the data line DL, a drain electrode connected to the node A, and a gate electrode connected to the first scan line SL1. As a result, the second transistor T2 applies the data voltage Vdata supplied from the data line DL1 to the node A in response to the first scan signal SCAN1 (n).

The third transistor T3 includes a source electrode connected to the high potential voltage line VDD, a drain electrode connected to the node A, and a gate electrode connected to the emission line EL. As a result, the third transistor T3 applies the high potential voltage VDD to the node A in response to the emission control signal EM.

The fourth transistor T4 includes a source electrode connected to the node C, a drain electrode connected to the node D, and a gate electrode connected to the emission line EL. The fourth transistor T4 forms a current path between the node C and the node D in response to the emission control signal EM.

The fifth transistor T5 includes a gate electrode connected to the source electrode connected to the drain electrode initialization voltage Vini input terminal connected to the node B and the (n-1) th second scan line SL2 [N-1] . The fifth transistor T5 applies the initializing voltage Vini to the node B in response to the (n-1) th second scan signal SCAN2 [N-1].

The sixth transistor T6 includes a gate electrode connected to the source electrode connected to the drain electrode initializing voltage Vini input terminal connected to the node D and the nth second scan line SL2 [N]. The fifth transistor T5 applies the initialization voltage Vini to the node D in response to the n-th second scan signal SCAN2 [N].

The storage capacitor Cst includes a first electrode coupled to node B and a second electrode coupled to a high potential voltage line VDD.

7 is a waveform diagram showing a gate signal for driving a subpixel and a diagram showing a main node voltage of the pixels according to the waveform diagram.

Referring to FIGS. 6 and 7, one frame period in the organic light emitting display according to the embodiment of the present invention can be divided into an initial period Ti, a sampling period Ts, and an emission period tE. The initial period Ti is a period for initializing the voltage of the gate electrode of the driving transistor. The sampling period Ts is a period for initializing the voltage of the anode electrode of the organic light emitting diode OLED and sampling the threshold voltage of the driving transistor DT and storing it in the node B. The emission period Te includes programming the source-gate voltage of the driving transistor DT including the sampled threshold voltage and causing the organic light emitting diode OLED to emit light with the driving current according to the programmed source- Period.

The initial period Pi of the nth pixel line overlaps the sampling period of the (n-1) th pixel line. That is, according to the present invention, the sampling period Ts can be sufficiently secured, so that the compensation of the threshold voltage can be more accurately performed.

During the initial period Pi, the fifth transistor T5 applies an initial voltage Vini to the node A in response to the n-th second scan signal SCAN2 (n). As a result, the gate electrode of the driving transistor DT is initialized to the initializing voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting device OLED and can be set to a voltage equal to or lower than the low potential driving voltage ELVSS. In the initial period Pi, the data voltage Vdata (n-1) of the previous frame is held at the node A.

During the sampling period Ts, the sixth transistor T6 applies the initializing voltage Vini to the node D in response to the n-th second scan signal SCAN2 (n). As a result, the anode electrode of the organic light emitting diode OLED is initialized to the initializing voltage Vini.

The second transistor T2 applies the data voltage Vdata (n) supplied from the data line DL1 to the node A in response to the n-th first scan signal SCAN1 [N]. The first transistor T1 is turned on in response to the n-th first scan signal SCAN1 [N], so that the driving transistor DT is diode-connected (the gate electrode and the drain electrode are short- .

In the sampling period Ps, a current Ids flows between the source and the drain of the driving transistor DT. Since the gate electrode and the drain electrode of the driving transistor DT are diode connected, the voltage of the node A of the driving transistor DT gradually rises due to the current Ids flowing from the source electrode to the drain electrode. During the sampling period Ts, the voltage of the node A increases from the data voltage Vdata (n) to the value (Vdata (n) -Vth) obtained by subtracting the threshold voltage Vth of the driving transistor DT.

During the emission period Pe, the third transistor T3 applies a high potential voltage to the node A in response to the emission signal EM (n). The fourth transistor T4 forms a current path of the node C and the node D in response to the nth emission signal EM (n). As a result, the driving current Ioled passing through the source electrode and the drain electrode of the driving transistor DT is applied to the organic light emitting diode OLED.

During the emission period Pe, a relational expression for the driving current Ioled flowing through the organic light emitting diode OLED is as shown in the following equation (1).

[Equation 1]

_{I OLED = k / 2 (Vgs} + | Vth |) 2 = k / 2 (Vg-Vs + | Vth |) 2 = k / 2 (Vdata- | Vth | -VDD + | Vth |) 2 = k / 2 (Vdata- VDD) ²

In Equation (1), k / 2 represents a proportional constant determined by electron mobility, parasitic capacitance, channel capacity, and the like of the driving transistor DT.

The threshold voltage (Vth) component of the driving transistor DT is erased in the relational expression of the driving current Ioled as shown in the following formula (1). This is because the organic light emitting display according to the present invention has the threshold voltage The drive current Ioled does not change.

FIG. 8 is a view showing a planar array of the first and second subpixels shown in FIG. 6, and FIG. 9 is a cross-sectional view showing a cutting plane I-I 'in FIG.

Referring to FIGS. 8 and 9, a first buffer layer 110 is disposed on a substrate in the subpixel of the OLED display according to the embodiment of the present invention. The first buffer layer 110 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

A semiconductor layer (ACT) is located on the first buffer layer (110). The semiconductor layer ACT forms a source electrode and a drain electrode of the driving transistor DT and the first to sixth transistors T1 to T6. The semiconductor layer ACT may be formed of a silicon semiconductor or an oxide semiconductor. As the impurity of the semiconductor layer (ACT), at least one p-type impurity of boron (B), aluminum (Al), gallium (Ga) and indium (In) can be used.

A gate insulating film 120 is disposed on the semiconductor layer ACT. The gate insulating film 120 may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof. Gate metal layers SL1 [N], SL2 [N], and SL2 [N-1] are located on the gate insulating film 120. [ The gate metal layer includes a first scan line SL1 [N], a second scan line SL2 [N-1], and SL2 [N]. The region where the semiconductor layer ACT overlaps with the gate metal layer is defined as the gate electrodes G11, G1 to G6 of the respective transistors DT, T1 to T6. The gate metal layer may be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper .

A second insulating layer 130 and a third insulating layer 140 are located on the gate metal layer. The second and third insulating films 130 and 140 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

After the third insulating layer 140 is formed, the first to third insulating layers 120, 130 and 140 are selectively etched to form contact holes. A part of the semiconductor layer ACT11 of the driving transistor DT is exposed by the contact hole.

The drain electrode C and the source electrode A of the driving transistor DT formed in the contact hole are located on the third insulating layer 160. The source electrode A may be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) Based alloy.

A fourth insulating layer 150 is located on the source electrode 221. The fourth insulating film 170 may be a planarizing film for alleviating the step difference of the lower structure and may be formed of organic materials such as polyimide, benzocyclobutene series resin, and acrylate.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the appended claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
DL: Data line 15: Gate line

Claims (6)

An organic light emitting diode display comprising a plurality of subpixels including an organic light emitting diode and a driving transistor for driving the organic light emitting diode,
The plurality of sub-
A first column of subpixels comprising a first voltage supply line;
A second column of subpixels sharing the first voltage supply line with the subpixels of the first column;
A third column of subpixels including a second voltage supply line; And
And a fourth column of subpixels sharing the second voltage supply line with the subpixels of the third column,
Wherein the first and fourth columns of subpixels represent a first color,
And the subpixels in the second and third columns display a second color or a third color. The method according to claim 1,
Wherein the first color has a highest luminance ratio among R, G, and B colors. 3. The method of claim 2,
Pixels of the odd-numbered rows among the pixels of the second column and the third column display the second hue, and pixels of the odd-th row display the third hue. The method according to claim 1,
a pair of subpixels sharing the first voltage supply line in an ith row; And
a pair of subpixels sharing the first voltage supply line in the (i + 1) th row constitute one pixel, and the organic light emission in which the R, G, and B color subpixels are included in the pixel Display device. The method according to claim 1,
Wherein the first and second voltage supply lines supply a high potential voltage, respectively. 6. The method of claim 5,
Wherein the driving transistor includes a first electrode for receiving a high voltage from the first or second voltage supply line, and a second electrode connected to an anode electrode of the organic light emitting diode.

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