KR102332424B1 - Electroluminscence display - Google Patents

Abstract

An electroluminescent display device according to an embodiment of the present specification includes a high potential driving voltage; A display panel comprising: an electroluminescent device supplied with a high potential driving voltage; and a display panel in which a plurality of pixels including a driving transistor for controlling a driving current flowing through the electroluminescent device are disposed, wherein the display panel is close to an input terminal of the high potential driving voltage The first sampling period for compensating the electrical characteristics of the driving transistor in the A region is different from the second sampling period for compensating the electrical characteristics of the driving transistor in the B region farther than the A region.

Description

ELECTROLUMINSCENCE DISPLAY

The present specification relates to an active matrix type electroluminescent display device.

The active matrix type electroluminescent display device includes an organic light emitting diode (OLED) that emits light by itself, and has advantages of fast response speed, luminous efficiency, luminance, and a large viewing angle.

An organic electroluminescent device (OLED), which is a self-luminous device, has a structure as shown in FIG. 1 . An organic electroluminescent device (OLED) includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode and cathode electrodes, holes passing through the hole transport layer (HTL) (indicated by + in the figure) and electrons passing through the electron transport layer (ETL) (indicated by - in the figure) are converted into the light emitting layer (EML). It moves to form excitons, and as a result, the emission layer EML generates visible light.

An electroluminescent display device arranges pixels each including an electroluminescent element in a matrix form, and adjusts the luminance of the pixels according to the gray level of video data. Each of the pixels has a driving transistor (Thin Film Transistor) that controls the driving current flowing through the electroluminescent device according to the gate-source voltage, a capacitor that keeps the gate-source voltage of the driving transistor constant for one frame, and a gate signal. and at least one switch transistor responsive to programming a gate-to-source voltage of the driving transistor. The driving current is determined by the gate-source voltage of the driving transistor according to the data voltage, and the luminance of the pixel is proportional to the size of the driving current flowing through the electroluminescent device.

The electroluminescent display device has advantages such as high contrast ratio and color gamut. However, in an actual display panel, the luminance of the entire panel may become non-uniform due to wiring resistance or the like.

In the above-described electroluminescent display device, IR drop may occur due to wiring resistance. Referring to FIG. 2 , the wiring resistance increases as the panel is positioned farther from the input terminal of the high potential driving voltage. Since an IR drop occurs when the wiring resistance increases, the high potential driving voltage VDD required for the driving transistor may vary depending on the spatial location. That is, since the IR drop is larger in the region farther from the high potential driving voltage supply unit, the high potential driving voltage applied to the far region becomes smaller than the high potential driving voltage actually required for the pixel. For this reason, in the prior art, as the distance from the input terminal of the high potential driving voltage increases, the luminance decreases and the luminance of the entire panel becomes non-uniform.

Accordingly, an object to be solved according to an embodiment of the present specification is to provide an electroluminescent display device capable of improving luminance uniformity by solving a problem in which luminance decreases due to an increase in wiring resistance in a region farther from the supply of a high potential driving voltage. will be.

In addition, an object to be solved according to an exemplary embodiment of the present specification is to provide an electroluminescent display device capable of compensating for reduced luminance due to IR drop by adjusting a gate signal for each gate line of the electroluminescent display device.

In addition, an object to be solved according to an exemplary embodiment of the present specification is to provide an electroluminescent display device capable of ensuring luminance uniformity by dividing a screen into a plurality of blocks and compensating for luminance in units of blocks.

The tasks of the present specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

An electroluminescent display device according to an embodiment of the present specification includes a plurality of driving transistors including an electroluminescent device receiving a high potential driving voltage (VDD), a high potential driving voltage, and a driving transistor controlling a driving current flowing through the electroluminescent device. A display panel comprising: a display panel in which pixels are disposed, wherein the display panel includes a first sampling period for compensating for electrical characteristics of a driving transistor of region A close to an input terminal of a high potential driving voltage, and a distance from the input terminal of region B farther than region A The second sampling period for compensating the electrical characteristics of the driving transistor of the region is different from each other.

In the electroluminescent display device according to an embodiment of the present specification, a plurality of pixels, gate lines and emission lines connected to the pixels along a row direction, and data lines connected to the pixels along a column direction are disposed. a display panel to be used, a high potential driving low voltage (VDD) supplying a driving voltage to the pixels, and a gate driving unit supplying a gate signal to the gate lines, wherein the gate driving unit displays the display according to a distance from an input terminal of the high potential driving voltage The width of the gate signal is controlled so that the sampling period for compensating for the electrical characteristics of the driving transistor of the panel is varied.

According to an exemplary embodiment of the present specification, since the sampling period of the driving transistor of the display panel is set differently according to the distance from the input terminal of the high potential driving voltage, the luminance is decreased due to an increase in wiring resistance in a region farther from the supply of the high potential driving voltage. Since the problem can be solved, the luminance uniformity can be improved.

In addition, according to an exemplary embodiment of the present specification, it is possible to compensate for reduced luminance due to IR drop by adjusting the gate signal of the electroluminescent display device.

In addition, according to an embodiment of the present specification, the luminance uniformity can be improved by dividing the screen of the electroluminescent display into a plurality of blocks and compensating for luminance in units of blocks.

The tasks of the present specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a view for explaining a light emitting principle of an electroluminescent device.
FIG. 2 is a diagram illustrating a luminance non-uniformity phenomenon of an electroluminescent display device;
3 is a view showing an electroluminescent display device according to an embodiment of the present specification.
4 is an equivalent circuit diagram showing a pixel structure of the present specification.
5 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 4;
6A, 6B, and 6C are equivalent circuit diagrams of pixels corresponding to the initial period, the sampling period, and the emission period of FIG. 5, respectively;
7 is a diagram illustrating voltage values for nodes A, B, and C of a pixel in an initial period, a sampling period, and an emission period;
8 is a block diagram illustrating a gate driver according to an embodiment of the present specification.
9 is a waveform diagram showing a gate signal of an electroluminescent display device according to an embodiment of the present specification;
10 is a view showing a screen division method for luminance correction of an electroluminescent display device according to an embodiment of the present specification;
11 is a view showing a luminance measurement point of an electroluminescent display device;
12 is a table showing measurement values at the luminance measurement points of FIG. 12 of the electroluminescent display device according to the embodiment of the present specification.
FIG. 13 is a table showing measured values at the luminance measurement points of FIG. 12 of the electroluminescent display device according to a comparative example;
14 is a diagram illustrating a gate signal correction point of an electroluminescent display device according to an embodiment of the present specification;
15 is a waveform diagram showing a gate signal input to the electroluminescent display device of FIG. 14;
16 is a diagram illustrating a gate signal correction point of an electroluminescent display device according to another exemplary embodiment of the present specification.
17 is a waveform diagram showing a gate signal input to the electroluminescent display device of FIG. 16;

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Although the embodiment of the present specification describes a case where all of the transistors constituting the pixel are implemented as a P-type, the technical spirit of the present specification is not limited thereto and may be applied to a case where the transistors are implemented as an N-type.

Hereinafter, embodiments of the present specification will be described with reference to the accompanying drawings.

3 is a block diagram of an electroluminescent display device according to an embodiment of the present specification.

The electroluminescent display device according to the embodiment includes a display panel 10 in which pixels PXL are arranged in a matrix form, a data driver 12 for driving a data line 14 , a gate line GL, and an EMI. It includes a gate driver 13 for driving the shun line EL, and a timing controller 11 for controlling driving timings of the data driver 12 and the gate driver 13 .

A plurality of pixels PXL are disposed on the display panel 10 , and each pixel is connected to a data line 14 , a gate line GL, and an emission line EL. The data lines 14 are arranged in a column direction, and transfer the data voltage received from the data driver 12 to the pixels PXL. The first gate lines GL1 to n-th gate lines GL(n) are arranged in pixel rows R#1 to R#(n) (n is a natural number) in the row direction, respectively, and the gate driver The gate voltage provided in (13) is transferred to the pixels PXL. The first emission line EL1 to the n-th emission line EL(n) are arranged in the pixel rows R#1 to R#(n) in the row direction, respectively, and the gate driver 13 . The emission voltage received from the pixel PXL is transferred to the pixels PXL.

The pixels PXL may receive the high and low potential driving voltages VDD and VSS and the initial voltage Vini in common from the power generator. The initial voltage Vini may be selected within a range sufficiently lower than the low potential driving voltage to prevent unnecessary light emission of the organic light emitting diode OLED.

Transistors constituting the pixel PXL may be implemented as transistors including an oxide semiconductor layer. The oxide semiconductor layer may be advantageous in increasing the area of the display panel 10 in consideration of electron mobility, process variation, and the like. In the case of forming the oxide semiconductor, it may be formed of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), or Indium Tin Zinc Oxide (ITZO), but is not limited thereto. The present specification is not limited thereto, and the semiconductor layer of the transistor may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an organic semiconductor.

Each of the pixels PXL includes a plurality of transistors and capacitors to compensate for a threshold voltage change of the driving transistor. A pixel structure according to an exemplary embodiment of the present specification will be described later.

The timing controller 11 rearranges digital video data RGB input from the outside to match the resolution of the display panel 10 and supplies it to the data driver 12 . In addition, the timing controller 11 is a data driver 12 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. A data control signal DDC for controlling the operation timing of , and a gate control signal GDC for controlling the operation timing of the gate driver 13 are generated.

The data driver 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DDC. The data driver 12 supplies a data voltage to the data line 14 . In this case, the data voltage may be a value corresponding to an image signal to be displayed by the organic light emitting diode.

The gate driver 13 generates a gate signal and an emission signal based on the gate control signal GDC. The gate driver 13 sequentially provides the gate signal to the gate line GL and sequentially provides the emission signal EM(j) to the emission line EL. That is, the gate driver 13 sequentially provides the gate signal GCLK from the first gate line GL1 to the n-th gate line GL(n), and applies the emission signal EM(j) to the first gate line GL(n). It is sequentially provided from the emission line EL1 to the n-th emission line EL(n). The gate driver 13 may be directly formed on the non-display area of the display panel 10 according to a gate-driver in panel (GIP) method.

4 is an equivalent circuit diagram showing a pixel structure of the present specification. 5 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 3 .

Referring to FIG. 4 , each pixel PXL disposed in an n-th pixel row (where n is a natural number) includes an organic light emitting diode OLED, a driving transistor DT, a first transistor T1, and a second transistor T2. , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a capacitor Cstg.

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. A multi-layered organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer may include at least one hole transport layer and an electron transport layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects or transports holes to the emission layer, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (Electron). blocking layer, EBL), but is not limited thereto. In addition, the electron transport layer is a layer that injects or transfers electrons to the light emitting layer, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer (Hole). blocking layer, HBL), but is not limited thereto. The anode electrode of the organic light emitting diode OLED is connected to the node C, and the cathode electrode of the organic light emitting element is connected to the input terminal of the low potential driving voltage VSS.

The driving transistor DT controls a driving current applied to the organic light emitting diode OLED according to its source-gate voltage Vsg. The gate electrode of the driving transistor DT is connected to the node A, the source electrode is connected to the node D, and the drain electrode is connected to the node B.

The first transistor T1 is connected between the data line 14 and the node D, and is turned on/off according to the n-th gate signal GCLK(n). The gate electrode of the first transistor T1 is connected to the n-th first gate line to which the n-th gate signal GCLK(n) is applied, and the source electrode of the first transistor T1 is connected to the data line 14 . and the drain electrode of the first transistor T1 is connected to the node D.

The second transistor T2 is connected between the node D and the input terminal of the high potential driving voltage VDD, and is turned on/off according to the n-th emission signal EM(n). The gate electrode of the second transistor T2 is connected to the n-th first emission line to which the n-th emission signal EM(n) is applied, and the source electrode of the second transistor T2 has a high potential driving voltage ( VDD), and the drain electrode of the second transistor T2 is connected to the node D.

The third transistor T3 is connected between the node A and the node B, and is turned on/off according to the n-th gate signal GCLK(n). The gate electrode of the third transistor T3 is connected to the n-th first gate line to which the n-th gate signal GCLK(n) is applied, the source electrode of the third transistor T3 is connected to the node A, and 3 The drain electrode of the transistor T3 is connected to the node B. Here, the third transistor T3 may be referred to as a sampling transistor.

The fourth transistor T4 is connected between the node B and the node C, and is turned on/off according to the n-th emission signal EM(n). The gate electrode of the fourth transistor T4 is connected to the n-th first emission line to which the n-th emission signal EM(n) is applied, and the source electrode of the fourth transistor T4 is connected to the node B. , the drain electrode of the fourth transistor T4 is connected to the node C. Here, the fourth transistor T4 may be referred to as an emission transistor.

The fifth transistor T5 is connected between the node A and the input terminal of the initial voltage Vini, and is turned on/off according to the n-1 th gate signal GCLK(n-1). The gate electrode of the fifth transistor T5 is connected to the n-1 th gate line to which the n-1 th gate signal GCLK(n-1) is applied, and the source electrode of the fifth transistor T5 is a node It is connected to A, and the drain electrode of the fifth transistor T5 is connected to the input terminal of the initial voltage Vini. Here, the fifth transistor T5 may be referred to as a first initial transistor.

The sixth transistor T6 is connected between the input terminal of the initial voltage Vini and the node C. The gate electrode of the sixth transistor T6 is connected to the n-1 th gate line to which the n-1 th gate signal GCLK(n-1) is applied, and the source electrode of the sixth transistor T6 is a node It is connected to C, and the drain electrode of the sixth transistor T6 is connected to the input terminal of the initial voltage Vini. Here, the sixth transistor T6 may be referred to as a second initial transistor.

The capacitor Cstg is connected between the node A and the input terminal of the initial voltage Vini.

An operation of the pixel of FIG. 4 will be described with reference to FIGS. 5 to 7 . FIG. 5 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 4 . 6A, 6B, and 6C are equivalent circuit diagrams of pixels operating in the initial period, sampling period, and emission period of FIG. 5, respectively. 7 is a diagram illustrating voltage values for nodes A, B, and C of a pixel in an initial period, a sampling period, and an emission period.

As shown in FIG. 5, one frame period includes an initial period Pi for initializing nodes A and C, a sampling period Ps for sampling and storing the threshold voltage of the driving transistor DT in the node A, and Emission period Pe for programming the source-gate voltage of the driving transistor DT including the sampled threshold voltage and emitting light from the organic light emitting diode OLED with a driving current according to the programmed source-gate voltage can be divided into Here, the low level is the on level (LON), and the high level is the off level (LOFF). Hereinafter, for ease of description, a low level will be described as an on level (LON) and a high level as an off level (LOFF) will be described below.

In FIG. 6A , a transistor operating in the initial period Pi is shown by a solid line, and a transistor not operating in the initial period Pi is shown by a dotted line. 5 and 6A , in the initial period Pi, the n-1 th gate signal GCLK(n-1) is applied to the on level LON, and the n th gate signal GCLK(n)) and the n-th emission signal EM(n) are applied at an off level LOFF. In the initial period Pi, the fifth and sixth transistors T5 and T6 are turned on in response to the n-1 th gate signal GCLK(n-1), so that the nodes A and C are connected to the initial voltage Vini ) is initialized to At this time, the gate electrodes of the fifth and sixth transistors T5 and T6 are connected to the gate electrode of the pixel disposed in the n-1 th row, so that the sampling period of the threshold voltage Vth of the driving transistor DT is sufficiently secured. Thus, the accuracy of threshold voltage compensation can be improved. That is, since the node A and the node C are initialized prior to the sampling operation, the reliability of sampling may be improved and unnecessary light emission of the OLED may be prevented.

In FIG. 6B , transistors operating in the sampling period Ps are shown as solid lines, and non-operating transistors are shown by dotted lines. 5 and 6B , in the sampling period Ps, the n-th gate signal GCLK(n) is applied to the on level LON, and the n-th gate signal GCLK(n-1)) and the n-th emission signal EM(n) are applied at an off level LOFF. During the sampling period Ps, the first and third transistors T1 and T3 are turned on in response to the n-th gate signal GCLK(n), so that the driving transistor DT is connected to a diode connection (a gate electrode). and the drain electrode are shorted so that the transistor operates like a diode), and a data voltage Vdata(m) is applied to the node D.

Therefore, in the sampling period Ps, a current Ids flows between the source and the drain of the driving transistor DT, and the potential of the node A is changed from the initial voltage Vini in the initialization state by the current Ids to the data voltage. (Vdata(m)) is increased to a value (Vdata(m)-Vth) obtained by subtracting the threshold voltage of the driving transistor DT. The initial voltage Vini is equal to or lower than the low potential driving voltage VSS. The voltage value of the node A, which is the gate electrode of the driving transistor DT, includes the threshold voltage Vth of the driving transistor DT, and thus the threshold voltage Vth of the driving transistor DT in the subsequent emission period Pe. ) can generate a driving current in the erased state.

In FIG. 6C , a transistor operating in the emission period Pe is shown by a solid line, and a transistor not operating is shown by a dotted line. 5 and 6C , in the emission period Pe, the n-th emission signal EM(n) is applied to the on level LON, and the n-1 th gate signal GCLK(n-1) )) and the n-th gate signal GCLK(n) are applied at an off level LOFF. In the emission period Pe, the second transistor T2 is turned on in response to the n-th emission signal EM(n) to connect the high potential driving voltage VDD to the source electrode of the driving transistor DT. do. In addition, the fourth transistor T4 is turned on in response to the n-th emission signal EM(n) so that the potentials of the nodes B and C are equal to the operating voltage Voled of the organic light emitting diode OLED. .

At this time, the fourth transistor T4 is connected to the anode electrode of the organic light emitting device and is turned off during the initial period Pi and the sampling period Ps other than the emission period Pe, and thus is turned off during the period other than the emission period Pe. It is possible to block the leakage current flowing to the organic light emitting device during the period. A relational expression for the driving current Ioled flowing through the organic light emitting diode OLED in the emission period Pe is expressed by Equation 2 below. The organic light emitting diode (OLED) realizes a desired display gradation by emitting light by a driving current.

[Equation 1]

I _OLED =k/2(Vsg-Vth) ² = k/2((Vs-Vg)-Vth) ² = k/2((VDD-(Vdata-Vth)) - Vth) ² = k/2(VDD -Vdata) ²

In Equation 1, k/2 indicates a proportional constant determined by electron mobility, parasitic capacitance, and channel capacity of the driving transistor DT.

The driving current (Ioled) equation is k/2(Vsg-Vth) ² . Since the threshold voltage (Vth) component of the driving transistor DT is already included in Vsg programmed through the emission period Pe, the equation As shown in 1, the threshold voltage Vth component of the driving transistor DT in the relational expression of the driving current Ioled is erased. Accordingly, the influence of the threshold voltage Vth change on the driving current Ioled may be minimized.

7 is a table showing the voltage values input to the nodes A, B, and C in the initial period Pi, the sampling period Ps, and the emission period Pe described in 6a to 6c. The node A that has passed through the sampling period Ps includes the threshold voltage Vth component of the driving transistor DT, so that when the organic light emitting diode emits light in the emission period Pe, the driving current of the driving transistor DT (Ioled) may represent a desired display grayscale by erasing the threshold voltage (Vth) component.

On the other hand, when the sampling period Ps is shortened, the voltage sampled at the node A is sampled at a voltage lower than (Vdata-Vth). When the sampling period is shortened and the voltage sampled at the node A is expressed as (Vdata-Vth-α), Equation 1 can be expressed as follows.

[Equation 2]

I _OLED =k/2(Vsg-Vth) ² = k/2((Vs-Vg)-Vth) ² = k/2((VDD-(Vdata-Vth-α)) - Vth) ²

In Equation 2, the variable α is a variable according to the change of the sampling period, and when the sampling period is sufficiently secured, the node A converges to (Vdata-Vth), so that α=0. On the other hand, when sampling is shortened, node A is charged with a voltage lower than (Vdata-Vth), so node A can be expressed as Vdata-Vth-α.

When the node A is Vdata-Vth-α, calculated by substituting into Equation 2 above, it is k/2(VDD-Vdata+α) ^{2 ,} so _{a larger current flows through the I OLED} than the intended current, and as a result, the luminance is increased. . The table shows the voltage at each node as follows.

[graph]

As described above, when the sampling time is reduced _{, the current flowing through the I OLED} becomes k/2(VDD-Vdata+α) ² , and a larger current flows through the I _OLED than the intended current. As a result, the luminance of the corresponding pixel increases. will do By using this characteristic, the luminance may be compensated for by reducing the sampling period of the driving transistor DT in the region where the luminance is decreased due to the IR drop.

FIG. 8 is a diagram illustrating the configuration of the gate driver 13 of FIG. 2 .

The gate driver may generate and supply gate signals to the gate lines in a row-sequential manner to drive at least one gate line connected to each pixel row. The gate driver includes a shift register. The shift register includes subordinately connected A stages (A stages, S1(1) to S1(n+1)). The emission driver may generate an emission signal in a row-sequential manner to drive at least one emission line connected to each pixel row and supply the emission signal to the emission lines. The emission driving unit includes an inverter. The inverter includes dependently connected B stages (B stages, EM Inv.(1) to EM Inv.(n+1)).

Stages A (S1(1) to S1(n+1)) and stages B (EM Inv.(1) to EM Inv.(n+1)) are symmetrical with respect to an active area in which an image is displayed and are active It may be disposed on either side of the area.

For example, when n is 2, the A stage S1(n-1) simultaneously outputs the n-1 th gate signal GCLK(n-1) in response to the start signal GVST. When n is 2 or more, the A stage (S1(n-1)) outputs a carry signal separate from the n-1th gate signal GCLK(n-1) to form the next start pulse GVST. It can be simultaneously supplied to the stage A stage (S1(n)). The carry signal may be input as a start pulse of the next stage.

The n-1 th gate signal GCLK(n-1) is simultaneously supplied to each of the n-1 th gate line of the n-1 th pixel and the n-1 th gate line of the n th pixel while in the B stage (EM Inv. ( n)) and stage A (S1(n)).

When the n-1 th gate signal GCLK(n-1) is supplied to the B stages EM Inv.(n), the n-1 th gate signal GCLK(n-1) is synchronized with the n-1 th gate signal GCLK(n-1). The n-th emission signal EM(n) inverted to the gate signal GCLK(n-1) is simultaneously supplied to the emission line of the n-th pixel.

Stage A (S1(n)) is a start signal when an n-1 th gate signal GCLK(n-1) is supplied or an n-1 th gate signal GCLK(n-1) and a carry signal are supplied. The n-th gate signal GCLK(n) is simultaneously supplied to the n-th gate line of the n-th pixel in response to gate timing control signals such as (GVST) and clock GCLK.

The n-th gate signal GCLK(n) is simultaneously supplied to each of the n-th gate line of the n-th pixel and the n-th gate line of the n+1-th pixel, and the B stage (EM Inv. (n+1)) and the A stage is supplied to (S1(n+1)).

When the n-th gate signal GCLK(n) is supplied to the B stages EM Inv.(n+1), the n-th gate signal GCLK(n) is synchronized with the n-th gate signal GCLK(n). The n+1-th emission signal EM(n+1), which is inverted to , is simultaneously supplied to the emission line of the n+1-th pixel.

The A stages S1(n+1) receive a start signal GVST and a clock The n+1th gate signal GCLK(n+1) corresponding to gate timing control signals such as GCLK) is simultaneously supplied to the n+1th gate line of the n+1th pixel.

As described above, the gate driver may supply a gate signal to each gate line.

Hereinafter, a method for reducing the sampling period will be described. The gate driver according to the embodiment of the present specification may control the width of the gate signal so that the sampling period for compensating the electric characteristic of the driving transistor of the display panel is varied according to the distance from the input terminal of the high potential driving voltage.

The gate driver may reduce the width of the gate signal so that the sampling period is shortened as the distance from the input terminal of the high potential driving voltage increases, and the same sampling period is maintained up to a certain distance, and after a certain distance, the input terminal of the high potential driving voltage is reduced. The width of the gate signal may be reduced so that the sampling period may be shortened as the distance from the gate increases.

As another embodiment, the gate driver may differently set a point at which the width of the gate signal is reduced when the even frame is displayed and when the odd frame is displayed.

Reducing the width of the gate signal is to improve the luminance by shortening the sampling period of the driving transistor. Various points on the display panel may be set as the starting point according to the region to compensate for the luminance, thereby reducing the width of the gate signal. .

9 illustrates a gate signal waveform of an electroluminescence display according to an embodiment of the present specification.

The gate driver may reduce the width of the gate signal so that the sampling period is shortened as the distance from the input terminal of the high potential driving voltage increases. 9 illustrates a waveform in which the width of the gate signal GCLK sequentially decreases after the first gate line after the vertical synchronization signal VSYNC and the start signal GVST are input. The gate line at which the width of the gate signal starts to decrease may be set in various ways according to IR drop characteristics of the display panel. Also, it is possible to reduce the width of the gate signal in units of a plurality of gate lines.

10 is a diagram illustrating a screen region division state for luminance correction of an electroluminescent display device according to an embodiment of the present specification. According to a screen division method for luminance correction of an electroluminescent display device according to an embodiment of the present specification, The display panel can be controlled by dividing it into 8 areas (①~⑧).

The input terminal of the high potential driving voltage VDD may be positioned at one side of the display panel to supply the high potential driving voltage to the electroluminescent device of each pixel. As the distance from the input terminal of the high potential driving voltage increases, the resistance increases and the IR drop increases. Accordingly, the region for luminance correction may be divided based on the distance from the input terminal of the high potential driving voltage.

Among the eight regions (① to ⑧), the first region (①) closest to the input terminal of the high potential driving voltage has the smallest IR drop, and the farthest eighth region (⑧) has the largest IR drop. Accordingly, even when data having the same luminance is input, the luminance of the displayed data may gradually decrease toward the eighth region ⑧.

Accordingly, the gate driver reduces the difference in luminance between the first region (①) and the eighth region (⑧) by controlling the sampling period of the driving transistor to sequentially decrease from the first region (①) to the eighth region (⑧). can do it In order to sequentially decrease the sampling period of the driving transistor, the gate driver has a width of the gate signal from the gate signal (①GCLK) input to the first region (①) to the gate signal (⑧GCLK) input to the eighth region (⑧). (width, W) can be gradually decreased. That is, the width of the gate signal input to the first region (①) is the largest and the width of the gate signal input to the eighth region (⑧) is the smallest (①W > ②W > ③W > ④W > ⑤W > ⑥W > ⑦W > ⑧W ).

11 to 13 show experimental results of comparing the luminance uniformity of the electroluminescent display device according to the embodiment of the present specification with the luminance uniformity of the electroluminescent display device according to the experimental example. 11 is a view showing luminance measurement points on a display panel, FIG. 12 is a table showing luminance measurement values of an electroluminescent display device according to an embodiment of the present specification, and FIG. 13 is an electroluminescent display device according to an experimental example. This is a table showing the luminance measurement values.

11 , the display area of the display panel may be divided in horizontal and vertical directions, and nine points at which horizontal and vertical dividing lines intersect may be set as luminance measurement points. Each of the points may be set three at the same distance as the input terminal of the high potential driving voltage. The luminance measurement experiment may be performed by measuring a luminance value at each point while displaying data of the same luminance on the entire display panel.

The table of FIG. 12 shows luminance values measured when the sampling period of the driving transistor is adjusted so that the sampling period of the driving transistor is sequentially decreased as it goes away from the input terminal of the high potential driving voltage according to the embodiment of the present specification. As a result of calculating the deviation by measuring the luminance value at each measurement point, in the case of the display panel to which the present invention is applied, the luminance uniformity was calculated to be 96.29%.

The table of FIG. 13 is a result of measuring the luminance uniformity of the display panel according to the experimental example. In the experimental example, the width of the gate signal was not adjusted. In the display panel according to the experimental example, when the luminance value at each point was measured while displaying data of the same luminance over the entire display panel, the luminance uniformity was calculated to be 90.31%.

Accordingly, in the case of the display panel to which the present invention is applied, it can be confirmed that the luminance uniformity is increased by about 6% compared to the display panel of the experimental example.

14 and 15 illustrate an electroluminescent display device according to another exemplary embodiment of the present specification. 14 is a diagram illustrating a sampling signal correction point according to another exemplary embodiment of the present specification, and FIG. 15 is a waveform diagram illustrating a gate signal input to the electroluminescent display device of FIG. 14 .

According to another embodiment of the present specification, the sampling period may be controlled to sequentially decrease from a point spaced apart by a set distance from the input terminal of the high potential driving voltage.

In the embodiment described with reference to FIGS. 9 and 10 , the sampling period of the driving transistor is controlled to decrease sequentially from the first region (①) to the eighth region (⑧), and the embodiment according to FIGS. 14 and 15 is controlled such that the sampling period is sequentially decreased from a specific point, for example, the fourth region (④).

When the sampling period is sequentially decreased immediately from the input terminal of the high potential driving voltage, the width of the gate signal is decreased, so that the luminance of the region most spaced apart from the input terminal of the high potential driving voltage is increased. Accordingly, a luminance reversal phenomenon in which luminance is higher than that of the high potential driving voltage input terminal may occur.

To prevent this, the width of the gate signal is maintained the same from the first region (①) to the fourth region (④), and the width (W) of the gate signal input from the fourth region (④) to the eighth region (⑧) is ) can be gradually reduced. Comparing the width of the gate signal in each area, it can be expressed as "①W = ②W = ③W = ④W > ⑤W > ⑥W > ⑦W > ⑧W".

As described above, by controlling the width of the gate signal from the middle region and limiting the luminance compensation region to a specific region, the luminance of the region most spaced apart from the input terminal of the high potential driving voltage is excessively compensated to prevent the luminance from being reversed.

16 and 17 illustrate an electroluminescent display device according to another exemplary embodiment of the present specification. FIG. 16 is a diagram illustrating a concept of adjusting the width of a gate signal according to another embodiment of the present invention, and FIG. 17 is a waveform diagram showing a gate signal input to the electroluminescence display of FIG. 16 .

According to another exemplary embodiment of the present specification, for an even frame and an odd frame, the width of the gate signal is set to decrease from different regions. For example, when displaying an even frame, the width of the gate signal is shortened from the third area (③), and when displaying an odd frame (Odd Frame), the gate signal starts from the fourth area (④). width can be shortened.

Therefore, if the width of the gate signal in each area is compared when displaying an even frame, it can be expressed as "①W = ②W > ③W > ④W > ⑤W > ⑥W > ⑦W > ⑧W".

Comparing the width of the gate signal in each area when displaying odd frames, it can be expressed as "①W = ②W = ③W > ④W > ⑤W > ⑥W > ⑦W > ⑧W".

If the gate signal width is set to decrease from different regions for an even frame and an odd frame, the luminance level may vary depending on the frame being displayed even in the same region. As a result, a step difference between regions displayed with the same luminance is prevented from being visually recognized, thereby further improving luminance uniformity.

In addition, the source electrode and the drain electrode of the transistors mentioned in the above description may be applied interchangeably. In particular, it may be applied to the first to sixth transistors serving as on/off functions other than the driving transistor DT.

In addition, the electroluminescent display device of the present specification is a display device including a TV, a mobile device, a tablet PC, a monitor, a smart watch, a laptop computer, and a vehicle display device, etc. can be applied. And, it can be applied to a display device implemented in various forms, such as a flat display, a bandable display, a foldable display, a wearable display, and a rollable display.

The electroluminescent display device according to the embodiment of the present specification may be described as follows.

An electroluminescent display device according to an embodiment of the present specification includes a high potential driving voltage; A display panel comprising: an electroluminescent device supplied with a high potential driving voltage; and a display panel in which a plurality of pixels including a driving transistor for controlling a driving current flowing through the electroluminescent device are disposed, wherein the display panel is close to an input terminal of the high potential driving voltage The first sampling period for compensating the electrical characteristics of the driving transistor of the region A and the second sampling period for compensating the electrical characteristics of the driving transistor of the region B farther than the region A may be different from each other.

The first sampling period may be maintained constant, and the second sampling period may be gradually decreased as the distance from the input terminal of the high potential driving voltage increases.

Regions A and B when the display panel displays even frames and regions A and B when displaying odd frames may be different from each other.

The display panel may further include a gate driver supplying a gate signal to the display panel, and the gate driver may vary the width of the gate signal so that the first sampling period and the second sampling period are different.

The gate driver maintains a constant width of the gate signal provided to the region A, and the gate signal provided to the region B may have a smaller width as it moves away from the input terminal of the high potential driving voltage.

Region A and region B are divided into a plurality of regions according to a distance from the input terminal of the high potential driving voltage, and driving transistors included in the same region may have the same sampling period.

The electroluminescent display device according to the embodiment of the present specification includes a plurality of pixels, gate lines and emission lines connected to the plurality of pixels along a row direction, and data connected to a plurality of pixels along a column direction. a display panel on which lines are disposed; a high potential driving voltage supplying a driving voltage to the plurality of pixels; and a gate driver supplying a gate signal to the gate lines, wherein the gate driver adjusts the width of the gate signal so that the sampling period of the driving transistor of the display panel varies according to a distance from the input terminal of the high potential driving voltage.

The gate driver may decrease the width of the gate signal as the distance from the input terminal of the high potential driving voltage increases.

The gate driver may reduce the width of the gate signal from a region that is separated from the high potential driving voltage by a predetermined distance or more.

The gate driver may reduce the width of the gate signal from points having different distances from the high potential driving voltage when the display panel displays an even frame and an odd frame.

The gate driver may divide the display panel into a plurality of regions according to a distance from the input terminal of the high potential driving voltage, and supply gate signals to driving transistors included in the same region to have the same sampling period.

The display panel may sample and store the threshold voltage of the driving transistor according to the gate signal input from the gate driver.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: data driver 13: gate driver
14: data line

Claims (12)

high potential driving voltage;
a display panel including a plurality of pixels including an electroluminescent device receiving the high potential driving voltage and a driving transistor controlling a driving current flowing through the electroluminescent device;
The display panel is
A first sampling period for compensating for electrical characteristics of the driving transistor in region A, which is close to the input terminal of the high potential driving voltage, and driving of region B, in which the distance to the input terminal of the high potential driving voltage is greater than that of region A An electroluminescent display device having a different second sampling period for compensating for electrical characteristics of a transistor.
According to claim 1,
The first sampling period is maintained constant and the second sampling period gradually decreases as the distance from the input terminal of the high potential driving voltage increases.
According to claim 1,
The region A and region B when the display panel displays even frames and region A and region B when the display panel displays odd frames are different from each other.
According to claim 1,
Further comprising a gate driver for supplying a gate signal to the display panel,
The gate driver varies the width of the gate signal so that the first sampling period and the second sampling period are different from each other.
5. The method of claim 4,
The gate driver,
maintaining a constant width of the gate signal provided to the region A;
The width of the gate signal provided to the region B becomes smaller as the distance from the input terminal of the high potential driving voltage increases.
According to claim 1,
The region A and the region B are divided into a plurality of regions according to a distance from the input terminal of the high potential driving voltage, and driving transistors included in the same region have the same sampling period.
a display panel in which a plurality of pixels, gate lines connected to the plurality of pixels in a row direction, and data lines connected to the plurality of pixels in a column direction are disposed;
a high potential driving voltage supplying a driving voltage to the plurality of pixels; and
a gate driver supplying a gate signal to the gate lines;
The gate driver adjusts the width of the gate signal so that the sampling period of the driving transistor of the display panel varies according to a distance from the input terminal of the high potential driving voltage.
8. The method of claim 7,
The gate driver,
An electroluminescence display device for decreasing a width of the gate signal as the distance from the input terminal of the high potential driving voltage increases.
8. The method of claim 7,
The gate driver,
An electroluminescent display device for reducing the width of the gate signal from a region that is separated from the high potential driving voltage by a predetermined distance or more.
8. The method of claim 7,
The gate driver,
An electroluminescence display device for reducing a width of the gate signal from points having different distances from the high potential driving voltage when the display panel displays even-numbered frames and odd-numbered frames.
8. The method of claim 7,
The gate driver,
The display panel is divided into a plurality of regions according to a distance from the input terminal of the high potential driving voltage, and the driving transistors included in the same region supply the gate signal to have the same sampling period.
8. The method of claim 7,
The display panel is
An electroluminescent display device for sampling and storing a threshold voltage of the driving transistor according to the gate signal input from the gate driver.

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