KR102328985B1 - Electroluminescent Display Device - Google Patents

Abstract

An electroluminescent display device includes a display panel in which a plurality of pixels are disposed. Here, each of the pixels, a light emitting device; a driving device for adjusting the current of the light emitting device to a gate-source voltage; a first switch TFT for turning on/off the flow of current between the gate electrode of the driving element and the data line; and a second switch TFT for turning on/off the current flow between the source electrode of the driving element and the sensing line. First and second pixel block lines each including the pixels and adjacent to each other share one gate line, and the gate electrode and the second pixel block line of the first switch TFT disposed on the first pixel block line The gate electrode of the second switch TFT disposed at

Description

Electroluminescent Display Device {Electroluminescent Display Device}

The present invention relates to an electroluminescent display device.

The electroluminescent display device is roughly classified into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. Among them, the active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter, referred to as "OLED"), which is a representative electroluminescent diode that emits light by itself, and has a response speed It has the advantages of fast speed, luminous efficiency, luminance and viewing angle.

OLED, which is a self-luminous device, includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween. The organic light emitting display device arranges pixels each including an OLED and a driving TFT (Thin Film Transistor) in a matrix form, and adjusts the luminance of an image implemented in the pixels according to the gradation of image data. The driving TFT controls the driving current flowing through the OLED according to the voltage applied between its gate electrode and the source electrode (hereinafter, referred to as “gate-source voltage”). The amount of light emitted and the luminance of the OLED are determined according to the driving current.

In general, when the driving TFT operates in the saturation region, the driving current Ids flowing between the drain-source of the driving TFT is expressed as follows.

Ids = 1/2*(u*C*W/L)*(Vgs-Vth) ²

Here, u denotes electron mobility, C denotes the capacitance of the gate insulating film, W denotes the channel width of the driving TFT, and L denotes the channel length of the driving TFT. And, Vgs represents the gate-source voltage of the driving TFT, and Vth represents the threshold voltage (or threshold voltage) of the driving TFT. Depending on the pixel structure, the gate-source voltage (Vgs) of the driving TFT may be the difference voltage between the data voltage and the reference voltage. Since the data voltage is an analog voltage corresponding to the gray level of the image data and the reference voltage is a fixed voltage, the gate-source voltage (Vgs) of the driving TFT is programmed (or set) according to the data voltage. The driving current Ids is determined according to the programmed gate-source voltage Vgs.

Electrical characteristics of the pixel, such as the threshold voltage (Vth) of the driving TFT, the electron mobility (u) of the driving TFT, and the operating point voltage of the OLED, become a factor that determines the driving current (Ids), so that in all pixels should be the same However, electrical characteristics may vary between pixels due to various causes, such as process variations and changes over time. This deviation of the electrical characteristics of the pixel causes image quality degradation and shortened lifespan.

An internal compensation method and an external compensation method may be applied to compensate for the deviation in the electrical characteristics of the pixel. The internal compensation method automatically compensates for variations in electrical characteristics of pixels between pixels in real time by using a gate-source voltage of the driving TFT that varies according to the electrical characteristics of the driving TFT. The external compensation method compensates for variations in electrical characteristics between pixels by sensing a voltage of a pixel that varies according to electrical characteristics of a driving TFT or OLED, and modulating input image data in an external circuit based on the sensed voltage.

In order to compensate for the variation in the electrical characteristics of the pixel, at least two or more switch TFTs are further required in each pixel. These switch TFTs are connected to the gate driving circuit through gate lines, and are operated by gate signals output from the gate driving circuit. Since the switch TFTs in each pixel must be independently controlled, at least two gate lines are required to drive one pixel, thereby complicating the configuration of the pixel array and the gate driving circuit.

Accordingly, an object of the present invention is to provide an electroluminescent display device in which pixels are configured to compensate for variations in electrical characteristics, and the configuration of a pixel array and a gate driving circuit can be simplified.

The electroluminescent display device of the present invention includes a display panel in which a plurality of pixels are disposed. Here, each of the pixels, a light emitting device; a driving device for adjusting the current of the light emitting device to a gate-source voltage; a first switch TFT for turning on/off the flow of current between the gate electrode of the driving element and the data line; and a second switch TFT for turning on/off the current flow between the source electrode of the driving element and the sensing line. First and second pixel block lines each including the pixels and adjacent to each other share one gate line, and the gate electrode and the second pixel block line of the first switch TFT disposed on the first pixel block line The gate electrode of the second switch TFT disposed at

The present invention is designed such that first and second pixel block lines each including pixels and adjacent to each other share one gate line. Through this, the present invention configures the pixel so that the electrical characteristic deviation is compensated, but the configuration of the pixel array and the gate driving circuit can be simplified.

The present invention can simplify the configuration of the pixel array to promote process convenience, increase the aperture ratio, and improve the yield, and can easily implement the narrow bezel technology by simplifying the configuration of the gate driving circuit.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.
2 is a circuit diagram illustrating an example of a sensing circuit.
3 is a flowchart illustrating an example of an external compensation method using a pixel driving characteristic sensing result.
4A is a diagram illustrating an example of deriving a reference curve.
4B is a diagram illustrating an average IV curve of a display panel and an IV curve of a pixel to be compensated.
4C is a view showing an average IV curve of a display panel, an IV curve of a pixel to be compensated, and an IV curve of a pixel that has been compensated.
5 is a diagram illustrating an example of a connection between a data driving circuit and a pixel.
6 is a diagram illustrating a pixel array and a gate driving circuit according to an exemplary embodiment of the present invention.
7 is a diagram illustrating a pixel array and a gate driving circuit according to another exemplary embodiment of the present invention.
8 and 9 are signal waveform diagrams for explaining the operation of the pixel and the driving circuit in the image display mode.
10 is a signal waveform diagram for explaining the operation of a pixel and a driving circuit in one sensing mode.
11A to 11C are equivalent circuit diagrams of pixels and driving circuits corresponding to respective operation sections of FIG. 10 .
12 is a signal waveform diagram for explaining the operation of a pixel and a driving circuit in another sensing mode.
13 is a signal waveform diagram for explaining the operation of a pixel and a driving circuit in another sensing mode.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

The first, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to substantially like elements throughout.

Features of various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship. have.

In the present invention, the pixel circuit and the gate driver formed on the substrate of the display panel may be implemented as TFTs having an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type TFT, since electrons flow from the source to the drain, the direction of the current flows from the drain to the source. In the case of a p-type TFT (PMOS), since a carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET may be changed according to an applied voltage.

Hereinafter, the gate-on voltage is the voltage of the gate signal at which the TFT can be turned on. The gate off voltage is a voltage at which the TFT can be turned off. In NMOS, the gate-on voltage is the gate-high voltage, and the gate-off voltage is the gate-low voltage. In a PMOS, a gate-on voltage is a gate-low voltage, and a gate-off voltage is a gate-high voltage.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the electroluminescent display device will be mainly described with respect to the organic light emitting display device including the organic light emitting material. However, it should be noted that the technical spirit of the present invention is not limited to the organic light emitting display device and may be applied to an inorganic light emitting display device including an inorganic light emitting material.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention. 2 is a circuit diagram illustrating an example of a sensing circuit.

1 and 2 , the electroluminescent display device of the present invention includes a display panel 10 , a drive integrated circuit (IC) 20 , a host system 100 , a memory 30 , and the like.

A screen that reproduces an input image on the display panel 10 includes a plurality of pixels P connected to signal lines. Each of the pixels P may include red (R), green (G), and blue (B) sub-pixels for color implementation. Each of the pixels may further include a white (W) sub-pixel in addition to the RGB sub-pixels. Each of the sub-pixels may compensate for a change in electrical characteristics of the pixel using the pixel circuit shown in FIG. 5 .

The signal lines may include data lines 11 supplying an analog data voltage Vdata to the pixels P and gate lines 12 supplying a gate signal to the pixels P. The gate signal may include two or more signals according to the configuration of the pixel circuit. The signal wirings may further include sensing lines 13 used to sense electrical characteristics of the pixels P.

The pixels P of the display panel 10 are arranged in a matrix form to constitute a pixel array. Each pixel P may be connected to any one of the data lines 11 , any one of the sensing lines 13 , and two of the gate lines 12 . Each pixel P is configured to receive a high potential driving voltage and a low potential driving voltage from the power generator.

The pixel array includes a plurality of pixel block lines (HL in FIGS. 6 and 7). Each of the pixel block lines consists of a plurality of horizontally adjacent pixels. In order to simplify the configuration of the pixel array, first and second pixel block lines adjacent to each other may share one gate line 12 .

The pixel array is connected to the gate driving circuit 15 through gate lines 12 , and is connected to the data driving circuit 25 through data lines 11 and sensing lines 13 . When two gate lines 12 are required to drive the pixels P arranged in one pixel block line, if two pixel block lines adjacent to each other are designed to share the gate line 12 , the gate line has the effect of reducing the number of When the number of gate lines 12 is reduced by half, the circuit configuration of the gate driving circuit 15 connected to the gate line 12 is also reduced by half.

The gate driving circuit 15 generates a gate signal and supplies it to the gate line 12 . The gate driving circuit 15 may sequentially supply a gate signal to each gate line 12 of the pixel block lines in an image display mode for displaying an input image. In such an image display mode, the gate signals adjacent to each other may have the same length of the on-level section and different phases of the on-level section. Meanwhile, in a sensing mode for sensing electrical characteristics of the pixel P with respect to a specific pixel block line, the gate driving circuit 15 applies first and second gate signals to two gate lines connected to a specific pixel block line. can be supplied individually. In this sensing mode, at least one of the length and number of on-level sections of the first and second gate signals may be different from each other. The gate driving circuit 15 may be built in the display panel 10 .

The drive IC 20 may include a timing controller 21 , a data driving circuit 25 , a compensation unit 26 , and a compensation memory 27 .

The data driving circuit 25 includes a data voltage generator 23 to generate a data voltage Vdata, and supply the data voltage Vdata to the data lines 11 through a first channel (not shown). do. The data driving circuit 25 includes the sensing unit 22 connected to the sensing lines 13 through a second channel (not shown) to supply a reference voltage to the pixels P or to the pixels P. By sensing the change in electrical characteristics of , the sensing result may be stored in the memory 30 .

The compensator 26 modulates the input image data with compensation values of the pixels P stored in the memory 30 . In this case, the compensation value of the pixels P may be supplied to the compensation unit 26 after being loaded into the compensation memory 27 . The compensator 26 supplies the corrected image data V-DATA to the data voltage generator 23 . Then, the data voltage generator 23 may generate the data voltage Vdata corresponding to the corrected image data V-DATA.

The timing controller 21 controls operations of the gate driving circuit 15 , the data driving circuit 25 , the compensation unit 26 , and the compensation memory 27 .

The timing controller 21 is based on timing signals input from the host system 100 , for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. Thus, the gate timing control signal GDC for controlling the operation timing of the gate driving circuit 15 and the data timing control signal DDC for controlling the operation timing of the data driving circuit 25 may be generated.

The data timing control signal DDC may include, but is not limited to, a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the data voltage generator 23 . The source sampling clock is a clock signal that controls the sampling timing of data based on a rising or falling edge. The source output enable signal controls the output timing of the data voltage generator 23 .

The gate timing control signal GDC may include a gate start pulse, a gate shift clock, and the like, but is not limited thereto. A gate start pulse is applied to the stage that produces the first output to activate the operation of that stage. The gate shift clock is a clock signal commonly input to the stages and is a clock signal for shifting the gate start pulse.

In the sensing mode for measuring the electrical characteristic deviation of pixels before product shipment or during product driving, the data voltage generator 23 converts the test data received from the grayscale-luminance measurement system (not shown) to generate a data voltage for sensing. and supplying the sensing data voltage to the sensing target pixels P of the display panel 10 through the data lines 11 . The grayscale-luminance measurement system senses the electrical characteristics of each pixel, derives a compensation value of the pixel that compensates for the electrical characteristic deviation between the pixels based on the sensing result, and stores the compensation value of the pixel in the memory 30 . or update a previously stored value. The memory 30 may be a flash memory, but is not limited thereto.

The grayscale-luminance measuring system used in the sensing mode may be electrically connected to the memory 30 during the sensing mode operation.

In the image display mode, when power is applied to the electroluminescent display device, the compensation value from the memory 30 is loaded into the internal compensation memory 27 of the drive IC 20 . The compensation memory 27 of the drive IC 20 may be a DDR SDRAM (Double Date Rate Synchronous Dynamic RAM) or SRAM, but is not limited thereto.

The sensing unit 22 may be configured to sense an electrical characteristic of each pixel in an aging process before shipment of a product and transmit it to the grayscale-luminance measuring system. Meanwhile, the sensing unit 22 may sense the electrical characteristics of the pixel in the sensing mode after shipment of the product to update the compensation value in real time.

As shown in FIG. 2 , the sensing unit 22 includes a sample and hold circuit SH, an analog-to-digital converter (hereinafter referred to as "ADC"), and first and second switches SW1 and SW2. ) is included. The sensing unit 22 may sense the electrical characteristics of the OLED (light emitting device) or the driving TFT (driving device) by sampling the source voltage of the driving TFT stored in the capacitor connected to the sensing line 13 . The first switch SW1 supplies the reference voltage Vref to the sensing line 13 . The second switch SW2 is turned on at the sampling timing of the analog sensing voltage Vsen. The ADC converts analog sensed values Vsen sampled by the sample and hold circuit SH into digital sensed data S-DATA. The sensing unit 22 is not limited to FIG. 2 . For example, the sensing unit 22 may be implemented as a known voltage sensing circuit or a current sensing circuit.

The host system 100 may be any one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile system, a wearable system, and a virtual reality system (VR). . The example of FIG. 1 illustrates a mobile system configuration. A configuration of a driving circuit of the display panel may vary depending on the host system 100 . The host system 100 may be implemented as an application processor in a mobile system, a wearable system, a virtual reality system, and the like.

3 is a flowchart illustrating an example of an external compensation method using a pixel driving characteristic sensing result. 4A is a diagram illustrating an example of deriving a reference curve. 4B is a diagram illustrating an average I-V curve of a display panel and an I-V curve of a pixel to be compensated. 4C is a view showing an average I-V curve of a display panel, an I-V curve of a compensation target pixel, and an I-V curve of a compensated pixel.

A compensation value calculation algorithm for compensating for a deviation in electrical characteristics of a pixel according to an external compensation method will be described in conjunction with FIGS. 3 to 4C . In FIGS. 4A to 4C , the horizontal axis is voltage (V), and the vertical axis is current (I).

Referring to FIGS. 3 and 4A , after sensing the electrical characteristics of pixels with respect to preset grayscales A to G, the average IV curve is calculated using Equation 1 and It is derived together (S1). However, the least-squares method disclosed in the present invention is only an example, and the present invention is not limited to the least-squares method, and applying alternative regression analysis [回歸分析, regression analysis], polynomial approximation, etc. possible,

Exemplary, in Equation 1, "a" is the electron mobility of the driving TFT, "b" is the threshold voltage of the driving TFT, and "c" represents the physical characteristic value of the driving TFT.

3 and 4B, based on the grayscales of the currents I1 and I2 and the data voltages Vdata1 and Vdata2) measured at two points of the low grayscale (X) and the high grayscale (Y), Equation 2 below As shown, a' value and b' value, which are parameter values of the sensing target pixel P, are calculated (S2).

Exemplary, in Equation 2, a' value and b' value, which are parameter values of the pre-sensing pixel P, may be calculated using a quadratic equation.

은 구동 TFT의 문턱 전압 편차를 보상하기 위한 보상값이다. 게인(Gain)

은 구동 TFT의 이동도 편차를 보상하기 위한 보상값이다. As shown in FIGS. 3 and 4C , pixel compensation values such as offset and gain are calculated so that the IV curve of the sensing target pixel P matches the average IV curve of all pixels P ( S3). Offset and gain are the same as in Equation 3. Exemplary, in Equation 3, "Vcomp" is the compensation voltage. Offset

is a compensation value for compensating for the threshold voltage deviation of the driving TFT. Gain

is a compensation value for compensating for the mobility deviation of the driving TFT.

The compensator 26 compensates the electrical characteristic deviation of the pixels P by applying a compensation value to the data of the input image (S4).

5 is a diagram illustrating an example of a connection between a data driving circuit and a pixel.

Referring to FIG. 5 , one pixel P of the present invention may include an OLED, a driving TFT DT, a storage capacitor Cst, a first switch TFT ST1 , and a second switch TFT ST2 . One pixel P may be driven according to two gate signals SCAN(n) and SEN(n).

The TFTs DT, ST1, and ST2 may be implemented as n-type MOSFETs, but are not limited thereto. The TFTs DT, ST1, ST2 are It can also be implemented as a p-type MOSFET. The semiconductor layers of the TFTs DT, ST1, and ST2 may be implemented with at least one of amorphous silicon, polysilicon, and oxide. In particular, when the first switch TFT ST1 is implemented as an oxide transistor, it is advantageous for low-speed driving. Specifically, the oxide transistor may be implemented as an NMOS (hereinafter, referred to as “oxide NMOS”) including an oxide semiconductor having a low off current. The off current is a leakage current flowing between the drain and the source of the TFT in the off state of the TFT. Since the TFT device having a low off-state current has no leakage current even when the off-state is long, the change in luminance of the pixels can be minimized when the pixels are driven at a low speed.

OLEDs are light emitting devices. The OLED includes an anode electrode connected to the source node N2, a cathode electrode connected to an input terminal of the low potential driving voltage EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). When a power voltage is applied to the anode and cathode electrodes, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) is produces visible light. A parasitic capacitor (Coled) may be generated in the OLED by the anode electrode, the cathode electrode, and a plurality of insulating layers present therebetween.

The driving TFT DT is a driving device that adjusts the current of the light emitting device to a gate-source voltage Vgs. The driving TFT DT controls the amount of current input to the OLED according to the gate-source voltage Vgs. The driving TFT DT includes a gate electrode connected to the gate node N1 , a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the source node N2 . The storage capacitor Cst is connected between the gate node N1 and the source node N2.

The first switch TFT ST1 turns on/off the current flow between the gate electrode of the driving element DT and the data line 11 according to the first gate signal SCAN(n). The first switch TFT ST1 includes a gate electrode connected to the first gate line 12A, a drain electrode connected to the data line 11 , and a source electrode connected to the gate node N1 . The first gate line 12A may be shared by two pixel block lines adjacent to each other.

The second switch TFT ST2 turns on/off the current flow between the source electrode of the driving element DT and the sensing line 13 according to the second gate signal SEN(n). The second switch TFT ST2 includes a gate electrode connected to the second gate line 12B, a drain electrode connected to the source node N2 , and a source electrode connected to the sensing line 13 . The second gate line 12B may be shared by two pixel block lines adjacent to each other.

Referring to FIG. 5 , the data driving circuit 25 includes a digital-to-analog converter (hereinafter, DAC) included in the data voltage generator 23 , switches SW1 and SW2 included in the sensing unit 22 , It has a sample and hold circuit (SH) and ADC.

The DAC generates a data voltage for sensing in the sensing mode and supplies it to the data lines 11 , and generates a data voltage for image display in the image display mode and supplies it to the data lines 11 . The sensing data voltage includes an on-level sensing data voltage capable of turning on the driving TFT and an off-level sensing data voltage capable of turning off the driving TFT. The data voltage for image display means an analog voltage value corresponding to the compensated image data.

The first switch SW1 switches an electrical connection between the input terminal of the reference voltage Vref and the sensing line 13 according to a reference voltage control signal (not shown). The second switch SW2 switches an electrical connection between the sensing line 13 and the sample and hold circuit SH according to a sampling control signal (not shown).

6 is a diagram illustrating a pixel array and a gate driving circuit according to an embodiment of the present invention.

Referring to FIG. 6 , in the pixel array according to the exemplary embodiment of the present invention, two adjacent pixel block lines HL(n-1) to HL(n+2) include a gate line 12(n-1). ) to 12(n+1)) can be shared one by one.

Specifically, the gate electrode of the first switch TFT ST1 disposed on the nth pixel block line HL(n) and the second switch TFT disposed on the n−1th pixel block line HL(n−1) The gate electrode of ST2 may be connected to the n-1 th gate line 12(n-1). Accordingly, the gate signal on the n-1 th gate line 12(n-1) is transmitted to the pixels P of the n-th pixel block line HL(n) with the first gate signal SCAN(n). may be supplied as the second gate signal SEN(n) to the pixels P of the n−1th pixel block line HL(n−1).

In addition, the gate electrode of the second switch TFT ST2 disposed on the nth pixel block line HL(n) and the first switch TFT (ST2) disposed on the n+1th pixel block line HL(n+1) The gate electrode of ST1 may be connected to the n-th gate line 12(n). Accordingly, the gate signal on the n-th gate line 12(n) is supplied to the pixels P of the n-th pixel block line HL(n) as the second gate signal SEN(n) and at the same time , may be supplied as the first gate signal SCAN(n) to the pixels P of the n+1th pixel block line HL(n+1).

7 is a diagram illustrating a pixel array and a gate driving circuit according to another exemplary embodiment of the present invention.

Referring to FIG. 7 , in the pixel array according to another embodiment of the present invention, two pixel block lines HL(n-1) to HL(n+2) adjacent to each other include a gate line 12(n-1). ) to 12(n+1)) can be shared one by one.

Specifically, the gate electrode of the first switch TFT ST1 disposed on the nth pixel block line HL(n) and the second switch TFT disposed on the n+1th pixel block line HL(n+1) The gate electrode of ST2 may be connected to the n-th gate line 12(n). Accordingly, the gate signal on the n-th gate line 12(n) is supplied to the pixels P of the n-th pixel block line HL(n) as the first gate signal SCAN(n) and at the same time , may be supplied as the second gate signal SEN(n) to the pixels P of the n+1th pixel block line HL(n+1).

In addition, the gate electrode of the second switch TFT ST2 disposed on the n-th pixel block line HL(n) and the first switch TFT disposed on the n-1th pixel block line HL(n-1) ( The gate electrode of ST1 may be connected to the n-1 th gate line 12(n-1). Accordingly, the gate signal on the n-th gate line 12(n-1) is transmitted to the pixels P of the n-th pixel block line HL(n) with the second gate signal SEN(n)). may be supplied as the first gate signal SCAN(n) to the pixels P of the n−1th pixel block line HL(n−1).

8 and 9 are signal waveform diagrams for explaining the operation of the pixel and the driving circuit in the image display mode. In the image display mode, the first switch TFTs ST1 of the pixel block lines must be sequentially driven so that the pixel block lines can be sequentially scanned. To this end, in the image display mode, adjacent gate signals must have the same length of the on-level section and different phases of the on-level section. In addition, it is preferable that the on-level sections of adjacent gate signals overlap each other by half so that the gate-source voltage of the driving TFT DT is simultaneously programmed.

This will be described in detail as follows.

FIG. 8 targets one pixel P of the nth pixel block line HL(n) in the pixel array of FIG. 6 . Referring to FIG. 8 , one pixel P of the nth pixel block line HL(n) is driven through a programming period A1 and a light emission period B1. The programming period A1 is for programming the gate-source voltage of the driving TFT DT to match the display gradation. During the programming period A1, the first switch TFT ST1 and the second switch TFT ST2 are sequentially turned on. In the programming period A1, while both the first switch TFT ST1 and the second switch TFT ST2 are turned on, the data voltage Vdata for displaying an image is applied to the gate node N1 of the driving TFT DT. is applied, and a reference voltage Vref is applied to the source node N2 of the driving TFT DT. To this end, the first gate signal SCAN(n) applied from the n-1 th gate line 12(n-1) and the second gate signal SEN applied from the n-th gate line 12(n)) (n)) may be shifted while the on-level (Lon) section has the same length and the on-level (Lon) section overlaps each other by half. Here, in the phase of the on-level Lon section, the first gate signal SCAN(n) precedes the second gate signal SEN(n).

In the programming period A1, the first switch SW1 of the data driving circuit 25 may be turned on within the on level Lon period of the second gate signal SEN(n), and the second switch SW1 SW2) continuously maintains the turned-off state.

The light emission period B1 is for allowing a driving current to flow through the driving TFT DT with a gate-source voltage of the driving TFT DT programmed in the programming period A1, and to emit light by the driving current. During the light emission period B1, the first gate signal SCAN(n) and the second gate signal SEN(n) are maintained at the off level Loff, and as a result, the first switch TFT ST1 and the second switch All TFTs ST2 are turned off.

In the light emission period B1 , the first switch SW1 and the second switch SW2 of the data driving circuit 25 continuously maintain a turn-off state.

Meanwhile, FIG. 9 targets one pixel P of the nth pixel block line HL(n) in the pixel array of FIG. 7 . Referring to FIG. 9 , one pixel P of the nth pixel block line HL(n) is driven through a programming period A2 and an emission period B2. The programming period A2 is for programming the gate-source voltage of the driving TFT DT to match the display gradation. During the programming period A2, the second switch TFT ST2 and the first switch TFT ST1 are sequentially turned on. In the programming period A2, while both the first switch TFT ST1 and the second switch TFT ST2 are turned on, the data voltage Vdata for displaying an image is applied to the gate node N1 of the driving TFT DT. is applied, and a reference voltage Vref is applied to the source node N2 of the driving TFT DT. To this end, the first gate signal SCAN(n) applied from the n-1 th gate line 12(n-1) and the second gate signal SEN applied from the n-th gate line 12(n)) (n)) may be shifted while the on-level (Lon) section has the same length and the on-level (Lon) section overlaps each other by half. Here, in the phase of the on-level (Lon) section, the second gate signal SEN(n) precedes the second gate signal SCAN(n).

In the programming period A2, the first switch SW1 of the data driving circuit 25 may be turned on within the on level Lon period of the second gate signal SEN(n), and the second switch SW1 SW2) continuously maintains the turned-off state.

The light emission period B2 causes a driving current to flow through the driving TFT DT with a gate-source voltage of the driving TFT DT programmed in the programming period A2, and the OLED emits light by this driving current. During the light emission period B2, the gate signal SCAN(n) and the second gate signal SEN(n) are maintained at the off level Loff, and as a result, the first switch TFT ST1 and the second switch TFT ST1 ST2) are all turned off.

In the light emission period B2 , the first switch SW1 and the second switch SW2 of the data driving circuit 25 continuously maintain a turn-off state.

10 is a signal waveform diagram for explaining the operation of a pixel and a driving circuit in one sensing mode. 11A to 11C are equivalent circuit diagrams of pixels and driving circuits corresponding to each operation section of FIG. 10 .

The sensing mode of FIG. 10 is for sensing the operating point voltage of the OLED. In the sensing mode of FIG. 10 , a specific pixel block line to be sensed may be selected from among a plurality of pixel block lines at every predetermined period. In particular, a specific pixel block line may be sequentially or non-sequentially selected from among a plurality of pixel block lines, one at a time period. This sensing mode may be performed within a power-on period before the system power is applied and an image is displayed, or within a power-off period before the image display is terminated and the system power is turned off.

In the sensing mode of FIG. 10 , the lengths of the on-level Lon sections of the first and second gate signals SCAN(n) and SEN(n) should be different from each other. The length of the on-level Lon section of the first gate signal SCAN(n) should be longer than that of the second gate signal SEN(n). In the sensing mode, the first and second gate signals SCAN(n), SEN(n) are applied only to a specific pixel block line, and furthermore, the n-1 th gate line 12(n-1) and the n th gate signal Since it is independently applied through the line 12(n), any number of designs are possible.

Referring to FIG. 10 , one sensing mode according to the present invention may be implemented through a programming period A3 , a discharge period B3 , and a sampling period C3 .

Referring to FIG. 10 , the first gate signal SCAN(n) is applied at an on level Lon in each of the programming period A3 , the discharge period B3 , and the sampling period C3 . The second gate signal SEN(n) is applied at the on level Lon during a part of the programming period A3 and the discharge period B3 and is applied at the off level Loff during the sampling period C3. In the sensing mode of FIG. 10 , an off-level sensing data voltage VOFF is applied to the gate node N1 of the driving TFT during the programming period A3 to maintain the driving TFT in a turned-off state.

Referring to FIG. 11A , during the programming period A3 , the off-level sensing data voltage VOFF is applied to the gate node N1 through the first switch TFT ST1 and the source node N2 is applied with the first The reference voltage Vref is applied through the switch SW1 and the second switch TFT ST2. The reference voltage Vref is charged in the sensing line 13 and the source node N2. Here, the reference voltage Vref is set to a value sufficiently higher than the operating point voltage of the OLED. During the programming period A3, the gate-source voltage VOFF-Vref of the driving TFT DT is less than the threshold voltage Vth of the driving TFT, so that the driving TFT DT is turned off.

Referring to FIG. 11B , in the discharge period B3 , the first switch SW1 is turned off, and the first and second switch TFTs ST1 and ST2 remain turned on. Accordingly, the reference voltage Vref charged in the sensing line 13 and the source node N2 is discharged through the OLED. This discharge operation is continued until the potential of the sensing line 13 and the source node N2 becomes the operating point voltage OLED_Vth of the OLED.

Referring to FIG. 11C , in the sampling period C3 , the first switch TFT ST1 remains turned on while the second switch TFT ST2 is turned off. Then, the second switch SW2 is turned on. Accordingly, the residual voltage discharged from the sensing line 13 is sensed as the OLED operating point voltage OLED_Vth of the corresponding pixel P. The OLED operating point voltage is output after being converted into sensing data SD1 through the ADC.

12 is a signal waveform diagram for explaining the operation of a pixel and a driving circuit in another sensing mode.

The sensing mode of FIG. 12 is for sensing the threshold voltage of the driving TFT DT. In the sensing mode of FIG. 12 , a specific pixel block line to be sensed may be selected from among a plurality of pixel block lines one at a time for a predetermined period. In particular, a specific pixel block line may be sequentially or non-sequentially selected from among a plurality of pixel block lines, one at a time period. This sensing mode may be performed within a power-on period before the system power is applied and an image is displayed, or within a power-off period before the image display is terminated and the system power is turned off. In addition, the sensing mode may be made within a period in which an image is displayed, specifically, a vertical blank period. When the sensing mode is performed within the vertical blank period, when specific pixel block lines are selected non-sequentially, the problem that a specific pixel block line is recognized as a line dim can be greatly reduced.

In the sensing mode of FIG. 12 , the first and second gate signals SCAN(n) and SEN(n) should have different lengths and numbers of on-level Lon sections. The length of the on-level Lon section of the first gate signal SCAN(n) should be longer than that of the second gate signal SEN(n). In addition, the number of on-level Lon sections of the second gate signal SEN(n) should be greater than that of the first gate signal SCAN(n). In the sensing mode, the first and second gate signals SCAN(n), SEN(n) are applied only to a specific pixel block line, and furthermore, the n-1 th gate line 12(n-1) and the n th gate signal Since it is independently applied through the line 12(n), any number of designs are possible.

Referring to FIG. 12 , another sensing mode according to the present invention may be implemented through a programming period A4 and a sampling period B4.

Referring to FIG. 12 , the first gate signal SCAN(n) is applied at the on level Lon in each of the programming period A4 and the sampling period B4. The second gate signal SEN(n) is applied at the on level Lon in a part of the programming period A4 and the sampling period B4. In the sensing mode of FIG. 12 , an on-level sensing data voltage Vdata is applied to the gate node N1 of the driving TFT during the programming period A4 to maintain the driving TFT in the turned-on state.

Referring to FIG. 12 , during the programming period A4 , the on-level sensing data voltage Vdata is applied to the gate node N1 through the first switch TFT ST1 , and the source node N2 is supplied with the first The reference voltage Vref is applied through the switch SW1 and the second switch TFT ST2. The reference voltage Vref is charged in the sensing line 13 and the source node N2. Here, the reference voltage Vref is set to a value sufficiently lower than the operating point voltage of the OLED. During the programming period A4, the gate-source voltage Vdata-Vref of the driving TFT DT is higher than the threshold voltage Vth of the driving TFT, so the driving TFT DT is turned on.

12, in the sampling period B4, the potential of the source node N2 is gradually increased by the current flowing through the driving TFT DT. The potential of the source node N2 continues to rise until the potential difference Vgs between the gate node N1 and the source node N2 becomes the threshold voltage Vth of the driving TFT DT. When the potential difference Vgs becomes the threshold voltage Vth of the driving TFT DT, the driving TFT DT is turned off, and the potential of the source node N2 is maintained in that state.

Referring to FIG. 12 , the voltage of the source node N2 is sensed as the threshold voltage of the driving TFT DT through the second switch TFT ST2 and the second switch SW2 in the sampling period B4 . The threshold voltage of the driving TFT (DT) is converted into sensing data through the ADC and then output.

13 is a signal waveform diagram for explaining the operation of a pixel and a driving circuit in another sensing mode.

The sensing mode of FIG. 13 is for sensing the electron mobility of the driving TFT DT. In the sensing mode of FIG. 13 , a specific pixel block line to be sensed may be selected from among a plurality of pixel block lines at every predetermined period. In particular, a specific pixel block line may be sequentially or non-sequentially selected from among a plurality of pixel block lines, one at a time period. This sensing mode may be performed within a power-on period before the system power is applied and an image is displayed, or within a power-off period before the image display is terminated and the system power is turned off. In addition, the sensing mode may be made within a period in which an image is displayed, specifically, a vertical blank period. When the sensing mode is performed within the vertical blank period, when specific pixel block lines are selected non-sequentially, the problem that a specific pixel block line is recognized as a line dim can be greatly reduced.

In the sensing mode of FIG. 13 , the first and second gate signals SCAN(n) and SEN(n) must have different lengths and numbers of on-level Lon sections. The length of the on-level Lon section of the second gate signal SEN(n) should be longer than that of the first gate signal SCAN(n). In addition, the number of on-level Lon sections of the first gate signal SCAN(n) should be greater than that of the second gate signal SEN(n). In the sensing mode, the first and second gate signals SCAN(n), SEN(n) are applied only to a specific pixel block line, and furthermore, the n-1 th gate line 12(n-1) and the n th gate signal Since it is independently applied through the line 12(n), any number of designs are possible.

Referring to FIG. 13 , another sensing mode according to the present invention may be implemented through a programming period A5 , a sensing period B5 , and a sampling period C5 .

Referring to FIG. 13 , in the programming period A5 , the first switch TFT ST1 is turned on according to the on-level first gate signal SCAN(n), and the on-level second gate signal SEN(n) is turned on. )), the second switch TFT ST2 is turned on and the first switch SW1 is turned on, so that the on-level sensing data voltage Vdata is applied to the gate node N1 of the driving TFT DT. is applied, and a reference voltage Vref is applied to the source node N2 of the driving TFT DT. Accordingly, the gate-source voltage Vgs of the driving TFT DT is set higher than the threshold voltage of the driving TFT DT, and a driving current flows through the driving TFT DT.

In the sensing period B5, since the first switch TFT ST1 and the first switch SW1 are turned off, the gate-source voltage Vgs of the driving TFT DT is kept constant, and the driving TFT DT is A constant current flows through As a result, in the sensing period B5, the potential of the source node N2 rises by the constant current flowing through the driving TFT DT. In the sensing period B5, the potential of the sensing line 13 also increases, similarly to the source node N2.

In the sampling period C5 , since the second switch SW2 is turned on, the voltage of the sensing line 13 is sensed with the electron mobility of the driving TFT DT. The electron mobility of the driving TFT (DT) is output after being converted into sensing data through the ADC.

On the other hand, in the sampling period C5, the first switch TFT ST1 is turned on according to the first gate signal SCAN(n) of the on level, so that the gate electrode N1 of the driving TFT DT has an off level. A data voltage VOFF for sensing is applied. As a result, unnecessary OLED emission is prevented while sampling is in progress.

As described above, the present invention is designed such that first and second pixel block lines each include pixels and adjacent to each other share one gate line. Through this, the present invention configures the pixel so that the electrical characteristic deviation is compensated, but the configuration of the pixel array and the gate driving circuit can be simplified.

The present invention can simplify the configuration of the pixel array to promote process convenience, increase the aperture ratio, and improve the yield, and can easily implement the narrow bezel technology by simplifying the configuration of the gate driving circuit.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 15: gate driving circuit
25: data driving circuit

Claims (12)

A display panel in which a plurality of pixels are disposed,
Each of the pixels,
light emitting element;
a driving device for adjusting the current of the light emitting device to a gate-source voltage;
a first switch TFT for turning on/off the flow of current between the gate electrode of the driving element and the data line; and
and a second switch TFT for turning on/off the current flow between the source electrode and the sensing line of the driving element,
First and second pixel block lines each including the pixels and adjacent to each other share one gate line,
a gate electrode of the first switch TFT disposed on the first pixel block line and a gate electrode of the second switch TFT disposed on the second pixel block line are connected to the one gate line;
In the image display mode for displaying the input image, adjacent gate signals are sequentially output so that the on-level section overlaps each other by half, and in the sensing mode for sensing electrical characteristics of a pixel, two gates connected to a specific pixel block line An electroluminescent display device to which first and second gate signals are independently applied to lines. The method of claim 1,
The gate electrode of the first switch TFT disposed on the nth pixel block line and the gate electrode of the second switch TFT disposed on the n−1th pixel block line are connected to the n−1th gate line,
The gate electrode of the second switch TFT disposed on the nth pixel block line and the gate electrode of the first switch TFT disposed on the n+1th pixel block line are connected to the nth gate line. The method of claim 1,
The gate electrode of the first switch TFT disposed on the nth pixel block line and the gate electrode of the second switch TFT disposed on the n+1th pixel block line are connected to the nth gate line,
The gate electrode of the second switch TFT disposed on the nth pixel block line and the gate electrode of the first switch TFT disposed on the n−1th pixel block line are connected to the n−1th gate line. . The method of claim 1,
In the image display mode for displaying the input image, further comprising a gate driving circuit for sequentially supplying a gate signal to each gate line of the pixel block lines,
In the image display mode, adjacent gate signals have the same length of an on-level section and different phases of an on-level section. The method of claim 1,
a gate driving circuit for respectively supplying the first and second gate signals to two gate lines connected to the specific pixel block line;
In the sensing mode, the first and second gate signals have at least one different length and number of on-level sections from each other. 6. The method of claim 5,
The specific pixel block line is selected from among a plurality of pixel block lines one by one for a predetermined period. 6. The method of claim 5,
The specific pixel block line is sequentially or non-sequentially selected from among a plurality of pixel block lines one by one for a predetermined period. 6. The method of claim 5,
The electrical characteristic of the pixel includes at least one of a threshold voltage of the driving element, electron mobility of the driving element, and an operating point voltage of the light emitting element. The method of claim 1,
a data driving circuit connected to the data line through a first channel and connected to the sensing line through a second channel;
The data driving circuit is
a digital-to-analog converter for generating a data voltage and supplying it to the data line; and
and a sensing unit configured to supply a reference voltage to the sensing line or sense an electrical characteristic of the pixel through the sensing line. 2. The method of claim 1
The normal sensing mode includes a programming period, a discharge period, and a sampling period,
the first gate signal is applied at an on level in each of the programming period, the discharge period, and the sampling period;
The second gate signal is applied at an on level in a part of the programming period and in the discharge period, and is applied at an off level in the sampling period. 2. The method of claim 1
The normal sensing mode includes a programming period and a sampling period,
the first gate signal is applied at an on level in each of the programming period and the sampling period;
The second gate signal is applied at an on level in a part of the programming period and the sampling period. 2. The method of claim 1
The sensing mode includes a programming period, a sensing period and a sampling period,
the first gate signal is applied at an on level in the programming period and the sampling period;
The second gate signal is applied at an on level in the programming period, the sensing period, and the sampling period.

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