KR20220089336A - Organic Light Emitting Display - Google Patents

Abstract

The organic light emitting diode display according to an embodiment of the present invention provides a pixel structure capable of improving display quality by securing a sampling time and a black voltage margin even when driving at a high speed. Each pixel disposed in the nth pixel row among pixels provided in the display panel includes a light emitting element and a driving TFT that receives a first high potential driving voltage and controls a driving current applied to the light emitting element 6 TFTs including , and one storage capacitor, and each pixel further includes a sixth TFT for applying a second high potential driving voltage to the gate of the driving TFT in an initialization period.

Description

Organic Light Emitting Display {Organic Light Emitting Display}

The present invention relates to an organic light emitting diode display capable of improving display quality by securing a sampling time and a black voltage margin even during high-speed driving.

In the information society, many technologies have been developed in the field of display devices for displaying visual information as images or images. Among display devices, the organic light emitting diode display uses an organic light emitting diode, which is a self-luminous element that emits light through the recombination of electrons and holes, so it has a fast response speed, high luminance, low driving voltage, ultra-thin film formation, and free shape. It can be realized as a next-generation display.

An organic light emitting diode display includes a display panel including data lines, scan lines, a plurality of sub-pixels formed at intersections of data lines and scan lines, a gate driver supplying scan signals to the scan lines, and the data and a data driver supplying data voltages to the lines.

Each sub-pixel of the display panel includes an organic light emitting diode (hereinafter, referred to as 'OLED') and a pixel circuit independently driving the organic light emitting diode.

The pixel circuit includes a driving TFT (Driving Thin Film Transistor) for controlling a driving current flowing through the OLED according to a gate-source voltage, a capacitor for maintaining a gate-source voltage of the driving TFT constant for one frame, and a gate and at least one switching thin film transistor (TFT) for programming a gate-source voltage of the driving TFT in response to the signal.

The driving current is determined by the gate-source voltage of the driving TFT according to the data voltage and the threshold voltage of the driving TFT, and the luminance of the pixel is proportional to the size of the driving current flowing through the OLED.

The threshold voltage of the driving TFT may vary for each pixel due to a process deviation in manufacturing the organic light emitting display panel or deterioration of the driving TFT due to long-term driving. That is, when the same data voltage is applied to the pixels, the current supplied to the organic light emitting diode should be the same, but due to the difference in the threshold voltage of the driving TFT between the pixels, even if the same data voltage is applied to the pixels, the The supplied current may vary for each pixel.

To solve this problem, a compensation method for compensating the threshold voltage of the driving TFT has been prepared.

In order to solve this problem, a technique for sensing a characteristic of a pixel and externally compensating for a characteristic deviation of the pixel based on the sensing result is mainly used.

The sensing method for extracting the change in the threshold voltage (Vth) of the driving TFT is to operate the driving TFT in a source follower method and then sense the source voltage of the driving TFT to determine the threshold voltage change amount of the driving TFT based on the sensing voltage. detect The amount of change in the threshold voltage of the driving TFT is determined according to the magnitude of the sensing voltage, and an offset value for data compensation is obtained through this.

The sensing method for extracting the change in mobility (μ) of the driving TFT is a constant voltage (Vdata) higher than the threshold voltage of the driving TFT at the gate of the driving TFT in order to define the current capability characteristics except for the threshold voltage (Vth) of the driving TFT. +X, where X is a voltage according to offset value compensation) is applied to turn on the driving TFT, and in this state, the source voltage (Vs) of the driving TFT charged for a predetermined time is input as a sensing voltage. The amount of change in the mobility of the driving TFT is determined according to the magnitude of the sensing voltage, and a gain value for data compensation is obtained through this.

In addition to this external compensation method, a 6T1C pixel circuit for compensating for deviations in the threshold voltage (Vth) and mobility (μ) of the driving TFT inside the pixel circuit has been proposed.

However, in the 6T1C pixel circuit, the deviation of the threshold voltage (Vth) of the driving TFT can be compensated, but the sampling time for sensing the threshold voltage (Vth) of the driving TFT is insufficient in high-speed driving. Since this is not sufficient, there is a problem in that the display quality is deteriorated due to the occurrence of stains and difficulty in implementing black due to insufficient black voltage margin.

An object of the present invention is to provide an organic light emitting diode display capable of securing a sampling time and a black voltage margin even when driving at a high speed.

Another object of the present invention is to provide an organic light emitting diode display capable of improving display quality by preventing stains even during high-speed driving.

In order to achieve the above object, an organic light emitting display device according to an embodiment of the present invention includes a display panel including a plurality of pixels, a gate driving circuit for driving scan lines and light emitting lines of the display panel, and the display and a data driving circuit for driving data lines of the panel. Among the pixels, each pixel arranged in the nth pixel row (where n is a natural number) includes a light emitting element and six driving TFTs including a light emitting element and a driving TFT that receives a first high potential driving voltage and controls a driving current applied to the light emitting element. It has a TFT and one storage capacitor. Each pixel further includes a sixth TFT for applying a second high potential driving voltage to the gate of the driving TFT in the initialization period.

The organic light emitting diode display according to the present invention having the above characteristics has the following effects.

In the initialization period, a second high potential lower than the first high potential driving voltage ELVDD1 and higher than the sum of the data voltage Vdata(n) and the threshold voltage of the driving TFT DT (Vdata(n)+Vth) Since the driving voltage ELVDD2 is applied to the node A (the gate of the driving TFT DT), the node A (the gate of the driving TFT DT) is connected to the data voltage Vdata(n) and the threshold of the driving TFT DT. The time for convergence to the summed voltage (Vdata(n)+Vth) can be shortened.

Since the sampling time can be reduced, the sampling time can be sufficiently secured even during high-speed driving.

In addition, it is possible to secure a black voltage margin even in a high-speed driving situation.

In addition, since it is possible to accurately compensate the threshold voltage of the driving TFT even during high-speed driving, it is possible to prevent the occurrence of unevenness, thereby improving display quality.

In addition, since the second high potential driving voltage ELVDD2 is supplied to each stage or each GIP of the gate driving circuit, when the second high potential driving voltage ELVDD2 is used as the initialization voltage, compensation is uniform at the top and bottom of the screen. It can be applied to the screen, so it is more advantageous in terms of screen blur improvement.

1 is a view showing an organic light emitting display device according to an embodiment of the present invention.
Fig. 2 is an equivalent circuit diagram showing one pixel structure for internal compensation;
3 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 2;
4 is an equivalent circuit diagram showing a pixel structure according to a first embodiment of the present invention;
5 is an equivalent circuit diagram showing a pixel structure according to a second embodiment of the present invention;
6 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 4;
7A, 7B, and 7C are equivalent circuit diagrams of pixels corresponding to the initialization period, sampling period, and light emission period of FIG. 6, respectively;
8 is a waveform diagram illustrating a data signal and a gate signal applied to the pixel of FIG. 5;

Hereinafter, a pixel circuit according to a preferred embodiment of the present invention having the above characteristics and an OLED display device including the same will be described in more detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout.

Although it is described that the device described below includes an n-type thin film transistor as an example, it may be implemented as a p-type thin film transistor or a form in which both n-type and p-type exist. The thin film transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In a thin film transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the thin film transistor. That is, in the thin film transistor, the flow of carriers flows from the source to the drain.

In the case of the n-type thin film transistor, since carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type thin film transistor, since electrons flow from the source to the drain, the current flows from the drain to the source. Contrary to this, in the case of the p-type thin film transistor, since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, since holes flow from the source to the drain, current flows from the source to the drain. However, the source and drain of the thin film transistor may be changed according to an applied voltage. Reflecting this, in the following description, any one of the source and the drain will be described as the first electrode, and the other one of the source and the drain will be described as the second electrode.

1 shows an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 1 , an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 10 on which pixels PXL are formed, a data driving circuit 12 for driving data lines 14 ; A gate driving circuit 13 for driving the gate lines 15 and a timing controller 11 for controlling driving timings of the data driving circuit 12 and the gate driving circuit 13 are provided.

A plurality of data lines 14 and a plurality of gate lines 15 cross each other in the display panel 10 , and pixels PXL are arranged in a matrix form in each crossed area. The pixels PXL arranged on the same horizontal line form one pixel row. The pixels PXL arranged in one pixel row are connected to one gate line 15 , and the one gate line 15 may include at least one scan line and at least one light emitting line. That is, each pixel PXL may be connected to one data line 14 and at least one scan line and a light emission line. The pixels PXL may receive the high potential and low potential driving voltages ELVDD and ELVSS and the initialization voltage Vinit from a power generator (not shown) in common. The initialization voltage (Vinit) is preferably selected within a voltage range sufficiently lower than the operating voltage of the OLED to prevent unnecessary light emission of the OLED during the initialization period and the sampling period, and may be set equal to or lower than the low potential driving voltage (ELVSS). have.

The TFTs constituting the pixel PXL may be implemented as an oxide TFT including an oxide semiconductor layer. The oxide TFT is advantageous in increasing the area of the display panel 10 in consideration of electron mobility, process variation, and the like. However, the present invention is not limited thereto, and the semiconductor layer of the TFT may be formed of amorphous silicon or polysilicon.

Each pixel PXL includes a plurality of TFTs and a storage capacitor to compensate for the threshold voltage change of the driving TFT. In the present invention, in the initialization period for sensing the threshold voltage Vth of the driving TFT in high-speed driving, We propose a pixel structure that can improve display quality by applying a voltage lower than the high potential driving voltage (ELVDD) and increasing the sampling time to prevent spotting and secure a black voltage margin. do. The specific configuration will be described later.

The timing controller 11 rearranges digital video data RGB input from the outside to match the resolution of the display panel 10 and supplies it to the data driving circuit 12 . In addition, the timing controller 11 includes a data driving circuit 12 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. A data control signal DDC for controlling the operation timing of , and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated.

The data driving circuit 12 converts digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DDC.

The gate driving circuit 13 may generate a scan signal and a light emitting signal based on the gate control signal GDC. The gate driving circuit 13 may include a scan driver and a light emission driver. The scan driver may generate and supply scan signals to the scan lines in a row-sequential manner to drive at least one scan line connected to each pixel row. The light emission driver may generate light emission signals in a row-sequential manner to drive at least one light emission line connected to each pixel row and supply the light emission signals to the light emission lines.

The gate driving circuit 13 may be directly formed on the non-display area of the display panel 10 by a gate-driver in panel (GIP) method.

2 is an equivalent circuit diagram showing a pixel structure for internal compensation. 3 is a waveform diagram illustrating a data signal and a gate signal applied to the pixel of FIG. 2 .

Referring to FIG. 2 , each pixel PXL disposed in an nth pixel row (where n is a natural number) has a 6T1C structure, and includes an OLED, a driving TFT (DT), a first TFT (T1), and a second TFT (T2). , a third TFT T3 , a fourth TFT T4 , a fifth TFT T5 , and a storage capacitor Cst.

The OLED emits light by the driving current supplied from the driving TFT DT. A multi-layered organic compound layer is formed between the anode electrode and the cathode electrode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). The anode electrode of the OLED is connected to node C, and its cathode electrode is connected to the input terminal of the low potential driving voltage ELVSS.

The driving TFT DT controls the driving current applied to the OLED according to its gate-source voltage Vgs. The gate electrode of the driving TFT DT is connected to the node A, the drain electrode is connected to the node B, and the source electrode is connected to the node D.

The first TFT T1 is connected between the node A and the node B, and is turned on/off according to the 1n-th scan signal SCAN1(n). The gate electrode of the first TFT (T1) is connected to the n-th first scan line to which the 1n-th scan signal SCAN1(n) is applied, its drain electrode is connected to the node B, and its source electrode is connected to the node A connected

The second TFT T2 is connected between the node C and the input terminal of the initialization voltage Vinit, and is turned on/off according to the 1n-th scan signal SCAN1(n). The gate electrode of the second TFT T2 is connected to the n-th first scan line to which the 1n-th scan signal SCAN1(n) is applied, its drain electrode is connected to the node C, and its source electrode is connected to an initialization voltage ( Vinit) is connected to the input terminal.

The third TFT T3 is connected between the data line 14 and the node D, and is turned on/off according to the 2n-th scan signal SCAN2(n). The gate electrode of the third TFT T3 is connected to the n-th second scan line to which the 2n-th scan signal SCAN2(n) is applied, the drain electrode thereof is connected to the data line 14 , and the source electrode thereof is connected to the connected to node D.

The fourth TFT T4 is connected between the input terminal of the high potential driving voltage ELVDD and the node B, and is turned on/off according to the 1n-th emission signal EM1(n). The gate electrode of the fourth TFT T4 is connected to the n-th first emission line to which the 1n-th emission signal EM1(n) is applied, and its drain electrode is connected to the input terminal of the high potential driving voltage ELVDD, Its source electrode is connected to node B.

The fifth TFT T5 is connected between the node D and the node C, and is turned on/off according to the 2n-th light emission signal EM2(n). The gate electrode of the fifth TFT T5 is connected to the n-th second emission line to which the 2n-th emission signal EM2(n) is applied, its drain electrode is connected to the node D, and its source electrode is connected to the node C. connected

The storage capacitor Cst is connected between the node A and the node C.

An operation of the pixel of FIG. 2 will be described with reference to FIG. 3 .

One frame period includes an initialization period (Pi) for initializing nodes A and C, a sampling period (Ps) for sampling and storing the threshold voltage of the driving TFT (DT) in the node A, and the sampled threshold voltage, as shown in FIG. 3 . and programming the gate-source voltage of the driving TFT DT and may be divided into an emission period Pe in which the OLED emits light with a driving current according to the programmed gate-source voltage.

3 , in the initialization period Pi, the 1n-th scan signal SCAN1(n) and the 1n-th emission signal EM1(n) are applied at an on level, and the 2n-th scan signal SCAN2(n)) and the 2n-th emission signal EM2(n) are applied at an off level. In the initialization period Pi, the first and second TFTs T1 and T2 are turned on in response to the 1n-th scan signal SCAN1(n), and the first and second TFTs T1 and T2 are turned on in response to the 1n-th light emitting signal EM1(n). As the 4 TFT T4 is turned on, the node A is initialized to the high potential driving voltage ELVDD, and the node C is initialized to the initialization voltage Vinit. The reason for initializing nodes A and C prior to the sampling operation is to increase the reliability of sampling and to prevent unnecessary light emission of the OLED. To this end, the initialization voltage Vinit is preferably selected within a voltage range sufficiently lower than the operating voltage of the OLED, and may be set equal to or lower than the low potential driving voltage ELVSS. On the other hand, in the initialization period Pi, the data voltage Vdata(n) is maintained at the node D.

In the sampling period Ps, the 1n-th scan signal SCAN1(n) and the 2n-th scan signal SCAN2(n) are applied at an on level, and the 1n-th light emission signal EM1(n) and the 2n-th light emission signal (EM2(n)) is applied at the off level. In the sampling period Ps, the first and second TFTs T1 and T2 are turned on in response to the 1n-th scan signal SCAN1(n), and the first and second TFTs T1 and T2 are turned on in response to the 2n-th scan signal SCAN2(n). 3 As the TFT (T3) is turned on, the driving TFT (DT) is diode-connected (the gate electrode and the drain electrode are shorted so that the TFT operates like a diode), and the data voltage (Vdata(n)) is applied to the node D this is authorized Here, the data voltage Vdata(n) is applied to a sufficiently low voltage (Vdata(n)<ELVDD-Vth) so that the driving TFT DT can be turned on during the sampling period Ps. In the sampling period Ps, a current Ids flows between the drain and source of the driving TFT DT, and by this current Ids, the potential of the node A is changed from the high potential driving voltage ELVDD in the initialization state to the data voltage (Vdata(n)) and the threshold voltage of the driving TFT (DT) are reduced to a value (Vdata(n)+Vth). In the sampling period Ps, the potential of the C node is maintained at the initialization voltage Vinit to provide the current Ids path.

The light emission period Pe corresponds to the remaining period of one frame period excluding the initialization period Pi and the sampling period Ps. In the emission period Pe, the 1n-th emission signal EM1(n) and the 2n-th emission signal EM2(n) are applied at an on level, and the 1n-th scan signal SCAN1(n) and the 2n-th scan signal (SCAN2(n)) is applied at the off level. In the light emission period Pe, the fourth TFT T4 is turned on in response to the 1n-th light emission signal EM1(n), thereby connecting the high potential driving voltage ELVDD to the drain electrode of the driving TFT DT; The fifth TFT T5 is turned on in response to the 2n-th light emission signal EM2(n) so that the potentials of the nodes C and D are equal to the operating voltage Voled of the OLED. In the light emission period Pe, the potential of the node C is changed from the initialization voltage Vinit, which is an initialization state, to the operating voltage Voled of the OLED. In the light emission period Pe, since the node A floats and is coupled to the node C through the storage capacitor Cst, the potential of the node A is also set in the sampling period Ps (Vdata(n)+Vth) is changed by the change in potential of node C (Voled-Vinit). That is, in the light emission period Pe, the potential of the node A is set to "Vdata(n)+Vth+Voled-Vinit", and the potential of the node C is set to "Voled", so that the driving TFT DT The gate-source voltage Vgs obtained by subtracting the source voltage Vs from the gate voltage Vg is programmed as “Vdata(n)+Vth-Vinit”.

However, in the pixel structure of 6T1C shown in FIG. 2 , since the sampling time is shortened when driving at a high speed of 120 Hz or higher, the compensation time is not sufficient, so that unevenness may occur and the black voltage margin is insufficient.

That is, the sum of the data voltage Vdata(n) and the threshold voltage of the driving TFT DT from the high potential driving voltage ELVDD in which the potential of the node A is initialized during the sampling period (Vdata(n)+Vth) When driving at a high speed of 120Hz or higher, the sampling time is shortened, so the potential of node A is the sum of the data voltage (Vdata(n)) and the threshold voltage of the driving TFT (DT) from the high potential driving voltage (ELVDD). The value (Vdata(n)+Vth) cannot be reached. Due to this, staining may occur, and a black voltage margin may be insufficient.

In order to solve this problem, the present invention provides a value (Vdata(n)) that is lower than the high potential driving voltage ELVDD and is the sum of the data voltage Vdata(n) and the threshold voltage of the driving TFT DT during the initialization period. A second high potential driving voltage ELVDD2 higher than +Vth) is applied to the node A (the gate of the driving TFT DT), so that the node A (the gate of the driving TFT DT) is changed to the data voltage Vdata(n) )) and the threshold voltage of the driving TFT DT, the time for convergence to a value (Vdata(n)+Vth) can be shortened.

4 is an equivalent circuit diagram showing a pixel structure according to the first embodiment of the present invention.

Referring to FIG. 4 , each pixel PXL disposed in the nth pixel row (n is a natural number) according to the first embodiment of the present invention has a 7T1C structure, and includes an OLED, a driving TFT (DT), and a first TFT ( T1 ), a second TFT ( T2 ), a third TFT ( T3 ), a fourth TFT ( T4 ), a fifth TFT ( T5 ), a sixth TFT ( T6 ), and a storage capacitor (Cst).

The OLED emits light by the driving current supplied from the driving TFT DT. A multi-layered organic compound layer is formed between the anode electrode and the cathode electrode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). The anode electrode of the OLED is connected to node C, and its cathode electrode is connected to the input terminal of the low potential driving voltage ELVSS.

The driving TFT DT controls the driving current applied to the OLED according to its gate-source voltage Vgs. The gate electrode of the driving TFT DT is connected to the node A, the drain electrode is connected to the node B, and the source electrode is connected to the node D.

The first TFT T1 is connected between the node A and the node B, and is turned on/off according to the 1n-th scan signal SCAN1(n). The gate electrode of the first TFT (T1) is connected to the n-th first scan line to which the 1n-th scan signal SCAN1(n) is applied, its drain electrode is connected to the node B, and its source electrode is connected to the node A connected

The second TFT T2 is connected between the node C and the input terminal of the initialization voltage Vinit, and is turned on/off according to the 1n-th scan signal SCAN1(n). The gate electrode of the second TFT T2 is connected to the n-th first scan line to which the 1n-th scan signal SCAN1(n) is applied, its drain electrode is connected to the node C, and its source electrode is connected to an initialization voltage ( Vinit) is connected to the input terminal.

The third TFT T3 is connected between the data line 14 and the node D, and is turned on/off according to the 2n-th scan signal SCAN2(n). The gate electrode of the third TFT T3 is connected to the n-th second scan line to which the 2n-th scan signal SCAN2(n) is applied, the drain electrode thereof is connected to the data line 14 , and the source electrode thereof is connected to the connected to node D.

The fourth TFT T4 is connected between the input terminal of the first high potential driving voltage ELVDD1 and the node B, and is turned on/off according to the 1n-th light emission signal EM1(n). The gate electrode of the fourth TFT T4 is connected to the n-th first emission line to which the 1n-th emission signal EM1(n) is applied, and its drain electrode is connected to the input terminal of the first high potential driving voltage ELVDD1. and its source electrode is connected to node B.

The fifth TFT T5 is connected between the node D and the node C, and is turned on/off according to the 2n-th light emission signal EM2(n). The gate electrode of the fifth TFT T5 is connected to the n-th second emission line to which the 2n-th emission signal EM2(n) is applied, its drain electrode is connected to the node D, and its source electrode is connected to the node C. connected

The sixth TFT T6 is connected between the input terminal of the second high potential driving voltage ELVDD2 and the node B, and is turned on/off according to the 3n-th scan signal SCAN3(n). The gate electrode of the sixth TFT T6 is connected to the n-th third scan line to which the 3n-th scan signal SCAN3(n) is applied, and its drain electrode is connected to the input terminal of the second high potential driving voltage ELVDD2. and its source electrode is connected to node B.

Here, the second high potential driving voltage ELVDD2 is lower than the first high potential driving voltage ELVDD1 and is the sum of the data voltage Vdata(n) and the threshold voltage of the driving TFT DT Vdata(n) )+Vth) is preferred.

In addition, the second high potential driving voltage supply line for supplying the second high potential driving voltage ELVDD2 includes the first to third scan signal lines SCAN1(n)-SCAN3(n) and the first and first Like the two light emitting signal lines EM1(n) - (EM2(n)), they are disposed for each stage or each GIP of the gate driving circuit 13 .

Accordingly, unlike the first high potential driving voltage supply line that supplies the first high potential driving voltage ELVDD1 , the second high potential driving voltage supply line is less affected by resistance across the top and bottom of the screen. Therefore, when the second high potential driving voltage ELVDD2 is used as the initialization voltage, the same voltage is applied at the top and bottom of the screen, so that it can be uniformly applied in terms of compensation. Accordingly, it is advantageous in terms of improving screen blur. FIG. 5 is an equivalent circuit diagram showing a pixel structure according to a second embodiment of the present invention.

It is important to simplify the pixel array in order to increase the degree of pixel integration in the display panel 10 or to make the manufacturing process easier and also to increase the yield.

In order to simplify the pixel array, the pixel PXL disposed in the n-th pixel row has the same n-th light emission signal EM(n) in the pixel configured as shown in FIG. 4 , the fourth and fifth TFTs T4 and T5 . ) can be designed to be on/off according to the

That is, as shown in FIG. 5 , the gate electrode of the fourth TFT T4 and the gate electrode of the fifth TFT T5 may be connected to the n-th emission line to which the n-th emission signal EM(n) is applied. When a portion of the gate signal is removed to reduce signal lines required to supply the gate signal, the aperture ratio of the pixel is increased accordingly. In addition, as the gate signal is reduced, the circuit size of the gate driving circuit for generating the gate signal can also be reduced, which is very important for realizing a narrow bezel.

In addition, in order to further simplify the pixel array, each pixel PXL of the display panel 10 is designed such that the drain electrode of the second TFT T2 is connected to the input terminal of the low potential driving voltage ELVSS as shown in FIG. 5 . can be Since the initialization voltage Vinit is unnecessary in the pixel array including the pixels PXL as shown in FIG. 5 , signal lines necessary to supply the initialization voltage Vinit may be removed.

In the pixel PXL of FIG. 5 , other components are substantially the same as those described with reference to FIG. 4 .

That is, in the pixel PXL as shown in FIG. 4 , the gate electrode of the fourth TFT ( T4 ) and the gate electrode of the fifth TFT ( T5 ) may be connected to the same light emitting line, or the drain electrode of the second TFT ( T2 ) It may be designed to be connected to the input terminal of the low potential driving voltage ELVSS.

In the pixel configuration of FIGS. 4 and 5 , the circuit configuration of the first to fifth TFTs T1-T5 for internal compensation, the driving TFT DT, and the storage capacitor Cst, except for the sixth TFT T6, is It can be configured in various ways. That is, one pixel configuration for internal compensation shown in FIG. 2 may be designed in various ways.

6 is a waveform diagram illustrating a data signal and a gate signal applied to the pixel of FIG. 4 . 7A, 7B, and 7C are equivalent circuit diagrams of pixels corresponding to the initialization period, sampling period, and light emission period of FIG. 6, respectively.

A method of driving the pixel structure according to the first embodiment of the present invention will be described as follows.

In the pixel structure configured as in the first embodiment of the present invention, one frame period includes an initialization period Pi for initializing nodes A and C, and a threshold voltage of the driving TFT DT by sampling as shown in FIG. 6 . The gate-source voltage of the driving TFT DT is programmed including the sampling period Ps stored in A and the sampled threshold voltage, and the OLED emits light with a driving current according to the programmed gate-source voltage. It may be divided into the light emission period Pe.

In the initialization period Pi, as shown in FIG. 6 , the 1n-th scan signal SCAN1(n) and the 3n-th scan signal SCAN3(n) are applied at an on level, and the 2n-th scan signal SCAN2(n)) and the 1n-th emission signal EM1(n) and the 2n-th emission signal EM2(n) are applied at an off level.

In the initialization period Pi, as shown in FIG. 7A , the first and second TFTs T1 and T2 are turned on in response to the 1n-th scan signal SCAN1(n), and the 3n-th scan signal SCAN3 In response to (n)), the sixth TFT T6 is turned on, and the 2n-th scan signal SCAN2(n), the 1n-th light-emitting signal EM1(n), and the 2n-th light-emitting signal EM2(n)) In response, the third to fifth TFTs T3, T4, and T5 are turned off.

Accordingly, the node A is initialized to the second high potential driving voltage ELVDD2 and the node C is initialized to the initialization voltage Vinit. The reason for initializing nodes A and C prior to the sampling operation is to increase the reliability of sampling and to prevent unnecessary light emission of the OLED. To this end, the initialization voltage Vinit is preferably selected within a voltage range sufficiently lower than the operating voltage of the OLED, and may be set equal to or lower than the low potential driving voltage ELVSS. On the other hand, in the initialization period Pi, the data voltage Vdata(n) is maintained at the node D.

In the sampling period Ps, as shown in FIG. 6 , the 1n-th scan signal SCAN1(n) and the 2n-th scan signal SCAN2(n) are applied at an on level, and the 3n-th scan signal SCAN3(n)) and the 1n and 2n-th emission signals EM1(n) and EM1(n) are applied at an off level.

In the sampling period Ps, as shown in FIG. 7B , the first and second TFTs T1 and T2 are turned on in response to the 1n-th scan signal SCAN1(n), and the 2n-th scan signal SCAN2 In response to (n)), the third TFT T3 is turned on, and in response to the 3n-th scan signal SCAN3(n) and the 1n and 2n-th emission signals EM1(n) and EM1(n)) The fourth to sixth TFTs T4 , T5 , and T6 are turned off.

Accordingly, in the sampling period Ps, the driving TFT DT has a diode connection (the gate electrode and the drain electrode are shorted so that the TFT operates like a diode), and the data voltage Vdata(n) is applied to the node D. is authorized Here, the data voltage Vdata(n) is applied to a sufficiently low voltage (Vdata(n)<ELVDD-Vth) so that the driving TFT DT can be turned on during the sampling period Ps. In the sampling period Ps, a current Ids flows between the drain and the source of the driving TFT DT, and by this current Ids, the potential of the node A is set at the second high potential driving voltage ELVDD2 in the initialization state. The data voltage Vdata(n) and the threshold voltage of the driving TFT DT are summed up to a value Vdata(n)+Vth. In the sampling period Ps, the potential of the C node is maintained at the initialization voltage Vinit or the low potential driving voltage ELVSS to provide a current Ids path.

In the emission period Pe, as shown in FIG. 6, the 1n to 3n-th scan signals SCAN1(n), SCAN2(n), and SCAN3(n) are applied at an off level, and the 1n-th and 2n-th emission signals ( EM1(n) and EM2(n)) are applied at the on level.

In the light emission period Pe, as shown in FIG. 7C , the fourth TFT T4 is turned on in response to the 1n-th light emission signal EM1(n), thereby driving a high potential to the drain electrode of the driving TFT DT. The voltage ELVDD is connected, and the fifth TFT T5 is turned on in response to the 2n-th light emission signal EM2(n) so that the potentials of the nodes C and D are equal to the operating voltage Voled of the OLED. , in response to the 1n to 3n-th scan signals SCAN1(n), SCAN2(n), and SCAN3(n)), the first to third TFTs T1, T2, T3 and the sixth TFT T6 are turned off do.

Accordingly, in the light emission period Pe, the potential of the node C is changed from the initialization voltage Vinit, which is an initialization state, to the operation voltage Voled of the OLED. In the light emission period Pe, since the node A floats and is coupled to the node C through the storage capacitor Cst, the potential of the node A is also set in the sampling period Ps (Vdata(n)+Vth) is changed by the change in potential of node C (Voled-Vinit). That is, in the light emission period Pe, the potential of the node A is set to "Vdata(n)+Vth+Voled-Vinit", and the potential of the node C is set to "Voled", so that the driving TFT DT The gate-source voltage Vgs obtained by subtracting the source voltage Vs from the gate voltage Vg is programmed as “Vdata(n)+Vth-Vinit”.

8 is a waveform diagram illustrating a data signal and a gate signal applied to the pixel of FIG. 5 .

A method of driving a pixel structure according to a second embodiment of the present invention will be described as follows.

In the pixel structure configured as in the second embodiment of the present invention, one frame period includes an initialization period Pi for initializing nodes A and C, and a threshold voltage of the driving TFT DT, as shown in FIG. 8 . The gate-source voltage of the driving TFT (DT) is programmed including the sampling period (Ps) for sampling and storing in the node A, and the sampled threshold voltage, and the OLED is converted to a driving current according to the programmed gate-source voltage. may be divided into an emission period Pe for emitting light.

In the initialization period Pi, the 1n-th scan signal SCAN1(n) and the 3n-th scan signal SCAN3(n) are applied at an on level, and the n-th light emission signal EM(n) and the 2n-th scan signal (SCAN2(n)) is applied at the off level, and the effect thereof is substantially the same as described with reference to FIG. 7A. However, the node C is initialized to the low potential driving voltage ELVSS.

In the sampling period Ps, the 1nth scan signal SCAN1(n) and the 2nth scan signal SCAN2(n) are applied at an on level, and the 3nth scan signal SCAN3(n) and the nth light emitting signal (EM(n)) is applied at an off level, and the effect thereof is substantially the same as described with reference to FIG. 7B .

In the emission period Pe, the n-th emission signal EM(n) is applied at an on level, and the 1n-th scan signals SCAN1(n) to the 3n-th scan signals SCAN3(n) are applied at an OFF level. and the effects thereof are substantially the same as those described in FIG. 7C .

As described above, in the initialization period, the sum of the data voltage Vdata(n) and the threshold voltage of the driving TFT DT lower than the first high potential driving voltage ELVDD1 (Vdata(n)+Vth) Since the second higher potential driving voltage ELVDD2 is applied to the node A (the gate of the driving TFT DT), the node A (the gate of the driving TFT DT) is connected to the data voltage Vdata(n) The time for convergence to the sum of the threshold voltages of the TFTs (DT) (Vdata(n)+Vth) can be shortened.

Accordingly, since it is possible to obtain an effect of reducing the sampling compensation time, it is possible to secure a black voltage margin even in a high-speed driving situation such as 120 Hz and prevent the occurrence of spots.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data line 15: gate line

Claims (7)

a display panel provided with a plurality of pixels;
a gate driving circuit for driving scan lines and light emitting lines of the display panel; and
a data driving circuit for driving data lines of the display panel;
Among the pixels, each pixel arranged in the nth pixel row (where n is a natural number) has six pixels including a light emitting element and a driving TFT that receives a first high potential driving voltage and controls a driving current applied to the light emitting element. a TFT and one storage capacitor;
Each pixel further includes a sixth TFT for applying a second high potential driving voltage to a gate of the driving TFT in an initialization period.
The method of claim 1,
The second high potential driving voltage is lower than the first high potential driving voltage and is higher than a sum of a data voltage and a threshold voltage of the driving TFT. The method of claim 1,
Each pixel,
an OLED having an anode electrode connected to the node C and a cathode electrode connected to an input terminal of a low potential driving voltage;
the driving TFT for controlling a driving current applied to the OLED including a gate electrode connected to the node A, a drain electrode connected to the node B, and a source electrode connected to the node D;
a first TFT connected between the node A and the node B;
a second TFT connected to the node C;
a third TFT connected between the data line and the node D;
a fourth TFT connected between the input terminal of the first high potential driving voltage and the node B;
a fifth TFT connected between the node D and the node C;
a sixth TFT connected between the node B and an input terminal of the second high potential driving voltage;
and a storage capacitor connected between the node A and the node C. 4. The method of claim 3,
The second TFT is
The organic light emitting diode display is connected between the input terminal of the initialization voltage and the node C, or between the input terminal of the low potential driving voltage and the node C. 5. The method of claim 4,
One frame period is
A gate-source voltage of the driving TFT including an initialization period for initializing the node A and the node C, a sampling period for sampling the threshold voltage of the driving TFT and storing it in the node A, and the sampled threshold voltage and a light emitting period in which the OLED emits light with a driving current according to the programmed gate-source voltage;
A gate electrode of each of the first and second TFTs is connected to an n-th first scan line to which a 1n-th scan signal is applied, and the gate electrode of the third TFT is an n-th second scan line to which a 2n-th scan signal is applied. is connected to, the gate electrode of the fourth TFT is connected to the n-th first light-emitting line to which the 1n-th light-emitting signal is applied, and the gate electrode of the fifth TFT is connected to the n-th second light-emitting line to which the 2n-th light-emitting signal is applied. is connected to, and the gate electrode of the sixth TFT is connected to an n-th third scan line to which a 3n-th scan signal is applied,
in the initialization period, the 1nth scan signal and the 3nth scan signal are applied at an on level, and the 2nth scan signal and the 1nth and 2nth light emitting signals are applied at an off level;
in the sampling period, the 1n-th scan signal and the 2n-th scan signal are applied at an on level, and the 3n-th scan signal and the 1n-th and 2n-th emission signals are applied at an off level;
In the emission period, the 1n-th emission signal and the 2n-th emission signal are applied at an on level, and the 1n to 3n-th scan signals are applied at an off level. 3. The method of claim 2,
One frame period is
A gate-source voltage of the driving TFT including an initialization period for initializing the node A and the node C, a sampling period for sampling the threshold voltage of the driving TFT and storing it in the node A, and the sampled threshold voltage and a light emitting period in which the OLED emits light with a driving current according to the programmed gate-source voltage;
A gate electrode of each of the first and second TFTs is connected to an n-th first scan line to which a 1n-th scan signal is applied, and a gate electrode of the third TFT is connected to an n-th second scan line to which a 2n-th scan signal is applied. and a gate electrode of each of the fourth and fifth TFTs is connected to an n-th emission line to which an n-th emission signal is applied, and a gate electrode of the sixth TFT is connected to an n-th third emission line to which a 3n-th scan signal is applied. connected to the scan line,
in the initialization period, the 1nth scan signal and the 3nth scan signal are applied at an on level, and the 2nth scan signal and the nth light emitting signal are applied at an off level;
in the sampling period, the 1n-th scan signal and the 2n-th scan signal are applied at an on level, and the 3n-th scan signal and the nth light-emitting signal are applied at an off level;
In the emission period, the nth emission signal is applied at an on level, and the 1n to 3nth scan signals are applied at an off level. The method of claim 1,
The second high potential driving voltage is separately applied to each stage of the gate driving circuit.

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