KR102188146B1 - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device. An organic light emitting display device according to an embodiment of the present invention includes a display panel in which data lines and scan lines are formed and pixels are arranged in a matrix form, and each of the pixels has a gate electrode at a first node. A driving transistor connected, the first electrode connected to the second node, and the second electrode connected to the third node; An organic light emitting diode emitting light according to a current between a drain and a source of the driving transistor; And a first transistor connected between the first node and the third node, wherein a gate electrode of the driving transistor overlaps a semiconductor layer of the first transistor.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present invention relates to an organic light emitting display device.

Recently, various flat panel display devices have been developed that can reduce the weight and volume, which are the disadvantages of a cathode ray tube. Flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, an organic light emitting display, and the like.

Among flat panel displays, an organic light emitting display device displays an image using an organic light emitting diode (OLED) that generates light by recombination of electrons and holes. The organic light emitting display device has an advantage of having a fast response speed and being driven with low power consumption.

A display panel of an organic light emitting display device includes a plurality of pixels arranged in a matrix form. Each of the pixels is a scan transistor that supplies a data voltage of a data line in response to a scan signal of a scan line, a driving transistor that adjusts the amount of drain-source current Ids according to the voltage of the gate electrode, and a driving transistor. And an organic light emitting diode that emits light according to the drain-source current Ids of

The drain-source current Ids of the driving transistor supplied to the organic light emitting diode may be expressed as Equation 1.

In Equation 1, k denotes a proportional coefficient determined by the structure and physical characteristics of the driving transistor, Vgs denotes a gate-source voltage of the driving transistor, and Vth denotes a threshold voltage of the driving transistor.

The drain-source current Ids of the driving transistor depends on the threshold voltage Vth of the driving transistor as shown in Equation 1 below. However, the threshold voltage of the driving transistor may be shifted due to deterioration according to the driving time. In particular, since the degree of deterioration of the threshold voltage of the driving transistor is different for each pixel, the shift degree of the threshold voltage of the driving transistor is also different for each pixel. Accordingly, a problem in which the luminance of the pixels of the display panel is not uniform may occur.

An embodiment of the present invention provides an organic light emitting display device capable of equalizing luminance of pixels of a display panel by compensating for a threshold voltage of a driving transistor.

An organic light emitting display device according to an embodiment of the present invention includes a display panel in which data lines and scan lines are formed and pixels are arranged in a matrix form, and each of the pixels has a gate electrode at a first node. A driving transistor connected, the first electrode connected to the second node, and the second electrode connected to the third node; An organic light emitting diode emitting light according to a current between a drain and a source of the driving transistor; And a first transistor connected between the first node and the third node, wherein a gate electrode of the driving transistor overlaps a semiconductor layer of the first transistor.

According to an embodiment of the present invention, a threshold voltage of a driving transistor may be compensated. As a result, according to the exemplary embodiment of the present invention, since the drain-source current of the driving transistor supplied to the organic light emitting diode does not depend on the threshold voltage of the driving transistor, the luminance of the pixels of the display panel can be uniform.

In addition, according to an exemplary embodiment of the present invention, an on-bias is applied to the driving transistor by discharging the gate electrode of the driving transistor to the initialization voltage for a predetermined period before the third period of supplying the data voltage. As a result, the embodiment of the present invention can solve the problem of deteriorating image quality due to the hysteresis characteristic of the driving transistor.

In addition, the embodiment of the present invention extends the gate electrode of the driving transistor to overlap the semiconductor layer of the first transistor so that the first electrode of the first transistor does not overlap the anode electrode of the organic light emitting diode. 1 Connect to the electrode. Accordingly, the embodiment of the present invention can minimize the size of the parasitic capacitance formed between the anode electrode of the organic light emitting diode and the gate electrode of the driving transistor. As a result, according to the embodiment of the present invention, it is possible to minimize the influence of the anode electrode of the organic light emitting diode due to the parasitic capacitance formed between the anode electrode of the organic light emitting diode and the gate electrode of the driving transistor, thereby preventing deterioration of image quality. I can.

1 is a circuit diagram showing a part of a threshold voltage compensation pixel structure of a diode connection method.
2 is a graph showing a drain-source current of a driving transistor according to a voltage difference between a gate and a source in a gate-on bias state and a gate-off bias state.
3 is a graph showing the luminance of a pixel when a peak black gradation voltage is supplied during a conventional p-th frame period and a peak white gradation voltage is supplied during a p+1th to p+3th frame period.
4 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention.
5 is an equivalent circuit diagram showing the pixel of FIG. 4 in detail.
6 is a waveform diagram showing signals input to the pixel of FIG. 5;
7 is a flowchart showing an operation of a pixel during first to fourth periods.
8A to 8D are equivalent circuit diagrams showing pixels during first to fourth periods.
9 is a graph showing the luminance of a pixel when a peak black gradation voltage is supplied during a p-th frame period and a peak white gradation voltage is supplied during a p+1th to p+3th frame period in an embodiment of the present invention.
10 is a plan view illustrating an example of a driving transistor and a first transistor of FIG. 5.
11 is an exemplary view showing a cross section taken along line A-A' of FIG. 10;
12 is a plan view illustrating still another example of the driving transistor and the first transistor of FIG. 5.
13 is an exemplary view showing a cross section taken along line B-B' of FIG. 12;

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, focusing on an organic light emitting display device. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. The names of the constituent elements used in the following description are selected in consideration of ease of preparation of the specification, and may be different from the names of actual products.

1 is a circuit diagram showing a part of a threshold voltage compensation pixel structure of a diode connection method. FIG. 1 shows a driving transistor DT that supplies current to an organic light emitting diode, and a transistor ST connected between a gate node Ng and a drain node Nd of the driving transistor DT. The transistor ST connects the gate node Ng and the drain node Nd of the driving transistor DT while the data voltage is supplied to the driving transistor DT, so that the driving transistor DT becomes a diode. Let it drive.

Referring to FIG. 1, since the gate node Ng and the drain node Nd are connected during the data voltage supply period when the transistor ST is turned on, the gate node Ng and the drain node Nd are substantially equal. Has an electric potential When the voltage difference Vgs between the gate node Ng and the source node Ns is greater than the threshold voltage, the driving transistor DT has a voltage difference Vgs between the gate node Ng and the source node Ns. A current path is formed until the threshold voltage Vth of (DT) is reached, and accordingly, the voltages of the gate node Ng and the drain node Nd are charged. That is, when the data voltage Vdata is supplied to the source node Ns of the driving transistor DT, the voltages of the gate node Ng and the drain node Nd of the driving transistor DT are equal to the data voltage Vdata. It rises to the difference voltage Vdata-Vth between the threshold voltages Vth. For this reason, since the diode connection method can delete Vth in Equation 1, the threshold voltage Vth of the driving transistor DT can be compensated.

2 is a graph showing a current between a drain and a source of a driving transistor according to a voltage difference between a gate and a source in a gate-on bias state and a gate-off bias state. 1 and 2, a driving transistor according to a voltage difference between a gate and a source in an on bias state and an off bias state due to a hysteresis characteristic of the driving transistor DT. The drain-source current of is different.

The on-bias state refers to a state in which a gate-on voltage, such as a peak white grayscale voltage, is applied to the gate electrode of the driving transistor DT so that the drain-source current Ids of the driving transistor largely flows. The off-bias state refers to a state in which a gate-off voltage, such as a peak black grayscale voltage, is applied to the gate electrode of the driving transistor so that the drain-source current Ids of the driving transistor hardly flows. The peak white gradation voltage refers to a voltage applied to the gate electrode of the driving transistor DT to emit light by the organic light-emitting diode in the peak white gradation. It means the voltage applied to the gate electrode of (DT). Meanwhile, when the grayscale value is expressed as an 8-bit digital value, the peak black grayscale may mean "0" which is the minimum value, and the peak white grayscale may mean "255" which is the maximum value.

3 is a graph showing the luminance of a pixel when a peak black gradation voltage is supplied during a conventional p-th frame period and a peak white gradation voltage is supplied during the p+1th to p+3th frame periods. In FIG. 3, the peak black gray voltage is supplied to the gate electrode of the driving transistor DT during the p-th frame period, and the peak white gray voltage is supplied to the gate electrode of the driving transistor DT during the p+1th to p+3th frame periods. It was explained mainly about the supply of this.

1 to 3, since the peak black gradation voltage is supplied to the gate electrode of the driving transistor DT during the p-th frame period, the driving transistor DT is in the off-bias state during the p+1-th frame period. Receives the gradation voltage (PWGV). In contrast, since the peak white gray voltage is supplied to the gate electrode of the driving transistor DT during the p+1th frame period, the driving transistor DT is in the on-bias state during the p+2th frame period. ) Is supplied. Therefore, even if the same peak white gradation voltage PWMV is supplied to the gate electrode of the driving transistor DT during the p+1th and p+2th frame periods, the drain of the driving transistor DT during the p+1th frame period- The source-to-source current Ids is smaller than the drain-source current Ids of the driving transistor DT during the p+2th frame period. For this reason, as shown in FIG. 3, the amount of light emitted by the organic light emitting diode is smaller than that of the organic light emitting diode in the p+1th frame period than in the p+2th frame period. That is, the organic light emitting diode must emit light with the same peak white luminance during the p+1th and p+2th frame periods, but cannot emit light with the peak white luminance during the p+1th frame period as shown in FIG. 3. Accordingly, luminance deviation occurs in the p+1th frame period and the p+2th frame period, resulting in a problem of deteriorating image quality.

Hereinafter, an organic light emitting display device according to an embodiment of the present invention that solves the problem of image quality deterioration due to the hysteresis characteristic of the driving transistor DT described in conjunction with FIGS. 1 to 3 will be described with reference to FIGS. 4 to 11. It will be described in detail.

4 is a block diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention. 4, the organic light emitting display device according to an embodiment of the present invention includes a display panel 10, a data driver 20, a scan driver 30, a timing controller 40, a power supply source 50, and the like. Equipped.

The display panel 10 is formed such that the data lines DL1 to DLm, m is a positive integer greater than or equal to 2, and the scan lines SL1 to SLn+1, n is a positive integer greater than or equal to 2). In addition, emission lines EML1 to EMLn are formed in the display panel 10 in parallel with the scan lines SL1 to SLn+1. Further, pixels P arranged in a matrix form are formed on the display panel 10. A detailed description of the pixels P of the display panel 10 will be described later with reference to FIG. 5.

The data driver 20 includes a plurality of source drive ICs. The source drive ICs receive digital video data DATA from the timing controller 40. Source drive ICs generate data voltages by converting digital video data DATA into a gamma compensation voltage in response to a source timing control signal DCS from the timing controller 40, and display the data voltages in synchronization with the scan signals. It is supplied to the data lines DL of the panel 10. Accordingly, data voltages are supplied to the pixels P to which the scan signal is supplied.

The scan driver 30 includes a scan signal output circuit and a light emission signal output circuit. Each of the scan signal output circuit and the emission signal output circuit includes a shift register that sequentially generates an output signal, a level shifter for converting the output signal of the shift register into a swing width suitable for driving the transistor of the pixel P, and an output buffer. Can include.

The scan signal output circuit sequentially outputs scan signals to the scan lines SL1 to SLn of the display panel 10. The emission signal output circuit sequentially outputs emission signals to the emission lines EML1 to EMLn of the display panel 10. A detailed description of the scan signal and the emission signal will be described later with reference to FIG. 6.

The timing controller 40 receives digital video data DATA from a host system (not shown) through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 40 receives timing signals including a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The timing control unit 40 generates timing control signals for controlling operation timings of the data driver 20 and the scan driver 30 based on the timing signals. The timing control signals include a scan timing control signal SCS for controlling an operation timing of the scan driver 30 and a data timing control signal DCS for controlling an operation timing of the data driver 20. The timing controller 40 outputs the scan timing control signal SCS to the scan driver 30 and outputs the data timing control signal DCS to the data driver 20.

The power supply 50 supplies a first power voltage to the pixels P of the display panel 10 through a first power voltage line ViniL, and a second power voltage through the second power voltage line VDDL. Is supplied, and a third power voltage is supplied through the third power voltage line VSSL. Hereinafter, for convenience of explanation, the first power voltage is the initialization voltage Vini, the second power voltage is the high potential voltage ELVDD, and the third power voltage is the low potential voltage ELVSS. The high potential voltage ELVDD is a voltage higher than the low potential voltage ELVSS and the initialization voltage Vini. The high-potential voltage ELVDD, the initialization voltage Vini, and the low-potential voltage ELVSS may be preset to a voltage of an appropriate level through a pre-experiment.

In addition, the power supply source 50 may supply predetermined logic level voltages to the timing controller 40 and may supply a gate-on voltage and a gate-off voltage to the scan driver 30. The gate-on voltage refers to a turn-on voltage of the switch elements of the pixel P, and the gate-off voltage refers to the turn-off voltage of the switch elements of the pixel P.

5 is an equivalent circuit diagram showing the pixel of FIG. 4 in detail. Referring to FIG. 5, a pixel P according to an embodiment of the present invention includes a driving transistor DT, an organic light emitting diode (OLED), switch elements, and a storage capacitor (C). And the like. The switch elements include first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

The pixel P has a k-1th (k is a positive integer satisfying 2≤k≤n+1) scan line SLk-1, a kth scan line SLk, a kth emission line EMLk, And jth (j is a positive integer satisfying 1≦j≦m) data line Dj. In addition, the pixel P is a low-potential voltage line (VSSL) to which a low-potential voltage (ELVSS) is supplied, an initialization voltage line (ViniL) to which an initialization voltage (Vini) is supplied, and a high power supply to which a high-potential voltage (ELVDD) is supplied. It is connected to the above voltage line VDDL.

The driving transistor DT controls the drain-source current Ids according to the voltage of the gate electrode. The drain-source current Ids flowing through the channel of the driving transistor DT is proportional to the square of the difference between the gate-source voltage and the threshold voltage of the driving transistor DT, as shown in Equation 1. The gate electrode of the driving transistor DT is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3. Here, the first electrode may be a source electrode or a drain electrode, and the second electrode may be an electrode different from the first electrode. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode.

The organic light-emitting diode OLED emits light according to the drain-source current Ids of the driving transistor DT. The amount of light emitted from the organic light emitting diode OLED may be proportional to the drain-source current Ids of the driving transistor DT. The anode electrode of the organic light emitting diode OLED is connected to the second electrode of the fifth transistor ST5 and the first electrode of the sixth transistor ST6, and the cathode electrode is connected to the low potential voltage line VSSL.

The first transistor ST1 is connected between the first node N1 and the third node N3. The first transistor ST1 is turned on by the scan signal of the k-th scan line SLk to connect the first node N1 and the third node N3. That is, when the first transistor ST1 is turned on, since the gate electrode of the driving transistor DT and the second electrode are connected, the driving transistor DT is driven by a diode. The gate electrode of the first transistor ST1 is connected to the k-th scan line SLk, the first electrode is connected to the third node N3, and the second electrode is connected to the first node N1.

The second transistor ST2 is connected between the second node N2 and the data line DL. The second transistor ST2 is turned on by the scan signal of the k-th scan line SLk to connect the second node N2 and the j-th data line Dj. Accordingly, the data voltage of the jth data line Dj is supplied to the second node N2. The gate electrode of the second transistor ST2 is connected to the k-th scan line SLk, the first electrode is connected to the j-th data line DLj, and the second electrode is connected to the second node N2.

The third transistor ST3 is connected between the first node N1 and the initialization voltage line ViniL. The third transistor ST3 is turned on by the scan signal of the k-1th scan line SLk-1 to connect the first node N1 and the initialization voltage line ViniL. For this reason, the first node N1 is initialized to the initialization voltage Vini. The gate electrode of the third transistor ST3 is connected to the k-1th scan line SLk-1, the first electrode is connected to the first node N1, and the second electrode is connected to the initialization voltage line ViniL. Connected.

The fourth transistor ST4 is connected between the anode electrode of the organic light emitting diode OLED and the initialization voltage line ViniL. The fourth transistor ST4 is turned on by a scan signal of the k-1th scan line SLk-1 to connect the anode electrode of the organic light emitting diode OLED to the initialization voltage line ViniL. For this reason, the anode electrode of the organic light emitting diode OLED is discharged to the initialization voltage Vini. The gate electrode of the fourth transistor ST4 is connected to the k-1 th scan line SLk-1, the first electrode is connected to the anode electrode of the organic light emitting diode OLED, and the second electrode is connected to the initialization voltage line ( ViniL).

The fifth transistor ST5 is connected between the high potential voltage line VDDL and the second node N2. The fifth transistor ST5 is turned on by the emission signal of the kth emission line EMLk to connect the second node N2 and the high potential voltage line VDDL. For this reason, the high potential voltage ELVDD is supplied to the second node N2. The gate electrode of the fifth transistor ST5 is connected to the kth emission line EMLk, the first electrode is connected to the high potential voltage line VDDL, and the second electrode is connected to the second node N2.

The sixth transistor ST6 is connected between the third node N3 and the anode electrode of the organic light emitting diode OLED. The sixth transistor ST6 is turned on by the emission signal of the kth emission line EMLk to connect the third node N3 and the anode electrode of the organic light emitting diode OLED. The gate electrode of the sixth transistor ST6 is connected to the kth emission line EMLk, the first electrode is connected to the third node N3, and the second electrode is connected to the anode electrode of the organic light emitting diode (OLED). do. When the fifth and sixth transistors T5 and T6 are turned on, the drain-source current Ids of the driving transistor DT is supplied to the organic light emitting diode OLED.

The storage capacitor C is connected between the first node N1 and the high potential voltage line VDDL to maintain the voltage of the first node N1. One electrode of the storage capacitor C is connected to the first node N1, and the other electrode is connected to the high potential voltage line VDDL.

In addition, a parasitic capacitance (Coled) of the organic light emitting diode (OLED) may be formed between the anode electrode and the cathode electrode of the organic light emitting diode (OELD). In addition, a parasitic capacitance PC may be formed between the gate electrode GE of the driving transistor DT and the anode electrode of the organic light emitting diode OLED. As the parasitic capacitance PC between the gate electrode GE of the driving transistor DT and the anode electrode of the organic light emitting diode (OLED) increases, the anode electrode of the organic light emitting diode (OLED) is driven by the parasitic capacitance (PC). It may rise under the influence of the gate electrode GE of DT). In this case, there may be a problem in that the low potential voltage ELVSS supplied through the low potential voltage line VSSL is raised by the parasitic capacitor Colled of the organic light emitting diode OLED. An increase in the low potential voltage ELVSS may cause a problem in that the color coordinates are shifted. Accordingly, the embodiment of the present invention is implemented in a structure that minimizes the size of the parasitic capacitance (PC). A detailed description of this will be described later in conjunction with FIGS. 10 to 14.

The first node N1 can be considered to correspond to a gate node connected to the gate electrode of the driving transistor DT. The first node N1 is a contact point between the gate electrode of the driving transistor DT, the second electrode of the first transistor ST1, the first electrode of the third transistor ST3, and one electrode of the capacitor C. The second node N2 can be considered to correspond to a source node connected to the first electrode of the driving transistor DT. The second node N2 is a contact point between the first electrode of the driving transistor DT, the second electrode of the second transistor ST2, and the second electrode of the fifth transistor T5. The third node N3 can be considered to correspond to a drain node connected to the second electrode of the driving transistor DT. The third node N3 is a contact point between the second electrode of the driving transistor DT, the first electrode of the first transistor ST1, and the first electrode of the sixth transistor ST6.

The semiconductor layers of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, and the driving transistor DT may be formed of polysilicon, but are not limited thereto, and a- It may be formed of any of Si, and an oxide semiconductor, especially oxide. When the semiconductor layers of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, and the driving transistor DT are formed of polysilicon, the process for forming them is low temperature polysilicon. Poly Silicon: LTPS) process.

In addition, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6), and the driving transistor (DT) has been described focusing on the formation of a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but limited to this. It is not, and may be formed of an N-type MOSFET. When the first to sixth transistors ST1, ST2, ST3, ST4, ST5, ST6, and the driving transistor DT are formed of an N-type MOSFET, the timing diagram of FIG. 6 should be modified to match the characteristics of the N-type MOSFET. something to do.

Meanwhile, the high potential voltage ELVDD, the low potential voltage ELVSS, and the initialization voltage Vini may be set in consideration of the characteristics of the driving transistor DT and the characteristics of the organic light emitting diode OLED.

6 is a waveform diagram showing signals input to the pixel of FIG. 5. 6, the k-th scan line SLk-1 of the display panel 10 is supplied with a k-th during q (q is a positive integer) and q+1th frame periods FRq and FRq+1. A first scan signal SCANk-1, a kth scan signal SCANk supplied to the kth scan line SLk, and a kth emission signal EMk supplied to the kth emission line EMLk are shown.

Referring to FIG. 6, the k-1th scan signal SCANk-1 is a signal for controlling the third and fourth transistors ST3 and ST4, and the kth scan signal SCANk is the first and second transistors. These are signals for controlling (ST1, ST2), and the k-th light emitting signal EMk is a signal for controlling the fifth and sixth transistors ST5 and ST6. Each of the scan signals and the light emission signals occurs in a period of one frame as shown in FIG. 6.

Each of the scan signals may be generated as a gate-on voltage Von for one horizontal period 1H as shown in FIG. 6. One horizontal period 1H indicates one horizontal line scanning period in which a data voltage is supplied to each of the pixels P connected to one scan line of the display panel 10. The data voltages are supplied to the data lines DL1 to DLm in synchronization with the scan signals.

One frame period may be divided into first to fourth periods t1 to t4. The first period t1 is a period in which an on bias is applied to the driving transistor DT, and the second period t2 is a period in which the first node N1 connected to the gate electrode of the driving transistor DT is initialized. , The third period t3 is a period in which the data voltage is supplied and the threshold voltage of the driving transistor DT is sensed, and the fourth period t4 is a period in which the organic light emitting diode OLED emits light.

The k-1th scan signal SCANk-1 is generated as a gate-on voltage Von during the first and second periods t1 and t2, and the kth scan signal SCANk is gated during the third period t3. It occurs as an on voltage (Von). The k-th emission signal EMk is generated as a gate-off voltage Voff during the second and third periods t2 and t3. Each of the first to third periods t1, t2, and t3 may be appropriately determined in advance through a prior experiment. The gate-on voltage Von corresponds to a turn-on voltage capable of turning on each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6. The gate-off voltage Voff corresponds to a turn-off voltage capable of turning off each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

7 is a flowchart illustrating an operation of a pixel during first to fourth periods. 8A to 8D are equivalent circuit diagrams showing pixels during first to fourth periods. Hereinafter, the operation of the pixel P according to the first exemplary embodiment of the present invention during the first to fourth periods t1 to t4 will be described in detail with reference to FIGS. 6, 7, and 8A to 8D.

First, the operation of the pixel P during the first period t1 in which the on-bias is applied to the driving transistor DT will be described. During the first period t1, the k-1 th scan signal SCANk-1 having the gate-on voltage Von is supplied to the pixel P through the k-1 th scan line SLk-1 as shown in FIG. 6. Then, the k-th emission signal EMk having the gate-on voltage Von is supplied through the k-th emission line EMLk.

Referring to FIG. 8A, during a first period t1, the third and fourth transistors ST3 and ST4 are generated by the k-1th scan signal SCANk-1 of the k-1th scan line SLk-1. It turns on. The fifth and sixth transistors ST5 and ST6 are turned on by the kth emission signal EMk of the kth emission line EMLk.

Due to the turn-on of the third transistor ST3, the first node N1 is initialized to the initialization voltage Vini. Also, due to the turn-on of the fourth, fifth and sixth transistors ST4, ST5, and ST6, the high potential voltage line VDDL, the fifth transistor ST5, the driving transistor DT, and the sixth transistor ( A current path is formed through ST6, the fourth transistor ST4, and the initialization voltage line ViniL. Specifically, the drain-source current Ids of the driving transistor DT flows according to "Vini-ELVDD", which is the gate-source voltage Vgs of the driving transistor DT.

As described above, in the exemplary embodiment of the present invention, the gate electrode of the driving transistor DT is discharged to the initialization voltage Vini during the first period t1 to apply an on-bias to the driving transistor DT. As a result, in the first embodiment of the present invention, since a predetermined on-bias can be applied to the driving transistor DT before the third period t3 for supplying the data voltage, the hysteresis characteristic of the driving transistor DT The problem of deteriorating image quality can be solved. A detailed description of this will be described later with reference to FIG. 9. (S101 in Fig. 7)

Second, the operation of the pixel P during the second period t2 in which the first node N1 connected to the gate electrode of the driving transistor DT is initialized will be described. During the second period t2, the k-1 th scan signal SCANk-1 having the gate-on voltage Von is supplied to the pixel P through the k-1 th scan line SLk-1 as shown in FIG. 6. do.

Referring to FIG. 8B, during a second period t2, the third and fourth transistors ST3 and ST4 are generated by the k-1th scan signal SCANk-1 of the k-1th scan line SLk-1. It turns on.

Due to the turn-on of the third transistor ST3, the first node N1 is initialized to the initialization voltage Vini. Due to the turn-on of the fourth transistor ST4, the anode electrode of the organic light emitting diode OLED is initialized to the initialization voltage Vini. In order to prevent the organic light emitting diode OLED from emitting light during the second period t2, the initialization voltage Vini may be set to a level substantially the same as the low potential voltage ELVSS. (S102 in Fig. 7)

Third, the operation of the pixel P during the third period t3 in which the data voltage is supplied and the threshold voltage of the driving transistor DT is sensed will be described. During the third period t3, the k-th scan signal SCANk having the gate-on voltage Von is supplied to the pixel P through the k-th scan line SLk as shown in FIG. 6.

Referring to FIG. 8C, during a third period t3, the first and second transistors ST1 and ST2 are turned on by the kth scan signal SCANk of the kth scan line SLk.

Since the first node N1 is connected to the third node N3 due to the turn-on of the first transistor ST1, the driving transistor DT is driven by a diode. The data voltage Vdata is supplied to the second node N2 due to the turn-on of the second transistor ST2. At this time, since the voltage difference (Vgs=Vini-Vdata) between the gate electrode of the driving transistor DT and the first electrode is greater than the threshold voltage Vth, the driving transistor DT has a voltage difference between the gate electrode and the first electrode ( A current path is formed until Vgs) reaches the threshold voltage Vth. Accordingly, the voltage of the first node N1 rises to the difference voltage Vdata-Vth between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT during the third period t3. (S103 in Fig. 7)

Fourth, the operation of the pixel P during the fourth period t4 in which the organic light emitting diode OLED emits light will be described. During the fourth period t4, the k-th emission signal EMk having the gate-on voltage Von is supplied to the pixel P through the k-th emission line EMLk as shown in FIG. 6.

Referring to FIG. 8D, during a fourth period t4, the fifth and sixth transistors ST5 and ST6 are turned on by the kth emission signal EMk of the kth emission line EMLk.

Due to the turn-on of the fifth transistor ST5, the second node N2 connected to the first electrode of the driving transistor DT is connected to the first power voltage line ELVDDL. Due to the turn-on of the sixth transistor ST6, the second electrode of the driving transistor DT is connected to the organic light emitting diode OLED. That is, due to the turn-on of the fifth and sixth TFTs T5 and T6, the driving transistor DT has a drain-source current Ids according to the voltage of the first node N1 connected to its gate electrode. Is supplied to an organic light emitting diode (OLED). At this time, the first node N1 calculates the difference voltage Vdata-Vth between the data voltage Vdata sensed by the capacitor C during the third period t3 and the threshold voltage Vth of the driving transistor DT. Keep. The drain-source current Ids of the driving transistor DT may be defined as in Equation 2.

In Equation 2, k is a proportional coefficient determined by the structure and physical characteristics of the driving transistor DT, Vgs is the gate-source voltage of the driving transistor DT, Vth is the threshold voltage of the driving transistor DT, ELVDD Denotes a first power voltage, and Vdata denotes a data voltage. The gate voltage Vg of the driving transistor DT is {Vdata-Vth}, and the source voltage Vs is ELVDD. When Equation 2 is summarized, Equation 3 is derived.

Consequently, as shown in Equation 3, the drain-source current Ids of the driving transistor DT does not depend on the threshold voltage Vth of the driving transistor DT. That is, the threshold voltage Vth of the driving transistor DT is compensated. (S104 in Fig. 7)

As described above, the exemplary embodiment of the present invention may compensate for the threshold voltage of the driving transistor DT. As a result, since the drain-source current Ids of the driving transistor DT supplied to the organic light emitting diode OLED does not depend on the threshold voltage Vth of the driving transistor, the exemplary embodiment of the present invention relates to a pixel of a display panel. The brightness of the fields can be made uniform.

9 is a graph showing the luminance of a pixel when a peak black gradation voltage is supplied during a p-th frame period and a peak white gradation voltage is supplied during a p+1th to p+3th frame period in an exemplary embodiment of the present invention. In FIG. 9, a peak black gray voltage is supplied to the gate electrode of the driving transistor DT during the p-th frame period, and the peak white gray voltage is supplied to the gate electrode of the driving transistor DT during the p+1th to p+3th frame periods. It was explained mainly about the supply of this.

According to an exemplary embodiment of the present invention, the gate electrode of the driving transistor DT is discharged to the initialization voltage Vini during the first period t1 to apply an on-bias to the driving transistor DT. As a result, in the exemplary embodiment of the present invention, the same on-bias may be applied to the driving transistor DT regardless of the voltage supplied to the gate electrode of the driving transistor DT during the previous frame period. Referring to FIG. 9, even if the peak black gray voltage is supplied to the gate electrode of the driving transistor DT during the p-th frame period, the driving transistor DT is turned on during the first period t1 of the p+1-th frame period. Since is applied, the driving transistor DT is in an on-bias state during the p+1th frame period. Accordingly, during the p+1th frame period, the organic light-emitting diode OLED emits light with almost peak white luminance as shown in FIG. 9.

That is, in the exemplary embodiment of the present invention, the driving transistor DT is applied to a predetermined on-bias before the third period t3 in which the data voltage is supplied during one frame period. Therefore, since luminance deviation caused by the hysteresis characteristic of the driving transistor TD can be prevented, a problem of deteriorating image quality can be solved.

10 is a plan view showing in detail the driving transistor and the first transistor of FIG. 5. 11 is a cross-sectional view taken along line A-A' of FIG. 10. In the following, referring to FIGS. 10 and 11, the gate electrode GE of the driving transistor DT of the pixel P, the first electrode SO of the first transistor ST1, and The connection of the semiconductor layer ACT2 of the first transistor ST1 will be described in detail.

10 and 11, a semiconductor pattern ACT including the semiconductor layer ACT1 of the driving transistor DT and the semiconductor layer ACT2 of the first transistor ST1 is formed on the lower substrate 101. . The semiconductor pattern ACT may be formed on a buffer layer (not shown) of the lower substrate 101. The semiconductor pattern ACT may be formed of polysilicon, but is not limited thereto, and may be formed of any one of a-Si and an oxide semiconductor, especially oxide.

A gate insulating layer GI is formed on the semiconductor pattern ACT. The gate insulating layer GI may be formed of silicon nitride (SiNx).

A first gate metal pattern GM1 including the gate electrode GE of the driving transistor DT is formed on the gate insulating layer GI. The semiconductor pattern ACT and the first gate metal pattern GM1 are insulated by the gate insulating layer GI.

A first interlayer insulating layer ILD1 is formed on the first gate metal pattern GM1. The first interlayer insulating layer ILD1 may be formed of silicon nitride (SiNx). On the first interlayer insulating layer ILD1, a second gate metal pattern GM2 including a k-th scan line SLk, a gate electrode GE_ST1 of the first transistor ST1, a horizontal high potential voltage line H_VDDL, etc. Is formed. The first gate metal pattern GM1 and the second gate metal pattern GM2 are insulated by the first interlayer insulating layer ILD1.

A second interlayer insulating layer ILD2 is formed on the second gate metal pattern GM2. The second interlayer insulating layer ILD2 may be formed of a double layer of silicon nitride (SiNx)/silicon dioxide (SiO ₂ ).

A source/drain metal pattern SDM including a first electrode SO of the first transistor ST1 and a vertical high potential voltage line V_VDDL is formed on the second interlayer insulating layer ILD2. The source/drain metal pattern may be formed in a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti). The second gate metal pattern GM2 and the source/drain metal pattern SDM are insulated by the second interlayer insulating layer ILD2.

Meanwhile, the first electrode SO of the first transistor ST1 is connected to the gate electrode GE of the driving transistor DT and the semiconductor layer ACT2 of the first transistor ST1 through the first contact hole CNT1. Connected. The first contact hole CNT1 penetrates the gate insulating layer and the first and second interlayer insulating layers ILD1 and ILD2 to form the gate electrode GE of the driving transistor DT and the semiconductor layer ACT2 of the first transistor ST1. ) Is exposed.

Further, the high potential voltage line VDDL includes a horizontal high potential voltage line H_VDDL formed in a horizontal direction (x-axis direction) and a vertical high potential voltage line V_VDDL formed in a vertical direction (y-axis direction). I can. The horizontal high potential voltage line H_VDDL may be formed as the second gate metal pattern GM2, while the vertical high potential voltage line V_VDDL may be formed as a source/drain metal pattern SDM. In this case, the horizontal high potential voltage line H_VDDL and the vertical high potential voltage line V_VDDL may be connected through a predetermined contact hole. The predetermined contact hole may penetrate the second interlayer insulating layer IDL2 to expose the horizontal high potential voltage line H_VDDL. In addition, the overlapping region between the horizontal high potential voltage line H_VDDL formed by the second gate metal pattern GM2 and the gate electrode GE of the driving transistor DT formed by the first gate metal pattern GM1 is the storage capacitor C ).

A passivation layer PAS is formed on the source/drain metal pattern SDM. The passivation layer PAS may be formed of polyimide.

An anode electrode pattern ANDP including an anode electrode AND of an organic light emitting diode OLED is formed on the passivation layer PAS. The anode electrode pattern ANDP may be formed in a three-layer structure of ITO/Ag/ITO. The source/drain metal pattern SDM and the anode electrode pattern ANDP are insulated by the passivation layer PAS.

Meanwhile, referring to FIGS. 5, 6, 10 and 11, the organic light emitting diode OLED during the second and third periods t2 and t3 in which the anode electrode AND of the organic light emitting diode OLED is floating. The voltage of the anode electrode AND of may rise under the influence of the gate electrode GE of the driving transistor DT by the parasitic capacitance PC. In this case, there may be a problem in that the low potential voltage ELVSS supplied through the low potential voltage line VSSL is raised by the parasitic capacitor Colled of the organic light emitting diode OLED. An increase in the low potential voltage ELVSS may cause a problem in that the color coordinates are shifted. To prevent this, the parasitic capacitance PC formed between the gate electrode GE of the driving transistor DT and the anode electrode of the organic light emitting diode OLED should be minimized.

In an embodiment of the present invention, as shown in FIGS. 10 and 11, the driving transistor DT is to prevent the first electrode SO of the first transistor ST1 from overlapping with the anode electrode AND of the organic light emitting diode OLED. The gate electrode GE of is extended to overlap the semiconductor layer ACT2 of the first transistor ST1 and is connected to the first electrode SO of the first transistor ST1. Accordingly, in the embodiment of the present invention, the parasitic capacitance PC is formed in an overlapping region between the anode electrode AND of the organic light emitting diode OLED and the gate electrode GE of the driving transistor DT. The reason why the first electrode SO of the first transistor ST1 does not overlap the anode electrode AND of the organic light emitting diode OLED is that the first electrode SO of the first transistor ST1 is an organic light emitting diode. This is because, when overlapping with the anode electrode AND of the (OLED), the parasitic capacitance PC is formed in the overlapping region between them. The distance between the first electrode SO of the first transistor ST1 and the anode electrode AND of the organic light emitting diode OLED is the first of the anode electrode AND of the organic light emitting diode OLED and the driving transistor DT. Since it is closer than the distance between the gate electrodes GE1, the parasitic capacitance PC formed in the overlapping region between the first electrode SO of the first transistor ST1 and the anode electrode AND of the organic light emitting diode OLED The size is larger than the size of the parasitic capacitance PC formed in the overlapping region between the anode electrode AND of the organic light emitting diode OLED and the first gate electrode GE1 of the driving transistor DT.

That is, according to the exemplary embodiment of the present invention, the size of the parasitic capacitance PC formed between the anode electrode of the organic light emitting diode OLED and the gate electrode GE of the driving transistor DT can be minimized. As a result, the embodiment of the present invention is the anode electrode of the organic light emitting diode (OLED) due to the parasitic capacitance (PC) formed between the anode electrode of the organic light emitting diode (OLED) and the gate electrode (GE) of the driving transistor DT. You can minimize this effect. Accordingly, according to an exemplary embodiment of the present invention, a shift in color coordinates due to an increase in the low potential voltage ELVSS can be prevented, and thus a deterioration in image quality can be prevented.

12 is another plan view illustrating in detail the driving transistor and the first transistor of FIG. 5. 13 is an exemplary view showing a cross section taken along line B-B' of FIG. 12.

The cross section of FIG. 12A-A' is substantially the same as the cross section of FIG. 11 except that the kth scan line SLk of FIG. 11 is changed to the second island pattern IP2. Therefore, a detailed description of the cross-section of A-A' of FIG. 12 will be omitted.

Hereinafter, a cross-sectional view taken along line B-B' of FIG. 12 will be described in detail with reference to FIGS.

In the exemplary embodiment of the present invention, the gate electrode GE of the driving transistor DT is extended to overlap the active layer ACT2 of the first transistor ST1 as shown in FIG. 12. ) And the anode electrode (AND) of the organic light emitting diode (OLED) to minimize the parasitic capacitance (PC). In FIG. 10, in order to avoid a short circuit between the gate electrode GE of the driving transistor DT and the k-th scan line SLk, the k-th scan line SLk and the gate electrode GE1_ST1 of the first transistor ST1 are first formed. 2 formed by the gate metal pattern GM2. However, in FIG. 12, the k-th scan line SLk and the gate electrode GE1_ST1 of the first transistor ST1 are formed as the first gate metal pattern GM1. For this reason, a means for avoiding a short circuit between the gate electrode GE of the driving transistor DT and the k-th scan line SLk must be provided.

12 and 13, the k-th scan line SLk is connected to the first island patterns IP1 through the second contact hole CNT2. The first island patterns IP1 may be formed outside both sides of the gate electrode GE of the driving transistor DT. It should be noted that the first island patterns IP1 are preferably formed of a source/drain metal pattern SDM, but are not limited thereto. When the first island patterns IP1 are formed of the source/drain metal patterns SDM, the second contact hole CNT2 passes through the first and second interlayer insulating layers IDL1 and IDL2 to pass through the k-th scan line ( SLk).

Each of the first island patterns IP1 is connected to the second island pattern IP2 through a third contact hole CNT3. It should be noted that the second island pattern IP2 is preferably formed of the second gate metal pattern GM2, but is not limited thereto. When the second island pattern IP2 is formed of the second gate metal pattern GM2, the third contact hole CNT3 penetrates the second interlayer insulating layer IDL2 to expose the second island pattern IP2. Further, in this case, the second island pattern IP2 crosses the gate electrode GE of the driving transistor DT above the gate electrode GE of the driving transistor DT, as shown in FIGS. 12 and 13.

As a result, according to an embodiment of the present invention, the k-th scan line is connected to the first island patterns IP1, each of the first island patterns IP1 is connected to the second island pattern IP2, and the driving transistor DT The gate electrode GE of the driving transistor DT and the second island pattern IP2 are crossed over the gate electrode GE of ). As a result, in the exemplary embodiment of the present invention, even if the gate electrode GE and the k-th scan line SLk of the driving transistor DT are formed as the first gate metal pattern GM1, the gate electrode of the driving transistor DT ( GE) and the k-th scan line SLk can be avoided.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 20: data driver
30: scan driving unit 40: timing control unit
OLED: organic light emitting diode DT: driving transistor
ST1: first transistor ST2: second transistor
ST3: third transistor ST4: fourth transistor
ST5: fifth transistor ST6: sixth transistor
C: capacitor N1: first node
N2: second node N3: third node

Claims (15)

And a display panel on which data lines and scan lines are formed, and pixels arranged in a matrix form are formed,
Each of the pixels,
A driving transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
An organic light emitting diode emitting light according to a current between a drain and a source of the driving transistor; And
And a first transistor connected between the first node and the third node,
A first electrode of the first transistor is connected to the third node, a second electrode of the first transistor is connected to the first node,
The gate electrode of the driving transistor overlaps the semiconductor layer of the first transistor,
The organic light emitting display device, wherein the first electrode of the first transistor does not overlap with the anode electrode of the organic light emitting diode. The method of claim 1,
And the gate electrode of the driving transistor is connected to the first electrode of the first transistor through a first contact hole. The method of claim 2,
The first electrode of the first transistor is connected to the semiconductor layer of the first transistor through the first contact hole. The method of claim 3,
The first contact hole is an organic light emitting display device, characterized in that formed through a plurality of insulating layers. delete The method of claim 3,
Wherein the gate electrode of the driving transistor overlaps the semiconductor layer of the driving transistor on the semiconductor layer of the driving transistor. The method of claim 6,
Organic electroluminescence, characterized in that the gate electrode of the driving transistor is formed of a first gate metal pattern, and the gate electrode of the first transistor is formed of a second gate metal pattern formed above the first gate metal pattern. Display device. The method of claim 6,
An organic light emitting display device, wherein the gate electrode of the driving transistor and the gate electrode of the first transistor are formed in a first gate metal pattern. The method of claim 8,
The organic light emitting display device according to claim 1, wherein the scan line connected to the gate electrode of the first transistor is formed of the first gate metal pattern. The method of claim 9,
The scan line connected to the gate electrode of the first transistor is connected to the first island electrodes through second contact holes, and each of the first island electrodes is connected to the second island electrode through a third contact hole. An organic light emitting display device comprising: The method of claim 10,
The first island electrodes are formed in a source/drain metal pattern,
The second island electrode is formed of a second gate metal pattern. The method of claim 10,
And the second island electrode crosses the gate electrode of the driving transistor above the gate electrode of the driving transistor. The method of claim 1,
Light emitting lines parallel to the scan lines are further formed on the display panel,
Each of the pixels,
A second transistor that is turned on by a scan signal of a k-th (k is a positive integer equal to or greater than 2) scan line to connect the j-th (j is a positive integer) data line to the second node;
A third transistor turned on by a scan signal of a k-1th scan line to connect the first node to a first power voltage line to which a first power voltage is supplied;
A fourth transistor turned on by the scan signal of the k-1th scan line to connect the anode electrode of the organic light emitting diode to the first power voltage line;
A fifth transistor which is turned on by an emission signal of the k-th emission line to connect the second node and a second power voltage line to which a second power voltage is supplied;
A sixth transistor that is turned on by the emission signal of the k-th emission line to connect the third node and an anode electrode of the organic light emitting diode; And
And a capacitor connected between the first node and the second power voltage line. The method of claim 13,
The first transistor is turned on by a scan signal of the k-th scan line to connect the first node and the third node. The method of claim 14,
The scan signal of the k-1th scan line is generated as a gate-on voltage during the first and second periods,
The scan signal of the k-th scan line is generated as a gate-on voltage during a third period,
The organic light emitting display device according to claim 1, wherein the emission signal of the kth emission line is generated by a gate-on voltage during first and fourth periods.

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