KR102348669B1 - Organic light emitting display device and method for driving the same - Google Patents

Abstract

The present invention relates to an organic light emitting diode display capable of minimizing a change in the gate voltage of a driving transistor for each pixel due to a difference in capacitance of a storage capacitor due to a process variation in manufacturing the organic light emitting display device. An organic light emitting diode display according to an embodiment of the present invention includes a first scan line and a light emission control line. A driving transistor including a data line intersecting the first scan line and the emission control line, an organic light emitting diode, a gate electrode, a source electrode, and a drain electrode connected to the organic light emitting diode, by a first scan signal of the first scan line a first transistor that is turned on to connect the data line to the gate electrode of the driving transistor, a second transistor that is turned on by a light emission control signal of the emission control line to connect the first power voltage line to the source electrode of the driving transistor; A first capacitor is formed between the first power voltage line and the gate electrode of the driving transistor, and a second capacitor is formed between the emission control line and the gate electrode of the driving transistor.

Description

Organic light emitting display device and driving method thereof

The present invention relates to an organic light emitting display device and a driving method thereof.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have recently been used. Among them, the organic light emitting display device can be driven at a low voltage, is thin, has an excellent viewing angle, and has a fast response speed.

An organic light emitting display device includes a display panel including data lines, scan lines, pixels formed at intersections of data lines and scan lines, a scan driver supplying scan signals to the scan lines, and a data voltage to the data lines and a data driver for supplying them. Each of the pixels includes an organic light emitting diode, a driving transistor that adjusts the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, and data on the data line in response to the scan signal of the scan line. A scan transistor for supplying a voltage to the gate electrode of the driving transistor, and a storage capacitor for maintaining the voltage of the gate electrode of the driving transistor for a predetermined period.

The threshold voltage of the driving transistor may vary for each pixel due to a process deviation during manufacturing of the organic light emitting display device or deterioration of the driving transistor due to long-term driving. That is, when the same data voltage is applied to the pixels, the current supplied to the organic light emitting diode must be the same. However, even when the same data voltage is applied to the pixels due to the difference in the threshold voltage of the driving transistor between the pixels, The supplied current may vary for each pixel. To solve this problem, each of the pixels may further include a plurality of transistors and light emission control lines to compensate for the threshold voltage of the driving transistor.

However, the complexity of each of the pixels may be increased by the plurality of transistors and the emission control lines, and thus an unwanted parasitic capacitance may be formed between the scan line and the gate electrode of the driving transistor. In this case, the amount of voltage change of the scan signal applied to the scan line may be reflected in the gate electrode of the driving transistor by the parasitic capacitance. A voltage change amount of the scan signal reflected to the gate electrode of the driving transistor by the parasitic capacitance may be defined as a kickback voltage. After sampling the threshold voltage of the driving transistor to the gate electrode of the driving transistor, when the gate electrode of the driving transistor is affected by the kickback voltage, the threshold voltage sampled at the gate electrode of the driving transistor may be distorted.

Meanwhile, the capacity of the storage capacitor may vary for each pixel due to process variations in manufacturing the organic light emitting diode display, and the kickback voltage applied to the gate electrode of the driving transistor may vary according to the capacity of the storage capacitor. For example, if the capacity of the storage capacitor is greater than the originally intended design capacity, the magnitude of the kickback voltage applied to the gate electrode of the driving transistor may be reduced. In addition, if the capacity of the storage capacitor is smaller than the originally intended design capacity, the magnitude of the kickback voltage applied to the gate electrode of the driving transistor may be increased.

As described above, since the capacity of the storage capacitor varies due to a process deviation in manufacturing the organic light emitting diode display, the level of the kickback voltage applied to the gate electrode of the driving transistor may vary according to the parasitic capacitance for each pixel. Accordingly, there is a need for a method capable of minimizing the effect of the distortion of the threshold voltage sampled on the gate electrode of the driving transistor.

An object of the present invention is to provide an organic light emitting display device capable of minimizing a change in the gate voltage of a driving transistor for each pixel due to a difference in capacitance of a storage capacitor due to a process deviation in manufacturing the organic light emitting display device.

An organic light emitting diode display according to an embodiment of the present invention includes a first scan line and a light emission control line. A driving transistor including a data line intersecting the first scan line and the emission control line, an organic light emitting diode, a gate electrode, a source electrode, and a drain electrode connected to the organic light emitting diode, by a first scan signal of the first scan line a first transistor that is turned on to connect the data line to the gate electrode of the driving transistor, a second transistor that is turned on by a light emission control signal of the emission control line to connect the first power voltage line to the source electrode of the driving transistor; A first capacitor is formed between the first power voltage line and the gate electrode of the driving transistor, and a second capacitor is formed between the emission control line and the gate electrode of the driving transistor.

A method of driving an organic light emitting display device according to an embodiment of the present invention includes supplying an initialization voltage of an initialization line to a gate electrode of a driving transistor, supplying a data voltage of a data line to a first electrode of the driving transistor, and Sampling the threshold voltage of the driving transistor to the gate electrode, and calculating the voltage change amount of the gate electrode of the driving transistor due to the parasitic capacitor formed between the gate electrode and the scan line of the driving transistor is formed between the gate electrode of the driving transistor and the emission control line 2 Compensating by the capacitor, and emitting light from the organic light emitting diode according to the voltage of the gate electrode of the driving transistor.

According to an embodiment of the present invention, after sampling the threshold voltage at the gate electrode of the driving transistor for the second period, the voltage increase of the gate electrode of the driving transistor due to the parasitic capacitor is reduced by the voltage drop of the gate electrode of the driving transistor due to the second capacitor can be compensated in minutes. Accordingly, according to the embodiment of the present invention, it is possible to reduce a change in the current between the drain and the source of the driving transistor due to the parasitic capacitor.

In addition, according to an embodiment of the present invention, the gate electrode of the driving transistor includes a gate metal pattern and a data metal pattern, and the data metal pattern and the gate electrode of the first transistor are disposed adjacent to each other to form a first parasitic capacitor, A second parasitic capacitor is formed in an overlapping area of the data metal pattern and the kth scan line, and a second capacitor is formed in an overlapping area of the data metal pattern and the kth light emitting line. As a result, in the embodiment of the present invention, when the voltage of the k-th scan line changes, the voltage change amount of the gate electrode of the driving transistor due to the parasitic capacitor changes the voltage of the driving transistor due to the second capacitor when the voltage of the k-th light emitting line changes. It can be offset by the amount of voltage change of the gate electrode.

According to an embodiment of the present invention, even if a difference in capacitance of the first capacitor occurs due to a process deviation in manufacturing an organic light emitting display device, the voltage change amount of the kth light emitting line is reflected by the second capacitor, so that the driving transistor using the parasitic capacitor is used. can offset the change in gate voltage. As a result, according to the exemplary embodiment of the present invention, it is possible to minimize a change in the gate voltage of the driving transistor for each pixel due to a difference in capacitance of the first capacitor due to a process deviation in manufacturing the organic light emitting diode display.

1 is a perspective view illustrating an organic light emitting display device according to an embodiment of the present invention.
2 is a block diagram illustrating an organic light emitting display device according to an exemplary embodiment.
3 is a circuit diagram illustrating in detail a pixel according to an embodiment of the present invention.
4 is a k-1th scan signal applied to the k-1th scan line shown in FIG. 3, a kth scan signal applied to the kth scan line, and a kth emission control signal applied to the kth emission control line; and a waveform diagram showing the gate voltage of the driving transistor.
5 is a flowchart illustrating a method of driving a pixel according to an exemplary embodiment of the present invention.
6A to 6D are circuit diagrams illustrating the operation of the pixel of FIG. 3 during first to fourth periods of FIG. 4 .
FIG. 7 is a plan view illustrating in detail the driving transistor, the first transistor, the first capacitor, the second capacitor, and the parasitic capacitor shown in FIG. 3 .
8 is a cross-sectional view taken along line A-A' of FIG. 7 .
9 is a waveform diagram showing the gate voltage of the driving transistor according to the presence or absence of the second capacitor and the capacitance of the first capacitor.

Like reference numerals refer to substantially identical elements throughout. In the following description, a detailed description of configurations and functions known in the art and cases not related to the core configuration of the present invention may be omitted. The meaning of the terms described in this specification should be understood as follows.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than within the scope where the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of “at least one of the first, second, and third items” means that each of the first, second, or third items as well as two of the first, second and third items It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view illustrating an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 1 , an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 , a data driver 20 , a timing controller 50 , a flexible source film 61 , and a circuit board 62 . includes

The display panel 10 includes a first substrate 11 and a second substrate 12 . The first substrate 11 may be a glass substrate or a plastic film. A thin film transistor layer 11a, a light emitting device layer 11b, and an encapsulation layer 11c may be formed on the first substrate 11 as shown in FIG. 2 ,

The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film (barrier film).

The data driver 20 may be formed in a chip shape like a source drive integrated circuit (IC) and mounted on the source flexible film 61 . The source flexible film 61 may be a tape carrier package or a chip on film. The source flexible film 61 may be bent or bent. The source flexible film 61 may be attached to the first substrate 11 and the circuit board 62 . The flexible film 61 may be attached on the first substrate 11 by a tape automated bonding (TAB) method using an anisotropic conductive film.

1 illustrates that the data driver 20 includes one source drive IC, but is not limited thereto. The data driver 20 may include a plurality of source drive ICs 21 . In this case, each source drive IC 21 may be mounted on each source flexible film 61 and attached to the lower substrate 11 and the circuit board 62 of the display panel 10 .

The timing controller 50 may be formed in the form of a chip and mounted on the circuit board 62 . Also, the power supply unit may be mounted on the circuit board 62 . The circuit board 62 may be a flexible printed circuit board or a printed circuit board.

2 is a block diagram illustrating an organic light emitting display device according to an exemplary embodiment.

Referring to FIG. 2 , an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 , a data driver 20 , and a timing controller 50 , as well as a scan driver 30 and a light emission control driver 40 . ) is further included.

The display panel 10 includes a display area AA and a non-display area NDA provided around the display area AA. The display area AA is an area in which pixels P are provided to display an image. The display panel 10 includes data lines D1 to Dm, where m is a positive integer greater than or equal to 2), scan lines S1 to Sn, and n is a positive integer greater than or equal to 2), and light emission control lines E1 to En. this is formed The data lines D1 to Dm may be formed to cross the scan lines S1 to Sn and the emission control lines E1 to En. The scan lines S1 to Sn and the light emission control lines E1 to En may be formed in parallel with each other.

Each of the pixels P of the display panel 10 may include any one of the data lines D1 to Dm, any two of the scan lines S1 to Sn, and any one of the emission control lines E1 to En. can be connected to one. Each of the pixels P of the display panel 10 includes a driving transistor, a plurality of switching transistors controlled by scan signals of scan lines and an emission control signal of an emission control line, and an organic light emitting diode. diode), and a plurality of capacitors. A detailed description of the pixel P will be described later with reference to FIG. 3 .

The data driver 20 is connected to the data lines D1 to Dm to supply data voltages. The data driver 20 receives digital video data DATA and a source timing control signal DCS from the timing controller 50 . The data driver 20 converts the digital video data DATA into data voltages according to the source timing control signal DCS and supplies them to the data lines D1 to Dm.

The scan driver 30 is connected to the scan lines S1 to Sn to supply scan signals. The scan driver 30 sequentially supplies scan signals to the scan lines S1 to Sn according to the scan timing control signal SCS input from the timing controller 50 .

The light emission control driver 40 is connected to the light emission control lines E1 to En to supply light emission control signals. Specifically, the emission control driver 40 supplies emission control signals to the emission control lines E1 to En according to the emission timing control signal ECS input from the timing controller 50 .

The timing controller 50 receives digital video data DATA from the outside. The timing controller 50 generates timing control signals for controlling operation timings of the data driver 20 , the scan driver 30 , and the emission control driver 40 . The timing control signals are a data timing control signal DCS for controlling the operation timing of the data driver 20 , a scan timing control signal SCS for controlling the operation timing of the scan driver 30 , and the emission control driver 40 . and a light emission timing control signal ECS for controlling the operation timing of the .

The timing controller 50 outputs digital video data DATA and a data timing control signal DCS to the data driver 20 . The timing controller 50 outputs the scan timing control signal SCS to the scan driver 30 . The timing controller 50 outputs the initialization timing control signal SENCS to the initialization driver 40 .

3 is a circuit diagram illustrating in detail a pixel according to an embodiment of the present invention.

Referring to FIG. 3 , the pixel P includes a driving transistor DT, an organic light emitting diode (OLED), switch elements, a first capacitor C1, and a second capacitor. (C2) and the like. The switch elements include first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 .

The pixel P has a k-1th (k is a positive integer satisfying 2≤k≤n+1) scan line Sk-1, a kth scan line Sk, and a kth emission control line Ek. , and jth (j is a positive integer satisfying 1≤j≤m) data line Dj. In addition, the pixel P is supplied with the first power voltage line VSSL to which the first power voltage ELVSS is supplied, the initialization voltage line VIL to which the initialization voltage Vini is supplied, and the second power voltage ELVDD is supplied. connected to the second power supply voltage line VDDL.

The driving transistor DT controls the drain-source current Ids according to the voltage of the gate electrode DG. The drain-source current Ids flowing through the channel of the driving transistor DT is proportional to the square of the difference between the gate-source voltage of the driving transistor DT and the threshold voltage as shown in Equation (1).

The organic light emitting diode OLED emits light according to the drain-source current Ids of the driving transistor DT. The amount of light emitted from the organic light emitting diode OLED may be proportional to the drain-source current Ids of the driving transistor DT. The anode electrode of the organic light emitting diode OLED is connected to the first electrode of the fourth transistor ST4 and the second electrode of the fifth transistor ST5 , and the cathode electrode is connected to the low potential voltage line VSSL.

The first transistor ST1 is turned on by the scan signal of the k-th scan line Sk to connect the source electrode DS of the driving transistor DT and the j-th data line Dj. The gate electrode of the first transistor ST1 is connected to the k-th scan line Sk, the first electrode is connected to the j-th data line Dj, and the second electrode is the source electrode DS of the driving transistor DT. ) is connected to

The second transistor ST2 is turned on by the emission control signal of the k-th emission control line Ek to connect the source electrode DS of the driving transistor DT and the second power voltage line VDDL. The gate electrode of the second transistor ST is connected to the k-th emission control line Ek, the first electrode is connected to the second power voltage line VDDL, and the second electrode is the source electrode of the driving transistor DT. connected to (DS).

The third transistor ST3 is turned on by the scan signal of the k-th scan line Sk to connect the gate electrode DG and the drain electrode DD of the driving transistor DT. That is, when the third transistor ST3 is turned on, the gate electrode DG and the drain electrode DD of the driving transistor DT are connected, so that the driving transistor DT is driven as a diode. The gate electrode of the third transistor ST3 is connected to the k-th scan line Sk, the first electrode is connected to the drain electrode DD of the driving transistor DT, and the second electrode of the driving transistor DT is connected to the second electrode. It is connected to the gate electrode DG.

The fourth transistor ST4 is turned on by the scan signal of the k−1th scan line Sk−1 to connect the anode electrode of the organic light emitting diode OLED and the initialization voltage line VIL. Accordingly, the anode electrode of the organic light emitting diode (OLED) may be discharged to the initialization voltage (Vini). The gate electrode of the fourth transistor ST4 is connected to the k-1th scan line Sk-1, the first electrode is connected to the anode electrode of the organic light emitting diode OLED, and the second electrode is connected to the initialization voltage line Sk-1. VIL) is connected.

The fifth transistor ST5 is connected between the drain electrode DD of the driving transistor DT and the anode electrode of the organic light emitting diode OLED. The fifth transistor ST5 is turned on by the emission signal of the k-th emission control line Ek to connect the drain electrode DD of the driving transistor DT and the anode electrode of the organic light emitting diode OLED. The gate electrode of the fifth transistor ST5 is connected to the k-th light emitting line EMLk, the first electrode is connected to the drain electrode DD of the driving transistor DT, and the second electrode is the organic light emitting diode OLED. is connected to the anode electrode of When the second and fifth transistors T2 and T5 are turned on, the drain-source current Ids of the driving transistor DT is supplied to the organic light emitting diode OLED.

The sixth transistor ST6 is turned on by the scan signal of the k−1th scan line Sk−1 to connect the gate electrode DG of the driving transistor DT to the initialization voltage line VIL. The gate electrode of the fourth transistor ST4 is connected to the k-1 th scan line Sk-1, the first electrode is connected to the gate electrode DG of the driving transistor DT, and the second electrode is the initialization voltage. connected to the line VIL.

The first capacitor C1 is formed between the gate electrode DG of the driving transistor DT and the second power voltage line VDDL to maintain the voltage of the gate electrode DG of the driving transistor DT for a predetermined period of time. make it One electrode of the first capacitor C1 is connected to the gate electrode DG of the driving transistor DT, and the other electrode is connected to the second power voltage line VDDL.

The second capacitor C2 may be formed between the gate electrode DG of the driving transistor DT and the kth emission control line Ek. One electrode of the second capacitor C2 is connected to the gate electrode DG of the driving transistor DT, and the other electrode of the second capacitor C2 is connected to the k-th emission control line Ek.

In addition, a parasitic capacitance (Cp) may be formed between the gate electrode DG of the driving transistor DT and the k-th scan line Sk.

Each of the semiconductor layers of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, and the driving transistor DT may be formed of any one of polysilicon, amorphous silicon, and oxide semiconductor. may be When the semiconductor layers of the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , ST6 , and the driving transistor DT are each formed of polysilicon, a process for forming the semiconductor layer is low temperature polysilicon (Low Temperature). Poly Silicon: LTPS) process.

In addition, in FIG. 3 , the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 , and the driving transistor DT are mainly formed of a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). , but is not limited thereto, and may be formed of an N-type MOSFET. When the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , ST6 , and the driving transistor DT are formed of an N-type MOSFET, the timing diagram of FIG. 5 must be modified to match the characteristics of the N-type MOSFET. something to do.

The first power voltage EVSS, the second power voltage ELVDD, and the initialization voltage Vini may be set in consideration of the characteristics of the driving transistor DT and the characteristics of the organic light emitting diode OLED. In this case, the initialization voltage Vini may be set such that the difference between the initialization voltage Vini and the data voltage Vdata supplied to the pixels P is greater than the threshold voltage of the driving transistor DT of each of the pixels P. have.

4 is a k-1th scan signal applied to the k-1th scan line shown in FIG. 3, a kth scan signal applied to the kth scan line, and a kth emission control signal applied to the kth emission control line; and a waveform diagram showing the gate voltage of the driving transistor.

Referring to FIG. 4 , the k−1th scan signal SCANk−1 is a signal for controlling the sixth transistor ST6 , and the k−th scan signal SCANk is applied to the first, third and fourth transistors ST6. The signal is for controlling ST1 , ST3 , and ST4 , and the kth emission control signal EMk is a signal for controlling the second and fifth transistors ST2 and ST5 . Each of the scan signals and the emission signals may be generated with a period of one frame period.

One frame period may be divided into first to fourth periods t1 to t4. The first period t1 is a period for initializing the gate electrode DG of the driving transistor DT, and the second period t2 is for initializing the anode electrode of the organic light emitting diode OLED and the source of the driving transistor DT. A data voltage is supplied to the electrode DS and a threshold voltage is sampled to the gate electrode DG of the driving transistor DT, and the third period t3 is the The voltage increase of the gate electrode DG is removed by the second capacitor C2 , and the fourth period t4 is a period in which the organic light emitting diode OLED is emitted.

The k-1th scan signal SCANk-1 is generated as the gate-on voltage Von during the first period t1, and the k-th scan signal SCANk is the gate-on voltage Von during the second period t2. occurs with The kth emission signal EMk is generated as the gate-on voltage Von during the fourth period t4. The k-th emission signal EMk may fall twice at a falling edge according to the design of the emission control driver 40 .

In FIG. 5 , each of the first and second periods t1 and t2 is exemplified as one horizontal period 1H, but the present invention is not limited thereto and may be appropriately determined in advance through a prior experiment. One horizontal period 1H indicates one horizontal line scan period in which a data voltage is supplied to each of the pixels P connected to a certain scan line of the display panel 10 . The data voltages are supplied to the data lines D1 to Dm in synchronization with the scan signals.

The gate-on voltage Von corresponds to a turn-on voltage capable of turning on each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6. The gate-off voltage Voff corresponds to a turn-off voltage capable of turning off each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

5 is a flowchart illustrating a method of driving a pixel according to an exemplary embodiment of the present invention. 6A to 6D are circuit diagrams illustrating the operation of the pixel of FIG. 3 during first to fourth periods of FIG. 4 .

Hereinafter, the operation of the pixel P during the first to fourth periods t1 to t4 will be described in detail with reference to FIGS. 5 and 6A to 6D .

First, in the pixel P during the first period t1 , as shown in FIG. 5 , the k−1th scan signal SCANk− having the gate-on voltage Von through the k−1th scan line Sk−1 1) is supplied. During the first period t1 , as shown in FIG. 6A , the sixth transistor ST6 is turned on by the k−1th scan signal SCANk−1 having the gate-on voltage Von.

Due to the turn-on of the sixth transistor ST6 , the gate electrode DG of the driving transistor DT is initialized to the initialization voltage Vini. Due to the turn-on of the fourth transistor ST4 , the gate electrode DG of the driving transistor DT is initialized to the initialization voltage Vini. (S101 in FIG. 5)

Second, during the second period t2 , the k-th scan signal SCANk having the gate-on voltage Von is supplied to the pixel P through the k-th scan line Sk as shown in FIG. 5 . During the second period t2 , as shown in FIG. 6B , each of the first, third, and fourth transistors ST1 , ST3 , and ST4 is turned on by the k-th scan signal SCANk having the gate-on voltage Von. do.

Since the gate electrode DG of the driving transistor DT is connected to the drain electrode DD due to the turn-on of the first transistor ST1 , the driving transistor DT is driven as a diode. Due to the turn-on of the third transistor ST3 , the data voltage Vdata is supplied to the source electrode DS of the driving transistor DT. At this time, since the voltage difference (Vgs=Vini-Vdata) between the gate electrode DG and the source electrode DS of the driving transistor DT is greater than the threshold voltage Vth, the driving transistor DT has a gate electrode and a source electrode A current path is formed until the voltage difference Vgs between them reaches the threshold voltage Vth. Accordingly, the voltage of the gate electrode DG of the driving transistor DT is increased to a voltage Vdata+Vth that is the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT during the second period t2. rises As shown in FIG. 6 , when the driving transistor DT is formed of a P-type MOSFET, the threshold voltage Vth may be set to a negative value.

Also, due to the turn-on of the fourth transistor ST4 , the anode electrode of the organic light emitting diode OLED is initialized to the initialization voltage Vini. (S102 in FIG. 5)

Third, a signal having the gate-on voltage Von is not supplied to the pixel P during the third period t3 as shown in FIG. 5 . During the third period t3 , as shown in FIG. 6C , the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 are turned off.

Meanwhile, at a time point of the third period t3 , the k-th scan signal SCANk rises from the gate-on voltage Von to the gate-off voltage Voff. For this reason, the amount of voltage change of the k-th scan signal SCANk by the parasitic capacitor Cp formed between the gate electrode DG of the driving transistor DT and the k-th scan line Sk is the gate of the driving transistor DT. It may be reflected in the electrode DG. When the k-th scan signal SCANk increases from the gate-on voltage Von to the gate-on voltage Voff, the voltage increase ΔV1 of the gate electrode DG of the driving transistor DT due to the parasitic capacitor Cp may be defined as a kickback voltage.

At the end of the third period t3 , the k-th emission signal EMk falls from the gate-off voltage Voff to the gate-on voltage Von. Accordingly, the voltage change amount of the kth light emitting signal ENk by the second capacitor C2 formed between the gate electrode DG of the driving transistor DT and the kth light emitting line Ek is that of the driving transistor DT. It may be reflected in the gate electrode DG. When the k-th emission signal EMk falls from the gate-off voltage Voff to the gate-on voltage Von, the voltage drop of the gate electrode DG of the driving transistor DT due to the second capacitor C2 ( The voltage of the gate electrode DG of the driving transistor DT may be lowered by ΔV2 . Accordingly, the voltage increase ΔV1 of the gate electrode DG of the driving transistor DT due to the parasitic capacitor Cp is the voltage drop of the gate electrode DG of the driving transistor DT due to the second capacitor C2. It can be compensated by (ΔV2). (S103 in FIG. 5)

Fourth, during the fourth period t4 , the kth emission signal EMk is supplied to the pixel P by applying the gate-on voltage Von as shown in FIG. 5 . During the fourth period t4 , as shown in FIG. 6D , each of the second and fifth transistors ST2 and ST5 is turned on by the kth emission signal EMk having the gate-on voltage Von.

Due to the turn-on of the second transistor ST2 , the source electrode DS of the driving transistor DT is connected to the first power voltage line VDDL. Due to the turn-on of the fifth transistor ST5 , the drain electrode DD of the driving transistor DT is connected to the anode electrode of the organic light emitting diode OLED.

As a result, due to the turn-on of the second and fifth transistors ST2 and ST5, the driving transistor DT converts the drain-source current Ids according to the voltage of the gate electrode DG to the organic light emitting diode OLED. ) is supplied to At this time, the voltage of the gate electrode DG of the driving transistor DT may be “Vdata+Vth+ΔV1-ΔV2”, so that the drain-source current Ids of the driving transistor DT is obtained by Equation 2 and can be defined together.

In Equation 2, k' is a proportional coefficient determined by the structure and physical characteristics of the driving transistor DT, Vth is the threshold voltage of the driving transistor DT, ELVDD is the first power supply voltage, Vdata is the data voltage, and ΔV1 is A voltage increase of the gate electrode DG of the driving transistor DT due to the parasitic capacitor Cp, ΔV2 means a voltage drop of the gate electrode DG of the driving transistor DT due to the second capacitor C2 . The gate voltage Vg of the driving transistor DT is (Vdata+Vth), and the source voltage Vs is ELVDD. By rearranging Equation 2, Equation 3 is derived.

As a result, as shown in Equation 3, the drain-source current Ids of the driving transistor DT does not depend on the threshold voltage Vth of the driving transistor DT. That is, the threshold voltage Vth of the driving transistor DT is compensated. (S104 in FIG. 6)

As described above, in the embodiment of the present invention, the threshold voltage of the driving transistor DT can be compensated. As a result, the drain-source current Ids of the driving transistor DT supplied to the organic light emitting diode OLED does not depend on the threshold voltage Vth of the driving transistor. may emit light with uniform luminance.

In addition, according to the embodiment of the present invention, the gate of the driving transistor DT is caused by the parasitic capacitor Cp after sampling the threshold voltage Vth to the gate electrode DG of the driving transistor DT during the second period t2. The voltage increase ΔV1 of the electrode DG may be compensated by the voltage decrease ΔV2 of the gate electrode DG of the driving transistor DT due to the second capacitor C2 . Accordingly, according to the exemplary embodiment of the present invention, it is possible to reduce a change in the drain-source current of the driving transistor DT due to the parasitic capacitor Cp.

On the other hand, the voltage increase ΔV1 of the gate electrode DG of the driving transistor DT due to the parasitic capacitor Cp is the voltage decrease of the gate electrode DG of the driving transistor DT due to the second capacitor C2 Since it is desirable to make it substantially equal to (ΔV2), the capacitance of the second capacitor C2 may be set in consideration of this. The capacitance of the second capacitor C2 is preferably designed to be similar to the capacitance of the parasitic capacitor Cp. For example, the capacitance of the second capacitor C2 is 0.5 to 1 times the capacitance of the parasitic capacitor Cp. can be a boat In addition, in order to stably maintain the voltage of the gate electrode DG of the driving transistor DT by the first capacitor C1, the capacitance of the first capacitor C1 is equal to that of the second capacitor C2 and the parasitic capacitor Cp. ) It is desirable to design larger than each capacity.

FIG. 7 is a plan view illustrating in detail the driving transistor, the first transistor, the first capacitor, the second capacitor, and the parasitic capacitor shown in FIG. 3 . 8 is a cross-sectional view taken along line A-A' of FIG. 7 .

7 and 8 , the lower substrate 11 may include a support substrate 11a and a plastic substrate 11b. The support substrate 11a may be glass or plastic. When the support substrate 11a is plastic, it may be formed of polyethylene terephthalate (PET). The plastic substrate 11b may be a flexible polyimide film.

A buffer layer 110 may be formed on the lower substrate 11 . The buffer layer 110 may be formed on the lower substrate 11 to protect the thin film transistors and light emitting devices from moisture penetrating through the lower substrate 11 which is vulnerable to moisture permeation. The buffer layer 110 may be formed of a plurality of inorganic layers alternately stacked. For example, the buffer layer 110 may be formed as a multilayer in which one or more inorganic layers _{of a silicon oxide layer (SiO x} ), a silicon nitride layer (SiN _{x ), and SiON are alternately stacked.} The buffer layer 110 may be omitted.

A semiconductor pattern 120 is formed on the buffer layer 110 . The semiconductor pattern 120 may include a semiconductor layer of the driving transistor DT, a semiconductor layer of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, and connection patterns connecting them. have. The semiconductor pattern 120 may be formed of any one of polysilicon, amorphous silicon, and oxide semiconductor.

A gate insulating layer 130 is formed on the semiconductor pattern 120 . The gate insulating layer 130 may be formed of an inorganic layer, for example, a silicon oxide layer (SiO _x ), a silicon nitride layer (SiN _x ), or a multilayer thereof.

On the gate insulating layer 130 , the gate metal pattern GP of the gate electrode DG of the driving transistor DT, the gate electrode SG1 of the first transistor ST1, the kth scan line Sk, and the kth light emission The first metal pattern 140 including the line Ek is formed. The first metal pattern 140 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed as a single layer or multiple layers made of an alloy thereof. The semiconductor pattern 120 and the first metal pattern 140 are insulated by the gate insulating layer 130 .

A first interlayer insulating layer 150 is formed on the first metal pattern 140 . The first interlayer insulating layer 150 may be formed of an inorganic layer, for example, a silicon oxide layer (SiO _x ), a silicon nitride layer (SiN _x ), or a multilayer thereof.

A second metal pattern 160 including one side electrode CE1 of the first capacitor C1 is formed on the first interlayer insulating layer 150 . The second metal pattern 160 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed as a single layer or multiple layers made of an alloy thereof. The first metal pattern 140 and the second metal pattern 160 are insulated by the first interlayer insulating layer 150 .

A second interlayer insulating layer 170 is formed on the second metal pattern 160 . The second interlayer insulating layer 170 may be formed of an inorganic layer, for example, a silicon oxide layer (SiO _x ), a silicon nitride layer (SiN _x ), or a multilayer thereof.

On the second interlayer insulating layer 170 , the data metal pattern DP of the gate electrode DG of the driving transistor DT, the j-th data line Dj, the first power voltage line VDDL, and the anode connection pattern AP ) including a third metal pattern 180 is formed. The third metal pattern 180 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed as a single layer or multiple layers made of an alloy thereof. The second metal pattern 160 and the third metal pattern 180 are insulated by the second interlayer insulating layer 170 .

The gate electrode DG of the driving transistor DT includes a gate metal pattern GP and a data metal pattern DP. The data metal pattern DP penetrates through the first interlayer insulating layer 150 and the second interlayer insulating layer 170 to expose the gate metal pattern GP to the gate metal pattern GP through the first contact hole CH1. can be connected. In addition, the data metal pattern DP has a second contact hole CH2 penetrating through the gate insulating layer 130 , the first interlayer insulating layer 150 , and the second interlayer insulating layer 170 to expose the semiconductor pattern 120 . Through this, the semiconductor pattern 120 corresponding to the drain electrode of the first transistor T1 may be connected. Accordingly, the gate electrode DG of the driving transistor DT may be connected to the drain electrode of the first transistor T1 .

The second power supply voltage line VDDL passes through the second interlayer insulating layer 170 and passes through the third contact hole CH3 exposing one electrode CE1 of the first capacitor C1 to the first capacitor C1. may be connected to one side electrode CE1 of Accordingly, the first capacitor C1 is formed in the overlapping region of the gate metal pattern GP of the driving transistor DT and the one electrode CE1 of the first capacitor C1. The second capacitor C2 is formed in an overlapping region of the data metal pattern DP of the driving transistor DT and the k-th emission line Ek.

The parasitic capacitor Cp includes a first parasitic capacitor Cp1 formed between the data metal pattern DP of the gate electrode DG of the driving transistor DT and the gate electrode SG1 of the first transistor T1, and the driving A second parasitic capacitor Cp2 formed in an overlapping region of the data metal pattern DP of the gate electrode DG of the transistor DT and the k-th scan line Sk may be included. The first parasitic capacitor Cp1 may be an adjacent capacitor formed by disposing the data metal pattern DP adjacent to the gate electrode SG of the first transistor ST1.

The capacitance of the first capacitor C1 may be changed by adjusting the size of the overlapping region of the gate metal pattern GP of the driving transistor DT and the one electrode CE1 of the first capacitor C1 . The capacitance of the second capacitor C2 may be changed by adjusting the size of the overlapping area of the data metal pattern DP and the k-th light emitting line Ek. The capacitance of the first parasitic capacitor Cp1 is determined by the degree of proximity between the data metal pattern DP and the gate electrode SG of the first transistor T1, and the capacitance of the second parasitic capacitor Cp2 is determined by the data metal pattern. It is determined by the size of the overlapping area of (DP) and the k-th scan line (Sk).

As described above, according to the embodiment of the present invention, the gate electrode DG of the driving transistor DT includes a gate metal pattern SP and a data metal pattern DP, and the data metal pattern DP and A first parasitic capacitor Cp1 is formed by disposing the gate electrode SG of the first transistor ST1 adjacent to each other, and a second parasitic capacitor is formed in the overlapping region of the data metal pattern DP and the kth scan line Sk. Cp2 is formed, and a second capacitor C2 is formed in an overlapping region of the data metal pattern DP and the k-th emission line Ek. As a result, in the embodiment of the present invention, when the voltage of the k-th scan line Sk is changed, the voltage change amount of the gate electrode DG of the driving transistor DT due to the parasitic capacitor Cp is calculated by the k-th light emitting line Ek. ) may be offset by a voltage change of the gate electrode DG of the driving transistor DT due to the second capacitor C2.

9 is a detailed waveform diagram illustrating a gate voltage change of a driving transistor during a third period according to the presence or absence of the second capacitor and the capacitance of the first capacitor.

Referring to FIG. 9 , the first gate voltage Vg1 is the gate voltage of the driving transistor DT when the capacity of the first capacitor C1 is designed to be smaller than the original intention when the second capacitor C2 does not exist. It is a waveform diagram showing, and the second gate voltage Vg2 shows the gate voltage of the driving transistor DT when the capacitance of the first capacitor C1 is designed as originally intended when the second capacitor C2 does not exist. It is a waveform diagram, and the third gate voltage Vg3 is a waveform showing the gate voltage of the driving transistor DT when the capacity of the first capacitor C1 is designed to be larger than the original intention when the second capacitor C2 does not exist. It is also

In addition, the fourth gate voltage Vg4 is a waveform diagram showing the gate voltage of the driving transistor DT when the capacity of the first capacitor C1 is designed to be smaller than the original intention when the second capacitor C2 is present, The fifth gate voltage Vg5 is a waveform diagram showing the gate voltage of the driving transistor DT when the capacity of the first capacitor C1 is designed as originally intended when the second capacitor C2 is present, and the sixth gate voltage Vg5 is The gate voltage Vg6 is a waveform diagram showing the gate voltage of the driving transistor DT when the capacity of the first capacitor C1 is designed to be larger than the original intention when the second capacitor C2 is present.

As the capacitance of the first capacitor C1 decreases, the gate voltage of the driving transistor DT is more affected by the kickback voltage caused by the parasitic capacitor Cp. Accordingly, during the third period t3, the first gate voltage Vg1 and the fourth gate voltage Vg4 increase the most by the kickback voltage caused by the parasitic capacitor Cp, and the second gate voltage Vg2 and the second gate voltage Vg4 The fifth gate voltage Vg5 rises the next most, and the third gate voltage Vg3 and the sixth gate voltage Vg6 rise the least.

Meanwhile, when the second capacitor C2 does not exist, the gate voltage of the driving transistor DT maintains a voltage increase due to the parasitic capacitor Cp. Accordingly, each of the first to third gate voltages Vg1 , Vg2 , and Vg3 maintains a voltage increase due to the parasitic capacitor Cp during the third period t3 .

However, when the second capacitor C2 is present, the gate voltage of the driving transistor DT is lowered by reflecting the voltage change of the kth light emitting line EMk due to the second capacitor C2 . Accordingly, during the third period t3 , each of the fourth to sixth gate voltages Vg4 , Vg5 , and Vg6 is lowered by reflecting the voltage change amount of the kth light emitting line EMk. The k-th emission signal EMk may fall twice at a falling edge as shown in FIG. 4 according to the design of the emission control driver 40 , so that the fourth to sixth gate voltages Vg4 , Vg5, Vg6) can each be lowered twice.

When the second capacitor C2 is present, each of the fourth to sixth gate voltages Vg4, Vg5, and Vg6 is lowered by reflecting the voltage change of the k-th light emitting line EMk, and thus the fourth gate voltage Vg4 A difference between the and the sixth gate voltage Vg6 may be smaller than a difference between the first gate voltage Vg1 and the third gate voltage Vg3. That is, according to the embodiment of the present invention, even if a difference in capacitance of the first capacitor C1 occurs due to a process deviation during the manufacturing of the organic light emitting diode display, the k-th light emitting line EMk is reduced by the second capacitor C2. By reflecting the voltage change amount, the gate voltage change amount of the driving transistor DT due to the parasitic capacitor Cp may be offset. As a result, according to the exemplary embodiment of the present invention, it is possible to minimize a change in the gate voltage of the driving transistor DT for each pixel due to a difference in capacitance of the first capacitor C1 due to a process deviation in manufacturing the organic light emitting diode display.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

10: display panel 20: data driver
30: scan driver 40: light emission signal driver
50: timing controller 61: source flexible film
62: circuit board P: pixel
OLED: organic light emitting diode DT: driving transistor
ST1: first transistor ST2: second transistor
ST3: third transistor ST4: fourth transistor
ST5: fifth transistor ST6: sixth transistor
C1: first capacitor C2: second capacitor
Cp: parasitic capacitor

Claims (13)

a first scan line;
light emission control line;
a data line crossing the first scan line and the light emission control line;
organic light emitting diodes;
a driving transistor including a gate electrode, a source electrode, and a drain electrode connected to the organic light emitting diode;
a first transistor turned on by a first scan signal of the first scan line to connect the data line to a source electrode of the driving transistor;
a second transistor turned on by a light emission control signal of the light emission control line to connect a first power supply voltage line to a source electrode of the driving transistor;
a first capacitor formed between the first power voltage line and a gate electrode of the driving transistor; and
a second capacitor formed between the light emission control line and the gate electrode of the driving transistor;
The capacity of the second capacitor is smaller than that of the first capacitor. delete The method of claim 1,
and a parasitic capacitor formed between the scan line and a gate electrode of the driving transistor. 4. The method of claim 3,
A capacitance of the parasitic capacitor is smaller than a capacitance of the first capacitor. 4. The method of claim 3,
The gate electrode of the driving transistor,
a gate metal pattern overlapping the semiconductor layer and disposed on the same metal layer as the first scan line and the light emission control line; and
An organic light emitting diode display comprising a data metal pattern connected to the gate metal pattern through a first contact hole. 6. The method of claim 5,
The parasitic capacitor is formed in a region where the data metal pattern and the first scan line overlap each other;
The second capacitor is formed in a region where the data metal pattern and the light emission control line overlap each other. 6. The method of claim 5,
The first contact hole is formed through an interlayer insulating layer disposed between the gate metal pattern and the data metal pattern to insulate the gate metal pattern and the data metal pattern. 6. The method of claim 5,
The data metal pattern is connected to the semiconductor layer through a second contact hole. 9. The method of claim 8,
The second contact hole includes an interlayer insulating layer disposed between the gate metal pattern and the data metal pattern to insulate the gate metal pattern and the data metal pattern, and the gate metal pattern to insulate the gate metal pattern and the semiconductor layer. An organic light emitting diode display formed through a gate insulating layer disposed between the pattern and the semiconductor layer. The method of claim 1,
a third transistor turned on by the first scan signal of the first scan line to connect the gate electrode and the drain electrode of the driving transistor;
a fourth transistor turned on by the first scan signal of the first scan line to connect the anode electrode of the organic light emitting diode to an initialization voltage line; and
and a fifth transistor turned on by the emission control signal of the emission control line to connect the anode electrode of the organic light emitting diode to the drain electrode of the driving transistor. 11. The method of claim 10,
a second scan line parallel to the first scan line; and
and a sixth transistor turned on by a second scan signal of the second scan line to connect a gate electrode of the driving transistor to the initialization voltage line. 12. The method of claim 11,
During a first period, the second scan signal is generated as a gate-on voltage, and during a second period subsequent to the first period, the first scan signal is generated as a gate-on voltage;
The light emission control signal is generated as a gate-off voltage during the first period and the second period. supplying an initialization voltage of an initialization line to a gate electrode of the driving transistor;
supplying a data voltage of a data line to a source electrode of the driving transistor and sampling a threshold voltage of the driving transistor to a gate electrode of the driving transistor;
compensating for a voltage change of the gate electrode of the driving transistor due to the parasitic capacitor formed between the gate electrode and the scan line of the driving transistor by a second capacitor formed between the gate electrode of the driving transistor and the emission control line; and
and emitting light from the organic light emitting diode according to the voltage of the gate electrode of the driving transistor.

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