KR102463347B1 - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting diode display capable of reducing manufacturing cost by reducing the number of source drive ICs. The present invention includes data lines, scan lines intersecting the data lines and parallel to each other, and sensing lines, and pixels including a plurality of sub-pixels. Two sub-pixels adjacent to each other in the scan line direction are connected to the same data line and are connected to different scan lines. Sub-pixels of two pixels adjacent to each other in the data line direction are connected to the same sensing line.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

An embodiment of the present invention relates to an organic light emitting display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, various display devices, such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED), have recently been used.

Among them, the organic light emitting display device can be driven at a low voltage, is thin, has an excellent viewing angle, and has a fast response speed. An organic light emitting display device includes a display panel including data lines, scan lines, a plurality of pixels formed at intersections of data lines and scan lines, a scan driver supplying scan signals to the scan lines, and a data line. Source drive ICs supplying data voltages. Each of the pixels includes an organic light emitting diode, a driving transistor that adjusts the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, and data on the data line in response to the scan signal of the scan line. and a scan transistor supplying a voltage to the gate electrode of the driving transistor.

The threshold voltage of the driving transistor may vary for each pixel due to a process deviation during manufacturing of the organic light emitting display device or a threshold voltage shift of the driving transistor due to long-term driving. Therefore, when the same data voltage is applied to the pixels, the current Ids of the driving transistor supplied to the organic light emitting diode should be the same, but even when the same data voltage is applied to the pixels, the threshold voltage and electrons of the driving transistor between the pixels Due to the difference in mobility, the current Ids of the driving transistor supplied to the organic light emitting diode varies for each pixel. As a result, even when the same data voltage is applied to the pixels, the luminance emitted by the organic light emitting diode varies for each pixel. To solve this problem, a compensation method for compensating the threshold voltage of the driving transistor has been proposed.

The compensation method is largely divided into an internal compensation method and an external compensation method. The internal compensation method is a method of compensating by sensing the threshold voltage of the driving transistor inside the pixel. The external compensation method supplies a preset data voltage to the pixel, senses the current (Ids) of the driving transistor of the pixel according to the preset data voltage through a sensing line, converts it into digital data, and uses the sensed digital data to A method of compensating for digital video data to be supplied to the pixel.

The external compensation method requires a sensing data output unit that senses the current (Ids) of the driving transistor of the pixel through a sensing line, converts it into sensing data that is digital data, and outputs the sensed data. The sensing data output unit is built into the source drive IC. For this reason, in the external compensation method, the source drive ICs are connected to the sensing lines as well as the data lines. Accordingly, since the number of source drive ICs increases, there is a problem in that the manufacturing cost of the organic light emitting display device increases.

An embodiment of the present invention provides an organic light emitting diode display capable of reducing manufacturing cost by reducing the number of source drive ICs.

An organic light emitting diode display according to an embodiment of the present invention includes data lines, scan lines crossing the data lines and parallel to each other, sensing lines, and pixels including a plurality of sub-pixels. Two sub-pixels adjacent to each other in the scan line direction are connected to the same data line and are connected to different scan lines. Sub-pixels of two pixels adjacent to each other in the data line direction are connected to the same sensing line.

According to an embodiment of the present invention, a data voltage may be supplied to the first to fourth sub-pixels using two scan lines and two data lines. Accordingly, according to the embodiment of the present invention, the number of data lines can be reduced by half compared to when the data voltage is supplied to the first to fourth sub-pixels using one scan line and four data lines in the related art. Accordingly, the embodiment of the present invention can reduce the manufacturing cost by reducing the number of source drive ICs.

According to the embodiment of the present invention, sub-pixels of the other two pixels P adjacent to each other are connected to one sensing line and one reference voltage line. For this reason, according to the embodiment of the present invention, when a sensing signal is supplied to one sensing line, currents of driving transistors of sub-pixels of other two adjacent pixels may be sensed through one reference voltage line. Accordingly, in the embodiment of the present invention, the number of sensing lines can be reduced, so that the aperture ratio of each sub-pixel of the pixels can be increased.

1 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention.
FIG. 2 is an exemplary view illustrating a lower substrate, source drive ICs, timing controller, data compensation unit, flexible films, source circuit board, flexible cable, and control circuit board of the display panel of FIG. 1 .
3 is a block diagram illustrating the source drive IC of FIG. 2 in detail.
FIG. 4 is an exemplary view showing in detail some of the pixels of the display area of FIG. 1 .
FIG. 5 is a circuit diagram illustrating in detail some of the pixels of the display area of FIG. 1 .
6 illustrates first to eighth scan signals applied to first to eighth scan lines and first and second sensing signal lines applied to first and second sensing signal lines during Nth and N+1th frame periods; 2 It is a waveform diagram showing sensing signals.
FIG. 7 is another exemplary view showing in detail pixels of the display area of FIG. 1 .
8 is a circuit diagram illustrating in detail some of the pixels of FIG. 7 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described as 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than the range in which the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention. FIG. 2 is an exemplary view showing a lower substrate, source drive ICs, timing controller, data compensator, reference voltage supply unit, flexible films, source circuit board, flexible cable, and control circuit board of the display panel of FIG. 1 . 3 is a block diagram illustrating the source drive IC of FIG. 2 in detail.

1 to 3 , an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 , a data driver 20 , flexible films 22 , a scan driver 40 , and a source circuit board ( 50 ), a timing control unit 60 , a data compensation unit 70 , a reference voltage supply unit 80 , a flexible cable 91 , and a control circuit board 90 .

The display panel 10 includes a display area AA and a non-display area NDA provided around the display area AA. The display area AA is an area in which pixels P are formed to display an image. The display panel 10 includes data lines (D1 to Dm, m is a positive integer greater than or equal to 2), reference voltage lines (R1 to Rp, p is a positive integer greater than or equal to 2), and scan lines (S1 to Sn, n). is a positive integer greater than or equal to 2), and sensing lines SE1 to SEq, where q is a positive integer greater than or equal to 2) are provided. The data lines D1 to Dm and the reference voltage lines R1 to Rp may cross the scan lines S1 to Sn and the sensing lines SE1 to SEq. The data lines D1 to Dm and the reference voltage lines R1 to Rp may be parallel to each other. The scan lines S1 to Sn and the sensing lines SE1 to SEq may be parallel to each other.

Each of the pixels P includes two data lines among the data lines D1 to Dm, one reference voltage line among the reference voltage lines R1 to Rp, and two scans among the scan lines S1 to Sn. It may be connected to one of the lines and the sensing lines SE1 to SEp. Each of the pixels P of the display panel 10 may include a plurality of sub-pixels as shown in FIGS. 4 and 7 . Each of the plurality of sub-pixels may include an organic light emitting diode (OLED) and a plurality of transistors for supplying current to the organic light emitting diode (OLED) as shown in FIGS. 5 and 8 . A detailed description of the pixels P of the display area and sub-pixels of the pixels P will be described later with reference to FIGS. 4, 5, 7 and 8 .

The data driver 20 may include a plurality of source drive ICs 21 as shown in FIG. 2 . Each of the source drive ICs 21 may be mounted on each of the flexible films 22 . Each of the flexible films 22 may be a tape carrier package or a chip on film. Each of the flexible films 22 may be bent or bent. Each of the flexible films 22 may be attached to the lower substrate 11 and the source circuit board 80 . Each of the flexible films 22 may be attached on the lower substrate 11 by a tape automated bonding (TAB) method using an anisotropic conductive film, whereby the source drive ICs 21 are connected to the data line may be connected to the fields D1 to Dm. The source circuit board 80 may be connected to the control circuit board 90 by a flexible cable 91 . The source circuit board 80 may be a printed circuit board.

Each of the source drive ICs 21 may include a data voltage supply unit 110 , a first switching unit 120 , a second switching unit 130 , and a sensing data output unit 140 as shown in FIG. 3 . In FIG. 3 , for convenience of explanation, the data voltage supply unit 110 is connected to w (w is a positive integer satisfying 1≤w≤m) data lines D1 to Dw, and the first switching unit ( 120) and the initialization voltage supply unit 130 are mainly described as being connected to z (z is a positive integer satisfying 1≤z≤p) reference voltage lines R1 to Rz.

The data voltage supply unit 110 is connected to the data lines D1 to Dw to supply data voltages. The data voltage supply unit 110 receives compensation data CDATA or sensing data SDATA and a data timing control signal DCS from the timing control unit 60 .

The data voltage supply unit 110 converts the compensation data CDATA into light emitting data voltages according to the data timing control signal DCS in the display mode and supplies the converted data to the data lines D1 to Dw. The emission data voltage is a voltage for emitting light with a predetermined luminance of the organic light emitting diode (OLED) of the pixel P. When the compensation data CDATA supplied to the data driver 20 is 8 bits, the light emitting data voltage may be supplied as any one of 256 voltages.

The data voltage supply unit 110 converts the sensing data SDATA into a sensing data voltage according to the data timing control signal DCS in the sensing mode and supplies it to the data lines D1 to Dw. The sensing data voltage is a voltage for sensing the current of the driving transistor DT of the pixel P.

The first switching unit 120 is connected between the reference voltage lines R1 to Rz and the reference voltage supply unit 80 to switch the connection between the reference voltage lines R1 to Rz and the reference voltage supply unit 80 . . The first switching unit 120 may include first switches SW1 that are turned on and off by the first switch control signal input from the timing controller 60 as shown in FIG. 3 . When the first switches SW1 of the first switching unit 120 are turned on by the first switch control signal, the reference voltage lines R1 to Rz are connected to the reference voltage supply unit 80 , so that the reference voltage supply unit A reference voltage of 80 may be supplied to the reference voltage lines R1 to Rz.

The second switching unit 130 is connected between the reference voltage lines R1 to Rz and the sensing data output unit 140 to connect between the reference voltage lines R1 to Rz and the sensing data output unit 30 . switch The second switching unit 120 may include second switches SW2 that are turned on and off by the second switch control signal input from the timing controller 60 as shown in FIG. 3 . When the second switches SW2 of the second switching unit 130 are turned on by the second switch control signal, the reference voltage lines R1 to Rz are connected to the sensing data output unit 140 , so that the reference voltage Current flowing through each of the lines R1 to Rz may be sensed by the sensing data output unit 140 .

The sensing data output unit 140 converts current flowing through each of the reference voltage lines R1 to Rz into a voltage, and converts the converted voltage into sensing data SD, which is digital data. To this end, the sensing data output unit 140 converts the current flowing through each of the reference voltage lines R1 to Rz into a voltage, and converts the output voltage of the current-voltage converter and the current-voltage converter to the sensing data SD as digital data. ) may include an analog-to-digital converter (analog digital converter) for converting. The sensing data output unit 140 outputs the sensing data SD to the data compensator 70 .

The scan driver 40 includes a scan signal output unit 41 and a sensing signal output unit 42 . The scan signal output unit 41 is connected to the scan lines S1 to Sn to supply scan signals. The scan signal output unit 41 supplies scan signals to the scan lines S1 to Sn according to the scan timing control signal SCS input from the timing controller 60 . A detailed description of the scan signal supply of the scan signal output unit 41 will be described later with reference to FIG. 7 .

The sensing signal output unit 42 is connected to the sensing lines SE1 to SEq to supply sensing signals. The sensing signal output unit 42 supplies sensing signals to the sensing lines SE1 to SEq according to the sensing timing control signal SENCS input from the timing control unit 60 . A detailed description of the sensing signal supply of the sensing signal output unit 42 will be described later with reference to FIG. 7 .

Each of the scan signal output unit 41 and the sensing signal output unit 42 may include a plurality of transistors and may be formed directly in the non-display area NDA of the display panel 10 in a gate driver in panel (GIP) method. . Alternatively, each of the scan signal output unit 41 and the sensing signal output unit 42 may be formed in the form of a driving chip and mounted on a flexible film (not shown) connected to the display panel 10 .

The timing controller 60 receives compensation data CDATA or sensing data SDATA and timing signals from the data compensator 70 . The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing control unit 60 generates timing control signals for controlling the operation timings of the data driver 20 , the scan signal output unit 41 , and the sensing signal output unit 42 . The timing control signals include a data timing control signal DCS for controlling the operation timing of the data driver 20 , a scan timing control signal SCS for controlling the operation timing of the scan signal output unit 41 , and a sensing signal output. and a sensing timing control signal SENCS for controlling the operation timing of the unit 42 .

The timing controller 60 outputs compensation data CDATA or sensing data SDATA and a data timing control signal DCS to the data driver 20 . The timing controller 60 outputs the scan timing control signal SCS to the scan signal output unit 41 . The timing controller 60 outputs the sensing timing control signal SENCS to the sensing signal output unit 42 . The timing controller 60 transmits first and second switching control signals for controlling the first and second switches SW1 and SW2 of the first and second switching units 120 and 130 of the data driver 20 . can be printed out.

In addition, the timing controller 60 divides one frame period into an active period and a blank period as shown in FIG. 7 , and during the active period, the pixels P of the display panel 10 display an image, and during the blank period, the pixels P ) to sense the current of the driving transistor DT. A detailed description of the operation of the pixels P during the active period and the blank period of one frame period will be described later with reference to FIG. 7 .

The data compensator 70 receives sensing data SD from the data driver 20 . The data compensator 70 generates compensation data to compensate for the digital video data DATA by processing the sensing data SD. The data compensator 70 may include a memory in the form of a look-up table for storing compensation data. The data compensator 70 generates compensation data CDATA by applying compensation data to digital video data DATA from the outside. The data compensator 70 outputs the compensation data CDATA to the timing controller 60 . The data compensator 70 may be built in the timing controller 60 .

Specifically, the sensing data SD is data sensed by a current flowing through the driving transistor DT when a sensing data voltage is supplied to the gate electrode of each of the driving transistors DT of the pixels P. For example, the sensing data SD may be digital data of the source voltage of the driving transistor DT to which the threshold voltage of the driving transistor DT is reflected. In this case, the compensation data CDATA generated by applying the correction data to the digital video data DATA is data for which the threshold voltage of the driving transistor DT is compensated. Accordingly, according to the exemplary embodiment of the present invention, correction data is generated by processing the sensing data SD, and compensation data CDATA is generated by applying the correction data to the digital video data DATA, thereby generating the driving transistor DT. Threshold voltage can be compensated externally.

The reference voltage supply unit 80 generates a reference voltage and supplies it to the source drive ICs 21 of the data driver 20 .

The timing control unit 60 , the data compensator 70 , and the reference voltage supply unit 80 may be mounted on the control circuit board. The control circuit board 90 may be connected to the source circuit board 80 by a flexible cable 91 . The control circuit board 90 may be a printed circuit board.

FIG. 4 is an exemplary view showing in detail pixels of the display area of FIG. 1 . 4 illustrates that each of the pixels P of the display area AA includes the first to fourth sub-pixels RP, WP, BP, and GP arranged in the scan line (X-axis direction). The first sub-pixels RP are sub-pixels emitting red light, the second sub-pixels WP are sub-pixels emitting white light, and the third sub-pixels BP are sub-pixels emitting blue light. , the fourth sub-pixels GP may be sub-pixels emitting green light.

Referring to FIG. 4 , each of the pixels P is disposed in regions formed by intersections of the scan lines S1 to S6 , the sensing lines SE1 and SE2 , and the data lines D1 to D3 . can be

Two data lines D2 and D3 may be disposed between pixels P adjacent to each other in the scan line direction (X-axis direction). Accordingly, each of the pixels P may be connected to two data lines. Specifically, two adjacent sub-pixels are connected to one data line, and two other adjacent sub-pixels are connected to the other data line. For example, the first and second sub-pixels RP and WP are connected to the first data line D1 , and the third and fourth sub-pixels BP and GP are connected to the second data line D2 . can be connected to

Also, a plurality of scan lines S3 to S6 may be disposed between two adjacent pixels P among the three pixels P arranged in the data line direction (the Y-axis direction). Accordingly, each of the pixels P may be connected to two scan lines. Specifically, two sub-pixels of each of the pixels P are connected to one scan line, and the other two sub-pixels are connected to another scan line. In this case, two adjacent sub-pixels may be connected to different scan lines, and two other adjacent sub-pixels may also be connected to different scan lines. For example, the first and second sub-pixels RP and WP are connected to the first data line D1 , and the third and fourth sub-pixels BP and GP are connected to the second data line D2 . can be connected to

That is, each of the pixels P is connected to two data lines and two scan lines, so that when a scan signal is supplied to the first scan line S1 , the first data line is provided to the first sub-pixel RP. The data voltage of D1 may be supplied and the data voltage of the second data line D2 may be supplied to the fourth sub-pixel GP. Also, when the scan signal is supplied to the second scan line S2 , the data voltage of the first data line D1 is supplied to the second sub-pixel WP and the second data line ( BP) is supplied to the third sub-pixel BP. The data voltage of D2) can be supplied.

As a result, according to the embodiment of the present invention, data voltages may be supplied to the first to fourth sub-pixels RP, WP, BP, and GP using two scan lines and two data lines. Accordingly, in the exemplary embodiment of the present invention, the number of data lines is higher than when data voltages are supplied to the first to fourth sub-pixels RP, WP, BP, and GP using one scan line and four data lines in the related art. can be reduced by half. Accordingly, the embodiment of the present invention can reduce the number of source drive ICs, thereby reducing manufacturing cost.

In addition, one sensing line SE1 is disposed between the other two adjacent pixels P among the three pixels P arranged in the data line direction (the Y-axis direction). Accordingly, the other two pixels P adjacent to each other may be connected to one sensing line SE1.

Also, a reference voltage line R1 may be disposed between the second sub-pixel WP and the third sub-pixel BP. Accordingly, the first to fourth sub-pixels RP, WP, BP, and GP of each of the pixels P may be connected to one reference voltage line R1 .

That is, the sub-pixels RP, WP, BP, and GP of the other two adjacent pixels P are connected to one sensing line SE1 and connected to one reference voltage line R1. For this reason, in the embodiment of the present invention, when a sensing signal is supplied to one sensing line SE1, the current of the driving transistors of the sub-pixels RP, WP, BP, and GP of the other two pixels P adjacent to each other. may be sensed through one reference voltage line R1. Accordingly, in the embodiment of the present invention, since the number of sensing lines SE1 and SE2 can be reduced, the aperture ratio of each of the sub-pixels RP, WP, BP, and GP of the pixels P can be increased.

Hereinafter, a structure of some of the pixels of the display area AA will be described in detail with reference to FIG. 5 .

FIG. 5 is a circuit diagram illustrating in detail some of the pixels of the display area of FIG. 1 . Referring to FIG. 5 , each of the first to fourth sub-pixels RP, WP, BP, and GP included in the pixel P includes an organic light emitting diode (ROLED/WOLED/BOLED/GOLED) and a driving transistor DT. , a first transistor T1 , a second transistor T2 , and a capacitor C may be included.

The organic light emitting diodes (ROLED/WOLED/BOLED/GOLED) emit light according to a current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode (ROLED/WOLED/BOLED/GOLED) is connected to the first electrode of the driving transistor DT, and the cathode electrode is connected to the second power line to which a second power voltage lower than the first power voltage is supplied. can be connected.

Organic light emitting diodes (ROLED/WOLED/BOLED/GOLED) include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode. electrode) may be included. In organic light emitting diodes (ROLED/WOLED/BOLED/GOLED), when a voltage is applied to the anode and cathode electrodes, holes and electrons are moved to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light emitting layer to emit light. .

The first sub-pixel RP may include a red organic light-emitting diode ROLED emitting red light, and the second sub-pixel WP may include a white organic light-emitting diode WOLED emitting white light. In addition, the third sub-pixel BP may include a blue organic light-emitting diode BOLED emitting blue light, and the fourth sub-pixel GP may include a green organic light-emitting diode GOLED emitting green light. have. Alternatively, each of the first to fourth sub-pixels RP, WP, BP, and GP may include a white organic light emitting diode. In this case, the first sub-pixel RP may include a red color filter, the third sub-pixel BP may include a blue color filter, and the fourth sub-pixel GP may include a green color filter.

The driving transistor DT is disposed between the first power line EVL and the organic light emitting diodes ROLED/WOLED/BOLED/GOLED. The driving transistor DT adjusts the current flowing from the first power line EVL to the organic light emitting diodes ROLED/WOLED/BOLED/GOLED according to the voltage difference between the gate electrode and the first electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first transistor ST1, the first electrode is connected to the anode electrode of the organic light emitting diodes ROLED/WOLED/BOLED/GOLED, and the second electrode is It may be connected to the first power line EVL to which the first power voltage is supplied.

The first transistor ST1 is turned on by the kth scan signal of the kth (k is a positive integer satisfying 1≤k≤n) scan line Sk, and the jth (j is 1≤j≤m) (a positive integer that satisfies ) is supplied to the gate electrode of the driving transistor DT with the voltage of the data line Dj. The gate electrode of the first transistor T1 is connected to the k-th scan line Sk, the first electrode is connected to the gate electrode of the driving transistor DT, and the second electrode is connected to the j-th data line Dj. can be The first transistor ST1 may be collectively referred to as a scan transistor.

The second transistor ST2 is turned on by the vth sensing signal of the vth (v is a positive integer satisfying 1≤v≤q) sensing line SEv and the uth (u is 1≤u≤p). (a positive integer satisfying ) is connected to the reference voltage line Ru to the first electrode of the driving transistor DT. The gate electrode of the second transistor ST2 is connected to the v-th sensing line SEv, the first electrode is connected to the u-th reference voltage line Ru, and the second electrode is the first electrode of the driving transistor DT. can be connected to The second transistor ST2 may be collectively referred to as a sensing transistor.

The capacitor C is formed between the gate electrode and the first electrode of the driving transistor DT. The capacitor C stores the difference voltage between the gate voltage and the source voltage of the driving transistor DT.

In FIG. 5 , the driving transistor DT and the first and second transistors ST1 and ST2 are mainly described as being formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but it should be noted that the present invention is not limited thereto. The driving transistor DT and the first and second transistors ST1 and ST2 may be formed of a P-type MOSFET. In addition, the first electrode may be a source electrode and the second electrode may be a drain electrode, but it should be noted that the present invention is not limited thereto. That is, the first electrode may be a drain electrode and the second electrode may be a source electrode.

The operation in the display mode and the sensing mode of each of the sub-pixels is as follows.

In the display mode, when a scan signal is supplied to the k-th scan line Sk, the light emission data voltage of the j-th data line Dj is supplied to the gate electrode of the driving transistor DT, and is sensed by the v-th sensing line SEv. When the signal is supplied, the reference voltage of the u-th reference voltage line Ru is supplied to the source electrode of the driving transistor DT. Accordingly, in the display mode, the current of the driving transistor DT flowing according to the voltage difference between the voltage of the gate electrode and the voltage of the source electrode of the driving transistor DT is supplied to the organic light emitting diode OLED, and the organic light emitting diode OLED ) will emit light. In this case, since the light emitting data voltage is a voltage obtained by compensating for the threshold voltage of the driving transistor DT, the current of the driving transistor DT does not depend on the threshold voltage of the driving transistor DT.

In addition, when a scan signal is supplied to the k-th scan line Sk in the sensing mode, the sensing data voltage of the j-th data line is supplied to the gate electrode of the driving transistor DT, and the sensing signal is supplied to the v-th sensing line SEv. When is supplied, the reference voltage of the u-th reference voltage line Ru is supplied to the source electrode of the driving transistor DT. In addition, in the sensing mode, the second transistor ST2 is turned on by a sensing signal on the v-th sensing line SEv to flow according to the voltage difference between the voltage of the gate electrode of the driving transistor DT and the voltage of the source electrode. The current of the transistor DT flows to the u-th reference voltage line Ru. As a result, the sensing data output unit 30 may sense the current flowing through the u-th reference voltage line Ru according to the switching of the second switching unit 130 and output the sensing data SD, and the data compensator Reference numeral 70 externally compensates the threshold voltage of the driving transistor DT by using the sensing data SD.

Gate electrodes of the first transistors ST1 of two of the first to fourth sub-pixels RP, WP, BP, and GP included in the pixel P are connected to the k-th scan line, and the other two Gate electrodes of the first transistors ST1 of the sub-pixels may be connected to the k+1th scan line Sk+1. For example, when the gate electrodes of the first transistors ST1 of the first and fourth sub-pixels RP and GP are connected to the k-th scan line Sk, the second and third sub-pixels WP , BP), gate electrodes of the first transistors ST1 may be connected to the k+1th scan line Sk+1. Alternatively, when the gate electrodes of the first transistors ST1 of the first and fourth sub-pixels RP and GP are connected to the k+1th scan line Sk+1, the second and third sub-pixels Gate electrodes of the first transistors ST1 of (WP, BP) may be connected to the k-th scan line Sk.

Drain electrodes of the first transistors ST1 of two of the first to fourth sub-pixels RP, WP, BP, and GP included in the pixel P are connected to the j-th data line Dj, , drain electrodes of the first transistors ST1 of the other two sub-pixels may be connected to the j+1th data line Dj+1. For example, when the drain electrodes of the first transistors ST1 of the first and second sub-pixels RP and WP are connected to the j-th data line Dj, the third and fourth sub-pixels BP , GP, drain electrodes of the first transistors ST1 may be connected to the j+1th data line Dj+1.

That is, in the embodiment of the present invention, data voltages may be supplied to the first to fourth sub-pixels RP, WP, BP, and GP using two scan lines and two data lines. Accordingly, in the exemplary embodiment of the present invention, the number of data lines is higher than when data voltages are supplied to the first to fourth sub-pixels RP, WP, BP, and GP using one scan line and four data lines in the related art. can be reduced by half. Accordingly, the embodiment of the present invention can reduce the number of source drive ICs, thereby reducing manufacturing cost.

Also, the gate electrodes of the second transistors ST2 of the sub-pixels RP, WP, BP, and GP included in the pixel P may be connected to the same sensing line, and the drain electrodes may be connected to the same reference voltage line. have. In particular, the gate electrodes of the second transistors ST2 of the sub-pixels RP, WP, BP, and GP of the two adjacent pixels P are connected to the same sensing line, and the drain electrodes are connected to the same reference voltage line. can be For this reason, in the embodiment of the present invention, when a sensing signal is supplied to the same sensing line, the currents of the driving transistors of the sub-pixels RP, WP, BP, and GP of the two pixels P adjacent to each other are transferred to the same reference voltage line. can be sensed through Accordingly, since the embodiment of the present invention can reduce the number of sensing lines, the aperture ratio of each of the sub-pixels RP, WP, BP, and GP of the pixels P can be increased.

6 illustrates first to eighth scan signals applied to first to eighth scan lines and first and second sensing signal lines applied to first and second sensing signal lines during Nth and N+1th frame periods; 2 It is a waveform diagram showing sensing signals.

In FIG. 6 , only Nth (N is a positive integer) and N+1th frame periods are illustrated for convenience of explanation. When driven at a frequency of 60 Hz, 60 frame periods may be included in 1 second. In this case, each of the frame periods may be approximately 16.68 ms. Also, in FIG. 6 , only the first to eighth scan signals Scan1 to Scan8 and the first and second sensing signals Sense1 and Sense2 are exemplified for convenience of explanation.

Referring to FIG. 6 , each of the frame periods includes an active period (AP) and a blank period (BP). The active period AP is a data addressing period in which data voltages are supplied to the sub-pixels RP, WP, BP, and GP of the pixels P of the display panel 10 . The blank period BP may be a rest period, but in an exemplary embodiment of the present invention, a sensing period for sensing currents of the driving transistors DT of the sub-pixels RP, WP, BP, and GP connected to one sensing line. is operated with

During the active period AP, the scan signals Scan1 to Scan8 of the gate high voltage VGH are sequentially applied to the scan lines. At this time, the emission data voltages are supplied to the data lines in synchronization with the scan signals Scan1 to Scan8. Accordingly, the sub-pixels connected to the scan line to which the scan signal is supplied during the active period AP may receive the emission data voltages through the data lines.

During the active period AP, the sensing signals Sense1 and Sense2 of the gate high voltage VGH are sequentially applied to the sensing lines. At this time, the reference voltage is supplied to the reference voltage lines. Accordingly, the sub-pixels connected to the sensing line to which the sensing signal is supplied during the active period AP may receive the reference voltage through the reference voltage line.

The gate high voltage VGH corresponds to a voltage capable of turning on the first and second transistors T1 and T2 of the sub-pixels RP, WP, BP, and GP. The gate low voltage VGL corresponds to a voltage capable of turning off the first and second transistors T1 and T2 of the sub-pixels RP, WP, BP, and GP. The gate low voltage VGL may be a voltage at a lower level than the gate high voltage VGH.

Meanwhile, the sub-pixels RP, WP, BP, and GP of the two pixels P connected to one sensing line are connected to the four scan lines. For this reason, each of the sensing signals Sense1 and Sense2 may be applied every four scan signals. That is, the width of each of the sensing signals Sense1 and Sense2 is wider than the width of each of the scan signals, and the sub-pixels RP of the two pixels P connected to one sensing line as shown in FIGS. 4 and 5 . , WP, BP, and GP) are connected to the four scan lines, the width of each of the sensing signals Sense1 and Sense2 may be approximately 4 times wider than the width of each of the scan signals.

Operations of each of the sub-pixels RP, WP, BP, and GP during the active period AP are as follows.

First, during the active period AP, the first transistor ST1 is turned on when the k-th scan signal Scank of the gate high voltage VGH is supplied to the k-th scan line Sk. Accordingly, the light emission data voltage of the j-th data line Dj is supplied to the gate electrode of the driving transistor DT.

Second, during the active period AP, the second transistor ST2 is turned on by the vth sensing signal Sensev of the gate high voltage VGH supplied to the vth sensing line SEv. Accordingly, the reference voltage of the u-th reference voltage line Ru is supplied to the source electrode of the driving transistor DT.

A difference between the gate voltage and the source voltage of the driving transistor DT during the active period AP is stored in the capacitor C. When both the first and second transistors ST1 and ST2 are turned off, the current Ids according to the difference between the gate voltage and the source voltage of the driving transistor DT is the organic light emitting diode (ROLED/WOLED/BOLED/GOLED). ) flows to Since the emission data voltage is a voltage in which the threshold voltage of the driving transistor DT is compensated, the current flowing to the organic light emitting diodes ROLED/WOLED/BOLED/GOLED through the driving transistor DT is equal to the threshold voltage of the driving transistor DT. do not depend

The blank period BP is divided into first to second periods T1 and T2 . The first period T1 is a period in which scan signals are simultaneously supplied to the remaining scan lines except for one scan line, and the second period T2 is the one scan line and the sub-pixels connected to the one scan line. It is a period in which a sensing signal is supplied to a sensing line connected to the .

During the first period T1, scan signals of the gate high voltage VGH are simultaneously supplied to the remaining scan lines except for the k-th scan line. For example, as shown in FIG. 6 , during the first period T1 of the blank period BP of the Nth frame period, the scan signals Scan2 to the gate high voltage VGH are applied to the remaining scan lines except for the first scan line. Scan8) can be fed simultaneously. Also, as shown in FIG. 6 , during the first period T1 of the blank period BP of the N+1th frame period, scan signals Scan1 of the gate high voltage VGH are applied to the remaining scan lines except for the second scan line. Scan3~Scan8) can be supplied at the same time. In this case, the black data voltages are supplied to the data lines during the first period T1. Accordingly, during the first period T1 , the sub-pixels connected to the remaining scan lines may receive black data voltages through the data lines. During the first period T1 , the sensing signals Sense1 and Sense2 of the gate low voltage VGL are applied to the sensing lines.

During the second period T2, the scan signal of the gate high voltage VGH is supplied only to the k-th scan line. For example, as shown in FIG. 6 , the first scan signal Scan1 of the gate high voltage VGH may be supplied only to the first scan line during the second period T2 of the blank period BP of the Nth frame period. . Also, as shown in FIG. 6 , the scan signal Scan2 of the gate high voltage VGH may be supplied only to the second scan line during the second period T2 of the blank period BP of the N+1th frame period. In this case, the sensed data voltages are supplied to the data lines during the second period T2. Accordingly, during the second period T2 , the sub-pixels connected to the k-th scan line may receive sensing data voltages through the data lines.

During the second period T2, the sensing signal of the gate high voltage VGH is applied only to the v-th sensing line connected to the sub-pixels connected to the k-th scan line. For example, since sub-pixels connected to the first scan line are connected to the first sensing line as shown in FIGS. 4 and 5 , the first sensing is performed during the second period T2 of the blank period BP of the Nth frame period. The first sensing signal Sense1 of the gate high voltage VGH may be applied only to the line SE1 . In addition, since the sub-pixels connected to the second scan line are connected to the first sensing line as shown in FIGS. 4 and 5 , the first sensing is performed during the second period T2 of the blank period BP of the N+1th frame period. The first sensing signal Sense1 of the gate high voltage VGH may be applied only to the line SE1 .

Meanwhile, the width of the sensing signal applied during the second period T2 may be wider than the width of the scan signal applied during the second period T2 . Accordingly, the second period T2 may be divided into a 2-1 period T2-1 and a 2-2 period T2-2. The 2-1 period T2-1 represents a period in which the scan signal and the sensing signal are applied as the gate high voltage VGH in the second period T2, and the 2-2 period T2-2 is the second period T2. During the period T2, the scan signal is applied as the gate low voltage VGL and the sensing signal is applied as the gate high voltage VGH.

A reference voltage is supplied to the reference voltage lines during the first period T1 of the blank period BP. In addition, in the second period T2 of the blank period BP, the reference voltage is supplied to the reference voltage lines during the 2-1 period T2-1 in which the k-th scan signal is supplied, and the reference voltage is supplied to the reference voltage lines during the 2-1 period ( After T2-1), the reference voltage lines are connected to the sensing data output unit 140 through the second switching unit 130 during the 2-2 period T2 - 2 .

First, during the first period T1 of the blank period BP, scan signals are simultaneously applied to the remaining scan lines except for one of the scan lines connected to the sub-pixels connected to any one sensing line. is supplied The first transistor ST1 of each of the sub-pixels RP, WP, BP, and GP connected to the remaining scan lines is turned on when the scan signals of the gate high voltage VGH are supplied to the remaining scan lines. comes on Accordingly, the black data voltage of the data lines is supplied to the gate electrode of the driving transistor DT of each of the sub-pixels RP, WP, BP, and GP connected to the remaining scan lines.

Second, the scan signal is supplied to only the one scan line during the 2-1 th period T2-1 of the blank period BP. The second transistor ST2 of each of the sub-pixels RP, WP, BP, and GP connected to the one scan line is turned on when the scan signal of the gate high voltage VGH is supplied to the one scan line. comes on Accordingly, the sensing data voltage of the data lines is supplied to the gate electrode of the driving transistor DT of each of the sub-pixels RP, WP, BP, and GP connected to the one scan line.

During the second period T2, the second transistor ST2 is turned on by the sensing signal of the gate high voltage VGH supplied to any one sensing line. Reference voltages are supplied to the reference voltage lines during the 2-1 period T2-1, and the reference voltage lines are connected to the sensing data output unit 140 during the 2-2 period T2-2.

A difference between the gate voltage and the source voltage of the driving transistor DT is stored in the capacitor C during the 2-1 th period T2-1. A current Ids according to a difference between the gate voltage and the source voltage of the driving transistor DT flows to the reference voltage lines through the second transistor ST2 during the 2-2 period T2 - 2 . Since the reference voltage lines are connected to the sensing data output unit 140 during the 2-2 period T2 - 2 , the current of the driving transistor DT may be sensed by the sensing data output unit 140 .

As described above, in the embodiment of the present invention, since the sub-pixels RP, WP, GP, and BP of the two pixels P are connected to one sensing line, during the blank period BP, the two pixels Only sub-pixels connected to any one scan line among the scan lines connected to (P) are sensed. In particular, according to the embodiment of the present invention, a black data voltage is supplied to the remaining scan lines among the scan lines connected to the two pixels P, so that the other sub-pixels are not affected, and any one of the scan lines is not affected. Currents of the driving transistors DT of the sub-pixels connected to can be accurately sensed.

FIG. 7 is another exemplary view showing in detail pixels of the display area of FIG. 1 . 7 illustrates that each of the pixels P of the display area AA includes the first to third sub-pixels RP, GP, and BP arranged in the scan line direction (X-axis direction). Specifically, the first sub-pixels RP are sub-pixels emitting red light, the second sub-pixels GP are sub-pixels emitting green light, and the third sub-pixels BP are sub-pixels emitting blue light. They may be sub-pixels.

In FIG. 7 , each of the pixels P includes the first to third sub-pixels RP, GP, and BP arranged in the scan line direction (X-axis direction). The design is substantially the same as described in connection with FIG. 4 except that the arrangement position is changed. That is, the connection structure of the scan lines, data lines, sensing line, and reference voltage line of the four sub-pixels arranged in the scan line direction (X-axis direction) in FIG. 7 is substantially the same as that described in connection with FIG. 4 . do.

8 is a circuit diagram illustrating in detail some of the pixels of FIG. 7 . Referring to FIG. 8 , each of the first to third sub-pixels RP, GP, and BP included in the pixel P includes an organic light emitting diode (ROLED/GOLED/BOLED), a driving transistor DT, and a first transistor. ( T1 ), a second transistor T2 , and a capacitor C may be included.

The organic light emitting diode ROLED/GOLED/BOLED, the driving transistor DT, the first transistor T1, and the second transistor of each of the first to third sub-pixels RP, GP, and BP illustrated in FIG. 8 . Since T2 and the capacitor C are substantially the same as those described with reference to FIG. 5 , a detailed description thereof will be omitted.

Also, in FIG. 8 , each of the pixels P includes the first to third sub-pixels RP, GP, and BP arranged in the scan line direction (X-axis direction), so that the sub-pixels RP, GP, and BP ) is designed substantially the same as described in connection with FIG. 4 except that the arrangement position is changed. That is, the connection structure of the scan lines, data lines, sensing line, and reference voltage line of the four sub-pixels arranged in the scan line direction (X-axis direction) in FIG. 7 is substantially the same as that described in connection with FIG. 4 . do.

In addition, the scan signals and sensing signals shown in FIG. 6 may be supplied to the sub-pixels RP, GP, and BP of the pixels P shown in FIG. 8 , and the pixels P shown in FIG. The sub-pixels RP, GP, and BP may operate substantially the same as described with reference to FIG. 6 .

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

10: display panel 20: data driver
21: source drive IC 22: flexible film
40: scan driver 41: scan signal output unit
42: sensing signal output unit 50: source circuit board
60: timing control unit 70: data compensation unit
80: reference voltage supply 90: control circuit board
91: flexible cable 110: data voltage supply
120: first switching unit 130: second switching unit
140: sensing data output unit

Claims (10)

data lines;
scan lines and sensing lines that cross the data lines and are parallel to each other; and
having pixels including a plurality of sub-pixels,
two sub-pixels adjacent to each other in the scan line direction are connected to the same data line and connected to different scan lines;
The sub-pixels of the two pixels adjacent to each other in the data line direction are connected to the same sensing line. The method of claim 1,
Any two sub-pixels among the four sub-pixels arranged in the scan line direction are connected to a j-th (j is a positive integer) data line among the data lines, and k-th (k is a positive integer) and k-th sub-pixels. The organic light emitting diode display is connected to +1 scan lines, and the other two sub-pixels are connected to a j+1th data line among the data lines and connected to the kth and k+1th scan lines. 3. The method of claim 2,
Further comprising reference voltage lines parallel to the data lines,
The four sub-pixels are connected to the same reference voltage line. The method of claim 1,
The sub-pixels of each of the pixels are connected to two data lines among the data lines, two scan lines among the scan lines, and one sensing line among the sensing lines. 5. The method of claim 4,
Further comprising reference voltage lines parallel to the data lines,
The sub-pixels of each of the pixels are connected to one reference voltage line among the reference voltage lines. 6. The method of claim 5,
and each of the pixels includes four sub-pixels arranged in the scan line direction. 6. The method of claim 5,
Each of the pixels includes an organic light emitting diode display including three sub-pixels arranged in a scan line direction. The method of claim 1,
Each of the sub-pixels,
organic light emitting diodes;
a driving transistor for adjusting an amount of current flowing through the organic light emitting diode according to a voltage difference between a gate voltage and a source voltage;
a first transistor turned on by the scan signal of the scan line to supply the data voltage of the data line to the gate electrode of the driving transistor;
a second transistor turned on by a sensing signal of the sensing line to connect a source electrode of the driving transistor to a reference voltage line; and
and a capacitor formed between a gate electrode and a source electrode of the driving transistor. The method of claim 1,
One frame period includes an active period and a blank period, the blank period includes first and second periods,
During the active period, scan signals are sequentially supplied to the scan lines, and during the first period T1 of the blank period, any one of scan lines connected to sub-pixels connected to any one sensing line is scanned. a scan signal output unit that simultaneously supplies scan signals to the remaining scan lines except for the line and supplies scan signals to only one of the scan lines during the second period of the blank period; and
and a sensing signal output unit configured to supply a sensing signal to only the one sensing line during the second period of the blank period. 10. The method of claim 9,
A width of the sensing signal supplied during the second period is wider than a width of the scan signal supplied during the second period.

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