KR102417777B1 - Organic light emitting display device and method for manufacturing the same - Google Patents

Abstract

Embodiments of the present invention relate to an organic light emitting display device capable of minimizing luminance non-uniformity of a display panel due to an increase in a low potential voltage of a cathode electrode, and a method of manufacturing the same. An organic light emitting diode display according to an embodiment of the present invention includes data lines, reference voltage lines parallel to the data lines and power supply voltage compensation lines, scan lines crossing the data lines, initialization lines, and a power supply. and a display panel including pixels connected to voltage control lines, wherein the pixels apply a compensation power voltage of the power voltage compensation line to the cathode electrode of the organic light emitting diode when a control signal of the power voltage control line is supplied. supply

Description

Organic light emitting display device and manufacturing method thereof

An embodiment of the present invention relates to an organic light emitting display device and a method for manufacturing the same.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have recently been used.

Among display devices, the organic light emitting display device is a self-emission type display device, which has superior viewing angle and contrast ratio compared to a liquid crystal display device (LCD). . In addition, the organic light emitting display device can be driven with a low DC voltage, has a fast response speed, and has advantages of low manufacturing cost.

An organic light emitting diode display includes a display panel including a display area in which pixels displaying an image are formed and a non-display area that is a periphery of the display area. Each of the pixels includes an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. In this case, when a high potential voltage is applied to the anode electrode and a low potential voltage is applied to the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light emitting layer to emit light.

The organic light emitting display device is divided into a top emission type and a bottom emission type according to the emission direction. In the case of the top emission method, since the organic light emitting layer emits light in the direction of the cathode electrode, the cathode electrode is formed of a transparent metal or thinly made of a transflective metal. However, in this case, there is a problem in that the resistance of the cathode electrode is increased, so that the low potential voltage of the cathode electrode is increased. In the industry, this is sometimes referred to as "cathode rising". Due to the rise in the low potential voltage of the cathode electrode, the low potential voltage of the cathode voltage may vary depending on the position of the display panel, which may cause non-uniform luminance of the display panel.

SUMMARY Embodiments of the present invention provide an organic light emitting display device capable of minimizing luminance non-uniformity of a display panel due to an increase in a low potential voltage of a cathode electrode, and a method of manufacturing the same.

An organic light emitting diode display according to an embodiment of the present invention includes data lines, reference voltage lines parallel to the data lines and power supply voltage compensation lines, scan lines crossing the data lines, initialization lines, and a power supply. and a display panel including pixels connected to voltage control lines, wherein the pixels apply a compensation power voltage of the power voltage compensation line to the cathode electrode of the organic light emitting diode when a control signal of the power voltage control line is supplied. supply

An organic light emitting diode display according to an embodiment of the present invention includes a lower substrate, driving transistors formed on the lower substrate, and driving transistors and switching transistors each including an active layer, a gate electrode, a source electrode, and a drain electrode, and the driving transistor An anode electrode electrically connected to the drain electrode, a connection electrode electrically connected to one of the drain electrodes of the switching transistors, banks dividing the anode electrode and the connection electrode, an organic light emitting layer covering the anode electrode and the banks, and a cathode electrode covering the organic light emitting layer, wherein the cathode electrode is electrically connected to the connection electrode.

A method of manufacturing an organic light emitting display device according to an embodiment of the present invention includes forming a driving transistor and switching transistors on a lower substrate, an anode electrode electrically connected to a drain electrode of the driving transistor, and any one of the switching transistors forming a connection electrode electrically connected to the drain electrode of step, forming a cathode electrode on the organic light emitting layer, and applying a reverse bias voltage to the connection electrode and the cathode electrode.

In an embodiment of the present invention, a compensation power supply voltage is supplied to the cathode electrode of the organic light emitting diode by using the third transistor in the display mode. As a result, the embodiment of the present invention can prevent the power supply voltage supplied to the cathode electrode of the organic light emitting diode from rising. Accordingly, according to the embodiment of the present invention, it is possible to prevent the luminance uniformity of the pixels from being lowered due to the increase of the power voltage supplied to the cathode electrode.

In addition, in the embodiment of the present invention, the cathode electrode and the connection electrode are connected by applying a reverse bias voltage to the connection electrode electrically connected to the drain electrode of the third transistor and the cathode electrode to destroy the organic light emitting layer between the connection electrode and the cathode electrode. . As a result, in the embodiment of the present invention, since a separate manufacturing process for connecting the cathode electrode and the connection electrode is not added, manufacturing cost and time can be saved.

In addition, according to the embodiment of the present invention, the voltage of the cathode electrode of each of the pixels is sensed through the first and second sensing modes, and a compensation power voltage is supplied to the cathode electrode. As a result, the embodiment of the present invention can compensate for the resistance value between the cathode electrode and the connection electrode that varies depending on the degree of destruction of the organic light emitting layer.

1 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating the scan driver of FIG. 1 in detail.
FIG. 3 is a detailed block diagram of the data driver of FIG. 1 .
4 is a circuit diagram illustrating an example of the pixel of FIG. 1 .
5 is a waveform diagram illustrating a kth scan signal, a kth initialization signal, and a kth control signal supplied to a pixel in a display mode.
6A to 6C are circuit diagrams illustrating an operation of a pixel during first to third periods of FIG. 5 .
7 is a waveform diagram illustrating a kth scan signal, a kth initialization signal, and a kth control signal supplied to a pixel in the first sensing mode.
8 is a circuit diagram illustrating an operation of a pixel during a first period in a first sensing mode.
9 is a waveform diagram illustrating a kth scan signal, a kth initialization signal, and a kth control signal supplied to a pixel in the second sensing mode.
10 is a circuit diagram illustrating an operation of a pixel during a first period in a second sensing mode.
11 is a plan view illustrating an example of the pixel of FIG. 2 .
12 is a cross-sectional view taken along lines I-I' and II-II' of FIG. 11 .
13 is a flowchart illustrating a method of manufacturing an organic light emitting display device according to an embodiment of the present invention.
14A to 14F are cross-sectional views for explaining a method of manufacturing the organic light emitting display device of FIG. 13 .

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of writing the specification, and may be different from the component names of the actual product.

1 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention. Referring to FIG. 1 , an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 , a data driver 20 , a scan driver 30 , a timing controller 40 , and a power supply voltage compensator 50 . includes

The display panel 10 includes data lines (D1 to Dm, m is an integer greater than or equal to 2), power supply voltage compensation lines (V1 to Vm), reference voltage lines (R1 to Rp, p is an integer greater than or equal to 2), and a scan line. (S1 to Sn, n is an integer greater than or equal to 2), initialization lines I1 to In, and power supply voltage control lines C1 to Cn are provided. The data lines D1 to Dm, the power supply voltage compensation lines V1 to Vm, and the reference voltage lines R1 to Rp may be parallel to each other. The scan lines S1 to Sn, the initialization lines I1 to In, and the power supply voltage control lines C1 to Cn may be parallel to each other. The data lines D1 to Dm, the power supply voltage compensation lines V1 to Vm, and the reference voltage lines R1 to Rp are the scan lines S1 to Sn, the initialization lines I1 to In, and It may cross the power supply voltage control lines C1 to Cn.

Each of the pixels P includes any one of the data lines D1 to Dm, any one of the power supply voltage compensation lines V1 to Vm, any one of the reference voltage lines R1 to Rp, and the scan lines ( It may be connected to any one of S1 to Sn), any one of the initialization lines I1 to In, and any one of the power supply voltage control lines C1 to Cn. 1 illustrates that one power supply voltage compensation line is connected to one pixel P among pixels P connected to the same scan line for convenience of explanation, but the present invention is not limited thereto. That is, one power supply voltage compensation line may be connected to two or more pixels P among the pixels P connected to the same scan line. Also, in FIG. 1 , for convenience of explanation, one reference voltage line is illustrated as being connected to two pixels P among pixels P connected to the same scan line, but the present invention is not limited thereto. That is, one reference voltage line may be connected to one pixel P among the pixels P connected to the same scan line, or three or more pixels (P) among the pixels P connected to the same scan line. P) may be connected.

Each of the pixels P of the display panel 10 includes an organic light emitting diode (OLED) and a pixel driver PD supplying current to the organic light emitting diode (OLED) as shown in FIG. 4 . As shown in FIG. 4 , the pixel driver PD includes a driving transistor DT, a first transistor ST1 controlled by a scan signal of a scan line, and a second transistor ST2 controlled by an initialization signal of an initialization line. , a third transistor ST3 controlled by a control signal of the power supply voltage control line, and a capacitor C may include. A detailed description of the pixel P will be described later with reference to FIG. 4 .

When a scan signal is supplied from the scan line connected to the pixel P in the display mode, the pixel driver PD receives the data voltage of the data line connected to the pixel P, and according to the data voltage, the organic light emitting diode OLED ) to supply current. Accordingly, in the display mode, the organic light emitting diode (OLED) emits light. The pixel driver PD senses the voltage of the cathode of the organic light emitting diode OLED through the power supply voltage compensation line in the first sensing mode. The pixel driver PD supplies a predetermined voltage to the anode electrode of the organic light emitting diode OLED in the second sensing mode and senses the voltage of the cathode electrode of the organic light emitting diode OLED through a power supply voltage compensation line.

An embodiment of the present invention includes a display mode and first to third sensing modes. A detailed description of the operation of the pixel P in the display mode will be described later in conjunction with FIGS. 5 and 6A to 6C , and FIGS. 7 and 8 for a detailed description of the operation of the pixel P in the first sensing mode A detailed description of the operation of the pixel P in the second sensing mode will be described later in conjunction with FIGS. 9 and 10 . The operation of the pixel P in the third sensing mode will be briefly described later without referring to the drawings.

The data driver 20 includes a data voltage supply unit 21 , a compensation power voltage supply unit 22 , and a reference voltage supply unit 23 as shown in FIG. 3 .

The data voltage supply unit 21 is connected to the data lines D1 to Dm to supply data voltages. The data voltage supply unit 21 receives digital video data DATA and a data timing control signal DCS from the timing control unit 40 .

The data voltage supply unit 21 converts the digital video data DATA into data voltages according to the data timing control signal DCS in the display mode and supplies the data voltages to the data lines D1 to Dm. The data voltage is a voltage for emitting light with a predetermined luminance of the organic light emitting diode (OLED) of the pixel (P). When the digital video data DATA supplied to the data driver 20 is 8 bits, the data voltage may be any one of 256 voltages.

The data voltage supply unit 21 does not supply data voltages to the data lines D1 to Dm in the first and second sensing modes.

The data voltage supply unit 21 converts the sensing data SDATA into data voltages according to the data timing control signal DCS in the third sensing mode and supplies the data voltages to the data lines D1 to Dm. The sensing data SDATA is data for measuring the current or the anode voltage flowing through the organic light emitting diode OLED through the reference voltage line when the sensing data SDATA is supplied to the gate electrode of the driving transistor DT. .

The compensation power voltage supply unit 22 is connected to the power voltage compensation lines V1 to Vm to supply compensation power voltages. The compensation power supply voltage supply unit 22 receives the compensation data CDATA and the compensation timing control signal VCS from the timing control unit 40 .

The compensation power supply voltage supply unit 22 converts the compensation data CDATA into compensation power voltages according to the compensation timing control signal VCS in the display mode and supplies it to the power voltage compensation lines V1 to Vm. The compensation power voltage is a voltage for compensating for an increase in the power voltage supplied to the cathode electrode of the organic light emitting diode (OLED). That is, the compensation power supply voltage is a voltage for compensating for cathode rising.

The compensation power voltage supply unit 22 does not supply the compensation power voltages to the power voltage compensation lines V1 to Vm in the first to third sensing modes. The compensation power voltage supply unit 22 senses the voltage of the power voltage compensation line connected to the cathode electrode of the organic light emitting diode OLED of each of the pixels P in the first and second sensing modes. The compensation power voltage supply unit 22 converts the voltages sensed in the first sensing mode into first sensing data SD1 that is digital data and outputs the converted voltages to the power supply voltage compensator 50 . The compensation power supply voltage supply unit 22 converts the voltages sensed in the second sensing mode into second sensing data SD2 that is digital data and outputs the converted voltages to the power supply voltage compensator 50 .

The reference voltage supply unit 23 is connected to the reference voltage lines R1 to Rp to supply the first reference voltage VREF1 or the second reference voltage VREF2. The reference voltage supply unit 23 receives the first and second reference voltages VREF1 and VREF2 from a power supply unit (not shown).

The reference voltage supply unit 23 supplies the first reference voltage VREF1 to the reference voltage lines R1 to Rp in the display mode. The reference voltage supply unit 23 does not supply the first reference voltage VREF1 or the second reference voltage VREF2 to the reference voltage lines R1 to Rp in the first sensing mode. The reference voltage supply unit 23 supplies the second reference voltage VREF2 to the reference voltage lines R1 to Rp in the second sensing mode. The reference voltage supply unit 23 does not supply the first reference voltage VREF1 or the second reference voltage VREF2 in the third sensing mode. The reference voltage supply unit 23 senses the current or voltage of the reference voltage line connected to the anode electrode of the organic light emitting diode OLED of each of the pixels P in the third sensing mode. The reference voltage supply unit 23 converts currents or voltages sensed in the third sensing mode into third sensing data SD3 that is digital data and supplies the converted currents or voltages to the timing control unit 40 . The first and second reference voltages VREF1 and VREF2 may be predetermined through a prior experiment, and may be the same voltage or different voltages.

The scan driver 30 includes a scan signal supply unit 31 , an initialization signal supply unit 32 , and a control signal supply unit 33 as shown in FIG. 3 .

The scan signal supply unit 31 receives the scan timing control signal SCS from the timing control unit 40 . The scan signal supply unit 31 supplies the scan signals to the scan lines S1 to Sn according to the scan timing control signal SCS input from the timing control unit 40 . The scan signal supply unit 31 may sequentially supply scan signals to the scan lines S1 to Sn.

The initialization signal supply unit 32 receives the initialization timing control signal ICS from the timing control unit 50 . The initialization signal supply unit 32 supplies initialization signals to the initialization lines I1 to In according to the initialization timing control signal ICS. The initialization signal supply unit 32 may sequentially supply initialization signals to the initialization lines I1 to In.

The control signal supply unit 33 receives the control timing control signal CCS from the timing control unit 50 . The control signal supply unit 33 supplies control signals to the power supply voltage control lines C1 to Cn according to the control timing control signal CCS. The control signal supply unit 32 may sequentially supply control signals to the power supply voltage control lines C1 to Cn.

A detailed description of the scan signal, the initialization signal, and the control signal waveform in the display mode and the first and second sensing modes will be described later with reference to FIGS. 5, 7 and 9 .

The scan driver 30 is formed in the form of a driving chip and mounted on a flexible film connected to the display panel 10 , or includes a plurality of transistors in the display panel 10 in a gate driver in panel (GIP) manner. may be directly formed in the non-display area of The non-display area is an area in which pixels are not arranged and refers to an area in which an image is not displayed.

In addition, the scan driver 30 may be provided on one side or both sides of the display panel 10 . When the scan driver 30 is provided on both sides, delays of the scan signal, the initialization signal, and the control signal due to the RC delay can be reduced by simultaneously supplying the scan signals, the initialization signals, and the control signals from both sides.

The timing controller 40 receives digital video data DATA and timing signals from an external host system, and receives compensation data CDATA from the power supply voltage compensator 50 . The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing controller 40 generates timing control signals for controlling the operation timings of the data driver 20 and the scan driver 30 . The timing control signals are a data timing control signal DCS for controlling the operation timing of the data signal supply unit 21 of the data driver 20 and a compensation timing control signal (DCS) for controlling the operation timing of the compensation power supply voltage supply unit 22 . VCS), a scan timing control signal SCS for controlling the operation timing of the scan signal supply unit 31 of the scan driver 30 , and an initialization timing control signal ICS for controlling the operation timing of the initialization signal supply unit 32 . , and a control timing control signal CCS for controlling the operation timing of the control signal supply unit 33 .

The timing controller 40 may generate the mode signal MODE according to a setting previously stored in the memory. The timing controller 40 operates the data driver 20 and the scan driver 30 in any one of the display mode and the first to third sensing modes according to the mode signal MODE. The display mode is a mode in which the pixels P of the display panel 10 display an image, and the first and second sensing modes are the cathodes of the organic light emitting diodes (OLED) of each of the pixels P of the display panel 10 . This mode senses the voltage of the electrode. In particular, the first sensing mode is a mode for sensing the voltage of the cathode electrode of the organic light emitting diode (OLED) when no current flows through the organic light emitting diode (OLED), and the second sensing mode is the anode electrode of the organic light emitting diode (OLED) In this mode, the voltage of the cathode electrode is sensed when a predetermined current flows through the organic light emitting diode (OLED) by supplying the second reference voltage VREF2 to the device. The third sensing mode is a mode in which a predetermined data voltage is applied to each of the pixels P of the display panel 10 and a current flowing through the organic light emitting diode OLED or an anode voltage of the organic light emitting diode OLED is sensed. The timing controller 50 includes a data timing control signal DCS, a compensation timing control signal VCS, a scan timing control signal SCS, an initialization timing control signal ICS, and a data timing control signal DCS according to the display mode and the first to third sensing modes. and a control timing control signal CCS.

The timing controller 40 may receive the third sensing data SD3 from the reference voltage supply unit 23 and store the third sensing data SD3 in the internal memory. The timing controller 40 may compensate the digital video data DATA according to the third sensing data SD3 . Since the third sensing data SD3 is information about the current flowing through the organic light emitting diode OLED of each of the pixels P or the anode voltage of the organic light emitting diode OLED, the timing controller 40 controls the third sensing data ( SD3), threshold voltage compensation data for compensating for the threshold voltage of the driving transistor DT may be calculated. Accordingly, the timing controller 40 may output the digital video data DATA reflecting the threshold voltage of the driving transistor DT of each of the pixels P by applying the threshold voltage compensation data to the digital video data DATA. have.

The timing controller 40 outputs the digital video data DATA and the data timing control signal DCS to the data voltage supply unit 21 of the data driver 20 , and the compensation data CDATA and the compensation timing control signal VCS. is output to the compensation power voltage supply unit 22 . The timing control unit 50 outputs the scan timing control signal SCS to the scan signal supply unit 31 of the scan driver 30 , and outputs the initialization timing control signal ICS to the initialization signal supply unit 32 , the control timing The control signal CCS is output to the control signal driver 33 .

The power voltage compensator 50 receives the first and second sensing data SD1 and SD2 from the compensation power voltage supply unit 22 of the data driver 20 . The power supply voltage compensator 50 may store the first and second sensing data SD1 and SD2 in an internal memory.

The first sensing data SD1 is information on the cathode voltage of the organic light emitting diode OLED sensed when no current flows through the organic light emitting diode OLED of each of the pixels P, and the second sensing data SD2 is information on the cathode voltage of the organic light emitting diode (OLED) sensed when a predetermined current flows through each of the pixels (P). The power supply voltage compensator 50 processes a predetermined algorithm using the first and second sensing data SD1 and SD2, thereby compensating for the voltage increase of the cathode electrode of the organic light emitting diode (OLED) compensation data CDATA. ) can be created. That is, the power supply voltage compensator 50 may generate compensation data CDATA for compensating for cathode rising.

The power supply voltage compensator 50 supplies the compensation data CDATA to the timing control unit 40 in the display mode. The power voltage compensator 50 may be built in the timing controller 40 .

4 is a circuit diagram illustrating an example of the pixel of FIG. 1 . In FIG. 4, for convenience of explanation, a jth (j is an integer satisfying 1≤j≤m) data line Dj, a jth power supply voltage compensation line Vj, and qth (q is 1≤q≤p) a reference voltage line (Rq), a kth (k is an integer satisfying 1≤k≤n) scan line (Sk), a kth initialization line (Ik), and a kth power supply voltage control line (Ck) Only the pixel P connected to is shown.

Referring to FIG. 4 , the pixel P includes an organic light emitting diode OLED and a pixel driver PD. The pixel driver PD may include a driving transistor DT, a plurality of switching transistors, and a capacitor C as shown in FIG. 4 . The switching transistors include first to third transistors ST1 , ST2 , and ST3 .

The organic light emitting diode OLED emits light according to a current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode OLED may be connected to the source electrode of the driving transistor DT, and the cathode electrode may be connected to the low potential voltage line VSSL to which a low potential voltage lower than the high potential voltage is supplied.

An organic light emitting diode (OLED) may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In an organic light emitting diode (OLED), when a voltage is applied to an anode electrode and a cathode electrode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light emitting layer to emit light. The anode electrode of the organic light emitting diode OLED may be connected to the source electrode of the driving transistor DT, and the cathode electrode may be connected to the first power voltage line VSSL to which the first power voltage is supplied.

The driving transistor DT is disposed between the second power voltage line VDDL to which the second power voltage is supplied and the organic light emitting diode OLED. The driving transistor DT adjusts a current flowing from the second power voltage line VDDL to the organic light emitting diode OLED according to a voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first transistor ST1 , the source electrode is connected to the anode electrode of the organic light emitting diode OLED, and the drain electrode is connected to the second power voltage line VDDL. can be connected to

The first transistor ST1 is turned on by the k-th scan signal of the k-th scan line Sk to supply the voltage of the j-th data line Dj to the gate electrode of the driving transistor DT. The gate electrode of the first transistor ST1 is connected to the k-th scan line Sk, the first electrode is connected to the gate electrode of the driving transistor DT, and the second electrode is connected to the j-th data line Dj. can be The first transistor ST1 may be collectively referred to as a scan transistor.

The second transistor ST2 is turned on by the k-th initialization signal of the k-th initialization line Ik to connect the q-th reference voltage line Rq to the source electrode of the driving transistor DT. The gate electrode of the second transistor ST2 is connected to the k-th initialization line Ik, the first electrode is connected to the q-th reference voltage line Rq, and the second electrode is connected to the source electrode of the driving transistor DT. can be connected.

The third transistor ST3 is turned on by the kth control signal of the kth power supply voltage control line Ck to connect the jth power supply voltage compensation line Vj to the cathode electrode of the organic light emitting diode OLED. The gate electrode of the third transistor ST3 is connected to the kth power supply voltage control line Ck, the first electrode is connected to the jth power supply voltage compensation line Vj, and the second electrode is an organic light emitting diode (OLED). is connected to the cathode electrode of

The first electrode of each of the first to third transistors ST1 , ST2 , and ST3 may be a source electrode and the second electrode may be a drain electrode, but it should be noted that the present invention is not limited thereto. That is, a first electrode of each of the first to third transistors ST1 , ST2 , and ST3 may be a drain electrode, and a second electrode may be a source electrode.

The capacitor C is formed between the gate electrode and the source electrode of the driving transistor DT. The capacitor C stores the difference voltage between the gate voltage and the source voltage of the driving transistor DT.

In FIG. 4 , the driving transistor DT and the first to third transistors ST1 , ST2 , and ST3 are mainly described as being formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but it should be noted that the present invention is not limited thereto. do. The driving transistor DT and the first and second transistors ST1 and ST2 may be formed of a P-type MOSFET. In this case, the timing diagrams of FIGS. 5, 7 and 9 are appropriate for the characteristics of the P-type MOSFET. can be modified to

The organic light emitting display device according to an embodiment of the present invention is driven in a display mode and first to third sensing modes, and the pixel P is driven according to the display mode and which mode is selected from the first to third sensing modes. Waveforms of the scan signal, the initialization signal, and the control signal supplied to the controller are different. Due to this, the operation of the pixel P is different. Hereinafter, the operation of the pixel P in the display mode is examined in conjunction with FIGS. 5 and 6A to 6C, and the operation of the pixel P in the first sensing mode is examined in conjunction with FIGS. 7 and 8, The operation of the pixel P in the second sensing mode will be described in conjunction with FIGS. 9 and 10 .

Meanwhile, in the third sensing mode, the pixel P turns on the first transistor ST1 to supply a sensing data voltage to the gate electrode of the driving transistor DT and turns on the second transistor ST2 to turn on After supplying the first reference voltage to the source electrode of the driving transistor DT, only the second transistor ST2 is turned on to sense the current flowing through the organic light emitting diode OLED or the anode voltage of the organic light emitting diode OLED. and a detailed description thereof will be omitted.

5 is a waveform diagram illustrating a kth scan signal, a kth initialization signal, and a kth control signal supplied to a pixel in a display mode. In FIG. 5 , for convenience of explanation, the kth scan signal SCANk supplied to the kth scan line Sk connected to the pixel P of FIG. 4 and the kth initialization signal supplied to the kth initialization line Ik Only (INIk) and the kth control signal CSk supplied to the kth power supply voltage control line Ck are exemplified.

Referring to FIG. 5 , in the display mode, one frame period may be divided into first to third periods t1 to t3 . One frame period refers to a period in which data voltages are supplied to all pixels P of the display panel 10 .

The first period ST1 is a period in which the source electrode of the driving transistor DT is initialized to the first initialization voltage VREF1 and the data voltage Vdata is supplied to the gate electrode of the driving transistor DT. The first period ST1 may be one horizontal period. One horizontal period indicates a period in which data voltages are supplied to pixels P of one horizontal line, and the pixels P of one horizontal line may be connected to the same scan line. The second period ST2 is a period in which a compensation power voltage is supplied to the cathode electrode of the organic light emitting diode OLED. The second and third periods t2 and t3 are periods in which the organic light emitting diode OLED emits light according to the current of the driving transistor DT.

The scan signal supply unit 31 supplies the k-th scan signal SCANk of the gate-on voltage VGH during the first period ST1 to the k-th scan line Sk in the display mode, and in the second and third periods During (t2, t3), the kth scan signal SCANk of the gate-off voltage VGL is supplied. The initialization signal supply unit 32 supplies the k-th initialization signal INIk of the gate-on voltage VGH during the first period ST1 to the k-th initialization line Ik in the display mode, and in the second and third periods During (t2, t3), the kth initialization signal INIk of the gate-off voltage VGL is supplied. The control signal supply unit 33 supplies the k-th control signal CSk of the gate-off voltage VGL to the k-th power supply voltage control line Ck during the first and third periods t1 and t3 in the display mode, and , the k-th control signal CSk of the gate-on voltage VGH is supplied during the second period ST2.

When the first to third transistors T1 to T3 of each of the pixels P are formed of an N-type MOSFET as shown in FIG. 4 , the gate-on voltage VGH is the first to third transistors of each of the pixels P. It is a gate high voltage capable of turning on the three transistors T1 to T3 , and the gate-off voltage VGL turns off the first to third transistors T1 to T3 of each of the pixels P. It may be a gate-low voltage that can make For example, the gate high voltage may be a voltage of 15V or more, and the gate low voltage may be a voltage of 0V or less.

The data voltage supply unit 21 applies the data voltage to be supplied to the pixel P connected to the k-th scan line Sk and the j-th data line Dj during the first period ST1 in the display mode to the j-th data line ( ST1 ). Dj) is supplied. The compensation power supply voltage supply unit 22 applies the compensation power voltage to be supplied to the pixel P connected to the k-th scan line Sk and the j-th data line Dj in the display mode during the second period ST2 as the j-th power supply. It is supplied to the voltage compensation line (Vj). The reference voltage supply unit 23 supplies the first reference voltage VREF1 to the q-th reference voltage line Rq during the first to third periods t1 to t3 in the display mode.

Hereinafter, the operation of the pixel P in the display mode will be described in detail with reference to FIGS. 6A to 6C .

6A to 6C are circuit diagrams illustrating an operation of a pixel during first to third periods of FIG. 5 . 6A to 6C, the turned-off transistor is illustrated with a dotted line for convenience of description. Hereinafter, a method of driving a pixel in a display mode according to an embodiment of the present invention will be described in detail in conjunction with FIGS. 5 and 6A to 6C.

Referring to FIG. 6A , during the first period ST1, the first transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage VGH supplied to the k-th scan line Sk. , the second transistor ST2 is turned on by the kth initialization signal INIk of the gate-on voltage VGH supplied to the kth initialization line Ik. During the first period ST1, the third transistor ST3 is turned off by the k-th control signal CSk of the gate-off voltage VGL supplied to the k-th power supply voltage control line Ck.

During the first period ST1 , the data voltage Vdata of the j-th data line Dj is supplied to the gate electrode of the driving transistor DT due to the turn-on of the first transistor ST1 . Also, the first initialization voltage VREF1 of the q-th reference voltage line Rq is supplied to the source electrode of the driving transistor DT due to the turn-on of the second transistor ST2 during the first period ST1. That is, during the first period ST1 , the source electrode of the driving transistor DT is initialized to the first initialization voltage VREF1 . A voltage difference Vdata-VREF1 between the gate electrode and the source electrode of the driving transistor DT is stored in the capacitor C.

Referring to FIG. 6B , during the second period ST2, the first transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage VGL supplied to the k-th scan line Sk. , the second transistor ST2 is turned off by the k-th initialization signal INIk of the gate-off voltage VGL supplied to the k-th initialization line Ik. During the second period ST2, the third transistor ST3 is turned on by the k-th control signal CSk of the gate-on voltage VGH supplied to the k-th power supply voltage control line Ck.

During the second period ST2, the compensation power voltage CV of the j-th power voltage compensation line Vj is supplied to the cathode electrode of the organic light emitting diode OLED due to the turn-on of the third transistor ST3. The compensation power voltage CV is a voltage for compensating for an increase in the power voltage supplied to the cathode electrode of the organic light emitting diode (OLED). Therefore, by supplying the compensation power voltage CV to the cathode electrode of the organic light emitting diode OLED during the second period ST2, it is possible to prevent the power voltage supplied to the cathode electrode of the organic light emitting diode OLED from rising. have.

Referring to FIG. 6C , during the third period ST3 , the first transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage VGL supplied to the k-th scan line Sk. , the second transistor ST2 is turned off by the k-th initialization signal INIk of the gate-off voltage VGL supplied to the k-th initialization line Ik, and the third transistor ST3 is turned off by the k-th power supply voltage It is turned off by the k-th control signal CSk of the gate-off voltage VGL supplied to the control line Ck.

A voltage difference Vdata-VREF1 between the gate electrode and the source electrode of the driving transistor DT is maintained by the capacitor C during the second and third periods t2 and t3. Accordingly, a current Ids according to the voltage difference Vdata-VREF1 between the gate electrode and the source electrode of the driving transistor DT flows to the organic light emitting diode OLED. Accordingly, the organic light emitting diode (OLED) emits light. Hereinafter, for convenience of description, a “current Ids according to a voltage difference (Vdata-VREF1 ) between the gate electrode and the source electrode of the driving transistor DT” is defined as “the current Ids of the driving transistor”.

Since the data voltage Vdata is a voltage for which the threshold voltage of the driving transistor DT is compensated, the current Ids of the driving transistor DT flowing through the organic light emitting diode OLED during the second period ST2 is DT) does not depend on the threshold voltage.

As described above, in the embodiment of the present invention, the compensation power voltage CV is supplied to the cathode electrode of the organic light emitting diode (OLED) in the display mode. As a result, the embodiment of the present invention can prevent the power supply voltage supplied to the cathode electrode of the organic light emitting diode (OLED) from rising. Accordingly, according to the embodiment of the present invention, it is possible to prevent the luminance uniformity of the pixels from being lowered due to the increase of the power voltage supplied to the cathode electrode.

Also, in the exemplary embodiment of the present invention, the data voltage Vdata for which the threshold voltage of the driving transistor DT is compensated is supplied to the pixel P in the display mode. As a result, in the exemplary embodiment of the present invention, the organic light emitting diode OLED of the pixel P may emit light according to the current Ids of the driving transistor DT that does not depend on the threshold voltage of the driving transistor DT. Accordingly, according to the exemplary embodiment of the present invention, it is possible to prevent the luminance uniformity of the pixels P from being lowered according to the threshold voltage of the driving transistor DT.

7 is a waveform diagram illustrating a kth scan signal, a kth initialization signal, and a kth control signal supplied to a pixel in the first sensing mode. In FIG. 7 , for convenience of explanation, the kth scan signal SCANk supplied to the kth scan line Sk connected to the pixel P of FIG. 4 and the kth initialization signal supplied to the kth initialization line Ik Only (INIk) and the kth control signal CSk supplied to the kth power supply voltage control line Ck are exemplified.

Referring to FIG. 7 , in the first sensing mode, one frame period may be divided into first and second periods t1' and t2'. Meanwhile, one frame period may include an active period in which data voltages are supplied to the pixels P and a vertical blank period that is an idle period, and the pixel P in the first sensing mode may operate during the vertical blank period. . In this case, the vertical blank period in the first sensing mode may be divided into first and second periods t1' and t2'.

The first period t1' is a period in which the voltage of the cathode electrode of the organic light emitting diode OLED is sensed when no current flows through the organic light emitting diode OLED. The second period t2' is a period in which the sensed voltage is converted into the first sensing data SD1 which is digital data.

The scan signal supply unit 31 applies the k-th scan signal SCANk of the gate-off voltage VGL to the k-th scan line Sk during the first and second periods t1' and t2' in the first sensing mode. supply The initialization signal supply unit 32 applies the kth initialization signal INIk of the gate-off voltage VGL to the kth initialization line Ik during the first and second periods t1' and t2' in the first sensing mode. supply The control signal supply unit 33 supplies the kth control signal CSk of the gate-on voltage VGH to the kth power supply voltage control line Ck during the first period t1' in the first sensing mode, and the second During the period t2', the k-th control signal CSk of the gate-off voltage VGL is supplied.

The data voltage supply unit 21 does not supply the data voltage Vdata to the j-th data line Dj in the first sensing mode. The compensation power voltage supply unit 22 does not supply the compensation power voltage to the j-th power voltage compensation line Vj in the first sensing mode. The compensation power supply voltage supply unit 22 senses the voltage of the j-th power supply voltage compensation line Vj connected to the cathode electrode of the organic light emitting diode (OLED) in the first sensing mode by sensing the voltage of the cathode electrode of the organic light emitting diode (OLED). sense the voltage. The reference voltage supply unit 23 does not supply the first reference voltage VREF1 or the second reference voltage VREF2 to the q-th reference voltage line Rq in the first sensing mode.

Hereinafter, the operation of the pixel P in the first sensing mode will be described in detail with reference to FIG. 8 .

8 is a circuit diagram illustrating an operation of a pixel during a first period in a first sensing mode. In FIG. 8 , the turned-off transistor is illustrated with a dotted line for convenience of description. Hereinafter, a method of driving a pixel in the first sensing mode according to an embodiment of the present invention will be described in detail in conjunction with FIGS. 7 and 8 .

Referring to FIG. 8 , during the first period t1 ′, the first transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage VGL supplied to the k-th scan line Sk. and the second transistor ST2 is turned off by the k-th initialization signal INIk of the gate-off voltage VGL supplied to the k-th initialization line Ik. During the first period t1', the third transistor ST3 is turned on by the k-th control signal CSk of the gate-on voltage VGH supplied to the k-th power supply voltage control line Ck.

During the first period t1 ′, no voltage is applied to the gate electrode and the source electrode of the driving transistor DT due to the first and second transistors ST1 and ST2 being turned off. Accordingly, the current Ids of the driving transistor DT does not flow to the organic light emitting diode OLED.

During the first period t1 ′, the j-th power supply voltage compensation line Vj is connected to the cathode electrode of the organic light emitting diode OLED due to the turn-on of the third transistor ST3 . Accordingly, the voltage of the cathode electrode of the organic light emitting diode OLED may be sensed by the power voltage supply unit 22 through the j-th power voltage compensation line Vj.

Then, during the second period t2', the power supply voltage supply unit 22 converts the voltages sensed through the first to mth power supply voltage compensation lines V1 to Vm into the first sensing data SD1 as digital data. convert The power supply voltage supply unit 22 outputs the first sensing data SD1 to the power supply voltage compensator 50 .

9 is a waveform diagram illustrating a kth scan signal, a kth initialization signal, and a kth control signal supplied to a pixel in the second sensing mode. In FIG. 9 , for convenience of explanation, the kth scan signal SCANk supplied to the kth scan line Sk connected to the pixel P of FIG. 4 and the kth initialization signal supplied to the kth initialization line Ik are shown in FIG. Only (INIk) and the kth control signal CSk supplied to the kth power supply voltage control line Ck are exemplified.

Referring to FIG. 9 , in the second sensing mode, one frame period may be divided into first and second periods t1″ and t2″. Meanwhile, the pixel P in the second sensing mode may operate during the vertical blank period. In this case, the vertical blank period in the second sensing mode may be divided into first and second periods t1″ and t2″. have.

The first period t1" is a period in which the voltage of the cathode electrode of the organic light emitting diode OLED is sensed when a predetermined current flows through the organic light emitting diode OLED. The second period t2" is the It is a period during which digital data is converted into second sensing data SD2 .

The scan signal supply unit 31 applies the k-th scan signal SCANk of the gate-off voltage VGL to the k-th scan line Sk during the first and second periods t1″ and t2″ in the second sensing mode. supply The initialization signal supply unit 32 supplies the k-th initialization signal INIk of the gate-on voltage VGH for the first period to the k-th initialization line Ik in the first sensing mode, and during the second period t2" It supplies the kth initialization signal INIk of the gate-off voltage VGL. The control signal supply unit 33 gates on the kth power supply voltage control line Ck in the first sensing mode for the first period t1". The k-th control signal CSk of the voltage VGH is supplied, and the k-th control signal CSk of the gate-off voltage VGL is supplied during the second period t2 ″.

The data voltage supply unit 21 does not supply the data voltage Vdata to the j-th data line Dj in the second sensing mode. The compensation power voltage supply unit 22 does not supply the compensation power voltage to the j-th power voltage compensation line Vj in the second sensing mode. The compensation power supply voltage supply unit 22 senses the voltage of the j-th power supply voltage compensation line Vj connected to the cathode electrode of the organic light emitting diode (OLED) in the second sensing mode by sensing the voltage of the cathode electrode of the organic light emitting diode (OLED). sense the voltage. The reference voltage supply unit 23 supplies the second reference voltage VREF2 to the q-th reference voltage line Rq in the second sensing mode.

Hereinafter, the operation of the pixel P in the second sensing mode will be described in detail with reference to FIG. 10 .

10 is a circuit diagram illustrating an operation of a pixel during a first period in a second sensing mode. In FIG. 10 , a turned-off transistor is illustrated with a dotted line for convenience of description. Hereinafter, a method of driving a pixel in the second sensing mode according to an embodiment of the present invention will be described in detail in conjunction with FIGS. 9 and 10 .

Referring to FIG. 10 , during the first period t1 ″, the first transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage VGL supplied to the k-th scan line Sk. The second transistor ST2 is turned on by the k-th initialization signal INIk of the gate-on voltage VGH supplied to the k-th initialization line Ik. During the first period t1 ″, the third transistor ST2 is turned on. The transistor ST3 is turned on by the k-th control signal CSk of the gate-on voltage VGH supplied to the k-th power supply voltage control line Ck.

The second reference voltage VREF2 is supplied to the source electrode of the driving transistor DT due to the turn-on of the second transistor ST2 during the first period t1″. Accordingly, the anode electrode of the driving transistor DT Since the second reference voltage VREF2 is applied to , a predetermined current flows through the organic light emitting diode OLED.

During the first period t1″, the j-th power supply voltage compensation line Vj is connected to the cathode electrode of the organic light-emitting diode OLED due to the turn-on of the third transistor ST3. Accordingly, the organic light-emitting diode OLED ) may be sensed by the power supply voltage supply unit 22 through the j-th power supply voltage compensation line Vj.

Then, during the second period t2', the power supply voltage supply unit 22 converts the voltages sensed through the first to mth power supply voltage compensation lines V1 to Vm into the first sensing data SD1 as digital data. convert The power supply voltage supply unit 22 outputs the first sensing data SD1 to the power supply voltage compensator 50 .

As described above, in the embodiment of the present invention, when no current flows in the organic light emitting diode (OLED) in the first sensing mode, the cathode electrode of the organic light emitting diode (OLED) through the j th power voltage compensation line (Vj). The voltage may be sensed, and it may be output to the power voltage compensator 50 as the first sensing data SD1 . In addition, in the embodiment of the present invention, when the second reference voltage VREF2 is supplied to the anode electrode of the organic light emitting diode (OLED) in the second sensing mode and a current flows through the organic light emitting diode (OLED), the jth power supply voltage compensation line The voltage of the cathode electrode of the organic light emitting diode OLED may be sensed through Vj, and the voltage may be output to the power supply voltage compensator 50 as the second sensing data SD2. For this reason, in the embodiment of the present invention, it is possible to calculate how non-uniform the voltage of the cathode electrode of the organic light emitting diode between the pixels P using the first and second sensing data SD1 and SD2. Compensation data CDATA for compensation may be calculated. As a result, the embodiment of the present invention can compensate for the increase in the power voltage supplied to the cathode electrode of the organic light emitting diode (OLED). Accordingly, according to the exemplary embodiment of the present invention, it is possible to prevent luminance non-uniformity of the display panel due to an increase in the power voltage supplied to the cathode electrode of the organic light emitting diode (OLED).

11 is a plan view illustrating an example of the pixel of FIG. 2 . 12 is a cross-sectional view taken along lines I-I' and II-II' of FIG. 11 . A structure of a pixel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 11 and 12 .

11 and 12 , a buffer layer BF is disposed on the lower substrate SUB. The buffer layer BF may include a plurality of inorganic layers for preventing moisture and oxygen from penetrating into the active layers AD and A3 of the driving transistor DT and the first to third transistors T1 to T3. can The inorganic films may include two or more types of inorganic films. For example, the buffer layer BF may be formed of a composite layer of silicon oxide (SiO ₂ ) and silicon nitride (SiNx). The buffer layer BF may be omitted.

Active layers AD and A3 are patterned on the buffer layer BF. Each of the active layers AD and A3 may be selectively doped with impurities. A gate insulating layer GI may be disposed on the active layers AD and A3 . The gate insulating layer GI may be formed of a single layer of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) or a composite layer of silicon oxide (SiO ₂ ) and silicon nitride (SiNx).

The scan lines Sk, the initialization lines Ik, the power supply voltage control lines Ck, and the gates of the driving transistor DT and the first to third transistors T1 to T3 are formed on the gate insulating layer GI. A first metal pattern including the electrodes GED and GE3 is patterned. The first metal pattern may be a gate metal pattern, for example, a single layer or molybdenum (Mo) using molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu) as a material. , titanium (Ti), aluminum (Al), or copper (Cu) may be formed in a multi-layer structure including at least two metals.

11 and 12 exemplify that the driving transistor DT and the gate electrode of each of the first to third transistors T1 to T3 are formed in a top gate (top gate) method positioned above the active layer However, it should be noted that the present invention is not limited thereto. That is, the driving transistor DT and the gate electrode of each of the first to third transistors T1 to T3 may be formed in a lower gate (bottom gate) method positioned below the active layer.

A first interlayer insulating layer ILD1 covering them is disposed on the first metal pattern, the active layers AD and A3 , the gate insulating layer GI, and the buffer layer BF. Data lines Dj, power supply voltage compensation lines Vj, reference voltage lines Rq, second power supply voltage lines VDDL, and a driving transistor DT and a first interlayer insulating layer ILD1 are disposed on the first interlayer insulating layer ILD1. A second metal pattern including the source electrodes SED and SE3 and the drain electrodes DED and DE3 of the first to third transistors T1 to T3 is patterned. The second metal pattern may be a source drain metal pattern, for example, a single layer or molybdenum (Mo) using molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu) as a material. ), titanium (Ti), aluminum (Al), or copper (Cu) may be formed in a multi-layer structure including at least two metals. Each of the source electrodes SED and SE3 and the drain electrodes DED and DE3 of the driving transistor DT and the first to third transistors T1 to T3 has a contact hole passing through the first interlayer insulating layer ILD1 . (contact hole) may be connected to the active layer.

A second interlayer insulating layer ILD2 covering the second metal pattern is disposed on the second metal pattern. A third metal pattern including the first auxiliary electrodes AE1 and the second auxiliary electrodes AE2 is patterned on the second interlayer insulating layer ILD2 . The third metal pattern is a single layer or molybdenum (Mo), titanium (Ti), aluminum (Al) using molybdenum (Mo), titanium (Ti), aluminum (Al) or copper (Cu) as a material. Alternatively, the copper (Cu) material may be formed in a multi-layer structure including at least two metals. The first auxiliary electrode AE1 may be connected to the drain electrode DED of the driving transistor DT through a contact hole passing through the second interlayer insulating layer ILD2 . The second auxiliary electrode AE2 may be connected to the drain electrode DED of the third transistor ST3 through another contact hole penetrating the second interlayer insulating layer ILD2 .

A third interlayer insulating layer ILD3 covering the third metal pattern is disposed on the third metal pattern. A fourth metal pattern including anode electrodes AND and connection electrodes CE is patterned on the third interlayer insulating layer ILD3 . In the top emission structure, since the organic light emitting layer OL emits light in the cathode electrode CAT direction, the fourth metal pattern is preferably formed of a metal material having high reflectance.

The anode electrode AND may be connected to the first auxiliary electrode AE1 through a contact hole penetrating the third interlayer insulating layer ILD3 . Accordingly, the anode electrode AND may be electrically connected to the drain electrode DED of the driving transistor DT. The connection electrode CE may be connected to the second auxiliary electrode AE2 through another contact hole penetrating the third interlayer insulating layer ILD3 . Accordingly, the connection electrode CE may be electrically connected to the drain electrode DE3 of the third transistor ST3 . Meanwhile, the third metal pattern and the second interlayer insulating layer ILD2 may be omitted depending on the process design. In this case, the anode electrode AND is directly connected to the drain electrode DED of the driving transistor DT, and the connection electrode (CE) may be directly connected to the drain electrode DE3 of the third transistor ST3.

Banks partitioning them are disposed on the anode electrodes AND and the connection electrodes CE. The banks may be formed of photoresist or photoacrylic, but is not limited thereto.

An organic light emitting layer OL is disposed on the anode electrodes AND and the banks. The organic light emitting layer OL may include a hole transporting layer, an organic layer, and an electron transporting layer. In this case, when a voltage is applied to each of the anode electrode AND and the cathode electrode CAT, holes and electrons move to the organic layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic layer to emit light.

Meanwhile, although the organic light emitting layer OL is destroyed on the connection electrode CE, a portion may remain on the connection electrode CE. A detailed description of the destruction of the organic light emitting layer OL will be described in connection with FIG. 14F .

A cathode electrode CAT is disposed on the organic light emitting layer OL. In addition, since the organic light emitting layer OL between the connection electrode CE and the cathode electrode CAT is destroyed, and the destroyed organic light emitting layer OLD does not function as an insulating layer, the cathode electrode CAT is the connection electrode ( CE) can be connected. Therefore, the cathode electrode CAT may be electrically connected to the connection electrode CE. That is, the cathode electrode CAT may receive the compensation power supply voltage from the j-th power supply voltage compensation line Vj through the third transistor ST3 , the second auxiliary electrode AE2 , and the connection electrode CE.

In addition, conductivity between the cathode electrode CAT and the connection electrode CE may vary according to the degree of destruction of the organic light emitting layer OL. For example, the more the organic light emitting layer OL remains on the connection electrode CE, the greater the electrical resistance between the cathode electrode CAT and the connection electrode CE. In the embodiment of the present invention, as described with reference to FIGS. 7 to 10 , the voltage of the cathode electrode CAT of each of the pixels P is sensed through the first and second sensing modes to obtain a compensated power supply voltage to the cathode electrode CAT. supply to As a result, the embodiment of the present invention can also compensate for a change in conductivity between the cathode electrode CAT and the connection electrode CE according to the degree of destruction of the organic light emitting layer OL.

In the top emission type structure, the organic light emitting layer OL emits light in the direction of the cathode electrode CAT. Therefore, the cathode electrode CAT is preferably formed of a transparent metal material such as indium tin oxide (ITO) and induim zinc oxide (IZO) or a semi-transmissive layer such as magnesium (Mg) or silver (Ag).

13 is a flowchart illustrating a method of manufacturing an organic light emitting display device according to an embodiment of the present invention. 14A to 14F are cross-sectional views for explaining a method of manufacturing the organic light emitting display device of FIG. 13 . Hereinafter, a method of manufacturing an organic light emitting display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 13 and 14A to 14F .

14A to 14F illustrate that the driving transistor DT and the gate electrode of each of the first to third transistors T1 to T3 are formed in a top gate (top gate) method positioned above the active layer. However, it should be noted that the present invention is not limited thereto. That is, the driving transistor DT and the gate electrode of each of the first to third transistors T1 to T3 may be formed in a lower gate (bottom gate) method positioned below the active layer.

First, thin film transistors such as the driving transistor DT and the first to third transistors T1 to T3 are formed on the lower substrate SUB as shown in FIG. 14A . The lower substrate SUB may be made of glass or a plastic film. Each of the driving transistor DT and the first to third transistors T1 to T3 includes an active layer AD and A3, the gate electrodes GED and GE3, the source electrodes SED and SE3, and the drain electrode DED; DE3).

Specifically, the buffer layer BF is formed on the lower substrate SUB. The buffer layer BF may include a plurality of inorganic layers for preventing moisture and oxygen from penetrating into the active layers AD and A3 of the driving transistor DT and the first to third transistors T1 to T3. can The inorganic films may include two or more types of inorganic films. For example, the buffer layer BF may be formed of a composite layer of silicon oxide (SiO ₂ ) and silicon nitride (SiNx). The buffer layer BF may be omitted.

Then, the active layers AD and A3 are patterned on the buffer layer BF. Each of the active layers AD and A3 may be selectively doped with impurities.

Then, a gate insulating layer GI is formed on the active layers AD and A3. The gate insulating layer GI may be formed of a single layer of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) or a composite layer of silicon oxide (SiO ₂ ) and silicon nitride (SiNx).

Then, the scan lines Sk, the initialization lines Ik, the power supply voltage control lines Ck, and the driving transistor DT and the first to third transistors T1 to T3 are formed on the gate insulating layer GI. ), a first metal pattern including the gate electrodes GED and GE3 is patterned. The first metal pattern may be a gate metal pattern, for example, a single layer or molybdenum (Mo) using molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu) as a material. , titanium (Ti), aluminum (Al), or copper (Cu) may be formed in a multi-layer structure including at least two metals.

A first interlayer insulating layer ILD1 covering the first metal pattern, the active layers AD and A3, the gate insulating layer GI, and the buffer layer BF is formed. Data lines Dj, power supply voltage compensation lines Vj, reference voltage lines Rq, second power supply voltage lines VDDL, and a driving transistor DT and a first interlayer insulating layer ILD1 are disposed on the first interlayer insulating layer ILD1. A second metal pattern including the source electrodes SED and SE3 and the drain electrodes DED and DE3 of the first to third transistors T1 to T3 is patterned. The second metal pattern may be a source-drain metal pattern, for example, a single layer or molybdenum (Mo) using molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu) as a material. ), titanium (Ti), aluminum (Al), or copper (Cu) may be formed in a multi-layer structure including at least two metals. Each of the source electrodes SED and SE3 and the drain electrodes DED and DE3 of the driving transistor DT and the first to third transistors T1 to T3 has a contact hole passing through the first interlayer insulating layer ILD1. (contact hole) may be connected to the active layer. (S101 in FIG. 13)

Second, auxiliary electrodes AE1 and AE2 are formed on thin film transistors such as the driving transistor DT and the first to third transistors T1 to T3 as shown in FIG. 14B .

Specifically, a second interlayer insulating layer ILD2 covering the second metal pattern is formed on the second metal pattern. Then, a third metal pattern including the first auxiliary electrodes AE1 and the second auxiliary electrodes AE2 is patterned on the second interlayer insulating layer ILD2 . The third metal pattern is a single layer or molybdenum (Mo), titanium (Ti), aluminum (Al) using molybdenum (Mo), titanium (Ti), aluminum (Al) or copper (Cu) as a material. Alternatively, the copper (Cu) material may be formed in a multi-layer structure including at least two metals. The first auxiliary electrode AE1 may be connected to the drain electrode DED of the driving transistor DT through a contact hole passing through the second interlayer insulating layer ILD2 . The second auxiliary electrode AE2 may be connected to the drain electrode DED of the third transistor ST3 through another contact hole penetrating the second interlayer insulating layer ILD2 . (S102 in FIG. 13)

Third, anode electrodes AND and connection electrodes CE are formed on auxiliary electrodes AE1 and AE2 as shown in FIG. 14C .

Specifically, a third interlayer insulating layer ILD3 covering the third metal pattern is formed on the third metal pattern. Then, a fourth metal pattern including the anode electrodes AND and the connection electrodes CE is patterned on the third interlayer insulating layer ILD3 . In the top emission structure, since the organic light emitting layer OL emits light in the cathode electrode CAT direction, the fourth metal pattern is preferably formed of a metal material having high reflectance.

The anode electrode AND may be connected to the first auxiliary electrode AE1 through a contact hole penetrating the third interlayer insulating layer ILD3 . Accordingly, the anode electrode AND may be electrically connected to the drain electrode DED of the driving transistor DT. The connection electrode CE may be connected to the second auxiliary electrode AE2 through another contact hole penetrating the third interlayer insulating layer ILD3 . Accordingly, the connection electrode CE may be electrically connected to the drain electrode DE3 of the third transistor ST3 .

Meanwhile, the third metal pattern and the second interlayer insulating layer ILD2 may be omitted depending on the process design. In this case, the anode electrode AND is directly connected to the drain electrode DED of the driving transistor DT, and the connection electrode (CE) may be directly connected to the drain electrode DE3 of the third transistor ST3. (S103 in FIG. 13)

Fourth, as shown in FIG. 14D , banks partitioning them are formed on the anode electrodes AND and the connection electrodes CE. To this end, the banks may be formed to have a higher height than the anode electrodes AND and the connection electrodes CE. The banks may be formed of photoresist or photoacrylic, but is not limited thereto. (S104 in FIG. 13)

Fifth, as shown in FIG. 14E , the organic light emitting layer OL is formed on the anode electrodes AND, the connection electrodes CE, and the banks BANK. The organic light emitting layer OL may include a hole transporting layer, an organic layer, and an electron transporting layer. In this case, when a voltage is applied to each of the anode electrode AND and the cathode electrode CAT, holes and electrons move to the organic layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic layer to emit light.

In addition, a cathode electrode CAT is formed on the organic light emitting layer OL. In the top emission type structure, the organic light emitting layer OL emits light in the direction of the cathode electrode CAT. Therefore, the cathode electrode CAT is preferably formed of a transparent metal material such as indium tin oxide (ITO) and induim zinc oxide (IZO) or a semi-transmissive layer such as magnesium (Mg) or silver (Ag). (S105 in FIG. 13)

Sixth, as shown in FIG. 14F , a reverse bias voltage is applied to the connection electrode CE and the cathode electrode CAT to destroy the organic light emitting layer OL between the connection electrode CE and the cathode electrode CAT. Since the organic light emitting diode has a structure in which current flows in the directions of the anode electrode AND, the organic light emitting layer OL, and the cathode electrode CAT, when a voltage greater than a predetermined voltage is applied in the reverse direction, the organic light emitting layer OL is can only be destroyed Accordingly, when a first voltage is applied to the cathode electrode CAT and a second voltage lower than the first voltage is applied to the connection electrode CE, the organic light emitting layer OL may be destroyed. Also, since the insulating layer is removed between the cathode electrode CAT and the connection electrode CE as the organic light emitting layer OL is destroyed, the cathode electrode CAT and the connection electrode CE may be electrically connected. (S106 in FIG. 13)

As described above, in the embodiment of the present invention, a reverse bias voltage is applied to the connection electrode CE and the cathode electrode CAT to destroy the organic light emitting layer OL between the connection electrode CE and the cathode electrode CAT. By doing so, the cathode electrode CAT and the connection electrode CE are connected. As a result, in the embodiment of the present invention, since a separate manufacturing process for connecting the cathode electrode CAT and the connection electrode CE is not added, manufacturing cost and time can be saved.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 20: data driver
21: data voltage supply part 22: compensation power supply voltage supply part
23: reference voltage supply unit 30: scan driver
31: scan signal supply unit 32: initialization signal supply unit
33: control signal supply unit 40: timing control unit
50: power supply voltage compensator P: pixel
DT: driving transistor ST1: first transistor
ST2: second transistor ST3: third transistor
C: capacitor OLED: organic light emitting diode
CE: connecting electrode CAT: cathode electrode
OL: organic light emitting layer AND: anode electrode

Claims (14)

A display panel comprising: data lines, power supply voltage compensation lines parallel to the data lines, scan lines crossing the data lines, and pixels connected to power supply voltage control lines;
The pixel is
an organic light emitting diode including an anode electrode and a cathode electrode; and
a third transistor connected to the cathode electrode;
A gate electrode of the third transistor is connected to the power supply voltage control line, a first electrode is connected to the power supply voltage compensation line, and a second electrode is connected to the cathode electrode,
and the third transistor is turned on by a power supply voltage control signal of the power supply voltage control line to supply a compensated power voltage of the power supply voltage compensation line to the cathode electrode. The method of claim 1,
Reference voltage lines parallel to the data lines and initialization lines crossing the data lines are disposed on the display panel;
The pixel is
a driving transistor for adjusting an amount of current flowing through the organic light emitting diode according to a voltage difference between a gate voltage and a source voltage;
a first transistor turned on by the scan signal of the scan line to supply the data voltage of the data line to the gate electrode of the driving transistor; and
and a second transistor turned on by an initialization signal of the initialization line to connect a source electrode of the driving transistor to the reference voltage line. 3. The method of claim 2,
In a display mode in which the organic light emitting diode emits light,
The scan signal and the initialization signal are supplied as a gate-on voltage during a first period and are supplied as a gate-off voltage during second to third periods,
The power supply voltage control signal is supplied as a gate-on voltage during the second period and is supplied as a gate-off voltage during the first and third periods. 3. The method of claim 2,
In the first sensing mode for sensing the power voltage of the cathode electrode,
The scan signal and the initialization signal are supplied as a gate-off voltage during first and second periods,
The power supply voltage control signal is supplied as a gate-on voltage during the first period and is supplied as a gate-off voltage during the second period. 3. The method of claim 2,
In the second sensing mode for sensing the power supply voltage of the cathode electrode when a reference voltage is applied to the anode electrode,
The scan signal is supplied as a gate-off voltage during first and second periods, the initialization signal and the power supply voltage control signal are supplied as a gate-on voltage during the first period, and are supplied as a gate-off voltage during the second period. Supplied organic light emitting display device. 3. The method of claim 2,
a data voltage supply unit supplying data voltages to the data lines;
a reference voltage supply unit for supplying a reference voltage to the reference voltage lines;
a compensation power supply voltage supply unit for supplying compensation power voltages to the power voltage compensation lines or sensing voltages of the power voltage compensation lines;
a scan signal supply unit supplying scan signals to the scan lines;
an initialization signal supply unit supplying initialization signals to the initialization lines; and
The organic light emitting display device further comprising a control signal supply unit for supplying control signals to the power supply voltage control lines. lower substrate;
a power supply voltage compensation line formed on the lower substrate;
driving transistors and switching transistors formed on the lower substrate and each including an active layer, a gate electrode, a source electrode, and a drain electrode;
an anode electrode and a connection electrode formed on the driving transistor and the switching transistors;
banks partitioning the anode electrode and the connection electrode;
an organic light emitting layer covering the anode electrode and the banks; and
A cathode electrode covering the organic light emitting layer,
A drain electrode of the driving transistor is electrically connected to the anode electrode,
A drain electrode of any one of the switching transistors is connected to the connection electrode, and a source electrode is connected to the power supply voltage compensation line,
and the cathode electrode is electrically connected to the connection electrode. 8. The method of claim 7,
The anode electrode and the connection electrode have the same material and are disposed on the same layer. 9. The method of claim 8,
a first auxiliary electrode disposed on the interlayer insulating layer and connected to the drain electrode of the driving transistor through a contact hole penetrating the interlayer insulating layer; and
and a second auxiliary electrode disposed on the interlayer insulating layer and connected to a drain electrode of any one of the switching transistors through another contact hole passing through the interlayer insulating layer. 10. The method of claim 9,
The anode electrode is disposed on a planarization layer covering the first and second auxiliary electrodes, and is connected to the first auxiliary electrode through a contact hole passing through the planarization layer. 11. The method of claim 10,
The connection electrode is disposed on the planarization layer and is connected to the second auxiliary electrode through another contact hole passing through the planarization layer. forming a power supply voltage compensation line, a driving transistor, and a switching transistor on a lower substrate;
forming an anode electrode and a connection electrode on the power supply voltage compensation line, the driving transistor, and the switching transistors;
forming banks that partition the anode electrode and the connection electrode;
forming an organic light emitting layer on the anode electrode, the connection electrode, and the banks;
forming a cathode electrode on the organic light emitting layer; and
applying a reverse bias voltage to the connection electrode and the cathode electrode;
A drain electrode of the driving transistor is electrically connected to the anode electrode,
A drain electrode of any one of the switching transistors is connected to the connection electrode, and a source electrode is connected to the power supply voltage compensation line,
and the cathode electrode is electrically connected to the connection electrode. 13. The method of claim 12,
The step of applying a reverse bias voltage to the connection electrode and the cathode electrode,
A method of manufacturing an organic light emitting display device, wherein a first voltage is applied to the cathode electrode and a second voltage lower than the first voltage is applied to the connection electrode. 13. The method of claim 12,
Forming an anode electrode electrically connected to the drain electrode of the driving transistor and a connection electrode electrically connected to any one drain electrode of the switching transistors comprises:
A method of manufacturing an organic light emitting display device in which the anode electrode and the connection electrode are simultaneously formed of the same material on a planarization layer.

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