KR20150069278A - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device. The organic light emitting display device according to an embodiment of the present invention is characterized by comprising a display panel in which data lines and scan lines are formed and pixels arranged in a matrix shape are formed, wherein each of the pixels comprises a driving transistor having a gate electrode connected to a first node, having a first electrode connected to a second node, and having a second electrode connected to a third node; an organic light emitting diode emitting light upon current between drain and source of the driving transistor; and a first transistor connected between the first node and the third node, wherein the gate electrode of the driving transistor is overlapped with a semiconductor layer of the first transistor.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

The present invention relates to an organic light emitting display.

2. Description of the Related Art Various flat panel display devices capable of reducing weight and volume, which are disadvantages of cathode ray tubes (CRTs), have recently been developed. Examples of the flat panel display include a liquid crystal display, a field emission display, a plasma display panel, and an organic light emitting display.

Of the flat panel display devices, the organic light emitting display device displays an image using an organic light emitting diode (OLED) that generates light by recombination of electrons and holes. The organic electroluminescent display device has advantages of fast response speed and low power consumption.

A display panel of an organic light emitting display includes a plurality of pixels arranged in a matrix form. Each of the pixels includes a scan transistor for supplying a data voltage of a data line in response to a scan signal of a scan line, a drive transistor for controlling an amount of a drain-source current Ids according to a voltage of the gate electrode, And an organic light emitting diode that emits light according to the drain-source current Ids of the organic light emitting diode.

The drain-source current Ids of the driving transistor supplied to the organic light emitting diode can be expressed by Equation (1).

In Equation 1, k denotes a proportional coefficient determined by the structure and physical characteristics of the driving transistor, Vgs denotes a gate-source voltage of the driving transistor, and Vth denotes a threshold voltage of the driving transistor.

The drain-source current Ids of the driving transistor depends on the threshold voltage (Vth) of the driving transistor as shown in Equation (1). However, the threshold voltage of the driving transistor can be shifted by deterioration depending on driving time. In particular, since the degree of deterioration of the threshold voltage of the driving transistor differs from pixel to pixel, the degree of shift of the threshold voltage of the driving transistor also varies from pixel to pixel. This may cause a problem that the brightness of the pixels of the display panel is not uniform.

An embodiment of the present invention provides an organic light emitting display device capable of uniformizing the brightness of pixels of a display panel by compensating a threshold voltage of a driving transistor.

An organic light emitting display according to an exemplary embodiment of the present invention includes a display panel in which data lines and scan lines are formed and pixels arranged in a matrix are formed and each of the pixels has a gate electrode connected to a first node A driving transistor having a first electrode connected to the second node and a second electrode connected to the third node; An organic light emitting diode emitting light according to a drain-source current of the driving transistor; And a first transistor connected between the first node and the third node, wherein a gate electrode of the driving transistor overlaps with a semiconductor layer of the first transistor.

The embodiment of the present invention can compensate the threshold voltage of the driving transistor. As a result, in the embodiment of the present invention, since the drain-source current of the driving transistor supplied to the organic light emitting diode does not depend on the threshold voltage of the driving transistor, the luminance of the pixels of the display panel can be made uniform.

In addition, the embodiment of the present invention discharges the gate electrode of the driving transistor to the initializing voltage for a predetermined period before the third period of supplying the data voltage to apply the on-bias to the driving transistor. As a result, the embodiment of the present invention can solve the problem that the image quality is deteriorated by the hysteresis characteristic of the driving transistor.

Also, in order to prevent the first electrode of the first transistor from overlapping with the anode electrode of the organic light emitting diode, the gate electrode of the driving transistor may be extended to overlap the semiconductor layer of the first transistor, To one electrode. Therefore, the embodiment of the present invention can minimize the size of the parasitic capacitance formed between the anode electrode of the organic light emitting diode and the gate electrode of the driving transistor. As a result, the embodiment of the present invention can minimize the influence of the anode electrode of the organic light emitting diode due to the parasitic capacitance formed between the anode electrode of the organic light emitting diode and the gate electrode of the driving transistor, .

1 is a circuit diagram showing a part of a threshold voltage compensation pixel structure of a diode connection type.
FIG. 2 is a graph showing a drain-source current of a driving transistor according to a gate-source voltage difference in a gate-on-bias state and a gate-off-bias state.
FIG. 3 is a graph showing the luminance of a pixel when a peak black gradation voltage is supplied during the conventional p-frame period and a peak white gradation voltage is supplied during the (p + 1) th to (p + 3) th frame periods.
4 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention.
5 is an equivalent circuit diagram showing the pixel of FIG. 4 in detail;
FIG. 6 is a waveform diagram showing signals input to the pixel of FIG. 5;
7 is a flowchart showing the operation of the pixels during the first to fourth periods.
8A to 8D are equivalent circuit diagrams showing pixels during the first to fourth periods.
9 is a graph showing the luminance of a pixel when a peak black gradation voltage is supplied during a p-frame period and a peak white gradation voltage is supplied during a p + 1 to p + 3 frame period in an embodiment of the present invention.
10 is a plan view showing an example of the driving transistor and the first transistor of FIG. 5;
11 is an exemplary view showing a cross section taken along line A-A 'in FIG. 10;
12 is a plan view showing another example of the driving transistor and the first transistor of FIG. 5;
13 is an exemplary view showing a cross section taken along the line B-B 'in FIG. 12;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

1 is a circuit diagram showing a part of a threshold voltage compensation pixel structure of a diode connection type. 1 shows a driving transistor DT for supplying a current to an organic light emitting diode and a transistor ST connected between a gate node Ng and a drain node Nd of the driving transistor DT. The transistor ST connects the gate node Ng and the drain node Nd of the driving transistor DT during a period in which the data voltage is supplied to the driving transistor DT so that the driving transistor DT is connected to the diode .

1, since the gate node Ng and the drain node Nd are connected during the data voltage supply period in which the transistor ST is turned on, the gate node Ng and the drain node Nd are substantially equal to each other . When the voltage difference Vgs between the gate node Ng and the source node Ns is larger than the threshold voltage, the driving transistor DT is turned on when the voltage difference Vgs between the gate node Ng and the source node Ns, The current path is formed until the threshold voltage Vth of the gate electrode Ng and the drain node Nd is reached, so that the voltages of the gate node Ng and the drain node Nd are charged. That is, when the data voltage Vdata is supplied to the source node Ns of the driving transistor DT, the voltages of the gate node Ng and the drain node Nd of the driving transistor DT become equal to the data voltage Vdata (Vdata-Vth) between the threshold voltages Vth. As a result, the diode connection method can eliminate Vth in Equation (1), so that the threshold voltage Vth of the driving transistor DT can be compensated.

2 is a graph showing the drain-source current of the driving transistor according to the gate-source voltage difference in the gate-on-bias state and the gate off-bias state. Referring to FIG. 1 and FIG. 2, the driving transistor DT is driven by the hysteresis characteristic of the driving transistor DT according to the gate-source voltage difference in an on bias state and an off bias state, The current between the drain and the source of the transistor is different.

The on-bias state means a state in which the gate-on voltage is applied to the gate electrode of the driving transistor DT, such as a peak white grayscale voltage, so that the drain-source current Ids of the driving transistor largely flows. The off-bias state means a state in which a gate-off voltage such as a peak black grayscale voltage is applied to the gate electrode of the driving transistor so that the drain-source current Ids of the driving transistor hardly flows. The peak white gradation voltage means a voltage applied to the gate electrode of the driving transistor DT so that the organic light emitting diode emits light in a peak white gradation. The peak black gradation voltage is a voltage applied to the driving transistor DT for the organic light emitting diode to emit light in the peak black gradation. Quot; means a voltage applied to the gate electrode of the transistor DT. On the other hand, when the gradation value is represented by an 8-bit digital value, the peak black gradation means "0" which is the minimum value, and the peak white gradation means "255" which is the maximum value.

FIG. 3 is a graph showing luminance of a pixel when a peak black gradation voltage is supplied during a conventional p frame period and a peak white gradation voltage is supplied during a (p + 1) th to (p + 3) th frame period. 3, the peak black gradation voltage is supplied to the gate electrode of the driving transistor DT during the p-th frame period, and the peak white gradation voltage And the like.

1 to 3, since the peak black gradation voltage is supplied to the gate electrode of the driving transistor DT during the p-th frame period, the driving transistor DT is in the off-bias state during the (p + 1) And receives the gradation voltage PWGV. On the other hand, since the peak white gradation voltage is supplied to the gate electrode of the driving transistor DT during the (p + 1) -th frame period, the driving transistor DT maintains the peak white gradation voltage PWGV ). Therefore, even if the same peak white gradation voltage PWGV is supplied to the gate electrode of the driving transistor DT during the p + 1 and p + 2 frame periods, the drain- Source current Ids is smaller than the drain-source current Ids of the driving transistor DT during the (p + 2) -th frame period. 3, the amount of light emission of the organic light emitting diode is smaller than that of the organic light emitting diode in the (p + 1) -th frame period rather than the (p + 2) -th frame period. That is, the organic light emitting diode should emit light with the same peak white luminance during the (p + 1) th and (p + 2) th frame periods, but not with the peak white luminance during the p + 1 frame period as shown in FIG. Therefore, a luminance deviation occurs in the (p + 1) -th frame period and the (p + 2) -th frame period, and the image quality is deteriorated.

Hereinafter, an organic light emitting display device according to an embodiment of the present invention, which solves the problem of deterioration in image quality due to the hysteresis characteristic of the driving transistor DT described with reference to FIGS. 1 to 3, Will be described in detail.

4 is a block diagram illustrating an organic light emitting display according to an exemplary embodiment of the present invention. 4, an organic light emitting display according to an exemplary embodiment of the present invention includes a display panel 10, a data driver 20, a scan driver 30, a timing controller 40, a power source 50, Respectively.

The display panel 10 is formed such that the data lines DL1 to DLm, m is a positive integer of 2 or more, and the scan lines SL1 to SLn + 1, where n is a positive integer of 2 or more. In addition, the display panel 10 is formed with emission lines EML1 to EMLn in parallel with the scan lines SL1 to SLn + 1. In addition, in the display panel 10, pixels P arranged in a matrix form are formed. A detailed description of the pixel P of the display panel 10 will be given later with reference to FIG.

The data driver 20 includes a plurality of source drive ICs. The source drive ICs receive the digital video data (DATA) from the timing control unit 40. The source driver ICs convert the digital video data DATA into gamma compensation voltages in response to the source timing control signal DCS from the timing controller 40 to generate data voltages and display the data voltages in synchronization with the scan signals To the data lines (DL) of the panel (10). Accordingly, the data voltages are supplied to the pixels P to which the scan signals are supplied.

The scan driver 30 includes a scan signal output circuit and a light emission signal output circuit. Each of the scan signal output circuit and the light emission signal output circuit includes a shift register for sequentially generating an output signal, a level shifter for converting an output signal of the shift register into a swing width suitable for driving the transistor of the pixel P, .

The scan signal output circuit sequentially outputs scan signals to the scan lines (SL1 to SLn) of the display panel (10). The light emitting signal output circuit sequentially outputs the light emitting signals to the light emitting lines (EML1 to EMLn) of the display panel (10). A detailed description of the scan signal and the light emission signal will be given later with reference to FIG.

The timing controller 40 receives digital video data (DATA) from a host system (not shown) through an interface such as an LVDS (Low Voltage Differential Signaling) interface or a TMDS (Transition Minimized Differential Signaling) interface. The timing controller 40 receives timing signals including a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The timing controller 40 generates timing control signals for controlling the operation timings of the data driver 20 and the scan driver 30 based on the timing signals. The timing control signals include a scan timing control signal SCS for controlling the operation timing of the scan driver 30 and a data timing control signal DCS for controlling the operation timing of the data driver 20. [ The timing controller 40 outputs a scan timing control signal SCS to the scan driver 30 and a data timing control signal DCS to the data driver 20.

The power supply source 50 supplies a first power voltage to the pixels P of the display panel 10 through the first power voltage line ViniL and a second power voltage VCC via the second power voltage line VDDL, And supplies the third power supply voltage via the third power supply voltage line VSSL. Hereinafter, for convenience of explanation, the first power supply voltage is the initialization voltage Vini, the second power supply voltage is the high potential voltage ELVDD, and the third power supply voltage is the low potential voltage ELVSS. The high-potential voltage ELVDD is a voltage higher than the low-potential voltage ELVSS and the initialization voltage Vini. The high-potential voltage ELVDD, the initialization voltage Vini, and the low-potential voltage ELVSS can be preset to an appropriate level of voltage through a preliminary experiment.

Also, the power source 50 may supply predetermined logic level voltages to the timing controller 40, and may supply the gate-on voltage and the gate-off voltage to the scan driver 30. The gate-on voltage means the turn-on voltage of the switch elements of the pixel P, and the gate-off voltage means the turn-off voltage of the switch elements of the pixel P.

5 is an equivalent circuit diagram showing the pixel of FIG. 4 in detail. 5, a pixel P according to an exemplary embodiment of the present invention includes a driving transistor DT, an organic light emitting diode (OLED), switching elements, a storage capacitor C, And the like. The switch elements include first through sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

The pixel P includes a scan line SLk-1, a k-th scan line SLk, a k-th emission line EMLk, a scan line SLk-1, And j (j is a positive integer satisfying 1? J? M) data line Dj. The pixel P includes a low potential voltage line VSSL to which the low potential voltage ELVSS is supplied, an initialization voltage line ViniL to which the initialization voltage Vini is supplied, And is connected to the upper voltage line VDDL.

The driving transistor DT controls the drain-source current Ids according to the voltage of the gate electrode. The drain-source current Ids flowing through the channel of the driving transistor DT is proportional to the square of the difference between the gate-source voltage and the threshold voltage of the driving transistor DT as shown in Equation (1). The gate electrode of the driving transistor DT is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3. Here, the first electrode may be a source electrode or a drain electrode, and the second electrode may be a different electrode from the first electrode. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode.

The organic light emitting diode OLED emits light in accordance with the drain-source current Ids of the driving transistor DT. The amount of light emission of the organic light emitting diode OLED may be proportional to the drain-source current Ids of the driving transistor DT. The anode electrode of the organic light emitting diode OLED is connected to the second electrode of the fifth transistor ST5 and the first electrode of the sixth transistor ST6 and the cathode electrode thereof is connected to the low potential voltage line VSSL.

The first transistor ST1 is connected between the first node N1 and the third node N3. The first transistor ST1 is turned on by the scan signal of the kth scan line SLk to connect the first node N1 and the third node N3. That is, when the first transistor ST1 is turned on, since the gate electrode of the driving transistor DT is connected to the second electrode, the driving transistor DT is driven by a diode. The gate electrode of the first transistor ST1 is connected to the kth scan line SLk, the first electrode thereof is connected to the third node N3, and the second electrode thereof is connected to the first node N1.

The second transistor ST2 is connected between the second node N2 and the data line DL. The second transistor ST2 is turned on by the scan signal of the kth scan line SLk to connect the second node N2 to the jth data line Dj. As a result, the data voltage of the jth data line Dj is supplied to the second node N2. The gate electrode of the second transistor ST2 is connected to the kth scan line SLk, the first electrode thereof is connected to the jth data line DLj, and the second electrode thereof is connected to the second node N2.

The third transistor ST3 is connected between the first node N1 and the initialization voltage line ViniL. The third transistor ST3 is turned on by the scan signal of the (k-1) th scan line SLk-1 to connect the first node N1 to the initialization voltage line ViniL. As a result, the first node N1 is initialized to the initializing voltage Vini. The gate electrode of the third transistor ST3 is connected to the (k-1) th scan line SLk-1, the first electrode is connected to the first node N1, and the second electrode is connected to the initialization voltage line ViniL Respectively.

The fourth transistor ST4 is connected between the anode electrode of the organic light emitting diode OLED and the initializing voltage line ViniL. The fourth transistor ST4 is turned on by the scan signal of the (k-1) th scan line SLk-1 to connect the anode electrode of the organic light emitting diode OLED with the initialization voltage line ViniL. As a result, the anode electrode of the organic light emitting diode OLED is discharged at the initializing voltage Vini. The gate electrode of the fourth transistor ST4 is connected to the (k-1) th scan line SLk-1, the first electrode of the fourth transistor ST4 is connected to the anode electrode of the organic light emitting diode OLED, ViniL.

The fifth transistor ST5 is connected between the high potential voltage line VDDL and the second node N2. The fifth transistor ST5 is turned on by the light emitting signal of the kth light emitting line EMLk to connect the second node N2 to the high potential voltage line VDDL. As a result, the high potential ELVDD is supplied to the second node N2. The gate electrode of the fifth transistor ST5 is connected to the kth light emitting line EMLk, the first electrode thereof is connected to the high potential voltage line VDDL and the second electrode thereof is connected to the second node N2.

The sixth transistor ST6 is connected between the third node N3 and the anode electrode of the organic light emitting diode OLED. The sixth transistor ST6 is turned on by the emission signal of the kth emission line EMLk to connect the third node N3 to the anode electrode of the organic light emitting diode OLED. The gate electrode of the sixth transistor ST6 is connected to the kth light emitting line EMLk and the first electrode thereof is connected to the third node N3 and the second electrode thereof is connected to the anode electrode of the organic light emitting diode OLED do. The drain-source current Ids of the driving transistor DT is supplied to the organic light emitting diode OLED by the turn-on of the fifth and sixth transistors T5 and T6.

The storage capacitor C is connected between the first node N1 and the high potential voltage line VDDL to maintain the voltage of the first node N1. One electrode of the storage capacitor C is connected to the first node N1 and the other electrode is connected to the high potential voltage line VDDL.

Also, a parasitic capacitance of the organic light emitting diode OLED may be formed between the anode electrode and the cathode electrode of the organic light emitting diode OELD. A parasitic capacitance PC may be formed between the gate electrode GE of the driving transistor DT and the anode electrode of the organic light emitting diode OLED. The parasitic capacitance PC between the gate electrode GE of the driving transistor DT and the anode electrode of the organic light emitting diode OLED increases as the anode electrode of the organic light emitting diode OLED is driven by the parasitic capacitance PC DT due to the influence of the gate electrode GE. In this case, there may arise a problem that the low potential voltage ELVSS supplied through the low potential voltage line VSSL rises by the parasitic capacitor Coled of the organic light emitting diode OLED. The rise of the low potential voltage (ELVSS) may cause a problem that the color coordinates are shifted. Therefore, the embodiment of the present invention is implemented with a structure that minimizes the size of the parasitic capacitance (PC). A detailed description thereof will be given later with reference to FIGS. 10 to 14. FIG.

The first node N1 may correspond to a gate node connected to the gate electrode of the driving transistor DT. The first node N1 is a contact point of the gate electrode of the driving transistor DT, the second electrode of the first transistor ST1, the first electrode of the third transistor ST3, and one electrode of the capacitor C. And the second node N2 corresponds to the source node connected to the first electrode of the driving transistor DT. The second node N2 is a contact of the first electrode of the driving transistor DT, the second electrode of the second transistor ST2, and the second electrode of the fifth transistor T5. And the third node N3 corresponds to a drain node connected to the second electrode of the driving transistor DT. The third node N3 is a contact point of the second electrode of the driving transistor DT, the first electrode of the first transistor ST1, and the first electrode of the sixth transistor ST6.

The semiconductor layer of each of the first to sixth transistors ST1 to ST6 and the driving transistor DT may be formed of polysilicon, Si, and an oxide semiconductor, particularly, oxide. When the semiconductor layers of the first to sixth transistors ST1 to ST6 and the driving transistor DT are formed of polysilicon, Poly Silicon (LTPS) process.

Although the first through sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 and the driving transistor DT are formed of a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) And may be formed of an N-type MOSFET. When the first to sixth transistors ST1, ST2, ST3, ST4, ST5, ST6 and the driving transistor DT are formed of N-type MOSFETs, the timing diagram of FIG. 6 should be modified something to do.

The high potential voltage ELVDD, the low potential voltage ELVSS and the initialization voltage Vini may be set in consideration of the characteristics of the driving transistor DT and the characteristics of the organic light emitting diode OLED.

6 is a waveform diagram showing signals input to the pixel of FIG. 6 shows a k-th scan line SLk-1 supplied to the (k-1) th scan line SLk-1 of the display panel 10 during the qth (q is a positive integer) 1 scan signal SCANk-1 supplied to the kth scan line SLk and a kth scan signal SCANk supplied to the k scan line SLk and a kth emission signal EMk supplied to the kth emission line EMLk.

Referring to FIG. 6, the k-1 scan signal SCANk-1 is a signal for controlling the third and fourth transistors ST3 and ST4, and the kth scan signal SCANk is a signal for controlling the first and second transistors ST3 and ST4. (ST1, ST2), and the kth emission signal EMk is a signal for controlling the fifth and sixth transistors ST5, ST6. As shown in FIG. 6, the scan signals and the emission signals are generated at intervals of one frame period.

Each of the scan signals may occur as a gate-on voltage Von during one horizontal period (1H) as shown in FIG. One horizontal period (1H) indicates one horizontal line scanning period in which a data voltage is supplied to each of the pixels P connected to one of the scan lines of the display panel 10. [ The data voltages are supplied to the data lines DL1 to DLm in synchronization with the scan signals.

One frame period may be divided into first to fourth periods t1 to t4. The first period t1 is a period for applying an on bias to the driving transistor DT and the second period t2 is a period for initializing the first node N1 connected to the gate electrode of the driving transistor DT A third period t3 is a period during which a data voltage is supplied and a threshold voltage of the driving transistor DT is sensed and a fourth period t4 is a period during which the organic light emitting diode OLED emits light.

The first k-th scan signal SCANk-1 is generated at the gate-on voltage Von during the first and second periods t1 and t2 and the k-th scan signal SCANk is generated during the third period t3. On voltage (Von). The kth emission signal EMk is generated at the gate-off voltage Voff during the second and third periods t2 and t3. Each of the first to third periods t1, t2 and t3 may be appropriately determined in advance through a preliminary experiment. The gate-on voltage Von corresponds to a turn-on voltage capable of turning on each of the first through sixth transistors ST1, ST2, ST3, ST4, ST5, ST6. The gate-off voltage Voff corresponds to a turn-off voltage capable of turning off each of the first through sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

7 is a flowchart showing the operation of the pixels during the first to fourth periods. 8A to 8D are equivalent circuit diagrams showing pixels during the first to fourth periods. Hereinafter, the operation of the pixel P according to the first exemplary embodiment of the present invention will be described in detail for the first to fourth periods t1 to t4 with reference to Figs. 6, 7, and 8A to 8D.

First, the operation of the pixel P during the first period t1 for applying the on-bias to the driving transistor DT will be described. During the first period t1, the (k-1) th scan signal SCANk-1 having the gate-on voltage Von is supplied to the pixel P through the (k-1) th scan line SLk- And the k-th emission signal EMk having the gate-on voltage Von is supplied through the k-th emission line EMLk.

8A, during the first period t1, the third and fourth transistors ST3 and ST4 are turned on by the k-1 scan signal SCANk-1 of the (k-1) th scan line SLk-1 Turn on. The fifth and sixth transistors ST5 and ST6 are turned on by the kth emission signal EMk of the kth emission line EMLk.

Due to the turn-on of the third transistor ST3, the first node N1 is initialized to the initializing voltage Vini. Further, due to the turn-on of the fourth, fifth and sixth transistors ST4, ST5 and ST6, the high-potential voltage line VDDL, the fifth transistor ST5, the driving transistor DT, ST6), the fourth transistor ST4, and the initialization voltage line ViniL. Specifically, the drain-source current Ids of the driving transistor DT flows in accordance with "Vini-ELVDD" which is the gate-source voltage Vgs of the driving transistor DT.

As described above, the embodiment of the present invention discharges the gate electrode of the driving transistor DT to the initializing voltage Vini during the first period t1 to apply the ON bias to the driving transistor DT. As a result, the first embodiment of the present invention can apply a predetermined on-bias to the driving transistor DT before the third period t3 for supplying the data voltage, so that the hysteresis characteristic of the driving transistor DT It is possible to solve the problem that the image quality deteriorates. A detailed description thereof will be given later with reference to FIG. (S101 in Fig. 7)

Secondly, the operation of the pixel P during the second period t2 for initializing the first node N1 connected to the gate electrode of the driving transistor DT will be described. During the second period t2, the (k-1) th scan signal SCANk-1 having the gate-on voltage Von through the (k-1) th scan line SLk-1 is supplied to the pixel P do.

8B, the third and fourth transistors ST3 and ST4 are turned on by the k-1 scan signal SCANk-1 of the (k-1) th scan line SLk-1 during the second period t2 Turn on.

Due to the turn-on of the third transistor ST3, the first node N1 is initialized to the initializing voltage Vini. Due to the turn-on of the fourth transistor ST4, the anode electrode of the organic light emitting diode OLED is initialized to the initializing voltage Vini. In order to prevent the light emission of the organic light emitting diode OLED during the second period t2, the initialization voltage Vini may be set to a level substantially equal to the low potential voltage ELVSS. (S102 in Fig. 7)

Third, the operation of the pixel P during the third period t3 during which the data voltage is supplied and the threshold voltage of the driving transistor DT is sensed will be described. During the third period t3, the pixel P is supplied with the k-th scan signal SCANk having the gate-on voltage Von through the k-th scan line SLk as shown in Fig.

Referring to FIG. 8C, during the third period t3, the first and second transistors ST1 and ST2 are turned on by the kth scan signal SCANk of the kth scan line SLk.

Due to the turn-on of the first transistor ST1, the first node N1 is connected to the third node N3, so that the driving transistor DT is driven by a diode. Due to the turn-on of the second transistor ST2, the data voltage Vdata is supplied to the second node N2. At this time, since the voltage difference (Vgs = Vini-Vdata) between the gate electrode and the first electrode of the driving transistor DT is larger than the threshold voltage Vth, the driving transistor DT has a voltage difference between the gate electrode and the first electrode Vgs) reach the threshold voltage (Vth). As a result, the voltage of the first node N1 rises to the difference voltage (Vdata-Vth) between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT during the third period t3. (S103 in Fig. 7)

Fourth, the operation of the pixel P during the fourth period t4 in which the organic light emitting diode OLED emits light will be described. During the fourth period t4, the pixel P is supplied with the kth emission signal EMk having the gate-on voltage Von through the kth emission line EMLk as shown in Fig.

Referring to FIG. 8D, during the fourth period t4, the fifth and sixth transistors ST5 and ST6 are turned on by the kth emission signal EMk of the kth emission line EMLk.

Due to the turn-on of the fifth transistor ST5, the second node N2 connected to the first electrode of the driving transistor DT is connected to the first power supply voltage line ELVDDL. Due to the turn-on of the sixth transistor ST6, the second electrode of the driving transistor DT is connected to the organic light emitting diode OLED. That is, due to the turn-on of the fifth and sixth TFTs T5 and T6, the driving transistor DT has the drain-source current Ids according to the voltage of the first node N1 connected to its gate electrode, To the organic light emitting diode (OLED). At this time, the first node N1 supplies the difference voltage (Vdata-Vth) between the data voltage Vdata sensed during the third period t3 and the threshold voltage Vth of the driving transistor DT by the capacitor C . The drain-source current Ids of the driving transistor DT can be defined as shown in Equation (2).

Vgs is the gate-source voltage of the driving transistor DT, Vth is the threshold voltage of the driving transistor DT, and ELVDD is the threshold voltage of the driving transistor DT. In the equation (2), k is a proportional coefficient determined by the structure and physical characteristics of the driving transistor DT, Denotes a first power supply voltage, and Vdata denotes a data voltage. The gate voltage Vg of the driving transistor DT is {Vdata-Vth}, and the source voltage Vs is ELVDD. Summarizing the expression (2), the expression (3) is derived.

As a result, the drain-source current Ids of the driving transistor DT does not depend on the threshold voltage Vth of the driving transistor DT as in Equation (3). That is, the threshold voltage Vth of the driving transistor DT is compensated. (S104 in Fig. 7)

As described above, the embodiment of the present invention can compensate the threshold voltage of the driving transistor DT. As a result, since the drain-source current Ids of the driving transistor DT supplied to the organic light emitting diode OLED does not depend on the threshold voltage Vth of the driving transistor, It is possible to make the luminance of the pixels uniform.

9 is a graph showing the luminance of a pixel when the peak black gradation voltage is supplied during the p-frame period and the peak white gradation voltage is supplied during the (p + 1) th to (p + 3) -th frame periods in the embodiment of the present invention. 9, the peak black gradation voltage is supplied to the gate electrode of the driving transistor DT during the p-th frame period, and the peak white gradation voltage (Vs) is applied to the gate electrode of the driving transistor DT during the (p + And the like.

The embodiment of the present invention discharges the gate electrode of the driving transistor DT to the initializing voltage Vini during the first period t1 to apply the on bias to the driving transistor DT. As a result, the embodiment of the present invention can apply the same on bias to the driving transistor DT regardless of the voltage supplied to the gate electrode of the driving transistor DT during the previous frame period. 9, during the first period t1 of the (p + 1) -th frame period, even if the peak black gradation voltage is supplied to the gate electrode of the driving transistor DT during the p-th frame period, The driving transistor DT is in an on-bias state during the (p + 1) -th frame period. As a result, the organic light emitting diode OLED emits light with a peak white luminance during the (p + 1) -th frame period as shown in FIG.

That is, the embodiment of the present invention applies the driving transistor DT to a predetermined on-bias before the third period t3 during which the data voltage is supplied in one frame period. Therefore, the luminance deviation caused by the hysteresis characteristic of the driving transistor TD can be prevented, and the problem of deterioration of image quality can be solved.

10 is a plan view showing the driving transistor and the first transistor of FIG. 5 in detail. 11 is a cross-sectional view taken along line A-A 'in Fig. 10 and 11, the gate electrode GE of the driving transistor DT of the pixel P according to the embodiment of the present invention, the first electrode SO of the first transistor ST1, Connection of the semiconductor layer ACT2 of the first transistor ST1 will be described in detail.

10 and 11, a semiconductor pattern ACT including the semiconductor layer ACT1 of the driving transistor DT and the semiconductor layer ACT2 of the first transistor ST1 is formed on the lower substrate 101 . The semiconductor pattern ACT may be formed on a buffer layer (not shown) of the lower substrate 101. The semiconductor pattern ACT may be formed of polysilicon, but not limited thereto, and may be formed of any one of a-Si and an oxide semiconductor, particularly, oxide.

A gate insulating film GI is formed on the semiconductor pattern ACT. The gate insulating film GI may be formed of silicon nitride (SiNx).

A first gate metal pattern GM1 including the gate electrode GE of the driving transistor DT is formed on the gate insulating film GI. The semiconductor pattern ACT and the first gate metal pattern GM1 are insulated by the gate insulating film GI.

A first interlayer insulating film ILD1 is formed on the first gate metal pattern GM1. The first interlayer insulating film ILD1 may be formed of silicon nitride (SiNx). A second gate metal pattern GM2 including a kth scan line SLk, a gate electrode GE_ST1 of the first transistor ST1, and a horizontal high voltage line H_VDDL is formed on the first interlayer insulating film ILD1 . The first gate metal pattern GM1 and the second gate metal pattern GM2 are insulated by the first interlayer insulating film ILD1.

A second interlayer insulating film ILD2 is formed on the second gate metal pattern GM2. The second interlayer insulating film (ILD2) may be formed in a double layer of silicon nitride (SiNx) / silicon dioxide (SiO _2).

A source / drain metal pattern SDM including a first electrode SO of the first transistor ST1 and a vertical high potential voltage line V_VDDL is formed on the second interlayer insulating film ILD2. The source / drain metal pattern may be formed in a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). The second gate metal pattern GM2 and the source / drain metal pattern SDM are insulated by the second interlayer insulating film ILD2.

The first electrode SO of the first transistor ST1 is connected to the gate electrode GE of the driving transistor DT and the semiconductor layer ACT2 of the first transistor ST1 through the first contact hole CNT1 Respectively. The first contact hole CNT1 penetrates the gate insulating film and the first and second interlayer insulating films ILD1 and ILD2 so that the gate electrode GE of the driving transistor DT and the semiconductor layer ACT2 of the first transistor ST1 ).

The high potential voltage line VDDL includes a horizontal high potential voltage line H_VDDL formed in the horizontal direction (x axis direction) and a vertical high potential voltage line V_VDDL formed in the vertical direction (y axis direction) . The horizontal high potential voltage line H_VDDL may be formed of a second gate metal pattern GM2 while the vertical high potential voltage line V_VDDL may be formed of a source / drain metal pattern SDM. In this case, the horizontal high-potential voltage line H_VDDL and the vertical high-potential voltage line V_VDDL may be connected through a predetermined contact hole. The predetermined contact hole may expose the horizontal high-potential voltage line H_VDDL through the second interlayer insulating film IDL2. The overlapped region between the horizontal high-potential voltage line H_VDDL formed of the second gate metal pattern GM2 and the gate electrode GE of the driving transistor DT formed of the first gate metal pattern GM1 is a storage capacitor C ).

A protective film PAS is formed on the source / drain metal pattern SDM. The passivation layer (PAS) may be formed of polyimide.

An anode electrode pattern (ANDP) including the anode electrode (AND) of the organic light emitting diode (OLED) is formed on the passivation film (PAS). The anode electrode pattern (ANDP) may be formed in a three-layer structure of ITO / Ag / ITO. The source / drain metal pattern SDM and the anode electrode pattern ANDP are insulated by the protective film PAS.

5, 6, 10 and 11, during the second and third periods t2 and t3 during which the anode electrode (AND) of the organic light emitting diode OLED is floated, the organic light emitting diode (OLED) The voltage of the anode electrode AND of the driving transistor DT can be increased due to the influence of the gate electrode GE of the driving transistor DT by the parasitic capacitance PC. In this case, there may arise a problem that the low potential voltage ELVSS supplied through the low potential voltage line VSSL rises by the parasitic capacitor Coled of the organic light emitting diode OLED. The rise of the low potential voltage (ELVSS) may cause a problem that the color coordinates are shifted. In order to prevent this, the parasitic capacitance PC formed between the gate electrode GE of the driving transistor DT and the anode electrode of the organic light emitting diode OLED must be minimized.

10 and 11, the driving transistor DT may be formed to prevent the first electrode SO of the first transistor ST1 from overlapping with the anode electrode of the organic light emitting diode OLED. The gate electrode GE of the first transistor ST1 is extended to overlap the semiconductor layer ACT2 of the first transistor ST1 and is connected to the first electrode SO of the first transistor ST1. Therefore, the parasitic capacitance PC is formed in the overlapping region between the anode electrode AND of the organic light emitting diode OLED and the gate electrode GE of the driving transistor DT. The reason why the first electrode SO of the first transistor ST1 is not overlapped with the anode electrode of the organic light emitting diode OLED is that the first electrode SO of the first transistor ST1 is connected to the organic light emitting diode OLED. (AND) of the organic light emitting diode (OLED), the parasitic capacitance PC is formed in the overlapping region between them. The distance between the first electrode SO of the first transistor ST1 and the anode electrode of the organic light emitting diode OLED is smaller than the distance between the anode electrode of the organic light emitting diode OLED and the first electrode Of the parasitic capacitance PC formed in the overlapping region between the first electrode SO of the first transistor ST1 and the anode electrode of the organic light emitting diode OLED, Is larger than the parasitic capacitance PC formed in the overlapping region between the anode electrode (AND) of the organic light emitting diode (OLED) and the first gate electrode (GE1) of the driving transistor (DT).

That is, the embodiment of the present invention can minimize the size of the parasitic capacitance PC formed between the anode electrode of the organic light emitting diode OLED and the gate electrode GE of the driving transistor DT. As a result, in the embodiment of the present invention, the parasitic capacitance PC formed between the anode electrode of the organic light emitting diode OLED and the gate electrode GE of the driving transistor DT causes the anode electrode of the organic light emitting diode OLED Can be minimized. Therefore, the embodiment of the present invention can prevent the color coordinate shift due to the rise of the low potential voltage (ELVSS), thereby preventing the deterioration of image quality.

12 is another plan view showing the driving transistor and the first transistor of FIG. 5 in detail. 13 is an exemplary view showing a cross section taken along the line B-B 'in FIG.

12 is substantially the same as the cross section shown in Fig. 11, except that the kth scan line SLk in Fig. 11 is changed to the second island pattern IP2. Therefore, a detailed description of the section taken along the line A-A 'in FIG. 12 will be omitted.

Hereinafter, the cross section taken along the line B-B 'in FIG. 12 will be described in detail with reference to FIG. 12 and FIG.

12, the gate electrode GE of the driving transistor DT is extended so as to overlap with the active layer ACT2 of the first transistor ST1, so that the gate electrode GE of the driving transistor DT And the parasitic capacitance PC between the anode electrode of the organic light emitting diode OLED and the organic light emitting diode OLED is minimized. 10, in order to avoid a short circuit between the gate electrode GE and the kth scan line SLk of the driving transistor DT, the kth scan line SLk and the gate electrode GE1_ST1 of the first transistor ST1 2 gate metal pattern GM2. However, in FIG. 12, the kth scan line SLk and the gate electrode GE1_ST1 of the first transistor ST1 are formed of the first gate metal pattern GM1. Therefore, means for avoiding a short circuit between the gate electrode GE of the driving transistor DT and the kth scan line SLk must be provided.

12 and 13, the kth scan line SLk is connected to the first island pattern IP1 through the second contact hole CNT2. The first island pattern IP1 may be formed on both sides of the gate electrode GE of the driving transistor DT. It should be noted that the first island patterns IP1 are preferably formed by a source / drain metal pattern SDM, but are not limited thereto. When the first island patterns IP1 are formed of the source / drain metal pattern SDM, the second contact hole CNT2 passes through the first and second interlayer insulating films IDL1 and IDL2, SLk).

Each of the first island pattern IP1 is connected to the second island pattern IP2 via the third contact hole CNT3. It should be noted that the second island pattern IP2 is preferably formed of the second gate metal pattern GM2, but is not limited thereto. When the second island pattern IP2 is formed of the second gate metal pattern GM2, the third contact hole CNT3 penetrates the second interlayer insulating film IDL2 to expose the second island pattern IP2. In this case, the second island pattern IP2 intersects the gate electrode GE of the driving transistor DT at the upper portion of the gate electrode GE of the driving transistor DT as shown in Figs.

As a result, the embodiment of the present invention connects the kth scan line to the first island pattern IP1, connects each of the first island patterns IP1 to the second island pattern IP2, The gate electrode GE of the driving transistor DT and the second island pattern IP2 are crossed over the gate electrode GE of the second transistor Tr2. As a result, even if the gate electrode GE and the kth scan line SLk of the driving transistor DT are formed of the first gate metal pattern GM1, GE) and the kth scan line (SLk) can be avoided.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 20: data driver
30: scan driver 40: timing controller
OLED: organic light emitting diode DT: driving transistor
ST1: first transistor ST2: second transistor
ST3: third transistor ST4: fourth transistor
ST5: fifth transistor ST6: sixth transistor
C: capacitor N1: first node
N2: second node N3: third node

Claims (15)

And a display panel in which data lines and scan lines are formed and pixels arranged in a matrix form are formed,
Each of the pixels includes:
A driving transistor having a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node;
An organic light emitting diode emitting light according to a drain-source current of the driving transistor; And
And a first transistor connected between the first node and the third node,
Wherein a gate electrode of the driving transistor overlaps with a semiconductor layer of the first transistor. The method according to claim 1,
And the gate electrode of the driving transistor is connected to the first electrode of the first transistor through the first contact hole. 3. The method of claim 2,
Wherein the first electrode of the first transistor is connected to the semiconductor layer of the first transistor through the first contact hole. The method of claim 3,
Wherein the first contact hole is formed through a plurality of insulating films. The method of claim 3,
Wherein the first electrode of the first transistor is not overlapped with the anode electrode of the organic light emitting diode. The method of claim 3,
Wherein the gate electrode of the driving transistor overlaps the semiconductor layer of the driving transistor on the semiconductor layer of the driving transistor. The method according to claim 6,
Wherein the gate electrode of the driving transistor is formed of a first gate metal pattern and the gate electrode of the first transistor is formed of a second gate metal pattern formed on the first gate metal pattern. Display device. The method according to claim 6,
Wherein the gate electrode of the driving transistor and the gate electrode of the first transistor are formed of a first gate metal pattern. 9. The method of claim 8,
And the scan line connected to the gate electrode of the first transistor is formed of the first gate metal pattern. 10. The method of claim 9,
The scan line connected to the gate electrode of the first transistor is connected to the first island electrodes via the second contact holes and each of the first island electrodes is connected to the second island electrode through the third contact hole Wherein the organic electroluminescent display device comprises: 11. The method of claim 10,
The first island electrodes are formed in a source / drain metal pattern,
And the second island electrode is formed of a second gate metal pattern. 11. The method of claim 10,
And the second island electrode intersects the gate electrode of the driving transistor at an upper portion of the gate electrode of the driving transistor. The method according to claim 1,
The display panel further includes light emission lines arranged in parallel with the scan lines,
Each of the pixels includes:
A second transistor that is turned on by a scan signal of a k-th scan line (k is a positive integer equal to or greater than two) to connect a j-th (j is a positive integer) data line to the second node;
A third transistor connected to the first node and a first power supply voltage line supplied with a first power supply voltage, the third transistor being turned on by a scan signal of a (k-1) th scan line;
A fourth transistor that is turned on by a scan signal of the (k-1) th scan line and connects the anode electrode of the organic light emitting diode with the first power supply voltage line;
A fifth transistor connected between the second node and a second power supply voltage line supplied with a second power supply voltage, the fifth transistor being turned on by an emission signal of the kth emission line;
A sixth transistor connected between the third node and the anode electrode of the organic light emitting diode, the sixth transistor being turned on by the light emitting signal of the kth light emitting line; And
And a capacitor connected between the first node and the second power supply voltage line. 14. The method of claim 13,
And the first transistor is turned on by a scan signal of the kth scan line to connect the first node and the third node. 15. The method of claim 14,
A scan signal of the (k-1) th scan line is generated at a gate-on voltage during the first and second periods,
The scan signal of the k < th > scan line is generated as a gate-on voltage during a third period,
And the emission signal of the k-th emission line is generated as a gate-on voltage during the first and fourth periods.

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