KR20130058507A - Organic light emitting diode display device - Google Patents

Abstract

PURPOSE: An organic light emitting diode display device is provided to compensate a threshold voltage of a driving TFT. CONSTITUTION: A high potential voltage source(VDD_S) supplies a DC high potential voltage(VDD) in consideration of a characteristic of a driving TFT(DT) and a characteristic of an organic light emitting diode(OLED). A low potential voltage source(VSS_S) supplies a DC low potential voltage. A reference voltage source(REF_S) supplies reference voltage for initializing first and third nodes(N1,N3). An initialization voltage source(Vini_S) supplies an initialization voltage for initializing a second node(N2). Voltage difference(REF-Vini) between the reference voltage and initialization voltage is set to voltage greater than threshold voltage of the driving TFT for sensing the threshold voltage of the driving TFT.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display device capable of compensating the threshold voltage of a driving TFT.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) have been used . Among these flat panel display devices, organic light emitting diode display devices are capable of low voltage driving, are thin, have excellent viewing angles, and have a high response speed. An active matrix type organic light emitting diode display device in which a plurality of pixels are arranged in a matrix form to display an image is widely used in organic light emitting diode display devices.

The display panel of the active matrix type organic light emitting diode display includes a plurality of pixels arranged in a matrix form. Each of the pixels supplies a current to the organic light emitting diode according to a scan thin film transistor (TFT) that supplies the data voltage of the data line in response to the scan signal of the scan line and the data voltage supplied to the gate electrode. It includes a driving TFT for adjusting the amount of. In this case, the drain-source current Ids of the driving TFT supplied to the organic light emitting diode may be expressed by Equation 1 below.

In Equation 1, k 'is a proportional coefficient determined by the structure and physical characteristics of the driving TFT, Vgs is a gate-source voltage of the driving TFT, and Vth is a threshold voltage of the driving TFT.

On the other hand, due to the shift of the threshold voltage Vth due to the deterioration of the driving TFT, the threshold voltage Vth of the driving TFT of each of the pixels may have different values. In this case, the drain-source current Ids of the driving TFT depends on the threshold voltage Vth of the driving TFT. Different. Therefore, even if the same data voltage is supplied to each of the pixels, a problem arises in that the luminance of light emitted from the organic light emitting diode of each of the pixels is changed. In order to solve this problem, various types of pixel structures for compensating the threshold voltage Vth of the driving TFT have been proposed.

1 is a circuit diagram illustrating a part of a conventional threshold voltage compensation pixel structure. 1 shows a driving TFT DT for supplying current to an organic light emitting diode and a switching TFT ST connected to a source node Ns of the driving TFT DT. The switching TFT ST connects the source node Ns of the driving TFT DT to an initialization voltage source for supplying the initialization voltage Vini during the initialization period of the driving TFT DT. Therefore, the source node Ns is discharged to the initialization voltage Vini during the initialization period. In FIG. 1, the driving TFT DT and the switching TFT ST are described as being implemented with an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

Meanwhile, in the conventional threshold voltage compensation pixel structure, a current pass Ipass is formed from the high potential voltage source supplying the high potential voltage to the initialization voltage source due to the turning-on of the switching TFT ST during the initialization period as shown in FIG. 1. do. That is, since an unnecessary current path is formed during the initialization period, a problem arises in that power consumption for driving the display panel increases. In addition, since the current pass Ipass is formed from the high potential voltage source to the initialization voltage source during the initialization period, the initialization voltage Vini may drop. In this case, since the source node Ns of the driving TFT DT is initialized to a voltage lower than the initialization voltage Vini during the initialization period, a problem may occur in the reliability of pixel driving.

The present invention provides an organic light emitting diode display that can compensate for the threshold voltage of a driving TFT and reduce power consumption.

An organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel on which data lines, scan lines, light emitting lines, sensing lines, and first and second initialization lines are formed, and a plurality of pixels formed in a matrix form. Each of the pixels includes: a driving TFT having a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to a high potential voltage source supplying a high potential voltage; An organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode connected to a low potential voltage source for supplying a low potential voltage; A first capacitor connected between the second node and a third node; A second capacitor having one electrode connected to the high potential voltage source; A first TFT connecting the second node and a reference voltage source for supplying a reference voltage in response to a first initialization signal through the first initialization line; A second TFT connecting an initialization voltage source for supplying an initialization voltage to a third node in response to a first initialization signal supplied through the first initialization line; A third TFT connecting the reference voltage source and a third node in response to a second initialization signal supplied through the second initialization line; A fourth TFT connecting the initialization voltage source and the second node in response to a second initialization signal supplied through the second initialization line; A fifth TFT connecting the first node and a third node in response to a light emission signal supplied through the light emission line; A sixth TFT connecting the other electrode of the second capacitor and the third node in response to a sensing signal supplied through the sensing line; And a seventh TFT connecting the data line and a third node in response to a scan signal supplied through the scan line.

The present invention interrupts the current path from the high potential voltage source to the initialization voltage source during the initialization period. As a result, the present invention can eliminate unnecessary current paths during the initialization period, thereby reducing power consumption for driving the display panel. In addition, the present invention can prevent the voltage drop of the initialization voltage source during the initialization period.

In addition, the present invention minimizes the number of switching TFTs connected to the gate node of the driving TFT. As a result, the present invention can reduce the influence that the gate node of the driving TFT is affected by the parasitic capacitance of the switching TFT, thereby reducing the error of the threshold voltage of the driving TFT reflected in the gate node of the driving TFT. For this reason, the present invention can improve the threshold voltage compensation interval of the driving TFT.

1 is a circuit diagram illustrating a part of a conventional threshold voltage compensation pixel structure.
2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
3 is a waveform diagram showing signals input to a pixel;
4 is a table showing a change in voltage of nodes of a pixel.
5 is a graph showing an error according to threshold voltages of gray level TFTs.
6 is a block diagram schematically illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

2 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention. Referring to FIG. 2, a pixel P according to an embodiment of the present invention includes a driving thin film transistor (TFT), an organic light emitting diode (OLED), a control circuit, and capacitors. Include.

The driving TFT DT controls the amount of the drain-source current Ids differently according to the amount of voltage applied to the gate electrode. The gate electrode of the driving TFT DT is connected to the first node N1, the source electrode is connected to the second node N2, and the drain electrode is a high potential voltage source VDD_S that supplies a high potential voltage VDD. Is connected to.

The organic light emitting diode OLED emits light according to the drain-source current Ids of the driving TFT DT. The anode electrode of the organic light emitting diode OLED is connected to the second node N2, and the cathode electrode is connected to the low potential voltage source VSS_S which supplies the low potential voltage VSS.

The control circuit includes first to seventh TFTs (T1, T2, T3, T4, T5, T6, T7). The first TFT T1 supplies a reference voltage source REF_S and a second supplying the reference voltage REF in response to the first initialization signal INI1 of the gate high voltage VGH supplied from the first initialization line IL1. The node N2 is connected. The gate electrode of the first TFT T1 is connected to the first initialization line IL1, the source electrode is connected to the reference voltage source REF_S, and the drain electrode is connected to the second node N2.

The second TFT T2 and the initialization voltage source Vini_S and the third supplying the initialization voltage Vini in response to the first initialization signal INI1 of the gate high voltage VGH supplied from the first initialization line IL1. The node N3 is connected. The gate electrode of the second TFT T2 is connected to the first initialization line IL1, the source electrode is connected to the initialization voltage source Vini_S, and the drain electrode is connected to the third node N3.

The third TFT T3 connects the reference voltage source REF_S and the third node N3 in response to the second initialization signal INI2 of the gate high voltage VGH supplied from the second initialization line IL2. The gate electrode of the third TFT T3 is connected to the second initialization line IL2, the source electrode is connected to the reference voltage source REF_S, and the drain electrode is connected to the third node N3.

The fourth TFT T4 connects the initialization voltage source Vini_S and the second node N2 in response to the second initialization signal INI2 of the gate high voltage VGH supplied from the second initialization line IL2. The gate electrode of the fourth TFT T4 is connected to the second initialization line IL2, the source electrode is connected to the initialization voltage source Vini_S, and the drain electrode is connected to the second node N2.

The fifth TFT T5 connects the first node N1 and the third node N3 in response to the light emission signal EM of the gate high voltage VGH supplied from the light emission line EML. The gate electrode of the fifth TFT T5 is connected to the light emitting line EML, the source electrode is connected to the first node N1, and the drain electrode is connected to the third node N3.

The sixth TFT T6 connects the second capacitor C2 and the third node N3 in response to the sensing signal SEN of the gate high voltage VGH supplied from the sensing line SENL. The gate electrode of the sixth TFT T6 is connected to the sensing line SENL, the source electrode is connected to the third node N3, and the drain electrode is connected to one electrode of the second capacitor C2.

The seventh TFT T7 is the data line DL and the third node N3 to which the data voltage DATA is supplied in response to the scan signal SCAN of the gate high voltage VGH supplied from the scan line SL. Connect it. The gate electrode of the seventh TFT T7 is connected to the scan line SL, the source electrode is connected to the third node N3, and the drain electrode is connected to the data line DL.

The first capacitor C1 is connected between the second node N2 and the third node N3, and stores the difference voltage between the second node N2 and the third node N3. One electrode of the first capacitor C1 is connected to the second node N2, and the other electrode is connected to the third node N3. The second capacitor C2 is connected between the drain electrode of the sixth TFT T6 and the high potential voltage source VDD_S, and stores the difference voltage between the drain electrode of the sixth TFT T6 and the high potential voltage source VDD_S. . One electrode of the second capacitor C2 is connected to the drain electrode of the sixth TFT T6, and the other electrode is connected to the high potential voltage source VDD_S.

The first node N1 is a contact between the gate electrode of the driving TFT DT and the source electrode of the fifth TFT T5. The second node N2 includes a source electrode of the driving TFT DT, an anode electrode of the organic light emitting diode OLED, a drain electrode of the first TFT T1, a drain electrode of the fourth TFT T4, and a first capacitor. It is a contact between one electrode of (C1). The third node N3 includes the drain electrode of the second TFT T2, the drain electrode of the third TFT T3, the drain electrode of the fifth TFT T5, the source electrode of the sixth TFT T6, and the seventh TFT. It is a contact point between the source electrode of T7 and the other electrode of the first capacitor C1.

The semiconductor layers of the first to fourth TFTs T1, T2, T3, and T4 and the driving TFT DT may be formed of any one of a-Si, Poly-Si, and oxide. In addition, although the first to fourth TFTs (T1, T2, T3, and T4) and the driving TFT (DT) are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in the embodiment of the present invention, The present invention is not limited thereto and may be implemented as a P-type MOSFET.

In consideration of the characteristics of the driving TFT DT and the characteristics of the organic light emitting diode OLED, the high potential voltage source VDD_S is set to supply a DC high potential voltage VDD, and the low potential voltage source VSS_S is a DC low potential. It can be set to supply the voltage VSS. The reference voltage source REF_S supplies the reference voltage REF to initialize the first and third nodes N1 and N3, and the initialization voltage source Vini_S supplies the initialization voltage Vini to initialize the second node N2. ). In order to sense the threshold voltage Vth of the driving TFT DT, the difference voltage REF-Vini of the reference voltage REF and the initialization voltage Vini is higher than the threshold voltage Vth of the driving TFT DT. Can be set.

3 is a waveform diagram illustrating changes in voltages of signals and nodes input to a pixel. 3, the first and second initialization signals INI1 and INI2, the light emission signal EM, the sensing signal SEN, and the scan input to the display panel 10 during the first to fifth periods t1 to t5. The signal SCAN and the nth (n is a natural number) data voltage DATAn are shown. The first period t1 is a first initialization period, the second period t2 is a second initialization period, and the third period t3 is a period for sensing the threshold voltage of the driving TFT DT, and the fourth period. (t4) is a data voltage supply period, and the fifth period t5 is an organic light emitting diode (OLED) emission period. The fifth period t5 is divided into an A period t5-A and a B period t5-B.

Referring to FIG. 3, the first and second initialization signals INI1 and INI2, the emission signal EM, the sensing signal SEN, and the scan signal SCAN may include first to seventh TFTs of the pixel P ( Signals for controlling T1, T2, T3, T4, T5, T6, and T7). The first and second initialization signals INI1 and INI2, the emission signal EM, the sensing signal SEN, and the scan signal SCAN are generated in one frame period. The data voltage DATA is generated at one horizontal period 1H, and FIG. 3 illustrates only the nth data voltage DATAn supplied during the fourth period t4 for convenience of description. One horizontal period means one line scanning time in which data is written in the pixels P of one horizontal line in the display panel 10.

The first initialization signal INI1 is generated at the gate high voltage VGH during the first period t1 and is generated at the gate low voltage VGL during the second to fifth periods t2, t3, t4, and t5. . The second initialization signal INI2 is generated at the gate high voltage VGH during the second period t2, and the gate low voltage VGL during the first and third to fifth periods t1, t3, t4, and t5. Occurs as The light emission signal EM is generated at the gate high voltage VGH during the A periods t1, t3, and t5-A of the first and third periods and the fifth period, and is generated from the second and fourth periods and the fifth period. It occurs at the gate low voltage VGL during the B periods t2, t4, and t5-B. The sensing signal SEN is generated at the gate high voltage VGH during the first to third periods t1, t2, and t3, and is generated at the gate low voltage VGL during the fourth and fifth periods t4 and t5. do. The scan signal SCAN is generated at the gate high voltage VGH during the fourth period t4 and at the gate low voltage VGL during the first to third and fifth periods t1, t2, t3, and t5. Occurs. The gate high voltage VGH may be set between approximately 14V and 20V, and the gate low voltage VGL may be set between approximately −12V and −5V.

4 is a table illustrating a change in voltage of nodes of a pixel. Hereinafter, the operation of the pixel P during the first to fifth periods t1, t2, t3, t4, and t5 will be described in detail with reference to FIGS. 2 to 4.

The first period t1 is a first initialization period, the second period t2 is a second initialization period, and the third period t3 is a period for sensing the threshold voltage of the driving TFT DT, and the fourth period. (t4) is a data voltage supply period, and the fifth period t5 is an organic light emitting diode (OLED) emission period. The fifth period t5 is divided into an A period t5-A and a B period t5-B. The second period t2 is continuous to the first period t1, the third period t3 is continuous to the second period t2, and the fourth period t4 is continuous to the third period t3. The fifth period t5 is continuous to the fourth period t4.

First, during the first period t1, the first initialization signal INI1 of the gate high voltage VGH is supplied through the first initialization line IL1, and the second initialization signal of the gate low voltage VGL ( INI2 is supplied through the second initialization line IL2. In addition, the emission signal EM of the gate high voltage VGH is supplied through the emission line EML during the first period t1, and the sensing signal SEN of the gate high voltage VGH is applied to the sensing line SENL. The scan signal SCAN of the gate low voltage VGL is supplied through the scan line SL.

The first TFT T1 is turned on in response to the first initialization signal INI1 of the gate high voltage VGH to connect the reference voltage source REF_S and the second node N2. The second TFT T2 is turned on in response to the first initialization signal INI1 of the gate high voltage VGH to connect the initialization voltage source Vini_S to the third node N3. The third TFT T3 is turned off by the second initialization signal INI2 of the gate low voltage VGL. The fourth TFT T4 is turned off by the second initialization signal INI2 of the gate low voltage VGL. The fifth TFT T5 is turned on in response to the light emission signal EM of the gate high voltage VGH to connect the first node N1 and the third node N3. The sixth TFT T6 is turned on in response to the sensing signal SEN of the gate high voltage VGH to connect the second capacitor C2 and the third node N3. The seventh TFT T7 is turned off by the scan signal SCAN of the gate low voltage VGL.

Due to the turn-on of the first TFT T1 and the turn-off of the fourth TFT T4, the second node N2 has a potential of the reference voltage REF. Due to the turn-on of the second TFT T2, the turn-off of the third TFT T3, and the turn-off of the seventh TFT T7, the third node N3 may change the potential of the initialization voltage Vini. Have Due to the turn-on of the fifth TFT T5, the first node N1 has a potential of the initialization voltage Vini. As a result, the first node N1 connected to the gate electrode of the driving TFT DT is discharged to the initialization voltage Vini, and the second node N2 connected to the source electrode is discharged to the reference voltage REF. In this case, when the driving TFT DT is turned on, since a current path is formed from the high potential voltage source VDD_S to the reference voltage source REF_S, power consumption increases due to unnecessary current paths. To prevent this, it is necessary to turn off the driving TFT DT by setting the difference voltage between the gate electrode and the source electrode of the driving TFT DT to be lower than the threshold voltage Vth. Therefore, the difference voltage Vini-REF between the initialization voltage Vini and the reference voltage REF is set lower than the threshold voltage Vth of the driving TFT DT.

Secondly, the first initialization signal INI1 of the gate low voltage VGL is supplied through the first initialization line IL1 during the second period t2, and the second initialization signal of the gate high voltage VGH is applied. INI2 is supplied through the second initialization line IL2. In addition, the emission signal EM of the gate low voltage VGL is supplied through the emission line EML during the second period t2, and the sensing signal SEN of the gate high voltage VGH is applied to the sensing line SENL. The scan signal SCAN of the gate low voltage VGL is supplied through the scan line SL.

The first TFT T1 is turned off by the first initialization signal INI1 of the gate low voltage VGL. The second TFT T2 is turned off by the first initialization signal INI1 of the gate low voltage VGL. The third TFT T3 is turned on in response to the second initialization signal INI2 of the gate high voltage VGH to connect the reference voltage source REF_S and the third node N3. The fourth TFT T4 is turned on in response to the second initialization signal INI2 of the gate high voltage VGH to connect the initialization voltage source Vini_S and the second node N2. The fifth TFT T5 is turned off by the light emission signal EM of the gate low voltage VGL. The sixth TFT T6 is turned on in response to the sensing signal SEN of the gate high voltage VGH to connect the second capacitor C2 and the third node N3. The seventh TFT T7 is turned off by the scan signal SCAN of the gate low voltage VGL.

Due to the turn-off of the first TFT T1 and the turn-on of the fourth TFT T4, the second node N2 has a potential of the initialization voltage Vini. Due to the turn-off of the second TFT T2, the turn-on of the third TFT T3, and the turn-off of the seventh TFT T7, the third node N3 reduces the potential of the reference voltage REF. Have Due to the turn-off of the fifth TFT T5, the first node N1 is floating and has a potential of the initialization voltage Vini supplied for approximately the first period t1. As a result, since the difference voltage between the gate electrode and the source electrode of the driving TFT DT is lower than the threshold voltage Vth of the driving TFT DT, the driving TFT DT is turned off. That is, due to the turn-off of the driving TFT DT, the current path from the high potential voltage source VDD_S to the initialization voltage source Vini is blocked for the second period t2. Therefore, since unnecessary current paths can be deleted during the second period t2, power consumption for driving the display panel can be reduced. In addition, the voltage drop of the initialization voltage source Vini_S may be prevented during the second period t2.

Third, the first initialization signal INI1 of the gate low voltage VGL is supplied through the first initialization line IL1 during the third period t3, and the second initialization signal of the gate low voltage VGL is applied. INI2 is supplied through the second initialization line IL2. In addition, the emission signal EM of the gate high voltage VGH is supplied through the emission line EML during the third period t3, and the sensing signal SEN of the gate high voltage VGH is applied to the sensing line SENL. The scan signal SCAN of the gate low voltage VGL is supplied through the scan line SL.

The first and second TFTs T1 and T2 are turned off by the first initialization signal INI1 of the gate low voltage VGL. The third and fourth TFTs T3 and T4 are turned off by the second initialization signal INI2 of the gate low voltage VGL. The fifth TFT T5 is turned on in response to the light emission signal EM of the gate high voltage VGH to connect the first node N1 and the third node N3. The sixth TFT T6 is turned on in response to the sensing signal SEN of the gate high voltage VGH to connect the second capacitor C2 and the third node N3. The seventh TFT T7 is turned off by the scan signal SCAN of the gate low voltage VGL.

Due to the turn-off of the first and fourth TFTs T1 and T4, the second node N2 is floated. Due to the turn-off of the second, third, and seventh TFTs T2, T3, and T7, the third node N3 is floated, and the reference voltages are formed by the first and second capacitors C1, C2. REF). Due to the turn-on of the fifth TFT T5, the first node N1 is floated at a potential substantially equal to the third node N3. As a result, the voltage difference Vgs between the first node N1 connected to the gate electrode of the driving TFT DT and the second node N2 connected to the source electrode is larger than the threshold voltage Vth. DT forms a current path until the voltage difference Vgs between the gate electrode and the source electrode reaches the threshold voltage Vth. Accordingly, the voltage of the second node N2 becomes the difference voltage REF-Vth between the reference voltage REF and the threshold voltage Vth of the driving TFT DT. That is, during the second period t2, the second node N2 senses the threshold voltage Vth of the driving TFT DT.

Meanwhile, the voltage change amount of the second node N2 may be reflected in the first node N1 by the first capacitor C1 during the second period t2. However, since the first and second capacitors C1 and C2 are connected in series, the second node (1) reflected by the first node N1 by adjusting the capacity of each of the first and second capacitors C1 and C2 ( The degree of the voltage change amount of N2) can be adjusted.

Fourth, the first initialization signal INI1 of the gate low voltage VGL is supplied through the first initialization line IL1 during the fourth period t4, and the second initialization signal of the gate low voltage VGL ( INI2 is supplied through the second initialization line IL2. In addition, the emission signal EM of the gate low voltage VGL is supplied through the emission line EML during the fourth period t4, and the sensing signal SEN of the gate low voltage VGL is applied to the sensing line SENL. The scan signal SCAN of the gate high voltage VGH is supplied through the scan line SL.

The first and second TFTs T1 and T2 are turned off by the first initialization signal INI1 of the gate low voltage VGL. The third and fourth TFTs T3 and T4 are turned off by the second initialization signal INI2 of the gate low voltage VGL. The fifth TFT T5 is turned off by the light emission signal EM of the gate low voltage VGL. The sixth TFT T6 is turned off by the sensing signal SEN of the gate low voltage VGL. The seventh TFT T7 is turned on in response to the scan signal SCAN of the gate high voltage VGH to connect the first node N1 and the data line DL.

Due to the turn-off of the second and third TFTs T2 and T3 and the turn-on of the seventh TFT T7, the third node N3 has a potential of the nth data voltage DATAn. Due to the turn-off of the fifth TFT T5, the first node N1 is floated and has a potential of the initialization voltage Vini supplied for approximately the first period t1. Therefore, the second node N2 has a potential of approximately the difference voltage REF-Vth between the reference voltage REF and the threshold voltage Vth of the driving TFT DT.

Fifth, the first initialization signal INI1 of the gate low voltage VGL is supplied through the first initialization line IL1 during the fifth period t5, and the second initialization signal of the gate low voltage VGL ( INI2 is supplied through the second initialization line IL2. Further, the light emission signal EM of the gate high voltage VGH is supplied through the light emission line EML during the A period t5-A of the fifth period t5, and the B period (the fifth period t5) During t5-B, the light emission signal EM of the gate low voltage VGL is supplied through the light emission line EML. In addition, the sensing signal SEN of the gate low voltage VGL is supplied through the sensing line SENL during the fifth period t5, and the scan signal SCAN of the gate low voltage VGL is supplied to the scan line SL. Supplied through.

The first and second TFTs T1 and T2 are turned off by the first initialization signal INI1 of the gate low voltage VGL during the fifth period t5. The third and fourth TFTs T3 and T4 are turned off by the second initialization signal INI2 of the gate low voltage VGL during the fifth period t5. The fifth TFT T5 is turned on in response to the light emission signal EM of the gate high voltage VGH during the A period t5-A of the fifth period t5 to be turned on in the first node N1 and the third node. The node N3 is connected and turned off by the light emission signal EM of the gate low voltage VGL during the B period t5-B of the fifth period t5. The sixth TFT T6 is turned off by the sensing signal SEN of the gate low voltage VGL during the fifth period t5. The seventh TFT T7 is turned on in response to the scan signal SCAN of the gate high voltage VGH during the fifth period t5 to connect the first node N1 and the data line DL.

Since the first node N1 and the third node N3 are connected during the A period t5-A of the fifth period t5 due to the turn-on of the fifth TFT T5, the first node N1. Has a potential of the nth data voltage DATAn. On the other hand, when the nth data voltage DATAn is applied to the first node N1 connected to the gate electrode of the driving TFT DT, the second node N2 connected to the source electrode of the driving TFT DT is applied. The voltage may be defined as 'Voled_anode'. In this case, since the first node N1 is floated, the voltage variation of the second node N2 is reflected by the first capacitor C1 to the first node N1. That is, 'REF-Vth-Voled_anode', which is a voltage change amount of the second node N2, is reflected in the first node N1. Therefore, the voltage of the first node N1 is changed to 'DATAn- {REF-Vth-Voled_anode}' during the A period t5-A of the fifth period t5.

Due to the turning-off of the fifth TFT T5 during the B period t5-B of the fifth period t5, the connection of the first node N1 and the third node N3 is cut off and is no longer performed. The amount of change in voltage of the second node N2 is not reflected by the one capacitor C1. During the B period t5-B of the fifth period t5, the drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode OLED is expressed as in Equation (2).

In Equation 2, k 'is a proportional coefficient determined by the structure and physical characteristics of the driving TFT DT, and is determined by the electron mobility, the channel width, the channel length, and the like of the driving TFT DT. Vgs denotes a voltage difference between the gate and source electrodes of the driving TFT DT, and Vth denotes a threshold voltage of the driving TFT DT. 'Vgs-Vth' is expressed by Equation 3 during the B period t5-B of the fifth period t5.

To sum up Equation 3, the drain-source current Ids of the driving TFT DT is derived as in Equation 4.

As a result, the drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode OLED during the B period t5-B of the fifth period t5 is represented by the equation (4). It does not depend on the threshold voltage (Vth) of. That is, the present invention can compensate for the threshold voltage of the driving TFT DT.

On the other hand, only the fifth TFT T5 is connected to the first node N1 connected to the gate electrode of the driving TFT DT. As a result, it is possible to minimize the influence that the first node N1 is affected by the parasitic capacitance of the TFTs other than the driving TFT DT. Therefore, the present invention can reduce the error of the threshold voltage (Vth) of the driving TFT (DT) reflected in the first node (N1), thereby improving the threshold voltage compensation interval of the driving TFT (DT).

5 is a graph showing an error according to threshold voltages of gray level TFTs. Referring to FIG. 5, the threshold voltage Vth of the driving TFT DT and the first to seventh TFTs T1, T2, T3, T4, T5, T6, and T7 is shown on the x axis, and on the y axis. An error of the drain-source current of the driving TFT DT is shown. The threshold voltage Vth of the x-axis is represented by the range of -4V to 10V, and the drain-source current of the driving TFT DT of the y-axis is represented by the range of 70% to 140% based on 100%. The graph of FIG. 5 illustrates that when the drain-source current of the driving TFT DT is set to 100% as a reference value when the threshold voltage Vth is -1V, the drain of the driving TFT DT according to the threshold voltage Vth is shown. Shows the error of current between sources. In particular, the graph of FIG. 5 shows an error of the drain-source current of the driving TFT DT according to the threshold voltage Vth at gray levels of 32, 64, 96, 128, 160, 192, 224, and 256, respectively. shows an error. Here, gray levels are described based on the case of 8 bits data having a value of 0 to 255.

As shown in FIG. 5, the error range of 95% to 105%, which is a ± 5% error range based on 100% at gray levels of 32, 64, 96, 128, 160, 192, 224, and 256, respectively. The threshold voltage Vth of the driving TFT DT and the first to seventh TFTs T1, T2, T3, T4, T5, T6, and T7 within the range of?) Is approximately -2V to 3.3V. That is, when the threshold voltage Vth of the driving TFT DT and the first to seventh TFTs T1, T2, T3, T4, T5, T6, and T7 is approximately −2 V to 3.3 V, almost all gray levels ( At the gray level, the drain-source current of the driving TFT DT has a ± 5% error range. As a result, in the present invention, the threshold voltage Vth compensation range of the driving TFT DT and the first to seventh TFTs T1, T2, T3, T4, T5, T6, and T7 is ± 5% error range. Since it is approximately 5.3V within, there is an advantage that can widen the threshold voltage (Vth) compensation range than the prior art (3 ~ 4V).

6 is a block diagram schematically illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention. Referring to FIG. 6, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 10, a data driver 20, a scan driver 30, a timing controller 40, a host system 50, and the like. It is provided.

The display panel 10 is formed such that the data lines DL and the scan lines SL cross each other. In addition, first and second initialization lines INIL1 and INIL2, sensing lines SEN, and emission lines EML are formed in the display panel 10 in parallel with the scan lines SL. In the display panel 10, pixels P arranged in a matrix form are formed. A detailed description of each of the pixels P of the display panel 10 has been described in detail with reference to FIG. 2.

The data driver 20 includes a plurality of source drive ICs. The source drive ICs receive digital video data RGB from the timing controller 40. The source drive ICs convert the digital video data RGB into a gamma compensation voltage in response to the source timing control signal DCS from the timing controller 40 to generate a data voltage, and convert the data voltage into the scan signal SCAN. The data lines DL of the display panel 10 are supplied to be synchronized with each other.

The scan driver 30 includes a scan signal output unit, first and second initialization signal output units, a sensing signal output unit, and a light emission signal output unit. The scan signal output unit sequentially outputs the scan signal SCAN to the scan lines SL of the display panel 10. The first initialization signal output unit sequentially outputs the first initialization signal INI1 to the first initialization lines INIL1 of the display panel 10. The second initialization signal output unit sequentially outputs the second initialization signal INI2 to the second initialization lines INL2 of the display panel 10. The sensing signal output unit sequentially outputs the sensing signal SEN to the sensing lines SENL of the display panel 10. The emission signal output unit sequentially outputs the emission signal EM to the emission lines EML of the display panel 10. The scan signal SCAN, the first and second initialization signals INI1 and INI2, the sensing signal SEN, and the emission signal EM are described in detail with reference to FIG. 3.

The timing controller 40 receives digital video data (RGB) from the host system 50 through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 40 transmits the digital video data RGB input from the host system 50 to the data driver 20.

The timing controller 40 receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a dot clock, and the like. The timing controller 40 generates timing control signals for controlling the operation timing of the data driver 20 and the scan driver 30 based on the timing signal from the host system. The timing control signals include a scan timing control signal for controlling the operation timing of the scan driver 30 and a data timing control signal for controlling the operation timing of the data driver 20.

The display panel may further include a power supply unit (not shown). The power supply unit includes a high potential voltage source VDD_S for supplying a high potential voltage VDD to the display panel 10, a low potential voltage source VSS_S for supplying a low potential voltage VSS, and a reference voltage source for supplying a reference voltage REF. REF_S, and an initialization voltage source Vini_S that supplies an initialization voltage Vini. In addition, the power supply unit supplies the gate high voltage VGH and the gate low voltage VGL to the scan driver 30.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

OLED: organic light emitting diode DT: driving TFT
T1: first TFT T2: second TFT
T3: third TFT T4: fourth TFT
T5: Fifth TFT T6: Sixth TFT
T7: seventh TFT C1: first capacitor
C2: second capacitor N1: first node
N2: second node N3: third node
SCAN: scan signal INI1: first initialization signal
INI2: second initialization signal EM: light emission signal
SEN: sensing signal 10: display panel
20: data driver 30: scan driver
40: timing controller 50: host system

Claims (9)

A display panel including a data line, a scan line, a light emitting line, a sensing line, and first and second initialization lines and a plurality of pixels formed in a matrix form,
Each of the pixels includes:
A driving TFT connected to a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to a high potential voltage source supplying a high potential voltage;
An organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode connected to a low potential voltage source for supplying a low potential voltage;
A first capacitor connected between the second node and a third node;
A second capacitor having one electrode connected to the high potential voltage source;
A first TFT connecting the second node and a reference voltage source for supplying a reference voltage in response to a first initialization signal supplied from the first initialization line;
A second TFT connecting an initialization voltage source for supplying an initialization voltage to a third node in response to a first initialization signal supplied from the first initialization line;
A third TFT connecting the reference voltage source and a third node in response to a second initialization signal supplied from the second initialization line;
A fourth TFT connecting the initialization voltage source and a second node in response to a second initialization signal supplied from the second initialization line;
A fifth TFT connecting the first node and a third node in response to a light emission signal supplied from the light emission line;
A sixth TFT connecting the other electrode of the second capacitor and the third node in response to a sensing signal supplied from the sensing line;
And a seventh TFT connecting the data line and a third node in response to a scan signal supplied from the scan line. The method of claim 1,
During a first period of supplying the initialization voltage to the first and third nodes and the sensing voltage to the second node,
The first initialization signal, the light emission signal, and the sensing signal are generated at a gate high voltage,
And the second initialization signal and the scan signal are generated at a gate low voltage lower than the gate high voltage. 3. The method of claim 2,
Continuous to the first period, during a second period of supplying the initialization voltage to the second node and of supplying the reference voltage to the third node,
The second initialization signal and the sensing signal are generated at the gate high voltage,
And the first initialization signal, the light emission signal, and the scan signal are generated at the gate low voltage. The method of claim 3, wherein
Continuous to the second period, and during the third period of sensing the threshold voltage of the driving TFT,
The emission signal and the sensing signal are generated at the gate high voltage,
And the first and second initialization signals and the scan signal are generated by the gate low voltage. The method of claim 4, wherein
Continuous to the third period, and during a fourth period in which an nth (n is a natural number) data voltage is supplied to the data line,
The scan signal is generated at the gate high voltage,
And the first and second initialization signals, the light emission signal, and the sensing signal are generated at the gate low voltage. The method of claim 5, wherein
The fifth period during which the organic light emitting diode emits light is divided into an A period and a B period,
During the A period of the fifth period, the light emission signal is generated at the gate high voltage, and the first and second initialization signals, the scan signal, and the sensing signal are generated at the gate low voltage.
And the first and second initialization signals, the light emission signal, the scan signal, and the sensing signal are generated at the gate low voltage during the B period of the fifth period. The method of claim 1,
And the difference voltage between the initialization voltage and the reference voltage is smaller than the threshold voltage of the driving TFT. The method of claim 7, wherein
And the difference voltage between the reference voltage and the initialization voltage is greater than the threshold voltage of the driving TFT. The method of claim 1,
A gate electrode of the first TFT is connected to the first initialization line, a source electrode is connected to the reference voltage source, a drain electrode is connected to the second node,
A gate electrode of the second TFT is connected to the first initialization line, a source electrode is connected to the initialization voltage source, a drain electrode is connected to the third node,
A gate electrode of the third TFT is connected to the second initialization line, a source electrode is connected to the reference voltage source, a drain electrode is connected to the third node,
A gate electrode of the fourth TFT is connected to the second initialization line, a source electrode is connected to the initialization voltage source, a drain electrode is connected to the second node,
A gate electrode of the fifth TFT is connected to the light emitting line, a source electrode is connected to the first node, a drain electrode is connected to the third node,
A gate electrode of the sixth TFT is connected to the sensing line, a source electrode is connected to the third node, a drain electrode is connected to the other electrode of the second capacitor,
And the gate electrode of the seventh TFT is connected to the scan line, the source electrode is connected to the third node, and the drain electrode is connected to the data line.

Images