KR20180131149A - Organic light emitting display device - Google Patents

Abstract

According to an embodiment of the present invention, the present invention relates to an organic light emitting display device, capable of preventing a problem in that a driving power line overlap a data line even when a pixel size and a gap between pixels are reduced. A plurality of driving power lines separately include a plurality of line patterns provided at regular intervals in a first direction and electrically connected to each other through a second electrode pattern. According to embodiments of the present invention, the organic light emitting display device does not singly form a driving power line, and connects two line patterns including source/drain patterns in a jumping structure by using an extension pattern of a top metal forming an upper metal layer of a storage capacitor, thereby facilitating a design of a central part of the driving power line, and preventing a problem in that a driving power line overlap a data line even when a pixel size and a gap between pixels are reduced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

One example of the present application relates to an organic light emitting display.

2. Description of the Related Art In recent years, the importance of display devices has been increasing with the development of multimedia. Various types of flat panel display devices such as a liquid crystal display device, a plasma display device, and an organic light emitting display device have been commercialized in response to this. Among the flat panel display devices, organic light emitting display devices are widely used as display devices for notebook computers, televisions, tablet computers, monitors, smart phones, portable display devices, and portable information devices due to their excellent characteristics such as thinness, light weight and low power consumption .

A display panel used in an organic light emitting display includes a thin film transistor (TFT) and a storage capacitor (Cst) as essential components. A pixel circuit constituting one pixel can be realized by using a plurality of thin film transistors and storage capacitors. Further, the organic light emitting display device has a plurality of driving power supply lines for supplying pixel driving power to a plurality of pixels.

The driving power supply lines are arranged for each pixel column. Accordingly, the driving power supply line is disposed adjacent to the data line. As the number of display device pixels increases, the number of pixel columns increases, and the size of the pixels and the interval between pixels decrease. Particularly, when the plastic organic light emitting device (POLED) is used in a high-resolution (UHD) portable terminal, there is a problem that the driving power line is overlapped with the data line and short- do.

An example of the present invention is to provide an OLED display capable of preventing a problem that a driving power supply line overlaps with a data line even if the size of a pixel and the interval between pixels are reduced.

An organic light emitting display according to an exemplary embodiment of the present invention includes a plurality of pixels having a pixel circuit including a driving transistor and a storage capacitor for controlling a current flowing in an organic light emitting diode and an organic light emitting diode, And a plurality of driving power supply lines for supplying the pixel driving power to the plurality of pixels. The storage capacitor of the present application is provided in an overlapping region between a first electrode pattern connected to the gate electrode of the driving transistor and a second electrode pattern connected to the driving power supply line. Each of the plurality of driving power supply lines of the present application includes a plurality of line patterns provided at regular intervals along the first direction and electrically connected to each other through the second electrode pattern.

The organic light emitting display according to the embodiments of the present invention can be applied to a structure in which a driving power supply line is not formed uniformly but a gap between two line patterns formed of a source / Thereby facilitating the design of the driving power supply line at the center and preventing the driving power supply line from being overlapped with the data line even if the pixel size and the interval between the pixels are reduced.

1 is a perspective view showing an application example of an organic light emitting diode display according to an example of the present application.
2 is a block diagram showing an organic light emitting display according to an example of the present application.
3 is a circuit diagram showing a pixel of an organic light emitting display according to an embodiment of the present invention in detail.
FIG. 4 is a waveform diagram illustrating input / output signals and voltages of each pixel of an OLED display according to an exemplary embodiment of the present invention.
5 is a plan view showing an active layer of a pixel of an OLED display according to an example of the present application.
6 is a plan view showing an active layer and a first electrode pattern of a pixel of an OLED display according to an exemplary embodiment of the present invention.
7 is a plan view showing an active layer, a first electrode pattern, and a second electrode pattern of a pixel of the organic light emitting diode display according to an example of the present application.
8 is a plan view showing an active layer, a first electrode pattern, a second electrode pattern, and contact holes of a pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention.
9 is a plan view of a pixel of an OLED display according to an example of the present application.
10 is a sectional view showing II 'in FIG.
11 is a plan view showing in detail a portion A of the pixel circuit according to an example of the present application.
12 is a plan view showing an active layer, a first electrode pattern, and a second electrode pattern of a pixel of an OLED display according to another example of the present application.
13 is a plan view of a pixel of an organic light emitting diode display according to another example of the present application.

Brief Description of the Drawings The advantages and features of the present application, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that this application is not limited to the examples disclosed herein, but may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein, To fully disclose the scope of the invention to those skilled in the art, and this application is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like described in the drawings for describing an example of the present application are illustrative, and thus the present application is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the description of the present application, a detailed description of known related arts will be omitted if it is determined that the gist of the present application may be unnecessarily obscured.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the scope of the present application.

The terms "first horizontal axis direction "," second horizontal axis direction ", and "vertical axis direction" should not be interpreted solely by the geometric relationship in which the relationship between them is vertical, It may mean having a wider directionality in the inside.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

Each of the features of the various embodiments of the present application may be combined or combined with each other partially or entirely, technically various interlocking and driving are possible, and the examples may be independently performed with respect to each other, .

Hereinafter, a preferred example of an electronic apparatus according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to the constituent elements of the drawings, the same constituent elements may have the same sign as possible even if they are displayed on different drawings

1 is a perspective view showing an application example of an organic light emitting diode display according to an example of the present application.

The OLED display according to an exemplary embodiment of the present invention includes a display area DA and a non-display area NDA.

The display area DA is an area for displaying information or representing an image through an image. The display area has a display panel. The display panel includes a thin film transistor (TFT) and a storage capacitor (Cst) as an essential component. A pixel circuit constituting one pixel can be realized by using a plurality of thin film transistors and storage capacitors. Further, the organic light emitting display device has a plurality of driving power supply lines for supplying pixel driving power to a plurality of pixels.

The non-display area NDA is provided outside the display area DA. The non-display area NDA prevents the rim of the display area DA from being broken. The non-display area NDA serves as a housing for determining the shape of the OLED display. 1, the non-display area NDA is formed to be extremely thin at both side edges of the portable terminal, which is the X axis direction of the four corners of the display area, Type portable terminal, and it may be provided relatively thick on the upper and lower portions of the portable terminal in the Y-axis direction.

The OLED display according to an exemplary embodiment of the present invention can be applied to a portable terminal as shown in FIG. However, the present invention is not limited thereto, and the organic light emitting diode display according to an exemplary embodiment of the present invention can be applied to various kinds of electronic apparatuses that display information or display images through images.

2 is a block diagram showing an organic light emitting display according to an example of the present application.

The OLED display includes a display area DA, a control unit 100, a data driving circuit unit 110, and a scan driving circuit unit 120. The control unit 100, the data driving circuit unit 110 and the scan driving circuit unit 120 may be a single driving unit mounted in a region outside the display area DA of the OLED display device, Chip driver-IC.

The display area DA includes a display area and a non-display area provided around the display area. The display area DA is an area where pixels P are provided to display an image. In the display area DA, scan lines SL1 to SLp for supplying scan signals, p is a positive integer of 2 or more, data lines DL1 to DLq for supplying data voltages, q is a positive integer of 2 or more, And driving power supply lines RL1 to RLq for supplying driving power. The data lines DL1 to DLq and the driving power lines RL1 to RLq may intersect the scan lines SL1 to SLp. The data lines DL1 to DLq and the driving power lines RL1 to RLq may be parallel to each other. The display area DA may include a lower substrate on which pixels P are provided and an upper substrate on which an encapsulation function is performed.

Each of the pixels P may be connected to any one of the scan lines SL1 to SLp and one of the data lines DL1 to DLq and the driving power supply lines RL1 to RLq. Each of the pixels P may include an organic light emitting diode (OLED) and a pixel circuit for supplying current to the organic light emitting diode OLED.

The control unit 100 generates digital video data (DATA) for implementing an image in the organic light emitting display and timing signals for controlling timing for driving the organic light emitting display. The timing signal includes a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The control unit 100 uses the timing signals to generate a data control signal DCS for controlling the operation timing of the data driving circuit unit 110 and a scan control signal SCS for controlling the operation timing of the scan driving circuit unit 120 . The control unit 100 outputs the digital video data DATA and the data control signal DCS to the data driving circuit unit 110. The control unit 100 outputs a scan control signal SCS to the scan driving circuit unit 120.

The data driving circuit unit 110 receives the data control signal DCS from the control unit 100. The data driving circuit 110 generates data voltages based on the data control signal DCS. The data driving circuit 110 supplies the data voltages to the data lines DL1 to DLq.

The scan driving circuit 120 receives the scan control signal SCS from the controller 100. The scan driving circuit unit 120 generates scan signals based on the scan control signal SCS. The scan driving circuit unit 120 supplies scan signals to the scan lines SL1 to SLp.

The control unit 100, the data driving circuit unit 110, and the scan driving circuit unit 120 are mounted in an area outside the display area DA of the organic light emitting display device. At this time, the control unit 100, the data driving circuit unit 110, and the scan driving circuit unit 120 are driven by a gate drive in panel (GIP) method, which is an external region surrounding the display area DA Area. ≪ / RTI >

The driver IC for mounting the data driving circuit unit 110 and the scan driving circuit unit 120 may be connected to the flexible printed circuit board (FPCB). The flexible printed circuit board may be attached to the interior, front and back edge regions of the OLED display.

In this case, the control unit 100 can be mounted on the flexible printed circuit board, and the data control signal DCS and the scan control signal SCS can be transferred to the driver IC on the control printed circuit board. The flexible printed circuit board is arranged in the folded state in the edge area inside the organic light emitting display. Therefore, the flexible printed circuit board can be mounted without providing a separate space inside the OLED display. In addition, when the control unit 100 is mounted on the flexible printed circuit board, it is possible to reduce the functions performed in the circuit in the Driver IC, thereby reducing the size of the Driver IC.

3 is a circuit diagram showing the pixel P in detail according to an example of the present application. The pixel P according to an exemplary embodiment of the present invention includes a driving transistor DT, an organic light emitting diode OLED, a storage capacitor Cst, and first through sixth transistors T1 through T6.

The driving transistor DT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the driving transistor DT is connected to the first node N1 to which the one electrode of the capacitor Cst, the drain electrode of the first transistor T1, and the source electrode of the fifth transistor T5 are connected. The source electrode of the driving transistor DT is connected to the drain electrode of the third transistor T3 which receives the pixel driving power ELVDD as a source electrode. The drain electrode of the driving transistor DT is connected to the source electrode of the fourth transistor T4.

And is turned on when a voltage higher than the threshold voltage is supplied to the gate electrode of the driving transistor DT. When the driving transistor DT is implemented as a P-type MOSFET, the turned-on driving transistor DT passes a driving current from the source electrode to the drain electrode.

The organic light emitting device OLED includes an anode electrode and a cathode electrode. The organic light emitting diode OLED supplies a driving current from the anode electrode to the cathode electrode. The anode electrode of the organic light emitting diode OLED is connected to the second node N2 to which the drain electrode of the fourth transistor T4 is connected. The cathode electrode of the organic light emitting diode OLED is connected to the cathode electrode of the ground line where the low potential power supply voltage ELVSS is formed. The organic light emitting device OLED emits light with brightness corresponding to the driving current flowing from the driving transistor DT.

The organic light emitting diode OLED further includes a hole transporting layer, an organic light emitting layer, and an electron transporting layer. In the organic light emitting diode OLED, when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and holes and electrons combine with each other in the organic light emitting layer.

The storage capacitor Cst has both electrodes. One electrode of the storage capacitor Cst is connected to the first node N1. The other electrode of the storage capacitor Cst is connected to the pixel drive power supply ELVDD line.

The storage capacitor Cst stores the difference voltage between the pixel drive power source ELVDD and the first node N1 when the fifth transistor T5 connected to the first node N1 is turned on. The storage capacitor Cst maintains the difference voltage stored in the first node N1 when the fifth transistor T5 is turned off. Further, the storage capacitor Cst can control driving of the driving transistor DT by using the stored and held voltage.

The gate electrode of the first transistor T1 receives the second scan signal Scan2. The source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor DT. The drain electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 is turned on by the second scan signal Scan2 so that the voltage of the first node N1 is set to Vdata which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. + Vtp.

The gate electrode of the second transistor T2 receives the second scan signal Scan2. The source electrode of the second transistor T2 is connected to the data line DL to receive the data voltage Vdata. The drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor DT. The second transistor T1 is turned on by the second scan signal Scan2 and supplies the data voltage Vdata to the source electrode of the driving transistor DT.

The gate electrode of the third transistor T3 is supplied with the emission control signal EM. The source electrode of the third transistor T3 is supplied with the pixel driving power ELVDD. The drain electrode of the third transistor T3 is connected to the source electrode of the driving transistor DT. The third transistor T3 is turned on by the emission control signal EM and supplies the pixel driving power ELVDD to the driving transistor DT so that the driving transistor DT allows the driving current to flow.

The gate electrode of the fourth transistor T4 is supplied with the emission control signal EM. The source electrode of the fourth transistor T4 is connected to the drain electrode of the driving transistor DT. The drain electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 is turned on by the emission control signal EM so that a driving current flows through the organic light emitting element OLED to emit the organic light emitting element OLED.

The gate electrode of the fifth transistor T5 receives the first scan signal Scan1. The source electrode of the fifth transistor T5 is supplied with the initializing voltage Vinit. The drain electrode of the fifth transistor T5 is connected to the first node N1. The fifth transistor T5 is turned on by the first scan signal Scan1 to initialize the voltage of the first node N1 to the initialization voltage Vinit.

The gate electrode of the sixth transistor T6 receives the first scan signal Scan1. The source electrode of the sixth transistor T6 is supplied with the initializing voltage Vinit. The drain electrode of the sixth transistor T6 is connected to the second node N2. The sixth transistor T6 is turned on by the first scan signal Scan1 to initialize the voltage of the second node N2 to the initializing voltage Vinit.

FIG. 4 is a waveform diagram illustrating input / output signals and voltages of each pixel of an OLED display according to an exemplary embodiment of the present invention. The driving transistor DT and the first to sixth transistors T1 to T6 in the pixel of the OLED display according to the exemplary embodiment of the present invention are implemented as a P-type MOSFET. Accordingly, when the first logic level L1 corresponding to the high logic level is supplied to the gate electrodes of the driving transistor DT and the first to sixth transistors T1 to T6, each transistor is turned off . Further, when the second logic level L2 corresponding to the low logic level is supplied to the gate electrodes of the driving transistor DT and the first to sixth transistors T1 to T6, each transistor is turned on.

In the first period S1, the first scan signal Scan1, the second scan signal Scan2, and the emission control signal EM are all at the first logic level L1. Thus, all the driving transistors DT and the first to sixth transistors T1 to T6 are turned off. The first node voltage VN1, which is the voltage of the first node N1, is zero.

In the second period S2, the first scan signal Scan1 is at the second logic level L2 and the second scan signal Scan2 and the emission control signal EM are at the first logic level L1. Thus, the fifth and sixth transistors T5 and T6 are turned on, and the driving transistor DT and the first to fourth transistors T1 to T4 maintain the turn-off state. The first node voltage VN1 is initialized to the initializing voltage Vinit by the fifth transistor T5. At the same time, the voltage of the second node N2 is also initialized to the initializing voltage Vinit by the sixth transistor T6.

In the third period S3, the first scan signal Scan1, the second scan signal Scan2, and the emission control signal EM are all at the first logic level L1. Thus, all the driving transistors DT and the first to sixth transistors T1 to T6 are turned off. At this time, the first node voltage VN1 maintains the initialization voltage Vinit by the storage capacitor Cst. In addition, the data voltage Vdata fluctuates in order to transmit the input data (data).

In the fourth period S4, the second scan signal Scan2 is at the second logic level L2 and the first scan signal Scan1 and the emission control signal EM are at the first logic level L1. Accordingly, the first and second transistors T1 and T2 are turned on, and the driving transistor DT and the third to sixth transistors T3 to T6 maintain the turn-off state. The second transistor T2 supplies the data voltage Vdata to the source electrode of the driving transistor DT. At the same time, the first node voltage VN1 is raised to Vdata + Vtp which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor.

In the fifth to seventh intervals S5 to S7, the first scan signal Scan1, the second scan signal Scan2, and the emission control signal EM are all at the first logic level L1. Thus, all the driving transistors DT and the first to sixth transistors T1 to T6 are turned off. At this time, the first node voltage VN1 maintains Vdata + Vtp which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor by the storage capacitor Cst. Further, the data voltage Vdata is returned to the original voltage after transmitting the input data (data).

In the eighth period S8, the emission control signal EM is the second logic level L2, and the first scan signal Scan1 and the second scan signal Scan2 are the first logic level L1. The third and fourth transistors T3 and T4 are turned on and the driving transistor DT and the first, second, fifth and sixth transistors T1, T2, T5 and T6 are turned off . The third transistor T3 supplies the pixel driving voltage ELVDD to the source electrode of the driving transistor DT. At the same time, the driving current flows through the organic light emitting device OLED by the fourth transistor T4, causing the organic light emitting device OLED to emit light.

5 is a plan view showing an active layer 210 of a pixel of an OLED display according to an exemplary embodiment of the present invention.

The active layer 210 is arranged from the upper left region where the sixth transistor T6 formed at the upper left corner is formed. The active layer 210 starts in the upper left region where the sixth transistor T6 is formed and extends in the first direction D1 by the length of the sixth transistor T6. The first direction D1 is a direction parallel to the direction in which the driving power supply line for supplying the pixel driving voltage ELVDD and the data line DL for supplying the data voltage Vdata are arranged.

The active layer 210 extends in the first direction D1 and then extends in the second direction D2 to the upper central region where the fifth transistor T5 is formed. The fifth transistor T5 is formed in the upper central region and divided into two regions. The second direction D2 is a direction intersecting the first direction D1 and is parallel to the direction in which the scan lines SL1 and SL2 for supplying the first and second scan signals Scan1 and Scan2 are arranged to be.

The active layer 210 extends in the direction opposite to the first direction D1 by the length of the fifth transistor T5 in the upper central region where the fifth transistor T5 is formed and then the width of the fifth transistor T5 In the second direction D2. The active layer 210 then extends in the first direction D1 to a region on the straight line parallel to the region in which the first transistor T1 is formed and in the second direction D2. Thereafter, the active layer 210 extends in the direction opposite to the second direction D2 and extends to the region where the first transistor T1 is formed. The first transistor T1 is formed in the left central region, and is formed in two regions. Then, the active layer 210 extends in the first direction D1 to the lower left region where the fourth transistor T4 is formed.

The active layer 210 extends in the first direction D1 from the right central region where the second transistor T2 is formed to the lower right region where the third transistor T3 is formed.

The active layer 210 extends in the second direction D2 between the region where the first transistor T1 is formed and the region where the fourth transistor T4 is formed and the second transistor T2 is formed And the region in which the third transistor T3 is formed, in the direction opposite to the second direction D2. The active layer 210 is arranged in the form of a driving transistor DT in a region where the driving transistor DT and the storage capacitor Cst are formed.

The active layer 210 may be formed of a metal oxide such as Zinc Oxide, Tin Oxide, Ga-In-Zn Oxide, In-Zn Oxide, or In-Sn Oxide, Zr, V, Hf, Ti, or the like. The active layer 210 changes into a channel layer, a drain layer, and a source layer. Each of the drain layer and the source layer is made conductive by a conducting process.

6 is a plan view showing an active layer 210 and a first electrode pattern 220 of a pixel of an OLED display according to an exemplary embodiment of the present invention.

The first electrode pattern 220 is disposed across the region where the sixth transistor T6 is formed and the region where the fifth transistor T5 is formed in the second direction D2. The first electrode pattern 220 thus formed forms a first scan line for supplying a first scan signal Scan1.

The first electrode pattern 220 is disposed across the region where the first transistor T1 is formed and the region where the second transistor T2 is formed in the second direction D2. The first electrode pattern 220 thus formed forms a second scan line for supplying a second scan signal Scan2.

The first electrode pattern 220 is disposed while crossing the region where the third transistor T3 is formed and the region where the fourth transistor T4 is formed in the second direction D2. The first electrode pattern 220 thus formed forms a light emission control line for supplying the light emission control signal EM.

The first electrode pattern 220 is disposed in a region where the storage capacitor Cst is formed, which is a part of a region where the driving transistor DT is formed. The first electrode pattern 220 thus formed forms a lower electrode of the storage capacitor Cst.

The first electrode pattern 220 serves as a gate metal layer. The first electrode pattern 220 may include at least one of Mo, Al, Cr, Au, Ti, Ni, Ne, They may be composed of a single layer of the metal or alloy or multiple layers of two or more layers.

7 is a plan view illustrating an active layer 210, a first electrode pattern 220, and a second electrode pattern 240 of a pixel of an OLED display according to an exemplary embodiment of the present invention. The first interlayer insulating film 230, which serves to prevent a short circuit between the first electrode pattern 220 and the second electrode pattern 240, is not shown because it is confused when expressed on a plan view.

The second electrode pattern 240 extends in the first direction D1 on the region where the sixth transistor T6 is formed. Then, the second electrode pattern 240 extends in the second direction D2. The second electrode pattern 240 overlaps the active layer 210 when extended in the first direction D1 and overlaps the active layer 210 when extended in the second direction D2 .

Then, the second electrode pattern 240 extends in a direction opposite to the first direction D1 on the region where the fifth transistor T5 is formed. Thereafter, the second electrode pattern 240 extends in the second direction. In this case, the second electrode pattern 240 is disposed so as not to overlap with the active layer 210 when extended in the first direction D1, and is disposed between the active layer 210 and the active layer 210 when extended in the second direction D2. They are placed in some overlap.

In addition, the second electrode pattern 240 is disposed in a region where the storage capacitor Cst is formed. The second electrode pattern 240 is disposed to overlap with the first electrode pattern 220. The second electrode pattern 240 formed in the storage capacitor region forms the upper electrode of the storage capacitor Cst.

Here, the second electrode pattern 240 disposed in the region where the storage capacitor Cst is formed further has the extension pattern EXP.

The extension pattern EXP extends from one side of the second electrode pattern 240 in a direction opposite to the first direction D1. More specifically, the extension pattern EXP extends from the second electrode pattern 240 on the right side of the upper edge of the region where the storage capacitor Cst is formed, in the direction opposite to the first direction D1.

The extension pattern EXP has a thicker portion that ends at a portion of the second electrode pattern 240 that starts to extend. The extension pattern EXP forms part of the driving power supply line.

The second electrode pattern 240 serves as a top metal layer, that is, an upper metal layer. The second electrode pattern 240 may be formed of at least one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, They may be composed of a single layer of the metal or alloy or multiple layers of two or more layers.

8 is a plan view showing an active layer 210, a first electrode pattern 220, a second electrode pattern 240, and contact holes of a pixel of an OLED display according to an exemplary embodiment of the present invention. 9 is a plan view of a pixel of an OLED display according to an example of the present application.

8 and 9, a pixel of an OLED display according to an exemplary embodiment of the present invention includes an active layer 210, a first electrode pattern 220, a second electrode pattern 240, contact holes, / Drain < / RTI > The second interlayer insulating film 250, which serves to prevent the short circuit between the second electrode pattern 240 and the source / drain pattern 260, is not shown because it is confused when expressed on a plan view.

The source / drain pattern 260 is arranged in the first direction D1 on the right side of the region where the second transistor T2 and the third transistor T3 are formed. A source / drain pattern 260 disposed on the right side of the region where the second transistor T2 and the third transistor T3 are formed forms a data line DL. The source / drain pattern 260 forming the data line DL supplies the data voltage Vdata to the pixel.

The source / drain pattern 260 extends in the first direction D1 at an upper portion of the region where the extension pattern EXP is formed in the second electrode pattern 240 and is arranged to partially overlap the extension pattern EXP . The source / drain pattern 260 disposed on the extension pattern EXP forms a first line pattern LP1. The source / drain pattern 260 forming the first line pattern LP1 forms a driving power supply line and receives the pixel driving power supply ELVDD from the data driving circuit 110. [

The source / drain pattern 260 extends in the first direction D1 from the lower portion of the region where the driving transistor TD is formed in the second electrode pattern 240 and has a region where the third transistor T3 is formed Respectively. The source / drain pattern 260 extending from the lower portion of the region where the driving transistor TD is formed forms the second line pattern LP2. The source / drain pattern 260 disposed on the extension pattern EXP supplies the pixel driving power ELVDD to the third transistor T3.

The source / drain pattern 260 is formed in a region where the active layer 210 and the storage capacitor Cst are formed in the first node N1 between the first transistor T1 and the fifth transistor T5 And the first electrode pattern 220 disposed on the first electrode pattern 220. A source / drain pattern 260 connecting the active layer 210 and the second electrode pattern 240 forms a node bridge pattern BP. The node bridge pattern BP is formed not to be parallel to the first direction D1 or the second direction D2 but inclined by a predetermined angle from the first direction D1. The node bridge pattern BP supplies the first node voltage VN1 to the first electrode pattern 220 forming the lower electrode of the storage capacitor Cst.

The source / drain patterns 260 are independently arranged on the region where the fourth transistor T4 is formed and on the region where the fifth transistor T5 is formed. The source / drain patterns 260 disposed in the regions where the fourth and fifth transistors T4 and T5 are formed form the source and drain electrodes of the fourth and fifth transistors T4 and T5.

The contact holes include a data line contact hole DLH, first and second power source line contact holes PLH1 and PLH2, first and second node contact holes NH1 and NH2, first and second emission control contact holes EH1, and EH2) and an initialization contact hole IH.

The data line contact hole DLH is provided in the active layer 210 disposed in a region where the second transistor T2 is formed. The data line contact hole DLH electrically connects the source / drain pattern 260 forming the data line DL and the active layer 210 of the second transistor T2. The data line contact hole DLH transfers the data voltage Vdata to the source electrode of the second transistor T2.

The first power line contact hole PLH1 is disposed on the extension pattern EXP of the second electrode pattern 240. [ The first power line contact hole PLH1 electrically connects the second electrode pattern 240 and the first line pattern LP1 disposed in the upper region of the source / drain pattern 260 forming the driving power line. The first power line contact hole PLH1 transmits the pixel driving power source ELVDD supplied to the first line pattern LP1 to the second electrode pattern 240. [

The second power line contact hole PLH2 is disposed on a region of the second electrode pattern 240 where the storage capacitor Cst is formed. The second power line contact hole PLH2 electrically connects the second electrode pattern 240 and the second line pattern LP2 disposed in the lower region among the source / drain patterns 260 forming the driving power line. The second power line contact hole PLH2 transfers the pixel drive power source ELVDD supplied to the second electrode pattern 240 to the second line pattern LP2.

The first node contact hole PLH1 is provided at a portion of the active layer 210 formed between the first transistor T1 and the fifth transistor T5 where the node bridge pattern BP is formed. The first node contact hole PLH1 electrically connects the active layer 210 and the node bridge pattern BP.

The second node contact hole PLH2 is provided at a portion where the first electrode pattern 220 is formed in the region where the storage capacitor Cst is formed. The second node contact hole PLH2 electrically connects the first electrode pattern 220 and the node bridge pattern BP.

The first emission control contact hole EH1 is formed on a region where the third transistor T3 is formed. The first emission control contact hole EH1 electrically connects the active layer 210 on the third transistor T3 to the driving power supply line. The first emission control contact hole EH1 allows the source electrode of the third transistor T3 to receive the pixel driving power supply ELVDD.

The second emission control contact hole EH2 is formed on a region where the fourth transistor T4 is formed. The second emission control contact hole EH2 electrically connects the active layer 210 on the fourth transistor T4 to the driving power supply line. The second emission control contact hole EH2 allows the source electrode of the fourth transistor T4 to receive the pixel driving power supply ELVDD.

The initialization contact hole IH is formed on the region where the fifth transistor T5 is formed. The initialization contact hole IH electrically connects the active layer 210 on the fifth transistor T5 to the second electrode pattern 240. [ The initialization contact hole IH allows the fifth transistor T5 to supply the initialization voltage Vinit to the first node N1.

In other words, the OLED display according to an exemplary embodiment of the present invention includes a driving transistor DT and a storage capacitor Cst for controlling a current flowing through the organic light emitting diode OLED and the organic light emitting diode OLED, A plurality of pixels P having a circuit and a plurality of driving power lines provided along the first direction D1 and supplying the pixel driving power ELVDD to the plurality of pixels P. [

The storage capacitor Cst according to an exemplary embodiment of the present invention is provided in an overlapping region between the first electrode pattern 220 connected to the gate electrode of the driving transistor DT and the second electrode pattern 240 connected to the driving power supply line.

Each of the plurality of driving power supply lines according to an exemplary embodiment of the present invention includes a plurality of line patterns LP1 and LP2 that are provided at regular intervals along the first direction D1 and are electrically connected to each other through the second electrode pattern 240. [ ). The driving power supply line according to an exemplary embodiment of the present invention includes a first line pattern LP1, an extension pattern EXP of the second electrode pattern 240, and a second line pattern LP2 arranged in a straight line, Power line.

When the plurality of line patterns LP1 and LP2 are electrically connected through the second electrode pattern 240 as described above, the plurality of line patterns LP1 and LP2 can be uniformly formed or physically contacted, Lines can be formed. In order to uniformly form a plurality of line patterns LP1 and LP2, a line pattern must be formed in a predetermined thickness to form a driving power supply line.

The driving power supply lines are arranged for each pixel column. Accordingly, the driving power supply line is disposed adjacent to the data line. As the number of display device pixels increases, the number of pixel columns increases, and the size of the pixels and the interval between pixels decrease. Particularly, when the plastic organic light emitting device (POLED) is used in a high-resolution (UHD) portable terminal, there is a problem that the driving power line is overlapped with the data line and short- do. That is, as the size of the pixel decreases, the space for forming the driving power supply line becomes insufficient.

In one embodiment of the present application, the first and second line patterns LP1 and LP2 are disposed on both sides of the pixel when forming the driving power supply line, and the line pattern forming the driving power supply line formed in the center of the pixel is Electrode pattern 240 by an extension pattern EXP. That is, the patterns formed in the order of the first line pattern LP1, the extension pattern EXP of the second electrode pattern 240, and the second line pattern LP2 form one driving power supply line.

Accordingly, one example of the present application can reduce the space occupied by the driving power supply line at the central portion of the pixel. The space occupied by the driving power source line at the central portion of the pixel can be reduced to further reduce the size of each pixel. In addition, it is possible to solve the problem that the driving power supply line is overlapped with the data line to cause a short circuit, thereby preventing driving problems that may occur when the area of the pixel is reduced.

The second electrode pattern 240 according to an exemplary embodiment of the present invention is provided on a different layer from the plurality of line patterns LP1 and LP2. As described above, the second electrode pattern 240 is a layer constituting the upper electrode of the storage capacitor Cst, which is defined as a top metal or an upper metal layer. On the other hand, the plurality of line patterns LP1 and LP2 are formed by forming the second interlayer insulating film 250 on the second electrode pattern 240 and then forming the source / drain pattern 250 formed on the second interlayer insulating film 250, (260). That is, in the driving power supply line according to an exemplary embodiment of the present invention, the second electrode pattern 240 between the first and second line patterns LP1 and LP2 has a jumping structure.

Accordingly, one example of the present application can save space for designing the central part of the driving power supply line in the same layer as the plurality of line patterns LP1 and LP2 by using the second electrode pattern 240. [ Further, even if the pixel according to an example of the present application reduces the distance between the driving power supply line and the data line or decreases the distance between the driving power supply line and the storage capacitor Cst, It is possible to prevent a short circuit from occurring.

The second electrode patterns 240 provided in each of the plurality of pixels according to an exemplary embodiment of the present invention are arranged along the second direction D2 intersecting the first direction D1 and electrically connected to each other. 9 are arranged in the second direction D2 and the second electrode patterns 240 are all connected in the same manner as the scan lines Scan1 and Scan2.

Conventionally, the second electrode patterns 240 are arranged separately for each pixel. In this case, each of the second electrode patterns 240 adjacent in the second direction D2 receives pixel driving voltage ELVDD individually from different driving power supply lines. In this case, a difference or ripple may occur in the pixel driving voltage ELVDD supplied from each of the driving power supply lines, resulting in a phenomenon that luminance is uneven in the second direction D2.

In one example of the present application, the second electrode patterns 240 of adjacent pixels in the second direction D2 are electrically connected. Accordingly, the pixel driving voltage ELVDD of the adjacent driving power supply lines is supplied to the adjacent pixels in the second direction D2. Accordingly, one example of the present application can solve the problem that the pixel driving voltage ELVDD can be uniformly supplied in the second direction D2, and the phenomenon that the luminance is uneven in the second direction D2 occurs.

As one specific implementation structure for realizing this, one example of the present application is a display device having a display area DA having a plurality of pixels, a non-display area surrounding the display area DA, a non-display area provided in the non- A first power application unit for applying the pixel driving power to the line patterns LP1 and LP2 of each of the adjacent plurality of driving power supply lines and a second power supply unit for applying at least one of the second electrode patterns 240 provided in the non- And a second power applying unit for applying the pixel driving power.

More specifically, the first and second power application units according to an exemplary embodiment of the present invention are provided in a non-display area connected to one side of a driving power supply line. That is, the first and second power application units according to an exemplary embodiment of the present invention are provided on the upper portion or the lower portion of the organic light emitting display. When the organic light emitting display according to an exemplary embodiment of the present invention is a portable terminal, the first power applying unit may be incorporated in a Driver IC including the data driving circuit unit 110. The wiring extending from the second power applying section extends to the side of the organic light emitting display device and is connected to the display area DA on the side surface.

The first power applying unit according to an exemplary embodiment of the present invention performs a role of supplying a basic driving power line voltage by applying a pixel driving power ELVDD to the line patterns LP1 and LP2 of driving power lines.

In addition, the second power application unit according to an exemplary embodiment of the present invention applies the pixel driving power source ELVDD to the second electrode pattern 240. Since the second electrode pattern 240 of the present invention is electrically connected in the second direction D2, the present application can reduce the pixel driving power ELVDD in the second direction D2 through the second electrode pattern 240 Can also be supplied. Accordingly, the organic light emitting display according to an exemplary embodiment of the present invention can apply the pixel driving power ELVDD while crossing the pixel driving power ELVDD in a mesh manner to uniformly supply the pixel driving power ELVDD to the display area DA .

10 is a cross-sectional view showing I-I` of FIG. 10 shows details of a power supply line contact portion of the OLED display according to an exemplary embodiment of the present invention.

Each of the plurality of pixels according to an exemplary embodiment of the present invention includes first and second line patterns LP1 and LP2 spaced apart from each other along the first direction DA1 in the pixel among the plurality of line patterns LP1 and LP2. And a power supply line contact portion electrically connecting the two-electrode pattern 240 to each other.

The lowest layer of the power line contact portion is the substrate 200. The substrate 200 may be made of flexible plastic so that the organic light emitting display device is flexible.

A first electrode pattern 220 is disposed on the substrate 200 to form a first scan line Scan1.

A first interlayer insulating film 230 is formed on the substrate 200 and the first electrode pattern 220. The first interlayer insulating film 230 is formed of a material having excellent insulating properties. The first interlayer insulating layer 230 electrically separates the first electrode pattern 220 from the layer disposed thereon.

A second electrode pattern 240 is disposed on the first interlayer insulating film 230.

A second interlayer insulating film 250 is formed on the first interlayer insulating film 240 and the second electrode pattern 250. The second interlayer insulating film 250 is formed of a material having excellent insulating properties. The second interlayer insulating film 250 electrically isolates the second electrode pattern 240 from the layer disposed above except for the portion where the contact hole is formed.

First and second line patterns LP1 and LP2 are formed on the second interlayer insulating film 250. [ The first and second line patterns LP1 and LP2 form a portion of the source / drain pattern 260 which forms the driving power supply line. Although the driving power supply line is generally formed in a single straight line in one pixel, the present application is formed by dividing the driving power supply line into the first and second line patterns LP1 and LP2 even in the pixel.

One example of the present application forms a driving power supply line using a first line pattern LP1, a second electrode pattern 240, and a second line pattern LP2 through a power line contact portion. When the driving power supply line is formed through the power supply line contact portion, the thickness and the layout area of the driving power supply line can be reduced as compared with a single wiring. Accordingly, one example of the present application can make the design easier in the pixel compared to the case where the driving power supply line is formed by a single wiring.

The power supply line contact portion according to an exemplary embodiment of the present invention includes an extension pattern EXP extending from one side of the second electrode pattern 240 toward the first line pattern LP1 opposite to the first direction D1, A first power line contact hole PLH1 for electrically connecting the first line pattern EXP to the first line pattern LP1 and a second power line contact hole PLH2 for electrically connecting the second electrode pattern 240 to the second line pattern LP2, And a contact hole PLH2.

The first and second power supply line contact holes PLH1 and PLH2 are formed through the second interlayer insulating film 250. [ Accordingly, the pixel driving power supply ELVDD is connected to the first power line contact hole PLH2, the first power line contact hole PLH1, the extension pattern EXP, the second electrode pattern 240, ), And a second line pattern (LP2).

One example of the present application provides a concrete method of forming the driving power supply line between the other layers by using the first and second power supply line contact holes PLH1 and PLH2. In particular, it is possible to reduce the thickness and the area of the driving power line by forming the driving power line by using the second electrode pattern 240, which was not utilized when forming the driving power line.

One example of the present application is provided along the second direction D2 so as to intersect with the first line pattern LP1 of each pixel arranged in the second direction D2 and a first scan signal Scan1 is applied to the pixel circuit, And a plurality of second scan lines provided along the second direction D2 intersecting the first direction D1 and supplying the second scan signal Scan2 to the pixel circuit, . Each of the plurality of second scan lines intersects the extension pattern EXP of each pixel arranged in the first direction D2.

Referring to FIG. 9, it can be seen that the extension pattern EXP and the first electrode pattern 220 forming the second scan line intersect with each other in a tenth shape. Thus, the extension pattern EXP is formed on the region where the second scan line is formed, so that the area occupied by the pixel circuit can be reduced.

Since the extension pattern EXP is a portion extended from the second electrode pattern 240, the extension pattern EXP is electrically separated from the first electrode pattern 220 by the first interlayer insulating film 230. One example of the application of the present application is to form two electrically insulated layers so as to intersect each other and to form an extension pattern EXP for transferring the pixel driving power supply ELVDD and a first scan line Can be arranged in a limited area while preventing them from colliding with each other physically or electrically.

The present application is directed to a liquid crystal display device which is provided along a first direction D1 and which intersects a plurality of data lines for supplying a data voltage to a pixel circuit and a second line pattern LP2 of each pixel arranged along a second direction D2 And a plurality of emission control lines provided along the two directions D2 and supplying the emission control signal EM to the pixel circuits. Each of the plurality of data lines crosses a plurality of emission control lines.

The data line of the present application is formed using a partial area of the source / drain pattern 260, and the emission control line is formed using a partial area of the first electrode pattern 220. Accordingly, one example of the present application can be arranged in a limited area while preventing the data lines supplying the data voltage Vdata and the emission control lines supplying the emission control signal EM from being physically or electrically collided with each other .

3, the pixel circuit according to one example of the present application includes a first node N1 connected to the gate electrode of the driving transistor DT, a first node N1 connected between the driving transistor DT and the organic light emitting diode OLED, A fifth transistor T5 for resetting the voltage of the first node N1 in response to the first scan signal Scan1 and a fifth transistor T5 for resetting the voltage of the second node N2 in response to the first scan signal Scan1, (Vdata + Vtp) corresponding to the sum of the data voltage (Vdata) and the threshold voltage (Vtp) of the driving transistor (DT) in response to the second scan signal (Scan2) A second transistor T2 for supplying the data voltage Vdata to the source electrode of the driving transistor DT and a second transistor T2 for supplying the data voltage Vdata to the source electrode of the driving transistor DT in response to the control signal EM. A third transistor T3 for controlling the pixel driving power supply ELVDD supplied to the driving transistor DT, In response to the signal (EM) and a fourth transistor (T4) for controlling a current flowing from the driving transistor (DT) to the organic light emitting device (OLED).

Accordingly, the pixel circuit according to an example of the present application can implement a 7T1C pixel circuit structure in which one pixel is composed of seven transistors and one capacitor. In the 7T1C pixel circuit structure, the compensation of the threshold voltage compensation of the driving transistor DT and the characteristic deviation of the organic light emitting element OLED in the pixel is completed. Accordingly, the OLED display according to an exemplary embodiment of the present invention does not need to sense the threshold voltage of the driving transistor DT or the voltage or current of the organic light emitting diode OLED outside the pixel. Accordingly, it is not necessary to design a wiring for sensing and a separate external compensation circuit, thereby reducing the size of the pixel circuit and the size of the Driver IC.

11 is a plan view showing in detail a portion A of the pixel circuit according to an example of the present application.

The first node N1 according to an example of the present application includes a node bridge pattern BP that electrically connects the gate electrode of the driving transistor DT and the fifth transistor T5.

The node bridge pattern BP overlaps the first scan line so as to be inclined along the diagonal direction between the first direction D1 and the second direction D2. The node bridge pattern BP is formed on the region where the first node N1 is formed by using the source / drain pattern 260. [

The node bridge pattern BP is partially overlapped with the first scan line while being arranged to be inclined with respect to the first direction D1 by the first angle? 1. The first angle? 1 can be variously set in consideration of the area of the overlapping area with the first scan line. In general, the first angle? 1 is not less than 30 degrees and not more than 60 degrees.

One example of the present invention is to electrically connect the gate electrode of the driving transistor DT and the fifth transistor T5 by using the node bridge pattern BP to electrically connect the first node N1 and the second node N2 at the same time Can be initialized. Conventionally, a separate scan signal and a scan line are needed for the second node N2, and the number of scan signals and the number of scan lines can be reduced by using the node bridge pattern BP. Accordingly, the size of the pixel circuit and the size of the driver IC can be reduced.

More specifically, one side of the node bridge pattern BP of the present application is electrically connected to the fifth transistor T5 through the first node contact hole NH1, and the other side of the node bridge pattern BP is electrically connected to the second node T5. And is electrically connected to the gate electrode of the driving transistor DT through the contact hole NH2.

Since the fifth transistor T5 is connected to the first node N1, the initialization voltage Vinit may be stored in the first node N1. The voltage of the first node N1 may rise to Vdata + Vtp which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. Further, the gate electrode of the driving transistor DT is connected to the first node N1. Therefore, the node bridge pattern BP of the present application plays a role of setting a voltage for driving the driving transistor DT.

The second transistor T2 of the present application is electrically connected to the data line through the data line contact hole DLH and the extended pattern EXP is electrically connected between the first node contact hole NH1 and the data line contact hole DLH Respectively. The extension pattern EXP does not overlap with the first node contact hole NH1 and the data line contact hole DLH. In addition, the extension pattern EXP is not electrically connected to the first node contact hole NH1 and the data line contact hole DLH, but is disposed so as to be separated.

The second transistor T2 of the present application supplies a data voltage to the driving transistor DT. On the other hand, the extended pattern EXP is connected to the first line pattern LP1 to receive the pixel driving power ELVDD. Accordingly, one example of the present application is to prevent the extension pattern EXP from contacting the data line contact hole DLH connected to the first node contact hole NH1 or the second transistor T2, can do. One example of the present application is to provide an extension pattern EXP for transmitting the pixel driving power ELVDD between the first node contact hole NH1 and the data line contact hole DLH, It is possible to reduce the area ratio occupied.

One example of the present application is such that the first power line contact hole PLH1, the first node contact hole NH1 and the data line contact hole DLH have widths of the first margin M1 ). The first margin M1 can be set according to the precision of the pixel manufacturing process. The first margin M1 has a value of 1 占 퐉 or more and 2 占 퐉 or less. The smaller the first margin M1, the smaller the contact hole, the smaller the width of the line, and the smaller the overall size of the pixel.

One example of the present application is an example in which the distance between the first node contact hole NH1 and the extension pattern EXP and the distance between the data line contact hole DLH and the extension pattern EXP are (M2) or less. The second margin M2 can be set according to the precision of the pixel manufacturing process. The second margin M2 has a value of 0.125 탆 or more and 0.5 탆 or less. The smaller the second margin M1, the smaller the area separating the contact hole from the line or the pattern, the smaller the width of the line, and the smaller the overall size of the pixel.

12 is a plan view showing an active layer 210, a first electrode pattern 220, and a second electrode pattern 240 of a pixel of an OLED display according to another example of the present application. 13 is a plan view of a pixel of an organic light emitting diode display according to another example of the present application.

The second electrode pattern 240 according to another example of the present application further includes an extension shield portion EXS overlapping the first electrode pattern 220 and the node bridge pattern BP.

The extension shield portion EXS may be formed by branching in the direction opposite to the second direction D2 in the extension pattern EXP. The extension shield portion EXS overlaps the first electrode pattern 220 forming the second scan line of the first electrode pattern 220. [ Further, the extended shield portion EXS overlaps with the node bridge pattern BP at the center portion.

The first electrode pattern 220 forming the second scan line and the node bridge pattern BP of the source / drain pattern 260 are formed in different layers, however, parasitic capacitance may be generated in the overlapped region. When parasitic capacitance occurs between the second scan line and the node bridge pattern BP, there arises a problem that the aperture ratio of the pixel decreases and the driving performance deteriorates.

Another example of the present application is to form the second electrode pattern 240 between the second scan line and the node bridge pattern BP by using the extension shield portion EXS. Thus, another example of the present application can prevent the parasitic capacitance between the second scan line and the node bridge pattern BP from occurring, thereby increasing the aperture ratio of the pixel and improving the driving performance.

The organic light emitting display according to the embodiments of the present invention can be applied to a structure in which a driving power supply line is not formed uniformly but a gap between two line patterns formed of a source / Thereby facilitating the design of the driving power supply line at the center and preventing the driving power supply line from being overlapped with the data line even if the pixel size and the interval between the pixels are reduced.

100: control unit 110: data driving circuit
120: scan drive circuit unit 200:
210: active layer 220: first electrode pattern
230: first interlayer insulating film 240: second electrode pattern
250: second interlayer insulating film 260: source / drain pattern
DA: display area NDA: non-display area
D1, D2: first and second directions DT: driving transistor
Cst: storage capacitors T1 to T6: first to sixth transistors
OLED: organic light emitting devices N1 and N2: first and second nodes
EXP: extension pattern DLH: data line contact hole
PLH1, PLH2: first and second power line contact holes
NH1, NH2: first and second node contact holes
EH1, EH2: first and second emission control contact holes
IH: initialization contact holes LP1 and LP2: first and second line patterns
BP: node bridge pattern EXS: extension shield part

Claims (15)

A plurality of pixels each having a pixel circuit including a driving transistor and a storage capacitor for controlling an electric current flowing through the organic light emitting element; And
And a plurality of driving power supply lines provided along the first direction and supplying pixel driving power to the plurality of pixels,
Wherein the storage capacitor is provided in an overlapping region between a first electrode pattern connected to a gate electrode of the driving transistor and a second electrode pattern connected to the driving power supply line,
Wherein each of the plurality of driving power supply lines includes a first line pattern dd and a second line pattern provided at regular intervals along the first direction,
Wherein the first and second line patterns are electrically connected to each other through the second electrode pattern. The method according to claim 1,
And the second electrode pattern is provided in a layer different from the plurality of line patterns. The method according to claim 1,
And a second electrode pattern provided in each of the plurality of pixels is arranged along a second direction intersecting the first direction and electrically connected to each other. The method according to claim 1,
A display region having the plurality of pixels;
A non-display area surrounding the display area;
A first power application unit that applies the pixel driving power to each of the first line patterns provided in the non-display area and adjacent to the non-display area; And
And a second power application unit that applies the pixel driving power to at least one of the second electrode patterns provided in the non-display area and adjacent to the non-display area. 2. The display device according to claim 1, wherein each of the plurality of pixels includes:
And a power supply line contact portion electrically connecting each of the first and second line patterns spaced apart in the first direction in the pixel among the plurality of line patterns to the second electrode pattern. 2. The display device according to claim 1, wherein each of the plurality of pixels includes:
An extension pattern extending from one side of the second electrode pattern to the first line pattern in a direction opposite to the first direction;
A first power line contact hole electrically connecting the extension pattern and the first line pattern; And
And a second power line contact hole electrically connecting the second electrode pattern and the second line pattern. 2. The display device according to claim 1, wherein each of the plurality of pixels includes:
A plurality of first scan lines provided along the second direction so as to intersect a first line pattern of each pixel arranged along the second direction and supplying a first scan signal to the pixel circuit; And
Further comprising a plurality of second scan lines provided along a second direction intersecting the first direction and supplying a second scan signal to the pixel circuit,
And each of the plurality of second scan lines crosses an extension pattern of each pixel arranged in the first direction. 2. The display device according to claim 1, wherein each of the plurality of pixels includes:
A plurality of data lines provided along the first direction and supplying data voltages to the pixel circuits; And
Further comprising a plurality of emission control lines provided along the second direction so as to intersect a second line pattern of each pixel arranged along the second direction and supplying a light emission control signal to the pixel circuit,
And each of the plurality of data lines crosses the plurality of light emission control lines. The method according to claim 1,
The pixel circuit includes:
A first node coupled to a gate electrode of the driving transistor;
A second node between the driving transistor and the organic light emitting element;
A fifth transistor for initializing a voltage of the first node in response to the first scan signal;
A sixth transistor for initializing a voltage of the second node in response to the first scan signal;
A first transistor for charging the first node with a voltage corresponding to a sum of the data voltage and the threshold voltage of the driving transistor in response to the second scan signal;
A second transistor for supplying a data voltage to a source electrode of the driving transistor;
A third transistor for controlling the pixel driving power supplied to the driving transistor in response to the light emission control signal; And
And a fourth transistor for controlling a current flowing from the driving transistor to the organic light emitting element in response to the light emission control signal. 10. The method of claim 9,
Wherein the first node includes a node bridge pattern electrically connecting the gate electrode of the driving transistor and the fifth transistor,
Wherein the node bridge pattern overlaps with the first scan line so as to be inclined along a diagonal direction between the first direction and the second direction. 11. The method of claim 10,
One side of the node bridge pattern being electrically connected to the fifth transistor through a first node contact hole,
And the other side of the node bridge pattern is electrically connected to the gate electrode of the driving transistor through the second node contact hole. 10. The method of claim 9,
The second transistor is electrically connected to the data line through a data line contact hole,
Wherein the extension pattern is provided between the first node contact hole and the data line contact hole. 13. The method of claim 12,
And a width of each of the first power line contact hole, the first node contact hole, and the data line contact hole is equal to or less than a first margin with respect to the second direction. 13. The method of claim 12,
Wherein an interval between the first node contact hole and the extension pattern and an interval between the data line contact hole and the extension pattern are equal to or less than a second margin based on the second direction. 13. The method of claim 12,
Wherein the second electrode pattern further includes an extension shield portion overlapping the first electrode pattern and the node bridge pattern.

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