KR101972574B1 - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of securing an area for designing a driving transistor and a storage capacitor in a pixel even in an ultra-high resolution organic light emitting display device in which a pixel size and a space between pixels are reduced. According to an embodiment of the present invention, the organic light emitting display device comprises: a plurality of pixels each having an organic light emitting element and a pixel circuit which includes a driving transistor and a storage capacitor for controlling a current flowing through the organic light emitting element; a plurality of driving power supply lines provided along a first direction and supplying pixel driving power to the plurality of pixels; and a plurality of initialization lines provided along a second direction intersecting the first direction and supplying an initialization voltage to the plurality of pixels. The plurality of initialization lines are composed of a first metal layer which is different from a source/drain layer constituting the plurality of driving power supply lines. According to the organic light emitting display device of an embodiment of the present invention, the plurality of driving power supply lines and a plurality of data lines are arranged to be spaced apart from each other on both sides within an arbitrary pixel.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

One example of the present application relates to an organic light emitting display.

2. Description of the Related Art In recent years, the importance of display devices has been increasing with the development of multimedia. Various types of flat panel display devices such as a liquid crystal display device, a plasma display device, and an organic light emitting display device have been commercialized in response to this. Among the flat panel display devices, organic light emitting display devices are widely used as display devices for notebook computers, televisions, tablet computers, monitors, smart phones, portable display devices, and portable information devices due to their excellent characteristics such as thinness, light weight and low power consumption .

A display panel used in an organic light emitting display includes a thin film transistor (TFT) and a storage capacitor (Cst) as essential components. A pixel circuit constituting one pixel can be realized by using a plurality of thin film transistors and storage capacitors.

As the number of display device pixels increases, the number of pixel columns increases, and the size of the pixels and the interval between pixels decrease. Particularly, when a plastic organic light emitting device (POLED) is used in an ultra high resolution (UHD) portable terminal, the size of the pixel and the interval between the pixels are reduced.

The organic light emitting diode display supplied initialization voltage to the thin film transistor for supplying the initialization voltage using an initialization line including a source / drain layer.

In an ultra-high resolution organic light emitting display, when an initialization voltage is supplied using an initialization line formed of a source / drain layer, there arises a problem that an area for designing a driving transistor and a storage capacitor in a pixel is insufficient.

Further, the organic light emitting display device has a data line for supplying a data voltage to the pixels and a driving power supply line for supplying pixel driving power to the pixels.

The driving power supply line and the data line are arranged for each pixel column. Both the data voltage and the pixel driving power supply are supplied to the driving transistor. Both the data voltage and the pixel driving power are arranged adjacent to the driving transistor so that the driving power supply line and the data line are arranged adjacent to each other in one pixel.

In the ultra-high resolution organic light emitting display, when the driving power supply line is adjacent to the data line, there arises a problem that the area for designing the driving transistor and the storage capacitor in the pixel is insufficient.

An example of the present invention is to provide an OLED display device capable of securing an area for designing a driving transistor and a storage capacitor in a pixel even in an ultra-high resolution organic light emitting display device in which the size of a pixel and the interval between pixels are reduced.

An organic light emitting display according to an exemplary embodiment of the present invention includes a plurality of pixels each having an organic light emitting element and a pixel circuit including a driving transistor and a storage capacitor for controlling a current flowing through the organic light emitting element, A plurality of driving power supply lines for supplying a pixel driving power to a plurality of pixels and a plurality of initialization lines provided along a second direction intersecting the first direction and supplying an initialization voltage to a plurality of pixels, The initialization line is composed of a first metal layer which is different from a source / drain layer constituting a plurality of driving power supply lines.

Further, in the organic light emitting diode display according to an example of the present application, a plurality of driving power supply lines and a plurality of data lines are disposed apart from each other in a certain pixel.

The organic light emitting display according to the examples of the present application can replace the initialization line made of the conventional source / drain layer as the first metal layer. Accordingly, the present application can secure an area for designing a driving transistor and a storage capacitor in a pixel even in an ultra-high resolution organic light emitting display device in which the size of a pixel and the interval between pixels are reduced.

In the organic light emitting diode display according to the examples of the present application, a plurality of driving power supply lines and a plurality of data lines are spaced apart from each other in a certain pixel to secure an area where the driving transistor and the storage capacitor are disposed at the center of the pixel . Accordingly, the present application can secure an area for designing a driving transistor and a storage capacitor in a pixel even in an ultra-high resolution organic light emitting display device in which the size of a pixel and the interval between pixels are reduced.

1 is a perspective view showing an application example of an organic light emitting diode display according to an example of the present application.
2 is a block diagram showing an organic light emitting display according to an example of the present application.
3 is a circuit diagram showing a pixel of an organic light emitting display according to an embodiment of the present invention in detail.
FIG. 4 is a waveform diagram illustrating input / output signals and voltages of each pixel of an OLED display according to an exemplary embodiment of the present invention.
5 is a plan view showing an active layer of a pixel of an OLED display according to an example of the present application.
6 is a plan view showing an active layer and a gate layer of a pixel of an organic light emitting diode display according to an example of the present application.
7 is a plan view showing an active layer, a gate layer, and a first metal layer of a pixel of an organic light emitting diode display according to an example of the present application.
8 is a plan view of a pixel of an organic light emitting diode display according to an example of the present application.
9 is a cross-sectional view showing II 'in FIG.
10 is a cross-sectional view showing II-II` of FIG.

Brief Description of the Drawings The advantages and features of the present application, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that this application is not limited to the examples disclosed herein, but may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein, To fully disclose the scope of the invention to those skilled in the art, and this application is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like described in the drawings for describing an example of the present application are illustrative, and thus the present application is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the description of the present application, a detailed description of known related arts will be omitted if it is determined that the gist of the present application may be unnecessarily obscured.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the scope of the present application.

The terms " first horizontal axis direction ", " second horizontal axis direction ", and " vertical axis direction " should not be interpreted solely by the geometric relationship in which the relationship between them is vertical, It may mean having a wider directionality in the inside.

It should be understood that the term " at least one " includes all possible combinations from one or more related items. For example, the meaning of " at least one of the first item, the second item and the third item " means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

Each of the features of the various embodiments of the present application may be combined or combined with each other partially or entirely, technically various interlocking and driving are possible, and the examples may be independently performed with respect to each other, .

Hereinafter, a preferred example of an electronic apparatus according to the present application will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings.

1 is a perspective view showing an application example of an organic light emitting diode display according to an example of the present application.

The OLED display according to an exemplary embodiment of the present invention includes a display area DA and a non-display area NDA.

The display area DA is an area for displaying information or representing an image through an image. The display area has a display panel. The display panel includes a thin film transistor (TFT) and a storage capacitor (Cst) as an essential component. A pixel circuit constituting one pixel can be realized by using a plurality of thin film transistors and storage capacitors. Further, the organic light emitting display device has a plurality of driving power supply lines (VDDL) for supplying pixel driving power to a plurality of pixels.

The non-display area NDA is provided outside the display area DA. The non-display area NDA prevents the rim of the display area DA from being broken. The non-display area NDA serves as a housing for determining the shape of the OLED display. 1, the non-display area NDA is formed to be extremely thin at both side edges of the portable terminal, which is the X axis direction of the four corners of the display area, Type portable terminal, and it may be provided relatively thick on the upper and lower portions of the portable terminal in the Y-axis direction.

The OLED display according to an exemplary embodiment of the present invention can be applied to a portable terminal as shown in FIG. However, the present invention is not limited thereto, and the organic light emitting diode display according to an exemplary embodiment of the present invention can be applied to various kinds of electronic apparatuses that display information or display images through images.

2 is a block diagram showing an organic light emitting display according to an example of the present application.

The OLED display includes a display area DA, a control unit 10, a data driving circuit unit 20, and a scan driving circuit unit 30. The control unit 10, the data driving circuit unit 20 and the scan driving circuit unit 30 are formed in a single drive (not shown) mounted in an area outside the display area DA of the OLED display device, (Driver IC), which is a chip.

The display area DA includes a display area and a non-display area provided around the display area. The display area DA is an area where pixels P are provided to display an image. In the display area DA, scan lines SL1 to SLp for supplying scan signals, p is a positive integer of 2 or more, data lines DL1 to DLq for supplying data voltages, q is a positive integer of 2 or more, And driving power supply lines RL1 to RLq for supplying driving power. The data lines DL1 to DLq and the driving power lines RL1 to RLq may intersect the scan lines SL1 to SLp. The data lines DL1 to DLq and the driving power lines RL1 to RLq may be parallel to each other. The display area DA may include a lower substrate on which pixels P are provided and an upper substrate on which an encapsulation function is performed.

Each of the pixels P may be connected to any one of the scan lines SL1 to SLp and one of the data lines DL1 to DLq and one of the drive power lines RL1 to RLq have. Each of the pixels P may include an organic light emitting diode (OLED) and a pixel circuit for supplying current to the organic light emitting diode OLED.

The control unit 10 generates digital video data (DATA) for implementing an image in the organic light emitting display and timing signals for controlling timing for driving the organic light emitting display. The timing signal includes a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The control unit 10 uses the timing signals to generate a data control signal DCS for controlling the operation timing of the data driving circuit unit 20 and a scan control signal SCS for controlling the operation timing of the scan driving circuit unit 30 . The control unit 10 outputs the digital video data DATA and the data control signal DCS to the data driving circuit unit 20. The control unit 10 outputs the scan control signal SCS to the scan driving circuit unit 30.

The data driving circuit unit 20 receives the data control signal DCS from the control unit 10. The data driving circuit portion 20 generates data voltages based on the data control signal DCS. The data driving circuit unit 20 supplies the data voltages to the data lines DL1 to DLq.

The scan driving circuit unit 30 receives the scan control signal SCS from the control unit 10. The scan driving circuit unit 30 generates scan signals based on the scan control signal SCS. The scan driving circuit unit 30 supplies scan signals to the scan lines SL1 to SLp.

As described above, the control section 10, the data driving circuit section 20, and the scan driving circuit section 30 are mounted in an area outside the display area DA of the organic light emitting display device. At this time, the control unit 10, the data driving circuit unit 20, and the scan driving circuit unit 30 are driven by a gate drive in panel (GIP) method, which is an external area surrounding the display area DA Area. ≪ / RTI >

The driver IC for mounting the data driving circuit portion 20 and the scan driving circuit portion 30 may be connected to the flexible printed circuit board (FPCB). The flexible printed circuit board may be attached to the interior, front and back edge regions of the OLED display.

In this case, the control unit 10 can be mounted on the flexible printed circuit board and the data control signal DCS and the scan control signal SCS can be transferred to the driver IC on the control printed circuit board. The flexible printed circuit board is arranged in the folded state in the edge area inside the organic light emitting display. Therefore, the flexible printed circuit board can be mounted without providing a separate space inside the OLED display. In addition, when the control unit 10 is mounted on the flexible printed circuit board, the functions performed in the circuit inside the driving integrated circuit can be reduced, and the size of the driving integrated circuit can be reduced.

3 is a circuit diagram showing the pixel P in detail according to an example of the present application. The pixel P according to an exemplary embodiment of the present invention includes a driving transistor DT, an organic light emitting diode OLED, a storage capacitor Cst, and first through sixth transistors T1 through T6.

The driving transistor DT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the driving transistor DT is connected to the first node N1 to which the one electrode of the capacitor Cst, the drain electrode of the first transistor T1, and the source electrode of the fifth transistor T5 are connected. The source electrode of the driving transistor DT is connected to the drain electrode of the third transistor T3 which receives the pixel driving power supply VDD as a source electrode. The drain electrode of the driving transistor DT is connected to the source electrode of the fourth transistor T4.

And is turned on when a voltage higher than the threshold voltage is supplied to the gate electrode of the driving transistor DT. When the driving transistor DT is implemented as a P-type MOSFET, the turned-on driving transistor DT passes a driving current from the source electrode to the drain electrode.

The organic light emitting device OLED includes an anode electrode and a cathode electrode. The organic light emitting diode OLED supplies a driving current from the anode electrode to the cathode electrode. The anode electrode of the organic light emitting diode OLED is connected to the second node N2 to which the drain electrode of the fourth transistor T4 is connected. A cathode electrode of the organic light emitting diode OLED is connected to a ground line where a base voltage VSS is formed. The organic light emitting device OLED emits light with brightness corresponding to the driving current flowing from the driving transistor DT.

The organic light emitting diode OLED further includes a hole transporting layer, an organic light emitting layer, and an electron transporting layer. In the organic light emitting diode OLED, when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and holes and electrons combine with each other in the organic light emitting layer.

The storage capacitor Cst has both electrodes. One electrode of the storage capacitor Cst is connected to the first node N1. The other electrode of the storage capacitor Cst is connected to the pixel driving power supply line VDD.

The storage capacitor Cst stores the difference voltage between the pixel drive power supply VDD and the first node N1 when the fifth transistor T5 connected to the first node N1 is turned on. The storage capacitor Cst maintains the difference voltage stored in the first node N1 when the fifth transistor T5 is turned off. Further, the storage capacitor Cst can control driving of the driving transistor DT by using the stored and held voltage.

The gate electrode of the first transistor T1 receives the second scan signal SCAN2. The source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor DT. The drain electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 is turned on by the second scan signal SCAN2 so that the voltage of the first node N1 is VDATA which is the sum of the data voltage VDATA and the threshold voltage Vtp of the driving transistor DT. + Vtp.

The gate electrode of the second transistor T2 receives the second scan signal SCAN2. The source electrode of the second transistor T2 is connected to the data line DL to receive the data voltage VDATA. The drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor DT. The second transistor T1 is turned on by the second scan signal SCAN2 to supply the data voltage VDATA to the source electrode of the driving transistor DT.

The gate electrode of the third transistor T3 is supplied with the emission control signal EM. The source electrode of the third transistor T3 is supplied with the pixel driving power supply VDD. The drain electrode of the third transistor T3 is connected to the source electrode of the driving transistor DT. The third transistor T3 is turned on by the emission control signal EM to supply the pixel driving power supply VDD to the driving transistor DT so that the driving transistor DT allows the driving current to flow.

The gate electrode of the fourth transistor T4 is supplied with the emission control signal EM. The source electrode of the fourth transistor T4 is connected to the drain electrode of the driving transistor DT. The drain electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 is turned on by the emission control signal EM so that a driving current flows through the organic light emitting element OLED to emit the organic light emitting element OLED.

The gate electrode of the fifth transistor T5 receives the first scan signal SCAN1. The source electrode of the fifth transistor T5 is supplied with the initializing voltage Vinit. The drain electrode of the fifth transistor T5 is connected to the first node N1. The fifth transistor T5 is turned on by the first scan signal SCAN1 to initialize the voltage of the first node N1 to the initialization voltage Vinit.

The gate electrode of the sixth transistor T6 receives the first scan signal SCAN1. The source electrode of the sixth transistor T6 is supplied with the initializing voltage Vinit. The drain electrode of the sixth transistor T6 is connected to the second node N2. The sixth transistor T6 is turned on by the first scan signal SCAN1 to initialize the voltage of the second node N2 to the initializing voltage Vinit.

FIG. 4 is a waveform diagram illustrating input / output signals and voltages of each pixel of an OLED display according to an exemplary embodiment of the present invention. The driving transistor DT and the first to sixth transistors T1 to T6 in the pixel of the OLED display according to the exemplary embodiment of the present invention are implemented as a P-type MOSFET. Accordingly, when the first logic level L1 corresponding to the high logic level is supplied to the gate electrodes of the driving transistor DT and the first to sixth transistors T1 to T6, each transistor is turned off . Further, when the second logic level L2 corresponding to the low logic level is supplied to the gate electrodes of the driving transistor DT and the first to sixth transistors T1 to T6, each transistor is turned on.

In the first period S1, the first scan signal SCAN1, the second scan signal SCAN2, and the emission control signal EM are all at the first logic level L1. Thus, all the driving transistors DT and the first to sixth transistors T1 to T6 are turned off. The first node voltage VN1, which is the voltage of the first node N1, is zero.

In the second period S2, the first scan signal SCAN1 is the second logic level L2 and the second scan signal SCAN2 and the emission control signal EM are the first logic level L1. Thus, the fifth and sixth transistors T5 and T6 are turned on, and the driving transistor DT and the first to fourth transistors T1 to T4 maintain the turn-off state. The first node voltage VN1 is initialized to the initializing voltage Vinit by the fifth transistor T5. At the same time, the voltage of the second node N2 is also initialized to the initializing voltage Vinit by the sixth transistor T6.

In the third period S3, the first scan signal SCAN1, the second scan signal SCAN2, and the emission control signal EM are all at the first logic level L1. Thus, all the driving transistors DT and the first to sixth transistors T1 to T6 are turned off. At this time, the first node voltage VN1 maintains the initialization voltage Vinit by the storage capacitor Cst. Further, the data voltage VDATA fluctuates in order to transmit the input data (data).

In the fourth period S4, the second scan signal SCAN2 is the second logic level L2 and the first scan signal SCAN1 and the emission control signal EM are the first logic level L1. Accordingly, the first and second transistors T1 and T2 are turned on, and the driving transistor DT and the third to sixth transistors T3 to T6 maintain the turn-off state. The second transistor T2 supplies the data voltage VDATA to the source electrode of the driving transistor DT. At the same time, the first node voltage VN1 rises to VDATA + Vtp, which is the sum of the data voltage VDATA and the threshold voltage Vtp of the driving transistor.

The first scan signal SCAN1, the second scan signal SCAN2 and the emission control signal EM are all at the first logic level L1 in the fifth to seventh intervals S5 to S7. Thus, all the driving transistors DT and the first to sixth transistors T1 to T6 are turned off. At this time, the first node voltage VN1 maintains VDATA + Vtp which is the sum of the data voltage VDATA and the threshold voltage Vtp of the driving transistor by the storage capacitor Cst. Further, the data voltage VDATA is returned to the original voltage after transmitting the input data (data).

In the eighth period S8, the emission control signal EM is the second logic level L2 and the first scan signal SCAN1 and the second scan signal SCAN2 are the first logic level L1. The third and fourth transistors T3 and T4 are turned on and the driving transistor DT and the first, second, fifth and sixth transistors T1, T2, T5 and T6 are turned off . The third transistor T3 supplies the pixel driving voltage VDD to the source electrode of the driving transistor DT. At the same time, the driving current flows through the organic light emitting device OLED by the fourth transistor T4, causing the organic light emitting device OLED to emit light.

5 is a plan view showing an active layer 120 of a pixel of an OLED display according to an example of the present application. 5 to 8 show two pixels adjacent to each other in the X-axis and Y-axis directions. Accordingly, a total of four pixels P1 to P4 are adjacent to each other in a 2x2 structure. Further, the lower substrate 110 is not shown because it is confused when expressed on a plan view.

The active layer 120 is disposed from the upper left region where the sixth transistor T6 formed at the upper left corner is formed. The active layer 120 starts in the upper left region where the sixth transistor T6 is formed and extends in the first direction by the length of the sixth transistor T6. The first direction is a direction parallel to the direction in which the driving power supply line VDDL for supplying the pixel driving voltage VDD and the data line DL for supplying the data voltage VDATA are disposed in the Y axis direction.

The active layer 120 extends in a first direction and then extends in a second direction to an upper central region where the fifth transistor T5 is formed. The fifth transistor T5 is formed in the upper central region and divided into two regions. The two regions may be represented by the fifth-and fifth transistors T5-1 and T5-2, respectively. The second direction is a direction intersecting with the first direction in the Y axis direction and parallel to the direction in which the scan lines SL1 and SL2 for supplying the first and second scan signals SCAN1 and SCAN2 are arranged .

The active layer 120 extends in the direction opposite to the first direction by the length of the fifth transistor T5 in the upper central region where the fifth transistor T5 is formed, Lt; / RTI > Thereafter, the active layer 120 extends in a first direction to a region on which the first transistor T1 is formed and a region on a straight line parallel to the second direction. Thereafter, the active layer 120 extends in a direction opposite to the second direction and extends to a region where the first transistor T1 is formed. The first transistor T1 is formed in the left central region, and is formed in two regions. The two regions may be represented by the 1-1 and 1-2 transistors T1-1 and T1-2, respectively. Then, the active layer 120 extends in the first direction to the lower left region where the fourth transistor T4 is formed.

The active layer 120 extends in the first direction from the right central region where the second transistor T2 is formed to the right lower region which is the region where the third transistor T3 is formed.

The active layer 120 extends in the second direction between the region where the first transistor T1 is formed and the region where the fourth transistor T4 is formed and the region where the second transistor T2 is formed And extends in the direction opposite to the second direction between the regions where the third transistor T3 is formed. The active layer 120 is arranged in the form of a driving transistor DT in a region where the driving transistor DT and the storage capacitor Cst are formed.

In addition, the active layer 120 protrudes in the second direction in the region where the fourth transistor T4 is formed.

The active layer 120 may be formed of a metal oxide such as Zinc Oxide, Tin Oxide, Ga-In-Zn Oxide, In-Zn Oxide, or In-Sn Oxide, Zr, V, Hf, Ti, or the like. The active layer 120 changes into a channel layer, a drain layer, and a source layer. Each of the drain layer and the source layer is made conductive by a conducting process.

6 is a plan view showing an active layer 120 and a gate layer 140 of a pixel of an organic light emitting diode display according to an example of the present application. The gate insulating layer 130 which plays a role of preventing a short circuit between the active layer 120 and the gate layer 140 is not shown because it is confused when expressed on a plan view.

The gate layer 140 is disposed across the region where the sixth transistor T6 is formed and the region where the fifth transistor T5 is formed, in the second direction. The gate layer 140 arranged to cross the region where the sixth transistor T6 is formed and the region where the fifth transistor T5 is formed forms a first scan line for supplying the first scan signal SCAN1 .

In addition, the gate layer 140 is disposed across the region where the first transistor T1 is formed and the region where the second transistor T2 is formed, in the second direction. The gate layer 140 disposed to cross the region where the first transistor T1 is formed and the region where the second transistor T2 is formed forms a second scan line for supplying the second scan signal SCAN2 .

In addition, the gate layer 140 is disposed across the region where the third transistor T3 is formed and the region where the fourth transistor T4 is formed, in the second direction. The gate layer 140 disposed to cross the region where the third transistor T3 is formed and the region where the fourth transistor T4 is formed forms a light emission control line for supplying the light emission control signal EM.

Further, the gate layer 140 is disposed in a part of the region where the driving transistor DT is formed. The gate layer 140 disposed in a part of the region where the driving transistor DT is formed forms the lower electrode of the storage capacitor Cst.

The gate layer 140 functions as a lower gate metal layer forming the lower electrode of the first and second scan lines, the emission control line, and the storage capacitor Cst. The gate layer 140 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper And may be a single layer of the metal or alloy, or a multilayer of two or more layers.

7 is a plan view showing an active layer 120, a gate layer 140, and a first metal layer 160 of a pixel of an OLED display device according to an example of the present application. The first interlayer insulating film 150, which plays a role of preventing a short circuit between the gate layer 140 and the first metal layer 160, is not shown because it is confused when expressed on a plan view.

The first metal layer 160 is disposed in a part of the region where the driving transistor DT is formed. The first metal layer 160 disposed in a part of the region where the driving transistor DT is formed forms the upper electrode of the storage capacitor Cst.

In addition, the first metal layer 160 is disposed across the region where the sixth transistor T6 is formed and the region where the fifth transistor T5 is formed, in the second direction. The first metal layer 160 disposed to cross the region where the sixth transistor T6 is formed and the region where the fifth transistor T5 is formed forms an initialization line for supplying the initialization voltage Vinit.

The first metal layer 160 disposed to intersect the region where the sixth transistor T6 is formed and the region where the fifth transistor T5 is formed may be divided into a region where the sixth transistor T6 is formed and a region where the fifth transistor T5 Are not overlapped with the gate layer 140 disposed so as to cross the region in which the gate electrode 140 is formed.

The first metal layer 160 disposed to cross the region where the fifth transistor T5 is formed is electrically connected to the active layer 120 through the first contact hole CNT1 on the region where the fifth transistor T5 is formed. Respectively. The first contact hole CNT1 is formed through the gate insulating film 130. [ To this end, the gate insulating layer 130 is formed and then the contact hole process is performed once to directly connect the first metal layer 160 and the active layer 120 through the first contact hole CNT1.

The organic light emitting diode display according to the present invention uses the first contact hole CNT1 to connect the first metal layer 160 supplying the initialization voltage Vint to the active layer 120 without using the source / Can be directly connected. Thus, the source / drain layer 180, which was arranged to supply the initialization voltage Vint, can be omitted. In the case of omitting the source / drain layer 180 arranged to supply the initialization voltage Vint, it is possible to increase the degree of freedom in designing the pixel used in the model of the ultra-high resolution organic light emitting display device, It can be easily manufactured.

In addition, the first metal layer 160 connects the region where the third transistor T3 of the arbitrary pixel is formed and the region where the fourth transistor T4 of another pixel adjacent to the arbitrary pixel is formed. For example, the first metal layer 160 connects a region where the third transistor T3 of the first pixel P1 is formed and a region where the fourth transistor T4 of the second pixel P2 is formed.

The first metal layer 160 is electrically connected to the active layer 120 in the region where the third transistor T3 is formed through the second contact hole CNT2. The first metal layer 160 may supply a direct voltage to the active layer 120 in the region where the third transistor T3 of any pixel is formed.

The first metal layer 160 serves as a top metal layer, that is, an upper metal layer. The first metal layer 160 may be formed of at least one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Alloy, and may be composed of a single layer of the metal or alloy or multiple layers of two or more layers.

8 is a plan view of a pixel of an organic light emitting diode display according to an example of the present application.

8 and 9, a pixel of an OLED display according to an exemplary embodiment of the present invention includes an active layer 120, a gate layer 140, a first metal layer 160, and a source / drain layer 180, . The second interlayer insulating film 170, which serves to prevent a short circuit between the first metal layer 160 and the source / drain layer 180, is not shown because it is confused when expressed on a plan view.

The source / drain layer 180 is disposed in the first direction so as to cross the region where the sixth transistor T6, the first transistor T1, and the fourth transistor T4 are formed. The source / drain layer 180 disposed to cross the region where the sixth transistor T6, the first transistor T1 and the fourth transistor T4 are formed forms a driving power supply line VDDL. The source / drain layer 180 forming the driving power supply line VDDL is supplied with the pixel driving power supply VDD from the data driving circuit portion 20.

The source / drain layer 180 forming the driving power supply line VDDL branches in the second direction in the region where the first transistor T1 is formed. The source / drain layer 180 branched in the second direction is connected to the active layer 120 in the region where the driving transistor DT is formed through the third contact hole CNT. The source / drain layer 180 may supply the pixel driving power source VDD to the active layer 120 through the third contact hole CNT.

The source / drain layer 180 forming the driving power supply line VDDL is connected to the first metal layer 160 through the fourth contact hole CNT4 in the region where the fourth transistor T4 is formed. The source / drain layer 180 forming the driving power supply line VDDL supplies the pixel driving power VDD to the first metal layer 160. Accordingly, the first metal layer 160 connected to the source / drain layer 180 forming the driving power supply line VDDL of a certain pixel is connected to the third transistor T3 of another adjacent pixel to supply the pixel driving power VDD Can supply.

The source / drain layer 180 for supplying the pixel driving power supply VDD in any pixel is connected to the source / drain layer 180 for supplying the data voltage VDATA, (180). Accordingly, it is possible to easily secure a space in which the storage capacitor Cst can be arranged in the pixel used in the ultra-high resolution organic light emitting display device model.

The source / drain layer 180 connects the region where the fifth transistor T5 is disposed and the region where the driving transistor DT is disposed. The source / drain layer 180 connecting the region where the fifth transistor T5 is arranged and the region where the driving transistor DT is arranged is arranged in an island type. The source / drain layer 180 connecting the region where the fifth transistor T5 is disposed and the region where the driving transistor DT is disposed is connected to the fifth contact hole CNT5 provided in the region where the fifth transistor T5 is disposed. And a sixth contact hole CNT6 provided in a region where the driving transistor DT is disposed.

In addition, the source / drain layer 180 is disposed in the first direction so as to cross the region where the second transistor T2 and the third transistor T3 are formed. The source / drain layer 180 disposed to cross the region where the second transistor T2 and the third transistor T3 are formed forms a data line DL. The source / drain layer 180 forming the data line DL supplies the data voltage VDATA to the pixel. Is connected to the active layer 120 in the region where the second transistor T2 is disposed through the seventh contact hole CNT7 of the source / drain layer 180 forming the data line DL.

In addition, the source / drain layer 180 is disposed in the region adjacent to the fourth transistor T4 and the driving transistor DT. The source / drain layer 180 disposed in the region adjacent to the fourth transistor T4 and the driving transistor DT is arranged in an island type. The source / drain layer 180 disposed in the region adjacent to the fourth transistor T4 and the driving transistor DT is electrically connected to the active layer 120 in the region where the fourth transistor T4 is disposed through the eighth contact hole CNT8 ).

9 is a cross-sectional view showing I-I` of FIG. The organic light emitting display according to the present invention includes a lower substrate 110, an active layer 120, a gate insulating layer 130, a first interlayer insulating layer 150, a first metal layer 160, a second interlayer insulating layer 170, A source / drain layer 180, a planarization layer 190, an anode electrode 200, and an upper layer 210.

The lower substrate 110 forms the lowest layer of the organic light emitting display. The lower substrate 110 may be formed of glass. Alternatively, the lower substrate 110 may be formed of flexible plastic so that the OLED display is flexible.

The active layer 120 is disposed on top of the lower substrate 110. The active layer 120 is disposed in a region where the fifth and sixth transistors T5 and T6 are formed. The active layer 120 forms a channel layer, a drain layer, and a source layer of the fifth and sixth transistors T5 and T6. The active layer 120 may be formed of a metal oxide such as Zinc Oxide, Tin Oxide, Ga-In-Zn Oxide, In-Zn Oxide, or In-Sn Oxide, Zr, V, Hf, Ti, or the like. The active layer 120 changes into a channel layer, a drain layer, and a source layer. Each of the drain layer and the source layer is made conductive by a conducting process.

The gate insulating layer 130 is disposed on the lower substrate 110 and the active layer 120. The gate insulating film 130 covers the active layer 120 as a whole. The gate insulating film 130 is formed of a material having excellent insulating properties. The gate insulating layer 130 electrically separates the active layer 120 from the layer disposed thereon. The gate insulating layer 130 is formed to a thickness of 1300 ANGSTROM to 1500 ANGSTROM or less.

The first interlayer insulating film 150 is disposed on the gate insulating film 130. The first interlayer insulating film 150 is formed of a material having excellent insulating properties. The first interlayer insulating layer 150 electrically isolates a layer disposed on the first interlayer insulating layer 150 and a layer disposed on the lower portion of the first interlayer insulating layer 150. The first interlayer insulating film 150 is formed to a thickness of 1200 ANGSTROM to 1300 ANGSTROM or less.

The first metal layer 160 is disposed on the first interlayer insulating film 150. The first metal layer 160 overlaps the fifth and sixth transistors T5 and T6 provided in the plurality of pixels arranged in the second direction. The first metal layer 160 is electrically connected to the active layer 120 through the first contact hole CNT1 in the region where the fifth transistor T5 is disposed. The first metal layer 160 supplies the initialization voltage Vini to the fifth transistor T5 in the plurality of pixels arranged in the second direction.

The first contact hole CNT 1 is formed through the gate insulating film 130 and the first interlayer insulating film 150. The first metal layer 160 is disposed on the active layer 120 in the first contact hole CNT1 and on the side walls of the first contact hole CNT1. The first contact hole CNT1 is formed to have a thickness of 2500A to 2800A. The first contact hole CNT1 is formed by adding a contact hole process after the first interlayer insulating layer 150 is formed and before the first metal layer 160 is formed.

The second interlayer insulating film 170 is disposed on the first metal layer 160. The second interlayer insulating film 170 is formed of a material having excellent insulating properties. The second interlayer insulating film 170 electrically isolates the layer disposed above the second interlayer insulating film 170 and the layers disposed below the second interlayer insulating film 170. The second interlayer insulating film 150 is formed to a thickness of 5500 angstroms or more and 6500 angstroms or less.

The source / drain layer 180 is disposed on the second interlayer insulating film 170. The source / drain layer 180 forms a driving power supply line VDDL for supplying the pixel driving power supply VDD and a data line DL for supplying the data voltage VDATA.

The planarizing film 190 is disposed on the second interlayer insulating film 170 and the source / drain layer 180. The planarizing film 190 reduces the height difference of the top. Accordingly, it is possible to prevent the flattening film 190 from generating a deviation in height in the Z-axis direction with respect to the lower substrate 110 according to the region.

The anode electrode 200 is disposed on the planarization film 190. The anode electrode 200 forms the anode electrode of the organic light emitting diode OLED according to the present application. The anode electrode 200 receives the pixel driving voltage VDD and the data voltage VDATA and supplies the pixel driving voltage VDD and the data voltage VDATA to the organic light emitting diode OLED.

The upper layer 210 is disposed on the upper portion of the anode electrode 200. The upper layer 210 includes an organic light emitting layer and a cathode electrode constituting the organic light emitting diode (OLED). The upper layer 210 emits light with a predetermined brightness according to the pixel driving voltage VDD and the data voltage VDATA supplied to the anode electrode 200.

10 is a cross-sectional view showing II-II` of FIG. The organic light emitting display according to the present invention includes a lower substrate 110, an active layer 120, a gate insulating layer 130, a gate layer 140, a first interlayer insulating layer 150, a first metal layer 160, An interlayer insulating film 170, a source / drain layer 180, a planarization film 190, an anode electrode 200, and an upper layer 210.

The gate insulating layer 130 is disposed on the lower substrate 110 and the active layer 120. The gate insulating film 130 is removed at the point where the first and third contact holes CNT1 and CNT3 are formed. The gate insulating layer 130 is formed to a thickness of 1300 ANGSTROM to 1500 ANGSTROM or less.

The gate layer 140 is disposed on the gate insulating layer 130. The gate layer 140 constitutes first and second scan lines for supplying the first and second scan signals SCAN1 and SCAN2. The gate layer 140 constituting the first scan line is disposed on a region where the fifth transistor T5 is formed. The gate layer 140 constituting the second scan line is disposed on a region adjacent to the first transistor T1.

The first interlayer insulating film 150 is formed on the gate insulating film 130 and the gate layer 140. The first interlayer insulating film 150 is removed at the point where the first and third contact holes CNT1 and CNT3 are formed. The first interlayer insulating film 150 is formed of a material having excellent insulating properties. The first interlayer insulating film 150 electrically separates the gate layer 140 from the layer disposed thereon. The first interlayer insulating film 150 is formed to a thickness of 1200 ANGSTROM to 1300 ANGSTROM or less.

The first metal layer 160 is disposed inside the first contact hole CNT1. The first metal layer 160 is electrically connected to the active layer 120 disposed on the region where the fifth transistor T5 is formed. The first metal layer 160 supplies the initialization voltage Vinit to the active layer 120 disposed on the region where the fifth transistor T5 is formed. Since the first contact hole CNT1 penetrates the gate insulating layer 130 and the first interlayer insulating layer 150, the first contact hole CNT1 is formed to have a thickness of 2500 ANGSTROM to 2800 ANGSTROM.

A second interlayer insulating film 170 is formed on the first interlayer insulating film 150 and the first metal layer 160. The second interlayer insulating film 170 is formed of a material having excellent insulating properties. The second interlayer insulating film 170 electrically isolates the first metal layer 160 from the layer disposed thereon. The second interlayer insulating film 150 is formed to a thickness of 5500 angstroms or more and 6500 angstroms or less.

The source / drain layer 180 is disposed inside the third contact hole CNT3. The source / drain layer 180 is electrically connected to the active layer 120 disposed on the region where the driving transistor TD is formed. The source / drain layer 180 supplies the pixel driving voltage VDD to the active layer 120 disposed on the region where the driving transistor TD is formed. The third contact hole CNT3 penetrates the gate insulating film 130, the first interlayer insulating film 150, and the second interlayer insulating film 170, so that the third contact hole CNT3 has a thickness of 8000 ANGSTROM or more and 9300 ANGSTROM or less.

The planarizing film 190 is disposed on the second interlayer insulating film 170 and the source / drain layer 180. The planarizing film 190 reduces the height difference of the top. Accordingly, it is possible to prevent the flattening film 190 from generating a deviation in height in the Z-axis direction with respect to the lower substrate 110 according to the region.

The anode electrode 200 is disposed on the planarization film 190. The anode electrode 200 forms the anode electrode of the organic light emitting diode OLED according to the present application. The anode electrode 200 receives the pixel driving voltage VDD and the data voltage VDATA and supplies the pixel driving voltage VDD and the data voltage VDATA to the organic light emitting diode OLED.

The upper layer 210 is disposed on the upper portion of the anode electrode 200. The upper layer 210 includes an organic light emitting layer and a cathode electrode constituting the organic light emitting diode (OLED). The upper layer 210 emits light with a predetermined brightness according to the pixel driving voltage VDD and the data voltage VDATA supplied to the anode electrode 200.

8, the first metal layer 160 of the present application has a region where the third transistor T3 of an arbitrary pixel is arranged and a region where the third transistor T3 of another pixel is adjacent to another pixel And the fourth transistor T4 of the second transistor T3 are arranged. The first metal layer 160 connecting the region where the third transistor T3 of the arbitrary pixel is arranged and the region where the fourth transistor T4 of another pixel adjacent to the arbitrary pixel is arranged is connected to the light- Respectively.

The first metal layer 160 connecting between the light emitting transistors of adjacent pixels is formed as an island type. Accordingly, the first metal layer 160 connecting between the light emitting transistors of the adjacent pixels is affected only by the pixel driving power supply VDD and the emission control signal EM. The first metal layer 160 connecting between the light emitting transistors of the pixels adjacent to each other is not affected by the influence of the first and second scan signals SCAN1 and SCAN2 or the data voltage VDATA.

The first metal layer 160 is connected to the active layer 120 through the second contact hole CNT2 in the region where the third transistor T3 of any pixel is disposed. The second contact hole CNT2 has a structure in which the first metal layer 160 and the active layer 120 are directly connected. Accordingly, the second contact hole CNT2 has the same structure as the first contact hole CNT1. Since the second contact hole CNT2 penetrates the gate insulating layer 130 and the first interlayer insulating layer 150, the second contact hole CNT2 is formed to have a thickness of 2500 angstroms or more and 2800 angstroms or less.

Also, the first metal layer 160 is connected to the source / drain layer 180 through the fourth contact hole CNT4 in an area disposed in the fourth transistor T4 of another pixel adjacent to any pixel. The source / drain layer 180 is a driving power supply line (VDDL) for supplying a pixel driving power supply (VDD) to another pixel adjacent to a certain pixel. The first metal layer 160 receives the pixel driving power supply voltage VDD from the driving power supply line VDDL. Accordingly, the first metal layer 160 can supply the pixel driving power supply voltage VDD to the third transistor T3 of an arbitrary pixel.

The first metal layer 160 is connected to the source / drain layer 180 in a region disposed in the fourth transistor T4 of another pixel adjacent to any pixel. Accordingly, the fourth contact hole CNT4 is formed through the second interlayer insulating film 170. [ Since the fourth contact hole CNT4 penetrates the second interlayer insulating film 170, the fourth contact hole CNT4 is formed to have a thickness of 5500 angstroms or more and 6500 angstroms or less.

Accordingly, the first pixel electrode 160 can be used to use the pixel-driving power supply VDD of the adjacent pixel, and the driving power supply line VDD can be disposed within the pixel at a distance from the data line DL . Accordingly, the driving power supply line VDD and the data line DL can be arranged on both sides of the pixel, and the driving transistor DT and the storage capacitor Cst can be arranged in the central region of the pixel. Accordingly, even when the physical size of a pixel is reduced due to application to an ultra-high resolution organic light emitting display, the minimum size of the driving transistor DT and the storage capacitor Cst can be secured, It is possible to facilitate the design of the pixel.

The organic light emitting display according to the exemplary embodiments of the present invention may replace the initialization line made up of the conventional source / drain layer having a plurality of initialization lines as a first metal layer which is different from a plurality of driving power lines. Accordingly, the present application can secure an area for designing a driving transistor and a storage capacitor in a pixel even in an ultra-high resolution organic light emitting display device in which the size of a pixel and the interval between pixels are reduced.

In the organic light emitting diode display according to the examples of the present application, a plurality of driving power supply lines and a plurality of data lines are spaced apart from each other in a certain pixel to secure an area where the driving transistor and the storage capacitor are disposed at the center of the pixel . Accordingly, the present application can secure an area for designing a driving transistor and a storage capacitor in a pixel even in an ultra-high resolution organic light emitting display device in which the size of a pixel and the interval between pixels are reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

DA: display area NDA: non-display area
10: control unit 20: data driving circuit
30: scan drive circuit P: pixel
T1 to T6: first to sixth transistors DT: driving transistor
Cst: Storage capacitor OLED: Organic light emitting device
P1 to P4: first and fourth pixels 110: lower substrate
120: active layer 130: gate insulating film
140: gate layer 150: first interlayer insulating film
160: first metal layer 170: second interlayer insulating film
180: source / drain layer 190: planarization layer
200: anode electrode 210: upper layer

Claims (15)

A plurality of pixels each having a pixel circuit including a driving transistor and a storage capacitor for controlling an electric current flowing through the organic light emitting element;
A plurality of driving power supply lines provided along the first direction and supplying pixel driving power to the plurality of pixels;
A plurality of data lines provided along the first direction and supplying data voltages to the plurality of pixels; And
And a plurality of initialization lines provided along a second direction intersecting the first direction and supplying an initialization voltage to the plurality of pixels,
Wherein the plurality of initialization lines comprise a first metal layer which is different from a source / drain layer constituting the plurality of driving power supply lines,
One of the plurality of driving power supply lines and one of the plurality of data lines may be disposed on both sides of the driving transistor and the storage capacitor arranged in any one of the plurality of pixels Organic light emitting display. The method according to claim 1,
Each of the plurality of pixels further includes a plurality of transistors for controlling driving of the driving transistor,
Wherein the plurality of initialization lines are electrically connected to a transistor that supplies the initializing voltage to the driving transistor among the plurality of transistors. The method according to claim 1,
Wherein the first metal layer constituting the plurality of initialization lines is connected to the active layer of the fifth transistor that supplies the initializing voltage to the driving transistor through the first contact hole. The method of claim 3,
Wherein the first contact hole is formed through a gate insulating film provided on the active layer and a first interlayer insulating film disposed under the first metal layer. The method according to claim 1,
And the driving power line is connected to an active layer constituting the driving transistor by using a third contact hole. 6. The method of claim 5,
And the third contact hole is formed through a gate insulating film provided on the active layer and first and second interlayer insulating films disposed under the source / drain layer. delete The method according to claim 1,
Wherein any one of the plurality of pixels is supplied with the pixel driving power from a driving power supply line passing through another pixel adjacent to the arbitrary pixel. The method according to claim 1,
And the emission control transistor of any one of the plurality of pixels is connected to the driving power supply line of another pixel adjacent to the arbitrary pixel to the first metal layer. 10. The method of claim 9,
Wherein the first metal layer connecting the adjacent pixels is connected to the active layer constituting the emission control transistor of the arbitrary pixel by using the second contact hole. 11. The method of claim 10,
And the second contact hole is formed through a gate insulating film provided on the active layer and a first interlayer insulating film disposed under the first metal layer. 10. The method of claim 9,
And the first metal layer connecting the adjacent pixels is connected to a source / drain layer constituting a driving power supply line of the other pixel using a fourth contact hole. 13. The method of claim 12,
And the fourth contact hole is formed through a second interlayer insulating film disposed on the upper portion of the first metal layer. A plurality of pixels each having a pixel circuit including a driving transistor and a storage capacitor for controlling an electric current flowing through the organic light emitting element;
A plurality of driving power supply lines provided along the first direction and supplying pixel driving power to the plurality of pixels; And
And a plurality of data lines provided along the first direction and supplying data voltages to the plurality of pixels,
One of the plurality of driving power supply lines and one of the plurality of data lines may be disposed on both sides of the driving transistor and the storage capacitor arranged in any one of the plurality of pixels Organic light emitting display. 15. The method of claim 14,
Wherein the pixel driving power is supplied to the emission control transistors of other pixels adjacent to the arbitrary pixel by using a first metal layer which is different from a source / drain layer constituting the driving power supply line.

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