CN113990902A

CN113990902A - Display panel and display device

Info

Publication number: CN113990902A
Application number: CN202111207173.7A
Authority: CN
Inventors: 王铸; 石领; 闫政龙
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-10-15
Filing date: 2021-10-15
Publication date: 2022-01-28

Abstract

A display panel and a display device, wherein the display panel includes: a display area and a non-display area surrounding the display area, the display area including: a first display area and a second display area located at least one side of the first display area; the second display area includes: the display device comprises a first area and a second area which are arranged at intervals, wherein the first area and the second area are arranged along a first direction, and a first display area is positioned between the first area and the second area; the display panel includes: the circuit structure layer and the light emitting structure layer are sequentially stacked on the substrate; the circuit structure layer includes: a plurality of driving circuits and a plurality of data signal lines extending in a second direction, the light emitting structure layer including: a plurality of light emitting elements; the data signal line is set up as to provide the data signal to the drive circuit, the drive circuit is set up as to drive the luminescent element to illuminate, the first direction and second direction intersect; the light emitting elements are located in the first display area and the second display area, and the driving circuit is located in the first area and the second area.

Description

Display panel and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, in particular to a display panel and a display device.

Background

Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, very high response speed, thinness, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting element and using a Thin Film Transistor (TFT) for signal control has become a mainstream product in the Display field at present.

At present, the concept of a full-screen mobile phone has received wide attention in the mobile phone market, and is also the development direction of future mobile phones. In the full-screen mobile phone, the camera can be hidden so that the front visible area is almost the screen, and therefore a user can obtain a better display effect.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

In a first aspect, the present disclosure provides a display panel comprising: a display area and a non-display area surrounding the display area, the display area including: the display device comprises a first display area and a second display area positioned on at least one side of the first display area; the second display area includes: the display device comprises a first area and a second area which are arranged at intervals, wherein a first display area is positioned between the first area and the second area;

the display panel includes: the LED display panel comprises a substrate, and a circuit structure layer and a light emitting structure layer which are sequentially stacked on the substrate; the circuit structure layer includes: a plurality of driving circuits and a plurality of data signal lines extending in a second direction, the light emitting structure layer including: a plurality of light emitting elements; the data signal line is configured to provide a data signal to a driving circuit, the driving circuit is configured to drive the light emitting element to emit light, and the first direction and the second direction intersect;

the light emitting elements are located in the first display area and the second display area, and the driving circuit is located in the first area and the second area.

In some possible implementations, a length of the first display area along the second direction is less than or equal to a length of the second display area along the second direction.

In some possible implementations, a length of the driving circuit in the first direction is smaller than a length of a light emitting element to which the driving circuit is connected in the first direction.

In some possible implementations, the driving circuit includes: a first driving circuit and a second driving circuit;

the first driving circuit is connected with a first light emitting element, the second driving circuit is connected with a second light emitting element, the first light emitting element is a light emitting element located in the second display area, and the second light emitting element is a light emitting element located in the first display area.

In some possible implementations, the driving circuit includes: first to seventh transistors; the light emitting element includes: an anode, an organic light emitting layer, and a cathode; a second electrode of a sixth transistor of the driving circuit is connected to an anode of the light emitting element;

and the orthographic projection of the second pole of the sixth transistor of the driving circuit on the substrate and the orthographic projection of the anode of the light-emitting element connected with the driving circuit on the substrate do not have an overlapping area.

In some possible implementations, the circuit structure layer further includes: a plurality of first junctions between a second electrode of the sixth transistor of the first driving circuit and an anode of the first light emitting element;

the first driving circuit is connected with the first light-emitting element through the first switching part, the orthographic projection of the first switching part on the substrate is at least partially overlapped with the orthographic projection of the second pole of the sixth transistor of the first driving circuit connected with the first switching part on the substrate, and the orthographic projection of the anode of the first light-emitting element connected with the first connecting part on the substrate is at least partially overlapped;

the first transfer part is made of materials including: a metal.

In some possible implementations, the circuit structure layer further includes: a plurality of second switching parts, wherein the second switching parts are positioned between a second pole of a sixth transistor of the second driving circuit and an anode of the second light-emitting element;

the second driving circuit is connected with the second light-emitting element through the second adapter part, the orthographic projection of the second adapter part on the substrate is at least partially overlapped with the orthographic projection of a second pole of a sixth transistor of the second driving circuit connected with the second adapter part on the substrate, and the orthographic projection of an anode of the second light-emitting element connected with the second connecting part on the substrate is at least partially overlapped;

the second adapter part is made of a material comprising: a transparent conductive material.

In some possible implementations, the second transition portion is disposed on the same layer as the first transition portion, or disposed on a different layer.

In some possible implementations, when the length of the first display area in the second direction is smaller than the length of the second display area in the second direction, the second display area further includes: a third region, the third region being located between the first region and the second region, the third region being surrounded outside the first display region;

the first region and the second region are symmetrically disposed along a centerline of the third region.

In some possible implementations, the circuit structure layer further includes: n rows of first dummy driving circuits;

the N rows of first dummy driving circuits are positioned in the third area, N is a positive integer greater than or equal to M, and M is the number of rows of light-emitting elements in the first display area;

the length of the first dummy drive circuit in the first direction is greater than or equal to the length of the drive circuit in the first direction.

In some possible implementations, the first region and the third region are symmetrically disposed along a centerline of the second region.

In some possible implementations, the first region includes: s first subregions are sequentially arranged along a first direction;

the adjacent first sub-areas are arranged at intervals.

In some possible implementations, the circuit structure layer further includes: at least one column of second dummy drive circuits located between adjacent first sub-regions.

In some possible implementations, the second region includes: the T second subregions are sequentially arranged along the first direction;

and the adjacent second sub-areas are arranged at intervals.

In some possible implementations, the circuit structure layer further includes: at least one column of third dummy drive circuits located between adjacent second sub-regions.

In some possible implementations, S ═ T.

In some possible implementations, the data signal line is located in the first region and the second region;

the driving circuits in the same column are connected to the same data signal line.

In some possible implementations, the circuit structure layer further includes: a plurality of first power lines extending in a second direction; the first power line is located in the first region and the second region;

when the driving circuits in the same column include the first driving circuits and the second driving circuits, the first driving circuits at two sides of the second driving circuits are respectively connected with different first power lines.

In some possible implementations, the circuit structure layer further includes: a plurality of second power lines; the second power line is positioned on one side of the first power line far away from the substrate;

the second driving circuits positioned in the same column are connected with the same second power line;

the voltage value of the signal of the second power line is greater than the voltage value of the signal of the first power line.

In some possible implementations, when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the second power line is located in the first area and the second area and extends along the second direction.

In some possible implementations, when the length of the first display area in the second direction is smaller than the length of the second display area in the second direction, each of the second power lines includes: the power supply comprises a first power supply section, a second power supply section, a third power supply section, a fourth power supply section and a fifth power supply section which are connected in sequence; the first, third and fifth power sections extend in the second direction, the second and fourth power sections extend in a first direction;

for each second power line, the first power supply segment and the fifth power supply segment are located in the third region;

for a second power line connected with a second driving circuit located in a first area, a second power supply section and a fourth power supply section are located in the first area and a third area, and a third power supply section is located in the first area;

for a second power line connected to a second driving circuit located in a second region, a second power segment and a fourth power segment are located in the second region and the third region, and a third power segment is located in the second region.

In some possible implementations, the display panel further includes: the first power supply connecting line and the second power supply connecting line are positioned in the non-display area; the first power supply connecting wire and the second power supply connecting wire are arranged on the same layer, and are arranged on the same layer as the second power supply wire;

when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first power supply connecting line is respectively connected with two ends of at least one second power supply line positioned in the first area, and the second power supply connecting line is respectively connected with two ends of at least one second power supply line positioned in the second area;

when the length of the first display area along the second direction is smaller than the length of the second display area along the second direction, the first power supply connecting line is respectively connected with a first power supply section and a fifth power supply section of at least one second power supply line connected with a second driving circuit positioned in the first area; the second power connecting line is respectively connected with a first power section and a fifth power section of at least one second power line connected with a second driving circuit positioned in the second area.

In some possible implementations, the display area includes: first and second oppositely disposed sides and third and fourth oppositely disposed sides;

the first power connection line includes: the first connecting section, the second connecting section, the third connecting section, the fourth connecting section and the fifth connecting section are connected in sequence; the first connecting section and the second connecting section are positioned on the first side of the display area, the third connecting section is positioned on the third side of the display area, and the fourth connecting section and the fifth connecting section are positioned on the second side of the display area; the first connecting section, the third connecting section and the fifth connecting section extend along the second direction, and the second connecting section and the fourth connecting section extend along the first direction;

when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first connecting section is connected with one end of at least one second power line located in the first area, and the fifth connecting section is connected with the other end of at least one second power line located in the first area;

when the length of the first display area along the second direction is smaller than the length of the second display area along the second direction, the first connecting section is connected with at least one first power section of a second power line connected with a second driving circuit located in the first area, and the fifth connecting section is connected with at least one fifth power section of the second power line connected with the second driving circuit located in the first area.

In some possible implementations, the second power connection line includes: the sixth connecting section, the seventh connecting section, the eighth connecting section, the ninth connecting section and the tenth connecting section are connected in sequence; the sixth connecting segment and the seventh connecting segment are located on a first side of the display area, the eighth connecting segment is located on a fourth side of the display area, and the ninth connecting segment and the tenth connecting segment are located on a second side of the display area; the sixth connecting section, the eighth connecting section and the tenth connecting section extend along the second direction, and the seventh connecting section and the ninth connecting section extend along the first direction;

when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the sixth connecting section is connected with one end of at least one second power line located in the second area, and the tenth connecting section is connected with the other end of at least one second power line located in the second area;

when the length of the first display area along the second direction is smaller than the length of the second display area along the second direction, the sixth connecting section is connected with at least one first power section of a second power line connected with a second driving circuit located in the second area, and the tenth connecting section is connected with at least one fifth power section of the second power line connected with the second driving circuit located in the second area.

In some possible implementations, the circuit structure layer includes: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer;

the first power line is positioned on the first conductive layer and/or the second conductive layer; the second power line and the first junction are located on the third conductive layer; the second switching part is positioned on the fourth conducting layer;

the first conductive layer, the second conductive layer and the third conductive layer are metal conductive layers, and the fourth conductive layer is a transparent conductive layer.

In some possible implementations, the circuit structure layer includes: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer;

the first power line is positioned on the first conductive layer and/or the second conductive layer; the second power line, the first transition portion and the second transition portion are located on the third conductive layer;

the first conductive layer and the second conductive layer are metal conductive layers.

In some possible implementations, the first display area is a transparent display area;

the resolution of the first display area is the same as the resolution of the second display area, or the resolution of the first display area is different from the resolution of the second display area.

In a second aspect, the present disclosure also provides a display device, including: the display panel is provided.

In some possible implementations, the method further includes: the photosensitive sensor is located in a first display area of the display panel.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not limit the disclosure.

Fig. 1A is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

fig. 1B is another schematic structural diagram of a display panel according to an embodiment of the disclosure;

FIG. 2A is a cross-sectional view of the display panel provided in FIG. 1A;

FIG. 2B is a cross-sectional view of the display panel provided in FIG. 1B;

fig. 3 is a schematic layout diagram of light emitting elements of a display panel according to an exemplary embodiment;

fig. 4 is a schematic arrangement diagram of light emitting elements of a display panel according to another exemplary embodiment;

FIG. 5 is an equivalent circuit diagram of a driving circuit;

FIG. 6 is a timing diagram of the operation of a driving circuit;

FIG. 7 is a dimensional comparison diagram of a driver circuit and a reference driver circuit in a display panel provided in an exemplary embodiment;

FIG. 8A is a schematic diagram of a display panel according to an exemplary embodiment;

fig. 8B is a schematic structural diagram of a display panel according to another exemplary embodiment;

FIG. 9 is a cross-sectional view of a display panel provided in an exemplary embodiment;

FIG. 10 is a schematic diagram of the arrangement of the first junctions in each of the first sub-regions provided by an exemplary embodiment;

FIG. 11 is an enlarged view of region R of FIG. 10;

fig. 12A is a schematic structural diagram of a display panel according to still another exemplary embodiment;

fig. 12B is a schematic structural diagram of a display panel according to still another exemplary embodiment;

FIG. 13 is a schematic diagram of a second power line according to an exemplary embodiment;

FIG. 14 is a schematic diagram of a first power connection provided in an exemplary embodiment;

fig. 15 is a schematic structural diagram of a second power connection line according to an exemplary embodiment.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict. To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and known components has been omitted from the present disclosure. The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design

In the drawings, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided to avoid mixing of the constituent elements, and are not limited in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electric function" is not particularly limited as long as it can transmit and receive an electric signal between components to be connected. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

"about" in this disclosure means a numerical value within the bounds of not narrowly defined tolerances, which allow for process and measurement error.

A display panel comprises a transparent display area, and data signal lines need to be wired by bypassing the transparent display area, so that the wiring difficulty of the data signal lines is increased.

Fig. 1A is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure, fig. 1B is another schematic structural diagram of the display panel provided in the embodiment of the present disclosure, fig. 2A is a cross-sectional view of the display panel provided in fig. 1A, and fig. 2B is a cross-sectional view of the display panel provided in fig. 1B. As shown in fig. 1 and 2, a display panel provided by an embodiment of the present disclosure may include: a display area AA and a non-display area (not shown in the drawings) surrounding the display area. Wherein, the display area AA includes: a first display region a1 and a second display region a2 positioned at least one side of the first display region a 1; the second display area a2 includes: the first region R1 and the second region R2 are spaced apart, the first region R1 and the second region R2 are arranged along the first direction D1, and the first display region a1 is located between the first region R1 and the second region R2.

In one exemplary embodiment, the display panel may include: a substrate 10, and a circuit structure layer 20 and a light emitting structure layer 30 sequentially stacked on the substrate. Wherein, the circuit structure layer may include: a plurality of driving circuits PA and a plurality of data signal lines D extending in a second direction D2, the light emitting structure layer may include: a plurality of light emitting elements; the data signal line D is provided to supply a data signal to the driving circuit PA, and the driving circuit PA is provided to drive the light emitting element to emit light, and the first direction D1 and the second direction D2 intersect.

The light emitting elements are positioned in the first display area a1 and the second display area a2, and the driving circuit PA is positioned in the first region R1 and the second region R2.

In one exemplary embodiment, the substrate 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass, metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

In an exemplary embodiment, the display panel may further include: a time sequence controller, a data driving circuit, a scanning driving circuit and a light-emitting driving circuit which are positioned in the non-display area. The display panel may further include a plurality of scan signal lines and a plurality of light emitting signal lines in the display area.

In one exemplary embodiment, the timing controller may supply a gray scale value and a control signal suitable for the specification of the data driving circuit to the data driving circuit, may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driving circuit to the scan driving circuit, and may supply a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driving circuit to the light emitting driving circuit.

In one exemplary embodiment, the data driving circuit may generate a data voltage to be supplied to the data signal line D using a gray scale value and a control signal received from the timing controller. For example, the data driving circuit may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal line in units of pixel rows.

In one exemplary embodiment, the scan driving circuit may generate the scan signal to be supplied to the scan signal line by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driving circuit may sequentially supply scan signals having on-level pulses to the scan signal lines. The scan driving circuit may be constructed in the form of a shift register, and may generate the scan signals in such a manner that the scan start signal provided in the form of the on-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal.

In one exemplary embodiment, the light emission driving circuit may generate the emission signal to be supplied to the light emission signal line by receiving a clock signal, an emission stop signal, or the like from the timing controller. The light emitting driver circuit may sequentially supply the emission signals having the off-level pulses to the light emitting signal lines. For example, the light emitting driving circuit may be constructed in the form of a shift register, and the light emitting signal may be generated in such a manner that the light emitting stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal. Each of the sub-pixels may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line.

In an exemplary embodiment, the first direction intersects the second direction, which means that an angle between the first direction and the second direction is about 70 degrees to 90 degrees. The first direction and the second direction may lie in the same plane. For example, the first direction may be a direction parallel to the extending direction of the scanning signal lines; the second direction may be a direction parallel to the extending direction of the data signal line. Fig. 1 illustrates an example in which the angle between the first direction and the second direction is 90 degrees.

In an exemplary embodiment, the shape of the light emitting element may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon and other polygons, and the disclosure is not limited herein.

In an exemplary embodiment, fig. 3 is a schematic layout diagram of light emitting elements of a display panel provided in an exemplary embodiment, and fig. 4 is a schematic layout diagram of light emitting elements of a display panel provided in another exemplary embodiment. As shown in fig. 3 and 4, the light emitting element may be any one of a red (R) light emitting element, a green (G) light emitting element, a blue (B) light emitting element, and a white light emitting element, and the present disclosure is not limited thereto. When the display panel includes a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element, the three light emitting elements may be arranged in a horizontal parallel, vertical parallel, or delta arrangement. When the display panel includes a red (R) light emitting element, a green (G) light emitting element, a blue (B) light emitting element, and a white light emitting element, the four light emitting elements may be arranged in a horizontal parallel manner, a vertical parallel manner, or an array manner, and the disclosure is not limited thereto. Fig. 3 illustrates an example in which three light emitting elements are horizontally arranged in parallel, and fig. 4 illustrates an example in which four light emitting elements are arranged in an array.

In an exemplary embodiment, the area of each driving circuit may be the same, which ensures that the load of each driving circuit is the same, and the risk of abnormal display may be largely avoided.

In some exemplary embodiments, the display area includes an arc-shaped display boundary. Illustratively, the boundary of the display area may be a rounded rectangle, which is not limited in any way by the present disclosure.

In one exemplary embodiment, the first display region may be a light transmissive display region. The light-transmitting display area can display or transmit light.

In an exemplary embodiment, the shape of the first display region in a plane parallel to the display panel may be any one or more of: rectangular, polygonal, circular, and elliptical. Fig. 1 illustrates a rectangular shape as an example.

In an exemplary embodiment, the area of the first display region may be larger than the area of the second display region, or the area of the first display region may be equal to the area of the second display region, or the area of the first display region may be smaller than the area of the second display region, and fig. 1 illustrates an example in which the area of the first display region is smaller than the area of the second display region.

In an exemplary embodiment, the resolutions of the first and second display regions may be the same or may be different. The resolution (PPI) refers to the number of Pixels in a unit area, and may be referred to as pixel density, where a higher PPI value indicates that the display panel displays a picture with a higher density, and the picture has rich details.

In an exemplary embodiment, the resolution of the second display region may be greater than that of the first display region, that is, the number of light emitting elements included in the second display region is greater than that of the first display region in a unit area, or the resolution of the second display region may be smaller than that of the first display region, that is, the number of light emitting elements included in the second display region is smaller than that of the first display region in a unit area, or the resolution of the second display region may be equal to that of the first display region, that is, the number of light emitting elements included in the second display region is equal to that of the first display region in a unit area.

In an exemplary embodiment, the boundary of the display area AA may include at least one arc. By way of example, as shown in fig. 1, the shape of the display area AA may be a rounded rectangle, which is not limited in any way by the present disclosure.

In an exemplary embodiment, the driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Fig. 5 is an equivalent circuit diagram of a driving circuit. As shown in fig. 5, the driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7), 1 storage capacitor C, and 7 signal lines (the data signal line D, the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the high-level power supply line VDD, and the low-level power supply line VSS).

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the high power line VDD, and a second terminal of the storage capacitor C is connected to the second node N2, that is, the second terminal of the storage capacitor C is connected to the control electrode of the third transistor T3.

In an exemplary embodiment, a control electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the initialization signal line INIT, and a second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.

In an exemplary embodiment, a control electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 with the second electrode.

In an exemplary embodiment, a control electrode of the third transistor T3 is connected to the second node N2, i.e., a control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, a first electrode of the third transistor T3 is connected to the first node N1, and a second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the high-level power line VDD and the low-level power line VSS according to a potential difference between the control electrode and the first electrode thereof.

In an exemplary embodiment, a control electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may be referred to as a switching transistor, a scan transistor, or the like, and when an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the driving circuit.

In an exemplary embodiment, a control electrode of the fifth transistor T5 is connected to the light emitting signal line E, a first electrode of the fifth transistor T5 is connected to the high level power source line VDD, and a second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the light emitting signal line E, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element. The fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When the on-level light emission signal is applied to the light emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emission element to emit light by forming a driving current path between the high-level power line VDD and the low-level power line VSS.

In an exemplary embodiment, a control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, a first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the anode of the light emitting element to initialize or release the amount of charge accumulated in the first pole of the light emitting element.

In an exemplary embodiment, the cathode of the light emitting element is connected to a low-level power line VSS, a signal of the low-level power line VSS is a low-level signal, and a signal of the high-level power line VDD is a high-level signal. The first scanning signal line S1 is a scanning signal line in the present display line driving circuit, the second scanning signal line S2 is a scanning signal line in the previous display line driving circuit, that is, for the nth display line, the first scanning signal line S1 is S (n), the second scanning signal line S2 is S (n-1), the second scanning signal line S2 of the present display line and the first scanning signal line S1 of the previous display line driving circuit are the same signal line, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

In one exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors or may be N-type transistors. The transistors of the same type are adopted in the driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors. When a low level is applied to the gate electrode of the P-type transistor, the P-type transistor is turned on, and when a high level is applied to the gate electrode of the P-type transistor, the P-type transistor is turned off. These two levels are also typically used to turn the transistor on and off, respectively, so the higher of the two is also typically referred to as the high level and the lower is also referred to as the low level.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ both a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature polysilicon (LTPS for short), and the active layer of the Oxide thin film transistor adopts Oxide (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, and the oxide thin film transistor has the advantages of low leakage current and the like. In an exemplary embodiment, a Low Temperature polysilicon thin film transistor and an Oxide thin film transistor may be integrated on a display substrate to form a Low Temperature Polysilicon Oxide (LTPO) display substrate, and may use advantages of the two, may implement high resolution (Pixel Per inc, PPI for short), may perform Low frequency driving, may reduce power consumption, and may improve display quality.

In one exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, and the initialization signal line INIT extend in a first direction, and the low-level power line VSS and the high-level power line VDD data signal line D extend in a second direction.

In one exemplary embodiment, the light emitting element may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked. The anode is connected with the driving circuit through the via hole, the organic light emitting layer is connected with the anode, the cathode is connected with the organic light emitting layer, and the organic light emitting layer emits light rays with corresponding colors under the driving of the anode and the cathode.

In an exemplary embodiment, the organic light Emitting Layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a light Emitting Layer (EML), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked one on another. In an exemplary embodiment, the hole injection layers of all the sub-pixels may be a common layer connected together, the electron injection layers of all the sub-pixels may be a common layer connected together, the hole transport layers of all the sub-pixels may be a common layer connected together, the electron transport layers of all the sub-pixels may be a common layer connected together, the hole blocking layers of all the sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.

In an exemplary embodiment, the anode may be made of a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In an exemplary embodiment, the cathode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

Fig. 6 is a timing diagram of the operation of a driving circuit. The exemplary embodiment of the present disclosure will be explained below by an operation process of the driving circuit illustrated in fig. 5, the driving circuit in fig. 6 including 7 transistors (the first transistor T1 to the sixth transistor T7), 1 storage capacitor C, and 7 signal lines (the data signal line D, the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the high-level power supply line VDD, and the low-level power supply line VSS), the 7 transistors each being a P-type transistor.

In an exemplary embodiment, the operation of the driving circuit may include:

in the first phase, referred to as a reset phase, the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scan signal line S2 is a low level signal, turning on the first transistor T1, and the signal of the initialization signal line INIT is provided to the second node N2, initializing the storage capacitor C, and clearing the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light emitting signal line E are high level signals, turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, and the OLED does not emit light at this stage.

In the second phase, which is referred to as a data write phase or a threshold compensation phase, the signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light-emitting signal line E are high level signals, and the data signal line D outputs a data voltage. At this stage, the second terminal of the storage capacitor C is at a low level, so the third transistor T3 is turned on. The signal of the first scan signal line S1 is a low level signal to turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output from the data signal line D is supplied to the second node N2 through the first node N1, the turned-on third transistor T3, the turned-on third node N3, and the turned-on second transistor T2, and the difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, the voltage at the second terminal (the second node N2) of the storage capacitor C is Vd- | Vth |, Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to supply the initial voltage of the initial signal line INIT to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, clear the pre-stored voltage therein, complete the initialization, and ensure that the OLED does not emit light. The signal of the second scanning signal line S2 is a high level signal, turning off the first transistor T1. The signal of the light emitting signal line E is a high level signal, turning off the fifth transistor T5 and the sixth transistor T6.

In the third stage, referred to as a light-emitting stage, a signal of the light-emitting signal line E is a low-level signal, and signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light emitting signal line E is a low level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power voltage output from the high level power line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the OLED to emit light.

During driving of the driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by a voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vdata- | Vth |, the driving current of the third transistor T3 is:

I＝K*(Vgs-Vth)²＝K*[(Vdd-Vd+|Vth|)-Vth]²＝K*[(Vdd-Vd]²

where I is a driving current flowing through the third transistor T3, that is, a driving current driving the OLED, K is a constant, Vgs is a voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is a threshold voltage of the third transistor T3, Vd is a data voltage output from the data signal line D, and Vdd is a power voltage output from the high-level power supply line Vdd.

The display panel provided by the embodiment of the disclosure includes: a display area and a non-display area surrounding the display area, the display area including: a first display area and a second display area located at least one side of the first display area; the second display area includes: the display device comprises a first area and a second area which are arranged at intervals, wherein the first area and the second area are arranged along a first direction, and a first display area is positioned between the first area and the second area; the display panel includes: the circuit structure layer and the light emitting structure layer are sequentially stacked on the substrate; the circuit structure layer includes: a plurality of driving circuits and a plurality of data signal lines extending in a second direction, the light emitting structure layer including: a plurality of light emitting elements; the data signal line is set up as to provide the data signal to the drive circuit, the drive circuit is set up as to drive the light-emitting component to illuminate, the first direction and second direction intersect; the light emitting elements are located in the first display area and the second display area, and the driving circuit is located in the first area and the second area. According to the display device and the display method, the driving circuit is located in the first area and the second area, the data signal lines do not need to be arranged in the first display area, and layout of the data signal lines is simplified.

In an exemplary embodiment, the length of the first display region a1 along the second direction D2 is less than or equal to the length of the second display region a2 along the second direction D2. Fig. 1A and 2A are illustrated by way of example that the length of the first display region a1 in the second direction D2 is less than the length of the second display region a2 in the second direction D2. Fig. 1B and 2B are illustrated by way of example that the length of the first display region a1 in the second direction D2 is equal to the length of the second display region a2 in the second direction D2.

In an exemplary embodiment, a length of any one of the driving circuits in the first direction is smaller than a length of the light emitting element to which the driving circuit is connected in the first direction.

In an exemplary embodiment, fig. 7 is a comparison graph of the sizes of a driving circuit and a reference driving circuit in a display panel provided by an exemplary embodiment. The reference driver circuit CPA refers to a driver circuit in the display panel in all the areas of the second display area. An exemplary embodiment provides a display panel in which a driving circuit is obtained by compressing a reference driving circuit CPA in an equal proportion. Wherein the proportional compression may include: the compression is done either proportionally in the first direction or proportionally in the row and column directions. As shown in fig. 7, l3 ═ l1 × k, and l4 ═ l 2. Where l1 is the length of the reference driver circuit CPA in the first direction, l2 is the length of the reference driver circuit CPA in the second direction, l3 is the length of the driver circuit PA in the first direction, l4 is the length of the driver circuit PA in the second direction, k is the compression ratio, 0< k < 1.

In an exemplary embodiment, the length of the light emitting element in the first direction is X micrometers, and the length of the driving circuit in the first direction is X-a micrometers, wherein a is determined according to the size of the first display region.

In an exemplary embodiment, fig. 8A is a schematic structural diagram of a display panel provided in an exemplary embodiment, and fig. 8B is a schematic structural diagram of a display panel provided in another exemplary embodiment. As shown in fig. 8, the driving circuit may include: a first driver circuit PA1 and a second driver circuit PA 2. The first driver circuit PA1 is connected to the first light-emitting element, and the second driver circuit PA2 is connected to the second light-emitting element. The first light-emitting element is a light-emitting element located in the second display region, and the second light-emitting element is a light-emitting element located in the first display region. Fig. 8A is an example in which the length of the first display region a1 in the second direction D2 is smaller than the length of the second display region a2 in the second direction D2. Fig. 8B is an example in which the length of the first display region a1 in the second direction D2 is equal to the length of the second display region a2 in the second direction D2.

In an exemplary embodiment, fig. 9 is a cross-sectional view of a display panel provided in an exemplary embodiment. As shown in fig. 9, there is no overlapping area of the orthographic projection of the second pole 64 of the sixth transistor T6 of the driving circuit on the substrate 10 and the orthographic projection of the anode 31 of the light emitting element connected to the driving circuit on the substrate 10.

In an exemplary embodiment, the circuit structure layer 20 may further include: an active layer 61, a gate electrode 62 and a first electrode 63 of the sixth transistor T6, first and second plates C1 and C2 of the storage capacitor, and a high level power line VDD.

In one exemplary embodiment, the light emitting structure layer 30 may further include: a pixel defining layer 34, an organic light emitting layer 32, and a cathode 33.

In an exemplary embodiment, the pixel defining layer may employ an organic material such as polyimide, acryl, or polyethylene terephthalate.

In an exemplary embodiment, as shown in fig. 9, the circuit structure layer 20 further includes: and a plurality of first switches VL1, a first switch VL1 being located between the second electrode 61 of the sixth transistor of the first driving circuit and the anode 31 of the first light emitting element.

In an exemplary embodiment, the first driving circuit is connected to the first light emitting element through a first switching part, an orthogonal projection of the first switching part on the substrate at least partially overlaps an orthogonal projection of a second pole of a sixth transistor of the first driving circuit connected to the first switching part on the substrate, and an orthogonal projection of an anode of the first light emitting element connected to the first connecting part on the substrate at least partially overlaps.

In an exemplary embodiment, the first transition portion may be made of a material including: a metal. The first switching part can be made of metal, so that impedance can be reduced, and the brightness uniformity of the second display area is ensured.

In one exemplary embodiment, the circuit structure layer may further include: and the second switching parts are positioned between the second pole of the sixth transistor of the second driving circuit and the anode of the second light-emitting element.

In an exemplary embodiment, the second driving circuit is connected to the second light emitting element through a second junction, an orthogonal projection of the second junction on the substrate at least partially overlaps an orthogonal projection of a second pole of the sixth transistor of the second driving circuit connected to the second junction on the substrate, and an orthogonal projection of an anode of the second light emitting element connected to the second connection portion on the substrate at least partially overlaps.

In an exemplary embodiment, the second adapter portion is made of a material including: a transparent conductive material. The second switching part is made of transparent conductive materials, so that the light transmittance of the second display area can be guaranteed.

In an exemplary embodiment, the second transition portion and the first transition portion are disposed in the same layer or in different layers, which is not limited in this disclosure.

In an exemplary embodiment, as shown in fig. 1A and 2A, when the length of the first display region a1 in the second direction is less than the length of the second display region a2 in the second direction, the second display region a2 may further include: a third region R3, a third region R3 being located between the first region R1 and the second region R2, the third region R3 being enclosed outside the first display region a 1.

In one exemplary embodiment, the first region R1 and the second region R2 are symmetrically disposed along a center line of the third region R3.

In an exemplary embodiment, as shown in fig. 2A and 8A, the circuit structure layer may further include: n columns of the first dummy driving circuit DPA 1. The N rows of first dummy driving circuits are located in the third area R3, where N is a positive integer greater than or equal to M, and M is the number of rows of light emitting elements in the first display area.

In one exemplary embodiment, each column of the first dummy driving circuits is not connected to any light emitting element. The display uniformity of the driving circuit driving display can be guaranteed by arranging the first dummy driving circuit, and the display effect of the display panel is improved. The value of N may be determined according to the size of the first display area in the display panel, which is not limited in this disclosure.

In one exemplary embodiment, a length of the first dummy driving circuit in the first direction is greater than or equal to a length of the driving circuit in the first direction. Illustratively, the length of the first dummy drive circuit in the first direction is equal to the length of the drive circuit in the first direction. The length of the first dummy driving circuit along the first direction is equal to the length of the driving circuit along the first direction, so that the manufacturing process of the display panel can be simplified, and the manufacturing cost of the display panel can be saved.

In an exemplary embodiment, as shown in fig. 8A and 8B, the first region includes: s first sub-regions R1_1 to R1_ S sequentially arranged along the first direction, where adjacent first sub-regions are disposed at intervals, S is a positive integer greater than or equal to 2, and S is illustrated as 3 in fig. 8.

In an exemplary embodiment, each of the first sub-regions may include the same number of columns of driving circuits.

In an exemplary embodiment, fig. 10 is a schematic layout diagram of the first transition portion in each first sub-region provided in an exemplary embodiment, and fig. 11 is an enlarged view of a region R in fig. 10, as shown in fig. 8, 10 and 11, the circuit structure layer may further include: at least one column of second dummy driving circuits DPA2 between adjacent first sub-regions.

In one exemplary embodiment, each column of the second dummy driving circuits is not connected to any light emitting element. The second dummy driving circuit is arranged between the adjacent first sub-regions, so that the uniformity of deviation of the driving circuit and the light-emitting element connected with the driving circuit can be better maintained, the display uniformity of the display panel can be ensured, and the display effect of the display panel is improved. Each first sub-region and the adjacent second dummy driving circuit can be used as a circulation unit, and the sizes and the arrangement of all the first switching parts in each circulation unit are the same, so that the manufacturing process of the display panel can be simplified, the realization of the first switching parts can be facilitated, and the overlong size of the first switching parts is avoided.

In an exemplary embodiment, as shown in fig. 8A and 8B, the second region R2 includes: t second subregions R2_1 to R2_ T are arranged along the first direction in sequence, wherein adjacent second subregions are arranged at intervals, and T is a positive integer greater than or equal to 2. Fig. 8 illustrates an example where T is 3.

In some possible implementations, the circuit structure layer further includes: at least one row of third dummy driving circuits DPA3 between adjacent second sub-regions.

In one exemplary embodiment, each column of the third dummy driving circuits is not connected to any light emitting element. The third dummy driving circuit is arranged between the adjacent first sub-regions, so that the uniformity of deviation of the driving circuit and the light-emitting elements connected with the driving circuit can be better maintained, the display uniformity of the display panel can be ensured, and the display effect of the display panel is improved. Referring to fig. 10 and 11, each second sub-region and the adjacent third dummy driving circuit may serve as a circulation unit, and all the first transfer portions in each circulation unit have the same size and arrangement, so that the manufacturing process of the display panel may be simplified, the implementation of the first transfer portions may be facilitated, and the first transfer portions may be prevented from being too long in size.

In one exemplary embodiment, S ═ T.

In one exemplary embodiment, as shown in fig. 1, the data signal line D may be positioned at the first region R1 and the second region R2. The driving circuits in the same column are connected to the same data signal line.

In an exemplary embodiment, fig. 12A is a schematic structural diagram of a display panel provided in yet another exemplary embodiment, and fig. 12B is a schematic structural diagram of a display panel provided in yet another exemplary embodiment. As shown in fig. 12A and 12B, the circuit structure layer further includes: a plurality of first power supply lines VDD1 extending in the second direction; the first power supply line VDD1 is located in the first region R1 and the second region R2. Fig. 12A and 12B illustrate an example where S is 2 and T is 2. Fig. 12A illustrates an example in which the length of the first display region in the second direction is smaller than the length of the second display region in the second direction. Fig. 12B is an example in which the length of the first display region in the second direction is equal to the length of the second display region in the second direction.

In an exemplary embodiment, when the driving circuits in the same column are all the first driving circuits, the first driving circuits in the same column are connected to the same first power line, and when the driving circuits in the same column include the first driving circuits and the second driving circuits, the first driving circuits on both sides of the second driving circuits are respectively connected to different first power lines.

In one exemplary embodiment, the first power line is a high-level power line to which the first driving circuit is connected.

In an exemplary embodiment, as shown in fig. 12, the circuit structure layer may further include: a plurality of second power supply lines VDD 2; the second power line VDD2 is located on a side of the first power line VDD1 away from the substrate 10.

In an exemplary embodiment, the second power line VDD2 is a high level power line to which the second driving circuit is connected.

In an exemplary embodiment, as shown in fig. 12A and 12B, the second driving circuits located in the same column are connected to the same second power line.

In an exemplary embodiment, the voltage value of the signal of the second power line VDD2 is greater than the voltage value of the signal of the first power line VDD 1.

In an exemplary embodiment, the second driving circuit is connected to the second light emitting element through the second switching portion, the second switching portion is made of a transparent conductive material, and the resistance of the transparent conductive material is relatively large, which may cause non-uniform display of the first light emitting element and the second light emitting element.

In one exemplary embodiment, as shown in fig. 12B, when the length of the first display region in the second direction is equal to the length of the second display region in the second direction, the second power line is located at the first region R1 and the second region and extends in the second direction.

In an exemplary embodiment, fig. 13 is a schematic structural diagram of a second power line provided in an exemplary embodiment. As shown in fig. 12A and 13, when the length of the first display region in the second direction is less than the length of the second display region in the second direction, each of the second power lines includes: the power supply comprises a first power supply section Va, a second power supply section Vb, a third power supply section Vc, a fourth power supply section Vd and a fifth power supply section Ve which are connected in sequence; the first power section Va, the third power section Vc, and the fifth power section Ve extend in the second direction, and the second power section Vb and the fourth power section Vd extend in the first direction.

In one exemplary embodiment, for each of the second power lines, the first power source segment Va and the fifth power source segment Ve are located in the third region.

In an exemplary embodiment, for a second power line connected to a second driving circuit located at the first region, the second power section Vb and the fourth power section Vd are located at the third region and the first region, and the third power section Vc is located at the first region.

In an exemplary embodiment, for a second power line connected to a second driving circuit located at a second region, the second power section Vb and the fourth power section Vd are located at the second region and a third region, and the third power section Vc is located at the second region.

In an exemplary embodiment, fig. 14 is a schematic structural diagram of a first power connection line provided in an exemplary embodiment, and fig. 15 is a schematic structural diagram of a second power connection line provided in an exemplary embodiment. As shown in fig. 12, 14 and 15, the display panel may further include: a first power connection line L1 and a second power connection line L2 positioned at the non-display area.

In an exemplary embodiment, the first power connection line L1 and the second power connection line L2 may be disposed at the same layer and at the same layer as the second power supply line.

In an exemplary embodiment, when the length of the first display region in the second direction is equal to the length of the second display region in the second direction, the first power connection lines L1 are respectively connected to both ends of at least one second power line located in the first region, and the second power connection lines L2 are respectively connected to both ends of at least one second power line located in the second region.

In an exemplary embodiment, the first power connection line L1 may be connected to the first power segment and the fifth power segment of at least one second power line connected to the second driving circuit located at the first region, respectively. The second power connection line L2 is connected to the first power section and the fifth power section of at least one second power line connected to the second driving circuit located in the second region, respectively.

In an exemplary embodiment, the display area includes: first and second oppositely disposed sides and third and fourth oppositely disposed sides.

In an exemplary embodiment, as shown in fig. 14, the first power connection line L1 includes: the first connecting section La, the second connecting section Lb, the third connecting section Lc, the fourth connecting section Ld and the fifth connecting section Le are connected in sequence.

In an exemplary embodiment, the first and second connection segments La and Lb are located at a first side of the display area, the third connection segment Lc is located at a third side of the display area, and the fourth and fifth connection segments Ld and Le are located at a second side of the display area.

In one exemplary embodiment, the first, third and fifth connection sections La, Lc and Le extend in the second direction, and the second and fourth connection sections Lb and Ld extend in the first direction.

In an exemplary embodiment, as shown in fig. 12B, when the length of the first display region in the second direction is equal to the length of the second display region in the second direction, the first connection section connects one end of at least one second power line located in the first region, and the fifth connection section connects the other end of at least one second power line located in the first region.

In an exemplary embodiment, when the length of the first display region in the second direction is less than the length of the second display region in the second direction, the first connection section La connects the first power section of at least one second power line connected to the second driving circuit located at the first region, and the fifth connection section Le connects the fifth power section of at least one second power line connected to the second driving circuit located at the first region.

In an exemplary embodiment, as shown in fig. 15, the second power connection line includes: the device comprises a sixth connecting section Lf, a seventh connecting section Lg, an eighth connecting section Lh, a ninth connecting section Li and a tenth connecting section Lj which are connected in sequence.

In an exemplary embodiment, the sixth and seventh connection segments Lf and Lg are located at the first side of the display area, the eighth connection segment Lh is located at the fourth side of the display area, and the ninth and tenth connection segments Li and Lj are located at the second side of the display area.

In an exemplary embodiment, the sixth, eighth and tenth connection segments Lf, Lh and Lj extend in the second direction, and the seventh and ninth connection segments Lg and Li extend in the first direction.

When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the sixth connecting section is connected with one end of at least one second power line located in the second area, and the tenth connecting section is connected with the other end of at least one second power line located in the second area.

In an exemplary embodiment, when the length of the first display region in the second direction is less than the length of the second display region in the second direction, the sixth connection section Lf connects the first power section of at least one second power line connected to the second driving circuit located in the second region, and the tenth connection section Lj connects the fifth power section of at least one second power line connected to the second driving circuit located in the second region.

In one exemplary embodiment, the circuit structure layer may include: the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, the third insulating layer, and the fourth conductive layer. The first power line is positioned on the first conductive layer and/or the second conductive layer; the second power line and the first switching part are positioned on the third conductive layer; the second switching part is positioned on the fourth conducting layer.

In one exemplary embodiment, the first conductive layer, the second conductive layer, and the third conductive layer may be metal conductive layers.

In one exemplary embodiment, the fourth conductive layer may be a transparent conductive layer.

In one exemplary embodiment, the circuit structure layer may include: when the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, the third insulating layer, and the fourth conductive layer, the circuit structure layer may further include: the buffer layer, the active layer, the fourth insulating layer, the first metal layer, the fifth insulating layer, the second metal layer and the sixth insulating layer are arranged between the substrate and the first conducting layer and sequentially stacked on the substrate.

In one exemplary embodiment, the active layer may include: an active layer of a plurality of transistors, the first metal layer may include: gate electrodes of the plurality of transistors and a first plate of the storage capacitor. The second metal layer may include: a second plate of the plurality of transistors. The conductive layer may further include: a first pole and a second pole of the plurality of transistors.

In one exemplary embodiment, the circuit structure layer may further include: and the flat layer is arranged on one side of the fourth conductive layer far away from the substrate.

In an exemplary embodiment, as shown in fig. 9, the circuit structure layer may further include: a first conductive layer, a first insulating layer 26, a second conductive layer, a second insulating layer 27, and a third conductive layer. The first power line VDD1 is located in the first conductive layer and/or the second conductive layer; the second power supply line, the first switching portion VL1, and the second switching portion are located on the third conductive layer.

In one exemplary embodiment, the first conductive layer and the second conductive layer are metal conductive layers.

In one exemplary embodiment, the circuit structure layer may further include: a buffer layer 22, an active layer, a third insulating layer 23, a first metal layer, a fourth insulating layer 24, a second metal layer and a fifth insulating layer 25, which are disposed between the substrate and the first conductive layer and are sequentially stacked on the substrate 10.

In one exemplary embodiment, the active layer may include: an active layer of a plurality of transistors, the first metal layer may include: gate electrodes of the plurality of transistors and a first plate C1 of the storage capacitor. The second metal layer may include: a second plate C2 of a plurality of transistors.

In one exemplary embodiment, the first conductive layer may further include: a first pole and a second pole of the plurality of transistors.

In one exemplary embodiment, the circuit structure layer may further include: a planarization layer 28 arranged on the side of the third conductive layer facing away from the substrate.

In one exemplary embodiment, the active layer may be an amorphous silicon layer, a polysilicon layer, or may be a metal oxide layer. Among them, the metal oxide layer may employ an oxide containing indium and tin, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, or may be a double layer, or may be a multilayer.

In an exemplary embodiment, the first metal layer, the second metal layer, the first conductive layer, and the second conductive layer may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, and the like.

In one exemplary embodiment, the first, second, third, fourth, fifth, and sixth insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer.

In an exemplary embodiment, the planarization layer may use an organic material such as polyimide, acryl, or polyethylene terephthalate.

In an exemplary embodiment, as shown in fig. 9, the display panel may further include: an encapsulation layer 40 and a spacer 50.

In an exemplary embodiment, the encapsulation layer 40 is disposed on a side of the light emitting structure layer 30 away from the substrate 10, and the spacer 50 is disposed on a side of the encapsulation layer 40 away from the substrate 10.

In one exemplary embodiment, the encapsulation layer 40 may adopt a stacked structure of inorganic material/organic material/inorganic material, with an organic material layer disposed between two inorganic material layers. Illustratively, the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer that are stacked, the first encapsulation layer and the third encapsulation layer may employ an inorganic material, the second encapsulation layer may employ an organic material, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which may ensure that external moisture cannot enter the light emitting device.

The embodiment of the present disclosure also provides a display device, including: a display panel.

In an exemplary embodiment, the display device may be: an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, a display and any other product or component with a display function. The drawings in this disclosure relate only to the structures to which the embodiments of the disclosure relate, and other structures may refer to general designs.

The display panel is the display panel provided by any of the foregoing embodiments, and the implementation principle and the implementation effect are similar, and are not described herein again.

In an exemplary embodiment, the display device may further include: the photosensitive sensor is located in the first display area of the display panel.

In one exemplary embodiment, the first display region may be rectangular, and an area of an orthogonal projection of the photosensor on the substrate may be less than or equal to an area of an inscribed circle of the first display region. That is, the size of the region where the photo sensor is located may be smaller than or equal to the size of the inscribed circle of the first display region. For example, the size of the area where the photosensitive sensor is located is equal to the size of the inscribed circle of the first display area, that is, the shape of the area where the photosensitive sensor is located may be a circle, and accordingly, the area where the photosensitive sensor is located may also be referred to as a light transmission hole.

In the drawings used to describe embodiments of the present disclosure, the thickness and size of layers or microstructures are exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made in the form and details without departing from the spirit and scope of the disclosure, but that the scope of the disclosure is to be determined solely by the appended claims.

Claims

1. A display panel, comprising: a display area and a non-display area surrounding the display area, wherein the display area comprises: the display device comprises a first display area and a second display area positioned on at least one side of the first display area; the second display area includes: the display device comprises a first area and a second area which are arranged at intervals, wherein the first area and the second area are arranged along a first direction, and a first display area is positioned between the first area and the second area;

the display panel includes: the LED comprises a substrate, and a circuit structure layer and a light emitting structure layer which are sequentially stacked on the substrate; the circuit structure layer includes: a plurality of driving circuits and a plurality of data signal lines extending in a second direction, the light emitting structure layer including: a plurality of light emitting elements; the data signal line is configured to provide a data signal to a driving circuit, the driving circuit is configured to drive the light emitting element to emit light, and the first direction and the second direction intersect;

2. The display panel according to claim 1, wherein a length of the first display region in the second direction is smaller than or equal to a length of the second display region in the second direction.

3. The display panel according to claim 1 or 2, wherein a length of the driver circuit in the first direction is smaller than a length of a light emitting element to which the driver circuit is connected in the first direction.

4. The display panel according to claim 3, wherein the driving circuit comprises: a first drive circuit and a second drive circuit;

5. The display panel according to claim 4, wherein the driving circuit comprises: first to seventh transistors; the light emitting element includes: an anode, an organic light emitting layer, and a cathode; a second electrode of a sixth transistor of the driving circuit is connected to an anode of the light emitting element;

6. The display panel of claim 5, wherein the circuit structure layer further comprises: a plurality of first junctions between a second pole of the sixth transistor of the first driving circuit and an anode of the first light emitting element;

the first transfer part is made of materials including: a metal.

7. The display panel according to claim 5 or 6, wherein the circuit structure layer further comprises: a plurality of second switching parts, wherein the second switching parts are positioned between the second pole of the sixth transistor of the second driving circuit and the anode of the second light-emitting element;

the second driving circuit is connected with the second light-emitting element through the second switching part, the orthographic projection of the second switching part on the substrate is at least partially overlapped with the orthographic projection of a second pole of a sixth transistor of the second driving circuit connected with the second switching part on the substrate, and the orthographic projection of an anode of the second light-emitting element connected with the second connecting part on the substrate is at least partially overlapped;

8. The display panel according to claim 7, wherein the second interposer is disposed on the same layer as the first interposer or on a different layer.

9. The display panel according to claim 2, wherein when the length of the first display region in the second direction is smaller than the length of the second display region in the second direction, the second display region further comprises: a third region, the third region being located between the first region and the second region, the third region being surrounded by the first display region;

10. The display panel of claim 9, wherein the circuit structure layer further comprises: n rows of first dummy driving circuits;

11. The display panel according to claim 2, wherein the first region comprises: s first subregions are sequentially arranged along a first direction;

the adjacent first sub-areas are arranged at intervals.

12. The display panel of claim 11, wherein the circuit structure layer further comprises: at least one column of second dummy driving circuits between adjacent first sub-regions.

13. The display panel according to claim 2, wherein the second region comprises: the T second subregions are sequentially arranged along the first direction;

and the adjacent second sub-areas are arranged at intervals.

14. The display panel of claim 13, wherein the circuit structure layer further comprises: and at least one column of third dummy driving circuits between adjacent second sub-regions.

15. The display panel of claim 13, wherein S-T.

16. The display panel according to claim 2, wherein the data signal line is located in the first region and the second region;

17. The display panel of claim 3, wherein the circuit structure layer further comprises: a plurality of first power lines extending in a second direction; the first power line is located in the first region and the second region;

18. The display panel of claim 17, wherein the circuit structure layer further comprises: a plurality of second power lines; the second power line is positioned on one side of the first power line far away from the substrate;

19. The display panel according to claim 18, wherein when a length of the first display region in the second direction is equal to a length of the second display region in the second direction, the second power supply line is located in the first region and the second region and extends in the second direction.

20. The display panel according to claim 18, wherein when a length of the first display region in the second direction is smaller than a length of the second display region in the second direction, each of the second power supply lines comprises: the power supply comprises a first power supply section, a second power supply section, a third power supply section, a fourth power supply section and a fifth power supply section which are connected in sequence; the first power section, the third power section and the fifth power section extend in the second direction, and the second power section and the fourth power section extend in the first direction;

21. The display panel according to claim 19 or 20, characterized by further comprising: the first power supply connecting line and the second power supply connecting line are positioned in the non-display area; the first power supply connecting wire and the second power supply connecting wire are arranged on the same layer, and are arranged on the same layer with the second power supply wire;

22. The display panel according to claim 21, wherein the display area comprises: first and second oppositely disposed sides and third and fourth oppositely disposed sides;

23. The display panel according to claim 21, wherein the second power connection line comprises: the sixth connecting section, the seventh connecting section, the eighth connecting section, the ninth connecting section and the tenth connecting section are connected in sequence; the sixth connecting segment and the seventh connecting segment are located on a first side of the display area, the eighth connecting segment is located on a fourth side of the display area, and the ninth connecting segment and the tenth connecting segment are located on a second side of the display area; the sixth connecting section, the eighth connecting section and the tenth connecting section extend along the second direction, and the seventh connecting section and the ninth connecting section extend along the first direction;

24. The display panel of claim 21, wherein the circuit structure layer comprises: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer;

the first power line is positioned on the first conductive layer and/or the second conductive layer; the second power line and the first switching part are positioned on the third conducting layer; the second switching part is positioned on the fourth conducting layer;

25. The display panel of claim 21, wherein the circuit structure layer comprises: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer;

the first power line is positioned on the first conductive layer and/or the second conductive layer; the second power line, the first switching part and the second switching part are positioned on the third conducting layer;

26. The display panel according to claim 1, wherein the first display region is a transparent display region;

27. A display device, comprising: a display panel as claimed in any one of claims 1 to 26.

28. The display device according to claim 27, further comprising: the photosensitive sensor is located in a first display area of the display panel.