CN115000092A - Display substrate, preparation method thereof and display device - Google Patents

Display substrate, preparation method thereof and display device Download PDF

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Publication number
CN115000092A
CN115000092A CN202210616222.0A CN202210616222A CN115000092A CN 115000092 A CN115000092 A CN 115000092A CN 202210616222 A CN202210616222 A CN 202210616222A CN 115000092 A CN115000092 A CN 115000092A
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China
Prior art keywords
substrate
transistor
orthographic projection
capacitor
plate
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CN202210616222.0A
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Chinese (zh)
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杨维
曲燕
冯宇
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN202210616222.0A priority Critical patent/CN115000092A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Abstract

A display substrate, a preparation method thereof and a display device are provided, wherein the display substrate comprises: a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer comprising: the light shielding layer is positioned on one side, far away from the substrate, of the at least one pixel circuit; the pixel circuit includes: at least one first transistor, at least one second transistor and at least one capacitor, wherein the capacitor comprises at least one first sub-capacitor; the orthographic projection of the light shielding layer on the substrate does not overlap with the orthographic projection of the at least one first transistor on the substrate; the orthographic projection of the light shielding layer on the substrate is overlapped with the orthographic projection of the at least one second transistor and the orthographic projection of the at least one first sub-capacitor on the substrate.

Description

Display substrate, preparation method thereof and display device
Technical Field
The embodiment of the disclosure relates to but is not limited to the technical field of display, and particularly relates to a display substrate, a preparation method thereof and a display device.
Background
Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high reaction speed, lightness, thinness, flexibility, low cost, and the like.
In recent years, Low Temperature polysilicon Thin Film transistors (LTPS TFTs) and Oxide TFTs have attracted attention in the display industry, and have advantages without being classified into any order. The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility and quick charging, and the oxide thin film transistor has the advantages of low leakage current and low power consumption.
Disclosure of Invention
The following is a summary of subject matter that is described in detail in this disclosure. This summary is not intended to limit the scope of the claims.
In a first aspect, an embodiment of the present disclosure provides a display substrate, including: a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer comprising: the light shielding layer is positioned on one side, far away from the substrate, of the at least one pixel circuit;
the pixel circuit includes: at least one first transistor, at least one second transistor and at least one capacitor, wherein the capacitor comprises at least one first sub-capacitor;
the orthographic projection of the light shielding layer on the substrate does not overlap with the orthographic projection of the at least one first transistor on the substrate;
the orthographic projection of the light shielding layer on the substrate overlaps with the orthographic projection of the at least one second transistor and the orthographic projection of the at least one first sub-capacitor on the substrate.
In an exemplary embodiment, an orthographic projection of the at least one first sub-capacitor on the substrate is located in an orthographic projection of the shading layer on the substrate, and an area of the orthographic projection of the at least one first sub-capacitor on the substrate is not larger than an area of the orthographic projection of the shading layer on the substrate.
In an exemplary embodiment, the at least one first sub-capacitor is located on a side of the at least one second transistor close to the substrate, and an orthographic projection of the at least one first sub-capacitor on the substrate overlaps with an orthographic projection of the at least one second transistor on the substrate.
In an exemplary embodiment, the pixel circuit further includes at least one third transistor, and a forward projection of one first sub-capacitor on the substrate overlaps with a forward projection of the at least one second transistor and the at least one third transistor on the substrate.
In an exemplary embodiment, the first sub-capacitor includes a first plate and a second plate sequentially disposed on the substrate, and the first plate and the second plate overlap in an orthogonal projection of the substrate.
In an exemplary embodiment, an orthographic projection of the first plate on the substrate is located in an orthographic projection of the second plate on the substrate, and an area of the orthographic projection of the first plate on the substrate is not larger than an area of the orthographic projection of the second plate on the substrate.
In an exemplary embodiment, the first transistor includes at least a first active layer pattern and a first gate sequentially disposed on the substrate, and an orthogonal projection of the first active layer pattern and the first gate on the substrate has an overlap.
In an exemplary embodiment, the driving circuit layer further includes: a semiconductor layer and a first conductive layer sequentially provided on the substrate;
the semiconductor layer includes the first active layer pattern and the first electrode plate;
the first conductive layer includes the first gate and the second plate.
In an exemplary embodiment, the driving circuit layer further includes: a semiconductor layer, a first conductive layer and a second conductive layer which are sequentially arranged on the substrate;
the semiconductor layer includes the first active layer pattern;
the first conductive layer comprises the first grid and the first polar plate;
the second conductive layer includes the second plate.
In an exemplary embodiment, the material of the first active layer pattern employs low temperature polysilicon.
In an exemplary embodiment, the capacitor further includes: and the at least one second sub-capacitor is electrically connected with the at least one first sub-capacitor, and the orthographic projection of the at least one second sub-capacitor on the substrate does not overlap with the orthographic projection of the light shielding layer on the substrate.
In an exemplary embodiment, an orthogonal projection of the at least one second sub-capacitor on the substrate overlaps an orthogonal projection of the at least one first transistor on the substrate.
In an exemplary embodiment, the second sub-capacitor includes a third plate and a fourth plate sequentially disposed on the substrate, and the orthographic projections of the third plate and the fourth plate on the substrate have an overlap.
In an exemplary embodiment, an orthographic projection of the third plate on the substrate is located in an orthographic projection of the fourth plate on the substrate, and an area of the orthographic projection of the third plate on the substrate is not larger than an area of the orthographic projection of the fourth plate on the substrate.
In an exemplary embodiment, the first transistor includes at least a first active layer pattern and a first gate sequentially disposed on the substrate, the first active layer pattern and the first gate overlap in an orthogonal projection of the substrate, and the third plate is multiplexed as the first gate.
In an exemplary embodiment, the second transistor includes a second gate, a second active layer pattern, and a third gate sequentially disposed on the substrate, the second gate is located on a side of the second active layer pattern close to the substrate, the third gate is located on a side of the second active layer pattern away from the substrate, and orthographic projections of the second gate, the second active layer pattern, and the third gate on the substrate overlap.
In an exemplary embodiment, the second transistor includes a second active layer pattern and a third gate sequentially disposed on the substrate, and the second active layer pattern and the third gate overlap in an orthogonal projection of the substrate.
In an exemplary embodiment, the second active layer pattern material includes an oxide semiconductor.
In a second aspect, embodiments of the present disclosure provide a display device including the display substrate as described above.
In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a display substrate, including:
forming at least one first transistor and at least one first sub-capacitor on a substrate;
forming at least one second transistor on the side, away from the substrate, of the at least one first sub-capacitor;
forming a light shielding layer on one side of the at least one second transistor far away from the substrate;
enabling the orthographic projection of the light shielding layer on the substrate not to be overlapped with the orthographic projection of the at least one first transistor on the substrate;
and enabling the orthographic projection of the shading layer on the substrate to overlap with the orthographic projection of the at least one second transistor and the at least one first sub-capacitor on the substrate.
Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.
Drawings
The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
Fig. 1 is a cross-sectional view of a related art display substrate;
FIG. 2 is a top view of a light-shielding layer in a display substrate according to an embodiment of the disclosure;
FIG. 3 is a top view of a first sub-capacitor in a display substrate according to an embodiment of the disclosure;
FIG. 4 is a schematic structural diagram of a display device according to an embodiment of the disclosure;
FIG. 5 is a schematic view of a display substrate according to an embodiment of the disclosure;
FIG. 6 is a schematic cross-sectional view of a display area of a display substrate according to an embodiment of the disclosure;
fig. 7 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the disclosure;
FIG. 8A is a first cross-sectional view of a display substrate according to an embodiment of the disclosure;
FIG. 8B is a cross-sectional view of a second display substrate according to an embodiment of the disclosure;
FIG. 8C is a cross-sectional view of a third display substrate according to an embodiment of the present disclosure;
FIG. 8D is a cross-sectional view of a fourth display substrate according to an embodiment of the present disclosure;
fig. 8E is a cross-sectional view of a display substrate according to an embodiment of the disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.
In the drawings, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.
The ordinal numbers such as "first", "second", and "third" in the present specification are provided to avoid confusion of the constituent elements, and are not limited in number.
In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.
In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.
In this specification, a transistor refers to an element including at least three terminals, that is, a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.
In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.
In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.
In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.
In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".
"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.
Fig. 1 is a cross-sectional view of a related art display substrate. As shown in fig. 1, the related art display substrate includes a substrate 101 and a driving circuit layer disposed on the substrate 101, the driving circuit layer including at least one pixel circuit, the pixel circuit including: a first transistor T3, a second transistor T1, a third transistor T2, and a capacitor C'.
The first Transistor T3 may be a Low Temperature polysilicon Thin Film Transistor (LTPS TFT), which has the advantages of high mobility and fast charging, and the first Transistor T3 may be a driving Transistor. The second transistor T1 and the third transistor T2 may be Oxide thin film transistors (Oxide) which have an advantage of low leakage current, and the second transistor T1 and the third transistor T2 may be switching transistors. The display substrate combines the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor together to form an LTPO product, and the display effect of the display substrate is improved.
Through the research of the inventor of the present disclosure, it is found that the capacitor C ' is located on a side of the active layer of the first transistor T3 away from the substrate 101, and there is an overlap between the capacitor C ' and the active layer of the first transistor T3 in the orthographic projection of the substrate 101, and the capacitor C ' is used for stabilizing the potential of the N1 point in the first transistor T3. The capacitance C 'may reduce the resolution, the aperture ratio and the transmittance of the pixel due to the overlap of the capacitance C' and the orthographic projection of the active layer of the first transistor T3 on the substrate 101. For the display substrate with fingerprint identification, if the transmittance is too low, the sensitivity and accuracy of fingerprint identification will be affected. The area of the capacitor C ' orthographically projected on the substrate 101 is limited, and the too large area of the capacitor C ' orthographically projected on the substrate 101 seriously affects the aperture ratio of the pixel opening, so that the capacitance of the capacitor C ' is limited and cannot be increased, and the stability of the potential at the point N1 in the first transistor T3 is affected.
An embodiment of the present disclosure provides a display substrate, including: a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer comprising: the light shielding layer is positioned on one side, far away from the substrate, of the at least one pixel circuit;
the pixel circuit includes: at least one first transistor, at least one second transistor and at least one capacitor, wherein the capacitor comprises at least one first sub-capacitor;
the orthographic projection of the light shielding layer on the substrate does not overlap with the orthographic projection of the at least one first transistor on the substrate;
the orthographic projection of the light shielding layer on the substrate overlaps with the orthographic projection of the at least one second transistor and the orthographic projection of the at least one first sub-capacitor on the substrate.
In an exemplary embodiment, the light shielding layer has a light shielding effect, and orthographic projections of the light shielding layer on the substrate are overlapped with the active layers in the at least one second transistor, so that the light shielding layer blocks light from irradiating the active layers in the second transistors, and the light is prevented from affecting the characteristics of the second transistors.
FIG. 2 is a top view of a light-shielding layer in a display substrate according to an embodiment of the disclosure. In an exemplary embodiment, the area of the light shielding layer 20 in the display substrate according to the embodiment of the present disclosure, which is orthographically projected on the substrate, is larger, and the display substrate according to the embodiment of the present disclosure can increase the area of the first sub-capacitor, which does not occupy the area of the area where the first transistor is located, thereby increasing the capacitance of the first sub-capacitor, so that the potential of the N1 point in the first transistor T3 is more stable, and the display effect of the display substrate is improved.
According to the display substrate, the light shielding layer and the orthographic projection of the first sub-capacitor of the capacitor on the substrate are overlapped, the orthographic projection of the first sub-capacitor of the capacitor and the orthographic projection of at least one first transistor on the substrate are not overlapped, the first sub-capacitor of the capacitor is moved to the side, close to the substrate, of the light shielding layer, and the resolution, the aperture opening ratio and the transmittance of a pixel are not affected by the first sub-capacitor of the capacitor. For the display substrate with fingerprint identification, the sensitivity and the accuracy of the fingerprint identification are ensured.
In an exemplary embodiment, an orthographic projection of the at least one first sub-capacitor on the substrate is located in an orthographic projection of the shading layer on the substrate, and an area of the orthographic projection of the at least one first sub-capacitor on the substrate is not larger than an area of the orthographic projection of the shading layer on the substrate.
In an exemplary embodiment, the at least one first sub-capacitor is located on a side of the at least one second transistor close to the substrate, and an orthographic projection of the at least one first sub-capacitor on the substrate overlaps with an orthographic projection of the at least one second transistor on the substrate.
In an exemplary embodiment, the pixel circuit further includes at least one third transistor, and a forward projection of one first sub-capacitor on the substrate overlaps with a forward projection of the at least one second transistor and the at least one third transistor on the substrate.
FIG. 3 is a top view of a first sub-capacitor in a display substrate according to an embodiment of the disclosure. In an exemplary embodiment, as shown in fig. 3, the first sub-capacitor includes a first plate 21 and a second plate 22 sequentially disposed on the substrate 101, the first plate 21 is located on a side of the second plate 22 close to the substrate 101, and there is an overlap between the first plate 21 and the second plate 22 in the orthographic projection of the substrate.
In an exemplary embodiment, as shown in fig. 3, the orthographic projection of the first plate 21 on the substrate is located in the orthographic projection of the second plate 22 on the substrate, and the area of the orthographic projection of the first plate 21 on the substrate is not greater than the area of the orthographic projection of the second plate 22 on the substrate, for example, the edges around the second plate 22 in the orthographic projection of the substrate exceed the edges around the first plate 21 in the orthographic projection of the substrate, so that the second plate 22 completely covers the first plate 21, thereby ensuring the size and uniformity of the first sub-capacitor.
Fig. 4 is a schematic structural diagram of a display device according to an embodiment of the disclosure. As shown in fig. 4, the display device may include: the display device includes a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light emitting driver, respectively. The data driver is respectively connected to a plurality of data signal lines (e.g., D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (e.g., S1 to Sm), and the light emission driver is respectively connected to a plurality of light emission control lines (e.g., E1 to Eo). Wherein n, m and o may be natural numbers. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers. The at least one sub-pixel Pxij may include: a pixel circuit and a light emitting element connected to the pixel circuit. The pixel circuits may be connected to the scan signal line, the light emission control line, and the data signal line, respectively.
In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may supply a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of the clock signal. The light emission driver may generate light emission control signals to be supplied to the light emission control lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission driver may sequentially supply the emission signals having the off-level pulses to the light emission control lines E1 to Eo. For example, the light emission driver may be configured in the form of a shift register, and the light emission control signal may be generated in such a manner that the emission stop signal provided in the form of off-level pulses is sequentially transmitted to the next stage circuit under the control of the clock signal
Fig. 5 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure. As shown in fig. 5, the display substrate according to the embodiment of the present disclosure may include a display area 100, a binding area 200 located at one side of the display area 100, and a bezel area 300 located at the other side of the display area 100. In some examples, the display area 100 may be a flat area including a plurality of subpixels Pxij constituting a pixel array, the plurality of subpixels Pxij may be configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an Active Area (AA). In some examples, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, e.g., rolled, bent, folded, or rolled.
In an exemplary embodiment, the bonding region 200 may include a fan-out region, a bending region, a driving chip region, and a bonding pin region sequentially arranged in a direction away from the display region 100. The fan-out area is connected to the display area 100 and includes at least a data fan-out line, and the plurality of data fan-out lines are configured to be connected to the data signal lines of the display area 100 in a fan-out routing manner. The bending region is connected to the fan-out region, and may include a composite insulating layer provided with a groove configured to bend the driving chip region and the bonding pin region to the back surface of the display region 100. The driving chip region may be provided with an Integrated Circuit (IC), and the IC may be configured to be connected to the plurality of data fan-out lines. The Bonding pin region may include a Bonding Pad (Bonding Pad), and the Bonding Pad may be configured to be bonded to an external Flexible Printed Circuit (FPC).
In some exemplary embodiments, the display substrate may include a plurality of pixel units arranged in a matrix manner. For example, the at least one pixel unit may include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, and a third sub-pixel and a fourth sub-pixel emitting light of a third color. Each of the sub-pixels may include a pixel circuit and a light emitting element, the pixel circuit being electrically connected to the scan signal line, the data signal line, and the light emission control line, respectively, and the pixel circuit may be configured to receive a data voltage transmitted from the data signal line and output a corresponding current to the light emitting element under the control of the scan signal line and the light emission control line. The light emitting element in each sub-pixel is connected to the pixel circuit of the sub-pixel, and the light emitting element is configured to emit light with a corresponding luminance in response to a current output from the pixel circuit of the sub-pixel.
In an exemplary embodiment, the first subpixel may be a red subpixel (R) emitting red light, the second subpixel may be a blue subpixel (B) emitting blue light, and the third subpixel and the fourth subpixel may be a green subpixel (G) emitting green light. In some examples, the light emitting elements of the sub-pixels may be rectangular, Diamond, pentagonal, or hexagonal in shape, and the light emitting elements of the four sub-pixels may be arranged in a Diamond (Diamond) manner to form an RGBG pixel arrangement. In other exemplary embodiments, the light emitting elements of the four sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a square manner, or the like, and the disclosure is not limited thereto. In other exemplary embodiments, the pixel unit may include three sub-pixels, and the light emitting elements of the three sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a delta-shaped manner, or the like, and the disclosure is not limited thereto.
Fig. 6 is a schematic cross-sectional view illustrating a display region of a display substrate according to an embodiment of the disclosure. Fig. 6 illustrates the structure of three sub-pixels in the display area 100. As shown in fig. 6, the display substrate may include, in a direction perpendicular to the display substrate: the light emitting diode package structure comprises a substrate 101, a driving circuit layer 102, a light emitting structure layer 103 and a packaging structure layer 104 which are sequentially arranged on the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, and the disclosure is not limited herein.
In an exemplary embodiment, the substrate 101 may be a flexible base or may be a rigid base. The driving circuit layer 102 of each sub-pixel may include a pixel circuit composed of a plurality of transistors and capacitors. The light emitting structure layer 103 of each sub-pixel may include at least an anode 301, a pixel defining layer 302, an organic light emitting layer 303, and a cathode 304, wherein the anode 301 is connected to the pixel circuit, the organic light emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light emitting layer 303, and the organic light emitting layer 303 emits light of corresponding color under the driving of the anode 301 and the cathode 304. The encapsulation structure layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 that are stacked, where the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, the second encapsulation layer 402 may be made of organic materials, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material/organic material/inorganic material stacked structure, which may ensure that external moisture cannot enter the light emitting structure layer 103.
In an exemplary embodiment, the organic light emitting layer 303 may include an emission layer (EML) and any one or more of: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). In some examples, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all the sub-pixels may be a common layer that are each connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated from each other.
Fig. 7 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the disclosure. In some examples, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. The pixel circuit of the present exemplary embodiment is explained taking the 7T1C structure as an example. However, this embodiment is not limited to this.
In some examples, as shown in fig. 7, the pixel circuit of the present example may include seven transistors (i.e., the second transistor T1 through the seventh transistor T7) and one capacitor C. Ten signal lines (including, for example, a data signal line DL, a first scanning signal line GL1, a second scanning signal line GL2, a third scanning signal line RST1, a fourth scanning signal line RST2, a light-emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first power supply line VDD, and a second power supply line VSS) are connected to the pixel circuits, respectively.
In some examples, the seven transistors of the pixel circuit may be N-type transistors. The same type of transistors are adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty of the display substrate is reduced, and the yield of products is improved.
In some examples, seven transistors of the pixel circuit may employ oxide thin film transistors. An Oxide semiconductor (Oxide) can be used as an active layer of the Oxide thin film transistor. The oxide thin film transistor has the advantages of low leakage current and the like, and the display substrate provided with the oxide thin film transistor can realize low-frequency driving, reduce power consumption and improve display quality.
In some examples, the first power line VDD may be configured to provide a constant first voltage signal to the pixel circuit, the second power line VSS may be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal is greater than the second voltage signal. The first SCAN signal line GL1 may be configured to supply the first SCAN signal SCAN1 to the pixel circuit, the second SCAN signal line GL1 may be configured to supply the second SCAN signal SCAN2 to the pixel circuit, the DATA signal line DL may be configured to supply the DATA signal DATA to the pixel circuit, and the light emission control line EML may be configured to supply the light emission control signal EM to the pixel circuit. The third scan signal line RST1 may be configured to provide the pixel circuit with a third scan signal Reset1, and the fourth scan signal line RST2 may be configured to provide the pixel circuit with a fourth scan signal Reset 2. In some examples, in the n-th row of pixel circuits, the third SCAN signal line RST1 may be electrically connected to the first SCAN signal line GL1 of the n-1 th row of pixel circuits to be input with the first SCAN signal SCAN1 (n-1). The fourth SCAN signal line RST2 of the pixel circuit of the nth row may be electrically connected to the first SCAN signal line GL1 of the pixel circuit of the nth row to be input with the first SCAN signal SCAN1 (n). In some examples, the fourth scan signal line RST2 to which the n-th row of pixel circuits are electrically connected and the third scan signal line RST1 to which the n + 1-th row of pixel circuits are electrically connected may be of unitary construction. Wherein n is an integer greater than 0. Therefore, signal lines of the display substrate can be reduced, and the narrow frame design of the display substrate is realized. However, this embodiment is not limited to this.
In some examples, the first initialization signal line INIT1 may be configured to provide a first initialization signal to the pixel circuit, and the second initialization signal line INIT2 may be configured to provide a second initialization signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second preliminary signals may be constant voltage signals, and the magnitude thereof may be, for example, between a first voltage signal provided from the first power line VDD and a second voltage signal provided from the second power line VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.
In some examples, as shown in fig. 7, the gate of the second transistor T1 is electrically connected to the third scan signal line RST1, the first pole of the second transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the second transistor T1 is electrically connected to the gate of the first transistor T3. A gate electrode of the third transistor T2 is electrically connected to the first scan signal line GL1, a first pole of the third transistor T2 is electrically connected to a gate electrode of the first transistor T3, and a second pole of the third transistor T2 is electrically connected to a first pole of the first transistor T3. A gate of the first transistor T3 is electrically connected to the first node N1, a first pole of the first transistor T3 is electrically connected to the second node N2, and a second pole of the first transistor T3 is electrically connected to the third node N3. The first transistor T3 may be referred to as a driving transistor, and the first transistor T3 determines an amount of driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between its gate and its first pole. A gate electrode of the fourth transistor T4 is electrically connected to the second scan signal line GL2, a first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and a second electrode of the fourth transistor T4 is electrically connected to the second electrode of the first transistor T3. A gate of the fifth transistor T5 is electrically connected to the light emission control line EML, a first pole of the fifth transistor T5 is electrically connected to the first power line VDD, and a second pole of the fifth transistor T5 is electrically connected to the first pole of the first transistor T3. A gate of the sixth transistor T6 is electrically connected to the emission control line EML, a first pole of the sixth transistor T6 is electrically connected to the second pole of the first transistor T3, and a second pole of the sixth transistor T6 is electrically connected to the anode of the light emitting element EL. The fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. A gate of the seventh transistor T7 is electrically connected to the fourth scan signal line RST2, a first pole of the seventh transistor T7 is electrically connected to the second initialization signal line INIT2, and a second pole of the seventh transistor T7 is electrically connected to the anode of the light emitting element EL. The first sub-capacitor plate of the capacitor C is electrically connected to the gate of the first transistor T3, and the second sub-capacitor plate of the capacitor is electrically connected to the anode of the light emitting element EL.
In this example, the first node N1 is a connection point of the capacitor C, the second transistor T1, the first transistor T3, and the third transistor T2, the second node N2 is a connection point of the third transistor T2, the fifth transistor T5, and the first transistor T3, the third node N3 is a connection point of the first transistor T3, the fourth transistor T4, and the sixth transistor T6, and the fourth node N4 is a connection point of the sixth transistor T6, the seventh transistor T7, the capacitor C, and the light emitting element EL.
In some examples, the light emitting element EL may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or may be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked. The second electrode of the light emitting element is connected to a second power line VSS, a signal of the second power line VSS is a low level signal continuously provided, and a signal of the first power line VDD is a high level signal continuously provided.
In some examples, taking the pixel circuit including the second to seventh transistors T1 to T7 each being an N-type transistor as an example, the operation process of the pixel circuit may include the following stages.
The first phase a1 is referred to as the initialization phase. The high level signal provided by the third scan line RST1 turns on the second transistor T1, and the first initialization signal provided by the first initialization line INIT1 is provided to the first node N1 to initialize the first node N1, thereby clearing the capacitor C from the original data voltage. The first scanning signal line GL1, the second scanning signal line GL2, the fourth scanning signal line RST2, and the emission control line EML supply low-level signals, turning off the third transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. At this stage, the light emitting element EL does not emit light.
The second phase a2 is referred to as the data write phase or the threshold compensation phase. The first scanning signal line GL1 provides a high level signal, the second scanning signal line GL2 provides a high level signal, and the DATA signal line DL outputs the DATA signal DATA. At this stage, the first transistor T3 is turned on because the first sub-capacitor plate of the capacitor C is at a high level. The first scanning signal line GL1 provides a high-level signal to turn on the third transistor T2, the first scanning signal line GL2 provides a high-level signal to turn on the fourth transistor T4, and the fourth scanning signal line RST2 provides a high-level signal to turn on the seventh transistor T7. The third transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output from the data signal line DL is supplied to the first node N1 through the third node N3, the turned-on first transistor T3, the turned-on second node N2, and the turned-on third transistor T2, and a difference between the data voltage Vdata output from the data signal line DL and the threshold voltage Vth of the first transistor T3 is charged into the capacitor. The seventh transistor T7 is turned on, so that the second initialization signal provided by the second initialization signal line INIT2 is provided to the anode of the light-emitting element EL, the anode of the light-emitting element EL is initialized (reset), the pre-stored voltage in the light-emitting element EL is cleared, the initialization is completed, and the light-emitting element EL is ensured not to emit light. The third scan signal line RST1 provides a low signal to turn off the second transistor T1. The light emission control line EML supplies a low level signal to turn off the fifth transistor T5 and the sixth transistor T6.
The third stage a3, referred to as the glow stage. The light-emission control line EML supplies a high-level signal, and the first scanning signal line GL1, the second scanning signal line GL2, the third scanning signal line RST1, and the fourth scanning signal line RST2 each supply a low-level signal. The light emission control line EML supplies a high level signal to turn on the fifth transistor T5 and the sixth transistor T6, and the first voltage signal output from the first power line VDD supplies a driving voltage to the anode of the light emitting element EL through the turned-on fifth transistor T5, first transistor T3, and sixth transistor T6, thereby driving the light emitting element EL to emit light.
During driving of the pixel driving circuit, a driving current flowing through the first transistor T3 (i.e., the driving transistor) is determined by a voltage difference between the gate and the first electrode thereof. Since the voltage of the first node N1 is Vdata- | Vth |, the driving current of the first transistor T3 is:
I＝K×(Vgs-Vth) 2 ＝K×[(Vdd-Vdata+|Vth|)-Vth] 2 ＝K×[Vdd-Vdata] 2 。
where I is a driving current flowing through the first transistor T3, that is, a driving current driving the light emitting element EL, K is a constant, Vgs is a voltage difference between the gate and the first electrode of the first transistor T3, Vth is a threshold voltage of the first transistor T3, Vdata is a data voltage output from the data signal line DL, and Vdd is a first voltage signal output from the first power line Vdd.
It can be seen from the above equation that the current flowing through the light emitting element EL is independent of the threshold voltage of the first transistor T3. The pixel circuit of this embodiment can better compensate the threshold voltage of the first transistor T3.
The display substrate of the present embodiment is exemplified below by some examples.
Fig. 8A is a first cross-sectional view of a display substrate according to an embodiment of the disclosure. In an exemplary embodiment, as shown in fig. 8A, in a direction parallel to the display substrate, the driving circuit layer of the display substrate of the embodiment of the present disclosure may include at least one pixel circuit, and the driving circuit layer includes at least: a first transistor T3, a second transistor T1, a third transistor T2, and a capacitor including at least one first sub-capacitor.
In an exemplary embodiment, the first transistor T3 in the display substrate of the embodiment of the present disclosure may be a driving transistor. The first transistor T1 may be a low temperature polysilicon transistor. The first transistor T1 may be one of a top gate type transistor, a bottom gate type transistor, and a double gate type transistor. For example, the first transistor T1 may be a top gate transistor, and the active layer in the first transistor is located on the side of the gate of the first transistor close to the substrate. The stability of the top gate transistor is good as shown in fig. 8A.
In an exemplary embodiment, the second transistor T1 and the third transistor T2 in the display substrate may both function as switching transistors. The second transistor T1 and the third transistor T2 may each be an oxide transistor. The second transistor T1 and the third transistor T2 may each be one of a top gate type transistor, a bottom gate type transistor, and a double gate type transistor. For example, the second transistor T1 and the third transistor T2 may each be a double gate type transistor. The second transistor T1 and the third transistor T2 are double-gate transistors, which can improve the on-state current and uniformity of the second transistor T1 and the third transistor T2, as shown in fig. 8A.
In an exemplary embodiment, as shown in fig. 8A, a driving circuit layer of a display substrate according to an embodiment of the present disclosure includes, in a direction perpendicular to the display substrate: a first semiconductor layer, a first conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer which are provided over the substrate 101 in this order.
In an exemplary embodiment, the substrate 101 may be a rigid base or a flexible base. For example, the rigid substrate may be, but is not limited to, one or more of glass, quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked on the first flexible material layer, the first flexible material layer and the second flexible material layer may be made of Polyimide (PI), polyethylene terephthalate (PET), or a polymer soft film with a surface treatment, and the first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx), silicon oxide (SiOx), or the like, for improving water and oxygen resistance of the substrate.
In an exemplary embodiment, as shown in fig. 8A, the first semiconductor layer includes at least the first active layer pattern 2 and the first plate 21. The first active layer pattern 2 and the first plate 21 are positioned at one side of the substrate 101. The first active layer pattern 2 may be made of the same material as the first electrode plate 21 through the same manufacturing process. Wherein, the first active layer pattern 2 and the first plate 21 may both adopt a semiconductor material. For example, Low Temperature Polysilicon (LTPS) may be used for both the first active layer pattern 2 and the first plate 21. But the disclosed embodiments are not so limited.
In an exemplary embodiment, as shown in fig. 8A, the first conductive layer includes at least a first gate electrode 3 and a second plate electrode 22, and the first gate electrode 3 and the second plate electrode 22 are both located on the first active layer pattern 2 and the first plate electrode 21 side away from the substrate 101. There is an overlap of the first gate electrode 3 and the first active layer pattern 2 in an orthographic projection of the substrate 101. The first gate electrode 3 may serve as a gate electrode of the first transistor T1, and the first active layer pattern 2 may serve as an active layer of the first transistor T1. The second plate 22 overlaps with the first plate 21 in the orthographic projection of the substrate 101, the first plate 21 can be one electrode plate in the first sub-capacitor, and the second plate 22 can be the other electrode plate in the first sub-capacitor. The first gate 3 and the second plate 22 may be made of the same material and manufactured through the same manufacturing process. Wherein, the first gate 3 and the second plate 22 can both adopt metal materials. But the disclosed embodiments are not so limited.
In an exemplary embodiment, as shown in fig. 8A, the second conductive layer includes at least a second gate 4 and a third gate 5, and the second gate 4 and the third gate 5 are located at the first gate 3 and the side of the second plate 22 away from the substrate 101. At least part of the second grid 4 overlaps at least part of the first plate 21 and at least part of the second plate 22 in the orthographic projection of the substrate 101; at least part of the third gate 5 overlaps with at least part of the first plate 21 and at least part of the second plate 22 in the orthographic projection of the substrate 101. The second gate electrode 4 may serve as a bottom gate of the second transistor T1, and the third gate electrode 5 may serve as a bottom gate of the third transistor T2. The second grid 4 and the third grid 5 can be made of the same material through the same preparation process. Wherein, the second gate 4 and the third gate 5 may both adopt metal materials. But the disclosed embodiments are not so limited.
In an exemplary embodiment, as shown in fig. 8A, the second semiconductor layer includes at least a second active layer pattern 61 and a third active layer pattern 62, and the second active layer pattern 61 and the third active layer pattern 62 are both located at a side of the second gate electrode 4 and the third gate electrode 5 away from the substrate 101. The second active layer pattern 61 overlaps with the second gate electrode 4 in an orthographic projection of the substrate 101, and the second active layer pattern 61 may serve as an active layer of the second transistor T1; the third active layer pattern 62 overlaps with the orthographic projection of the third gate electrode 5 on the substrate 101, and the third active layer pattern 62 may serve as an active layer of the third transistor T2. The second active layer pattern 61 and the third active layer pattern 62 may be made of the same material through the same manufacturing process. Both the second active layer pattern 61 and the third active layer pattern 62 may be made of Oxide semiconductor (Oxide). For example, one of an indium gallium zinc oxide material and an indium tin zinc oxide material may be used for each of the second and third active layer patterns 61 and 62.
In an exemplary embodiment, as shown in fig. 8A, the third conductive layer includes at least a fourth gate electrode 71 and a fifth gate electrode 72, and the fourth gate electrode 71 and the fifth gate electrode 72 are both located at a side of the second active layer pattern 61 and the third active layer pattern 62 away from the substrate 101. The fourth gate electrodes 71 each overlap with the second active layer pattern 61 and the second gate electrode 4 in an orthographic projection of the substrate 101. The fourth gate electrode 71 may serve as a top gate of the first transistor T1. The fifth gates 72 each overlap with the third active layer pattern 62 and the third gate 5 in an orthographic projection of the substrate 101. The fifth gate electrode 72 may serve as a top gate of the third transistor T2. The fourth gate electrode 71 and the fifth gate electrode 72 may be made of the same material and manufactured by the same manufacturing process. The fourth gate 71 and the fifth gate 72 may both be made of a metal material. But the disclosed embodiments are not so limited.
In an exemplary embodiment, as shown in fig. 8A, the fourth conductive layer includes at least a first electrode 81, a second electrode 82, a third electrode 83, and a fourth electrode 84, and the first electrode 81, the second electrode 82, the third electrode 83, and the fourth electrode 84 are all located on the side of the fourth gate 71 and the fifth gate 72 away from the substrate 101. The first electrode 81 may be connected to the third active layer pattern 62 through a first via hole, a first end of the second electrode 82 may be connected to the third active layer pattern 62 through a second via hole, the first electrode 81 may serve as a source of the third transistor T2, and the second electrode 82 may serve as a drain of the third transistor T2. A second end of the second electrode 82 is connected to the second active layer pattern 61 through a third via hole, a first end of the third electrode 83 is connected to the second active layer pattern 61 through a fourth via hole, the second electrode 82 may serve as a source of the second transistor T1, and the third electrode 83 may serve as a drain of the second transistor T1. A second end of the third electrode 83 is connected to the first active layer pattern 2 through a fifth via hole, the fourth electrode 84 is connected to the first active layer pattern 2 through a sixth via hole, the third electrode 83 may serve as a source of the first active layer pattern 2, and the fourth electrode 84 may serve as a drain of the first active layer pattern 2. The first electrode 81, the second electrode 82, the third electrode 83 and the fourth electrode 84 may be made of the same material and manufactured through the same manufacturing process. The first electrode 81, the second electrode 82, the third electrode 83, and the fourth electrode 84 may be made of a metal material. But the disclosed embodiments are not so limited.
In an exemplary embodiment, as shown in fig. 8A, the first active layer pattern 2, the first gate electrode 3, the third electrode 83, and the fourth electrode 84 form a first transistor T3; the second gate electrode 4, the second active layer pattern 61, the fourth gate electrode 71, the second electrode 82, and the third electrode 83 form a second transistor T1; the third gate electrode 5, the third active layer pattern 62, the fifth gate electrode 72, the first electrode 81, and the second electrode 82 form a third transistor T2; the first plate 21 and the second plate 22 form a first sub-capacitor. The orthographic projection of one first sub-capacitor on the substrate is overlapped with the orthographic projection of at least one second transistor T1 and at least one third transistor T2 on the substrate.
In an exemplary embodiment, as shown in fig. 8A, the fifth conductive layer includes at least a light shielding layer 30. The light shielding layer 30 is located on the side of the first electrode 81, the second electrode 82, the third electrode 83, and the fourth electrode 84 away from the substrate 101. The orthographic projection of the light shielding layer 30 on the substrate 101 does not overlap with the orthographic projection of the first transistor T3 on the substrate 101; the orthographic projection of the light shielding layer 30 on the substrate 101 overlaps with the orthographic projection of the second active layer pattern 61 of the second transistor T1 on the substrate 101 and the orthographic projection of the third active layer pattern 62 of the third transistor T2 on the substrate 101. For example, the orthographic projection of the second active layer pattern 61 of the second transistor T1 on the substrate 101 is located in the orthographic projection of the light shielding layer 30 on the substrate 101, and the area of the orthographic projection of the second active layer pattern 61 of the second transistor T1 on the substrate 101 is not larger than the area of the light shielding layer 30 on the orthographic projection of the substrate 101, so that the light shielding layer 30 covers the second active layer pattern 61 of the second transistor T1; the orthographic projection of the third active layer pattern 62 of the third transistor T2 on the substrate 101 is positioned in the orthographic projection of the light shielding layer 30 on the substrate 101, and the area of the orthographic projection of the third active layer pattern 62 of the third transistor T2 on the substrate 101 is not larger than the area of the light shielding layer 30 on the orthographic projection of the substrate 101, so that the light shielding layer 30 covers the third active layer pattern 62 of the third transistor T2.
In an exemplary embodiment, as shown in fig. 8A, an orthogonal projection of the light shielding layer 30 on the substrate 101 overlaps an orthogonal projection of the first sub-capacitor on the substrate 101, for example, the orthogonal projection of the first sub-capacitor on the substrate 101 is located in the orthogonal projection of the light shielding layer 30 on the substrate 101, and an area of the orthogonal projection of the first sub-capacitor on the substrate 101 is not larger than an area of the orthogonal projection of the light shielding layer 30 on the substrate 101. Specifically, the orthographic projections of the light shielding layer 30 on the substrate 101 are overlapped with the orthographic projections of the first polar plate 21 and the second polar plate 22 on the substrate 101. For example, the orthographic projection of the first electrode plate 21 on the substrate 101 is located in the orthographic projection of the light shielding layer 30 on the substrate 101, and the area of the orthographic projection of the first electrode plate 21 on the substrate 101 is not larger than the area of the orthographic projection of the light shielding layer 30 on the substrate 101; and the orthographic projection of the second plate 22 on the substrate 101 is positioned in the orthographic projection of the light shielding layer 30 on the substrate 101, and the orthographic projection area of the second plate 22 on the substrate 101 is not larger than the orthographic projection area of the light shielding layer 30 on the substrate 101.
In an exemplary embodiment, the light shielding layer 30 may be made of an opaque material or a reflective material. For example, the light-shielding layer 30 may be made of a metal material.
In an exemplary embodiment, as shown in fig. 8A, the driving circuit layer may further include: the first barrier layer 11, the first inorganic dielectric layer 12, the second inorganic dielectric layer 13, the first interlayer dielectric layer 14, the second barrier layer 15, the third inorganic dielectric layer 16, the second interlayer dielectric layer 17 and the planarization layer 18 are sequentially disposed on the substrate 101. The first barrier layer 11 is located between the substrate 101 and the first semiconductor layer; the first inorganic dielectric layer 12 is positioned between the first semiconductor layer and the first conductive layer; the second inorganic medium layer 13 is positioned between the first conductive layer and the second conductive layer; the first interlayer dielectric layer 14 and the second barrier layer 15 are positioned between the second conducting layer and the second semiconductor layer, and the first interlayer dielectric layer 14 is positioned on one side, close to the substrate, of the second barrier layer 15; the third inorganic dielectric layer 16 is positioned between the second semiconductor layer and the third conductive layer; the second interlayer dielectric layer 17 is positioned between the third conductive layer and the fourth conductive layer; the planarization layer 18 is located between the fourth conductive layer and the fifth conductive layer. The first inorganic dielectric layer 12 may also be referred to as a first gate insulator (GI1) layer, the second inorganic dielectric layer may also be referred to as a second gate insulator (GI2) layer, and the third inorganic dielectric layer 16 may also be referred to as a third gate insulator (GI3) layer.
In an exemplary embodiment, silicon nitride (SiNx) may be used as the material of the first, second, and third inorganic dielectric layers 12, 13, and 16. The silicon nitride may improve the performance of the first transistor T3. But the disclosed embodiments are not so limited.
Fig. 8B is a second cross-sectional view of a display substrate according to an embodiment of the disclosure. In an exemplary embodiment, as shown in fig. 8B, the capacitor of the display substrate according to the embodiment of the present disclosure further includes: at least one second sub-capacitance. The second sub-capacitor of the display substrate of the embodiment of the disclosure can increase the capacitance of the capacitor, so that the potential at the N1 point in the first transistor T3 is more stable, and the display effect of the display substrate is improved.
In an exemplary embodiment, as shown in fig. 8B, an orthogonal projection of the second sub-capacitor on the substrate 101 does not overlap with an orthogonal projection of the light shielding layer 30 on the substrate 101, and the second sub-capacitor may not be covered by the light shielding layer 30.
In an exemplary embodiment, as shown in fig. 8B, the second sub-capacitance overlaps with the orthographic projection of the first transistor T3 on the substrate 101. Illustratively, there is an overlap of the second sub-capacitance with the orthographic projection of the first active layer pattern 23 in the first transistor T3 on the substrate 101. For example, an orthographic projection of the second sub-capacitor on the substrate 101 is located in an orthographic projection of the first active layer pattern 23 on the substrate 101, and an area of the orthographic projection of the second sub-capacitor on the substrate 101 is not larger than an area of the orthographic projection of the first active layer pattern 23 on the substrate 101.
In an exemplary embodiment, as shown in fig. 8B, the second sub-capacitor includes a third plate and a fourth plate 24 sequentially disposed on the substrate 101, and the orthographic projections of the third plate and the fourth plate 24 on the substrate 101 have an overlap. For example, the orthographic projection of the fourth plate 24 on the substrate is located in the orthographic projection of the third plate on the substrate, and the area of the orthographic projection of the fourth plate 24 on the substrate is not larger than the area of the orthographic projection of the third plate on the substrate.
In an exemplary embodiment, as shown in fig. 8B, the first gate 3 of the first transistor T3 in the display substrate of the embodiment of the disclosure is multiplexed as the third plate of the second sub-capacitor, that is, the first gate 3 of the first transistor T3 may be used as the gate of the first transistor T3 and may also be used as the electrode plate of the second sub-capacitor.
In an exemplary embodiment, as shown in fig. 8B, the second conductive layer in the display substrate of the embodiment of the present disclosure at least includes the second gate 4, the third gate 5 and the fourth plate 24, and the fourth plate 24 may be made of the same material as the second gate 4 and the third gate 5 by the same manufacturing process.
Fig. 8C is a third cross-sectional view of a display substrate according to an embodiment of the disclosure. In an exemplary embodiment, as shown in fig. 8C, the pixel circuit of the display substrate of the embodiment of the disclosure may omit the second conductive layer, and both the second transistor T1 and the third transistor T2 in the pixel circuit employ a top gate type transistor. The pixel circuit can eliminate the second sub-capacitor, the second gate of the second transistor T1 and the third gate of the third transistor T2, thereby reducing the number of manufacturing steps and the production cost.
Fig. 8D is a cross-sectional view of a display substrate according to an embodiment of the disclosure. In an exemplary embodiment, as shown in fig. 8D, the second transistor T1 and the third transistor T2 in the pixel circuit each employ a top gate type transistor. The first conductive layer in the pixel circuit comprises at least a first gate 3 and a first plate 21, the second conductive layer comprises at least a second plate 22, and the second conductive layer does not comprise a second gate and a third gate. The first electrode plate 21 and the second electrode plate 22 form a first sub-capacitor, so that the first sub-capacitor does not affect the resolution, the aperture ratio and the transmittance of the pixel.
In some embodiments, the second transistor T1 and the third transistor T2 in the pixel circuit both employ double gate type transistors. The second plate is multiplexed into the bottom gate of the second transistor T1 and the bottom gate of the third transistor T2; alternatively, the second conductive layer includes a second plate, a second gate electrode as a bottom gate of the second transistor T1, and a third gate electrode as a bottom gate of the third transistor T2.
Fig. 8E is a cross-sectional view of a display substrate according to an embodiment of the disclosure. In an exemplary embodiment, as shown in fig. 8E, the capacitor of the display substrate according to the embodiment of the present disclosure further includes: at least one second sub-capacitance. The second sub-capacitor of the display substrate of the embodiment of the disclosure can increase the capacitance of the capacitor, so that the potential at the N1 point in the first transistor T3 is more stable, and the display effect of the display substrate is improved.
In an exemplary embodiment, as shown in fig. 8E, an orthogonal projection of the second sub-capacitor on the substrate 101 does not overlap with an orthogonal projection of the light shielding layer 30 on the substrate 101, and the second sub-capacitor may not be covered by the light shielding layer 30. The second sub-capacitance overlaps with the orthographic projection of the first transistor T3 on the substrate 101. The second sub-capacitor comprises a third plate and a fourth plate 24 which are sequentially arranged on the substrate 101, and the orthographic projections of the third plate and the fourth plate 24 on the substrate 101 are overlapped. The first gate 3 of the first transistor T3 in the display substrate of the embodiment of the disclosure is reused as the third plate of the second sub-capacitor, that is, the first gate 3 of the first transistor T3 may be used as the gate of the first transistor T3, and may also be used as the electrode plate of the second sub-capacitor.
As shown in fig. 8E, the second transistor T1 and the third transistor T2 in the pixel circuit each employ a top gate type transistor. The first conductive layer in the pixel circuit comprises at least the first gate 3 and the first plate 21, the second conductive layer comprises at least the fourth plate 24 and the second plate 22, and the second conductive layer does not comprise the second gate and the third gate. The first grid 3 and the fourth plate 24 form a second sub-capacitor, and the first plate 21 and the second plate 22 form a first sub-capacitor, so that the second sub-capacitor can increase the capacitance of the capacitor, and the first sub-capacitor does not affect the resolution, the aperture ratio and the transmittance of the pixel.
In some embodiments, the second transistor T1 and the third transistor T2 in the pixel circuit both employ double gate type transistors. The second plate is multiplexed into the bottom gate of the second transistor T1 and the bottom gate of the third transistor T2; alternatively, the second conductive layer includes a second plate, a second gate electrode as a bottom gate of the second transistor T1, and a third gate electrode as a bottom gate of the third transistor T2.
The embodiment also provides a preparation method of the display substrate, which comprises the following steps:
forming at least one first transistor and at least one first sub-capacitor on a substrate;
forming at least one second transistor on the side, away from the substrate, of the at least one first sub-capacitor;
forming a light shielding layer on one side of the at least one second transistor far away from the substrate;
enabling the orthographic projection of the shading layer on the substrate and the orthographic projection of the at least one first transistor on the substrate not to overlap;
and overlapping the orthographic projection of the light shielding layer on the substrate with the orthographic projection of the at least one second transistor and the orthographic projection of the at least one first sub-capacitor on the substrate.
The embodiment also provides a display device, which comprises the display substrate.
In some exemplary embodiments, the display substrate may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be: the OLED display, the mobile phone, the tablet computer, the television, the display, the notebook computer, the digital photo frame, the navigator and other products or components with display functions, which is not limited in the embodiments of the present disclosure.
The drawings in this disclosure relate only to the structures to which this disclosure relates and other structures may be referred to in the general design. Without conflict, features of embodiments of the present disclosure, i.e., embodiments, may be combined with each other to arrive at new embodiments.
It will be understood by those skilled in the art that various modifications and equivalent arrangements may be made in the present disclosure without departing from the spirit and scope of the present disclosure, and the scope of the appended claims should be accorded the full scope of the disclosure.

Claims (20)

1. A display substrate, comprising: a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer comprising: the light shielding layer is positioned on one side, far away from the substrate, of the at least one pixel circuit;
the pixel circuit includes: at least one first transistor, at least one second transistor and at least one capacitor, wherein the capacitor comprises at least one first sub-capacitor;
the orthographic projection of the light shielding layer on the substrate does not overlap with the orthographic projection of the at least one first transistor on the substrate;
the orthographic projection of the light shielding layer on the substrate overlaps with the orthographic projection of the at least one second transistor and the orthographic projection of the at least one first sub-capacitor on the substrate.
2. The display substrate according to claim 1, wherein an orthographic projection of the at least one first sub-capacitor on the substrate is located in an orthographic projection of the light shielding layer on the substrate, and an area of the orthographic projection of the at least one first sub-capacitor on the substrate is not larger than an area of the light shielding layer on the orthographic projection of the substrate.
3. The display substrate of claim 1, wherein the at least one first sub-capacitor is located on a side of the at least one second transistor close to the substrate, and an orthogonal projection of the at least one first sub-capacitor on the substrate overlaps with an orthogonal projection of the at least one second transistor on the substrate.
4. The display substrate of claim 3, wherein the pixel circuit further comprises at least one third transistor, and wherein a front projection of a first sub-capacitor on the substrate overlaps with both the at least one second transistor and the at least one third transistor.
5. The display substrate of claim 1, wherein the first sub-capacitor comprises a first plate and a second plate sequentially disposed on the substrate, and an orthographic projection of the first plate and the orthographic projection of the second plate overlap with each other.
6. The display substrate of claim 5, wherein the orthographic projection of the first plate on the substrate is located in the orthographic projection of the second plate on the substrate, and the area of the orthographic projection of the first plate on the substrate is not larger than the area of the orthographic projection of the second plate on the substrate.
7. The display substrate of claim 5, wherein the first transistor comprises at least a first active layer pattern and a first gate sequentially disposed on the substrate, and an orthographic projection of the first active layer pattern and the first gate on the substrate overlaps.
8. The display substrate according to claim 7, wherein the driving circuit layer further comprises: a semiconductor layer and a first conductive layer sequentially provided on the substrate;
the semiconductor layer includes the first active layer pattern and the first electrode plate;
the first conductive layer includes the first gate and the second plate.
9. The display substrate according to claim 7, wherein the driving circuit layer further comprises: a semiconductor layer, a first conductive layer and a second conductive layer which are sequentially arranged on the substrate;
the semiconductor layer includes the first active layer pattern;
the first conductive layer comprises the first grid and the first polar plate;
the second conductive layer includes the second plate.
10. The display substrate according to claim 7, wherein the material of the first active layer pattern is low temperature polysilicon.
11. The display substrate of claim 1, wherein the capacitor further comprises: and the at least one second sub-capacitor is electrically connected with the at least one first sub-capacitor, and the orthographic projection of the at least one second sub-capacitor on the substrate does not overlap with the orthographic projection of the light shielding layer on the substrate.
12. The display substrate of claim 11, wherein an orthographic projection of the at least one second sub-capacitor on the substrate overlaps with an orthographic projection of the at least one first transistor on the substrate.
13. The display substrate of claim 11, wherein the second sub-capacitor comprises a third plate and a fourth plate sequentially disposed on the substrate, and an orthogonal projection of the third plate and the fourth plate on the substrate overlap.
14. The display substrate of claim 13, wherein an orthographic projection of the third plate on the substrate is located in an orthographic projection of the fourth plate on the substrate, and an area of the orthographic projection of the third plate on the substrate is not greater than an area of the orthographic projection of the fourth plate on the substrate.
15. The display substrate of claim 13, wherein the first transistor comprises at least a first active layer pattern and a first gate sequentially disposed on the substrate, the first active layer pattern and the first gate overlap in an orthographic projection of the substrate, and the third plate is reused as the first gate.
16. The display substrate according to claim 1, wherein the second transistor comprises a second gate electrode, a second active layer pattern and a third gate electrode sequentially disposed on the substrate, the second gate electrode is located on a side of the second active layer pattern close to the substrate, the third gate electrode is located on a side of the second active layer pattern away from the substrate, and an orthographic projection of the second gate electrode, the second active layer pattern and the third gate electrode on the substrate overlaps.
17. The display substrate according to claim 1, wherein the second transistor comprises a second active layer pattern and a third gate electrode sequentially disposed on the substrate, and an orthogonal projection of the second active layer pattern and the third gate electrode on the substrate has an overlap.
18. The display substrate according to claim 16 or 17, wherein the second active layer pattern material comprises an oxide semiconductor.
19. A display device comprising the display substrate according to any one of claims 1 to 18.
20. A method for manufacturing a display substrate, comprising:
forming at least one first transistor and at least one first sub-capacitor on a substrate;
forming at least one second transistor on the side, away from the substrate, of the at least one first sub-capacitor;
forming a light shielding layer on one side of the at least one second transistor far away from the substrate;
enabling the orthographic projection of the light shielding layer on the substrate not to be overlapped with the orthographic projection of the at least one first transistor on the substrate;
and overlapping the orthographic projection of the light shielding layer on the substrate with the orthographic projection of the at least one second transistor and the orthographic projection of the at least one first sub-capacitor on the substrate.
CN202210616222.0A 2022-05-31 2022-05-31 Display substrate, preparation method thereof and display device Pending CN115000092A (en)

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Application Number Priority Date Filing Date Title
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116249394A (en) * 2023-02-28 2023-06-09 惠科股份有限公司 Display panel, display device and preparation method of display panel
CN116249394B (en) * 2023-02-28 2024-05-03 惠科股份有限公司 Display panel, display device and preparation method of display panel

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116249394A (en) * 2023-02-28 2023-06-09 惠科股份有限公司 Display panel, display device and preparation method of display panel
CN116249394B (en) * 2023-02-28 2024-05-03 惠科股份有限公司 Display panel, display device and preparation method of display panel

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