CN114743989A

CN114743989A - Array substrate and display panel

Info

Publication number: CN114743989A
Application number: CN202210386228.3A
Authority: CN
Inventors: 周思思; 吴忠厚
Original assignee: Hefei Visionox Technology Co Ltd
Current assignee: Hefei Visionox Technology Co Ltd
Priority date: 2022-04-13
Filing date: 2022-04-13
Publication date: 2022-07-12

Abstract

The application provides an array substrate and a display panel, and relates to the technical field of display. The array substrate comprises a compensation transistor, a driving transistor, a reference signal line, a first power signal line and a first connecting part; the compensating transistor is connected between the grid electrode and the second electrode of the driving transistor, and the active part of the compensating transistor comprises a conductor part; the first connection portion is electrically connected with the reference signal line, an overlapping region exists between an orthographic projection of the first connection portion on the substrate and an orthographic projection of the conductor portion on the substrate, and no overlapping region exists between the orthographic projection of the first connection portion on the substrate and the orthographic projection of the first power signal line on the substrate. Thus, the leakage phenomenon of the compensating transistor is improved, the parasitic capacitance is reduced, and the transmittance of the display panel is improved.

Description

Array substrate and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate and a display panel.

Background

With the continuous development of display technology, an organic light-emitting diode (OLED) display panel gradually becomes a trend of industrial development due to its characteristics of self-luminescence, high response speed, high contrast, flexibility, and the like.

An array substrate in a display panel includes a pixel driving circuit including a driving transistor and a compensating transistor connected to a gate of the driving transistor. The gate voltage of the driving transistor may be changed due to the leakage problem of the compensation transistor, so that the output current provided by the driving transistor to the light emitting device is changed, thereby causing image quality problems such as flicker (flicker) or crosstalk (crosstalk) of the display panel.

Therefore, the image quality problems such as flicker and crosstalk of the display panel can be improved by improving the leakage phenomenon of the compensation transistor. However, the current method for improving the leakage phenomenon of the compensation transistor causes the problems of increased parasitic capacitance and reduced transmittance.

Disclosure of Invention

In view of the foregoing problems, embodiments of the present disclosure provide an array substrate and a display panel to improve the leakage phenomenon of the compensation transistor, and at the same time, reduce the parasitic capacitance and increase the transmittance.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions:

a first aspect of an embodiment of the present application provides an array substrate, including: a substrate and a plurality of pixel driving circuits disposed on the substrate, each pixel driving circuit including a compensation transistor, a driving transistor, a reference signal line, a first power supply signal line, and a first connection portion; the first pole of the compensation transistor is electrically connected with the second pole of the driving transistor, and the second pole of the compensation transistor is electrically connected with the grid electrode of the driving transistor; the active part of the compensation transistor comprises a conductor part; the first connection portion is electrically connected with the reference signal line, an overlapping region exists between an orthographic projection of the first connection portion on the substrate and an orthographic projection of the conductor portion on the substrate, and no overlapping region exists between the orthographic projection of the first connection portion on the substrate and the orthographic projection of the first power signal line on the substrate.

In this way, by adding the first connection part in each pixel driving circuit, electrically connecting the first connection part with the reference signal line, and overlapping the first connection part with the conductor part in the active part of the compensation transistor to form a coupling capacitor, the potential stability of the conductor part in the active part of the compensation transistor can be improved, thereby improving the leakage phenomenon of the compensation transistor; in addition, since the added first connection portion and the first power signal line do not have an overlapping region, that is, the first connection portion and the first power signal line have a certain distance, the area of the added first connection portion in the second conductive layer can be smaller, so that parasitic capacitance is reduced, and transmittance of the display panel is improved.

In one possible implementation, the active portion of the compensation transistor further includes a first channel region and a second channel region, the conductor portion being located between the first channel region and the second channel region; the conductor part comprises a first conductor part and a second conductor part which are connected with each other; the first conductor part extends along a first direction, the second conductor part extends along a second direction, and the first direction and the second direction are crossed; an overlapping region exists between the orthographic projection of the first connecting part on the substrate and the orthographic projection of the first conductor part and/or the second conductor part on the substrate. In this way, in the case where the first connection portion overlaps with both the first conductor portion and the second conductor portion, the capacitance value of the coupling capacitance formed between the first connection portion and the conductor portion is large, so that the potential of the conductor portion is more stable; and under the condition that the first connecting part is overlapped with the first conductor part or the second conductor part, the capacitance value of the coupling capacitance formed between the first connecting part and the conductor part is smaller, so that the parasitic capacitance of the reference signal line can be reduced.

In one implementation, each of the pixel driving circuits further includes a second connection portion, one end of the second connection portion is electrically connected to the reference signal line, and the other end of the second connection portion is electrically connected to the first connection portion. Thus, the first connecting part is electrically connected with the reference signal line based on the original second connecting part in the array substrate, so that the area of the increased first connecting part is smaller, and the parasitic capacitance of the reference signal line is reduced.

In one implementation, the reference signal line and the first power signal line are disposed in different layers, the first connection portion and the reference signal line are disposed in the same layer, and the second connection portion and the first power signal line are disposed in the same layer. In this way, the first connecting part and the reference signal line are arranged on the same layer, so that the total film quantity of the array substrate can be reduced, and the total thickness of the array substrate can be reduced; in addition, the spacing distance between the first connecting part and the conductor part of the compensation transistor can be reduced, so that the coupling capacitance formed between the first connecting part and the conductor part of the compensation transistor is improved, and the electric leakage phenomenon of the compensation transistor is better improved.

In one implementation, the first connection portion and the second connection portion are disposed on the same layer, and the first connection portion is further disposed on the same layer as the first power signal line. In this way, the increased first connecting parts and the second connecting parts are arranged on the same layer, so that the total film quantity of the array substrate can be reduced, and the total thickness of the array substrate can be reduced; and when the first connecting part and the second connecting part are arranged on the same layer, the first connecting part and the second connecting part do not need to be electrically connected through the through hole of the penetrating interlayer dielectric layer, so that the process complexity in the process of manufacturing the through hole is reduced.

In one implementable embodiment, the pixel drive circuit further includes a first scan signal line and a first reset transistor; the grid electrode of the first reset transistor is controlled by a first scanning signal line, the first pole of the first reset transistor is electrically connected with the reference signal line through a second connecting part, and the second pole of the first reset transistor is electrically connected with the grid electrode of the driving transistor; the orthographic projection of the second connecting part on the substrate is crossed with the orthographic projection of the first scanning signal line on the substrate; and, the first connection portion and the reference signal line are respectively located at both sides of the first scanning signal line in the second direction. Therefore, the newly added first connecting part is positioned on one side of the first scanning signal line far away from the reference signal line, so that the extension length of the first connecting part is smaller, the area of the first connecting part can be reduced, the parasitic capacitance can be reduced, and the transmittance of the display panel can be improved.

In one implementable embodiment, each pixel drive circuit further includes a second scanning signal line, a light emission control signal line, and a data line; the reference signal line, the first scanning signal line, the second scanning signal line, and the light emission control signal line extend in a first direction, the first power signal line and the data line extend in a second direction, and the first direction intersects the second direction; the first scanning signal line is located between the reference signal line and the second scanning signal line, and the second scanning signal line is located between the first scanning signal line and the light-emitting control signal line.

In one embodiment, the gate of the compensation transistor is controlled by the second scan signal line, and the gate of the compensation transistor is a part of the second scan signal line, which has an overlapping region with the channel region of the compensation transistor; each of the pixel driving circuits further includes: a data writing transistor, a second reset transistor, a first light emitting control transistor, a second light emitting control transistor and a storage capacitor; a gate of the data writing transistor is controlled by the second scanning signal line, a first pole of the data writing transistor is electrically connected with the data line, and a second pole of the data writing transistor is electrically connected with the first pole of the driving transistor; a gate of the second reset transistor is controlled by the first scan signal line, a first electrode of the second reset transistor is electrically connected to the reference signal line through the second connection portion, and a second electrode of the second reset transistor is electrically connected to the first electrode of the light emitting device; a gate of the first light emission control transistor is controlled by a light emission control signal line, a first pole of the first light emission control transistor is electrically connected with the first power signal line, and a second pole of the first light emission control transistor is electrically connected with the first pole of the driving transistor; a gate of the second light emission control transistor is controlled by the light emission control signal line, a first pole of the second light emission control transistor is electrically connected to the second pole of the driving transistor, and the second pole of the second light emission control transistor is electrically connected to the first pole of the light emitting device; the first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the first power signal line. In this way, the second scanning signal line is directly adopted as the grid electrode of the compensation transistor, so that the circuit arrangement of the pixel driving circuit is simpler; and based on the connection relationship among the data writing transistor, the second reset transistor, the first light-emitting control transistor, the second light-emitting control transistor and the storage capacitor in the pixel driving circuit, the pixel driving circuit can drive the light-emitting device to normally emit light.

In one possible implementation, the active part of the compensation transistor is located in the active layer; the first scanning signal line, the second scanning signal line, the light-emitting control signal line and the first polar plate of the storage capacitor are positioned on the first conductive layer; the reference signal line and the second polar plate of the storage capacitor are positioned on the second conductive layer; the first power signal line and the data line are located in the third conductive layer; a first gate insulating layer is arranged between the first conducting layer and the active layer, a second gate insulating layer is arranged between the second conducting layer and the first conducting layer, an interlayer dielectric layer is arranged between the third conducting layer and the second conducting layer, and the third conducting layer is positioned on one side, away from the substrate, of the interlayer dielectric layer.

A second aspect of the embodiments of the present application provides a display panel, including the array substrate described above.

The effects of the various possible implementations of the second aspect are similar to those of the first aspect and the possible designs of the first aspect, and are not described herein again.

The construction and other objects and advantages of the present application will be more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 2 is a timing diagram of the pixel driving circuit shown in FIG. 1;

fig. 3 is a schematic structural view of an array substrate in the related art;

fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of an active layer in an array substrate according to an embodiment of the present disclosure;

fig. 6 is a schematic structural view of an active layer and a first conductive layer in an array substrate according to an embodiment of the present disclosure;

fig. 7 is a schematic structural view of an active layer, a first conductive layer and a second conductive layer in an array substrate according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of an active layer, a first conductive layer and a second conductive layer and through vias in an array substrate according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.

Detailed Description

The OLED display panel is provided with an array substrate, the array substrate comprises a substrate and a plurality of sub-pixels arranged on the substrate in an array distribution mode, and each sub-pixel comprises a pixel driving circuit and a light emitting device electrically connected with the pixel driving circuit. As shown in fig. 1, the pixel driving circuit may include a driving transistor M1, a data writing transistor M2, a compensating transistor M3, a first reset transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, a second reset transistor M7, and a storage capacitor C1; in addition, the pixel driving circuit includes a reference signal line REF, a first power source signal line VDD, a first Scan signal line Scan1, a second Scan signal line Scan2, a light emission control signal line EM, and a Data line Data.

The gate of the Data write transistor M2 is controlled by the second Scan signal line Scan2, the first pole of the Data write transistor M2 is electrically connected to the Data line Data, and the second pole of the Data write transistor M2 is electrically connected to the first pole of the driving transistor M1.

The gate of the compensation transistor M3 is controlled by the second Scan signal line Scan2, the first pole of the compensation transistor M3 is electrically connected to the second pole of the driving transistor M1, and the second pole of the compensation transistor M3 is electrically connected to the gate of the driving transistor M1 and the first plate of the storage capacitor C1.

The gate of the first reset transistor M4 is controlled by a first Scan signal line Scan1, a first pole of the first reset transistor M4 is electrically connected to the reference signal line REF, and a second pole of the first reset transistor M4 is electrically connected to the gate of the driving transistor M1.

The gate of the second reset transistor M7 is controlled by a first Scan signal line Scan1, a first pole of the second reset transistor M7 is electrically connected to the reference signal line REF, and a second pole of the second reset transistor M7 is electrically connected to the first pole of the light emitting device EL.

The gate of the first light emission controlling transistor M5 is controlled by the light emission control signal line EM, a first pole of the first light emission controlling transistor M5 is electrically connected to the first power signal line VDD, and a second pole of the first light emission controlling transistor M5 is electrically connected to the first pole of the driving transistor M1.

The gate of the second light emission controlling transistor M6 is controlled by the light emission control signal line EM, the first pole of the second light emission controlling transistor M6 is electrically connected to the second pole of the driving transistor M1, and the second pole of the second light emission controlling transistor M6 is electrically connected to the first pole of the light emitting device EL.

A first plate of the storage capacitor C1 is electrically connected to the gate of the driving transistor M1, and a second plate of the storage capacitor C1 is electrically connected to the first power signal line VDD; the second pole of the light emitting device EL is electrically connected to the second power source signal line VSS. The voltage transmitted on the first power signal line VDD may be higher than the voltage transmitted on the second power signal line VSS.

In some embodiments, the driving transistor M1, the data writing transistor M2, the compensation transistor M3, the first reset transistor M4, the first light emission control transistor M5, the second light emission control transistor M6, and the second reset transistor M7 are all P-type transistors. At this time, the pixel driving circuit shown in fig. 1 can be driven using the timing chart shown in fig. 2.

As shown in fig. 2, in the reset phase t11, the first Scan signal inputted from the first Scan signal line Scan1 is at a low level, so that the first reset transistor M4 and the second reset transistor M7 are turned on, and the reference signal inputted from the reference signal line REF is transmitted to the gate of the driving transistor M1 through the first reset transistor M4, so as to reset the gate of the driving transistor M1; the reference signal inputted to the reference signal line REF is also transmitted to the first electrode of the light emitting device EL through the second reset transistor M7, and resets the first electrode of the light emitting device EL.

In addition, in the reset phase t11, the second Scan signal inputted from the second Scan signal line Scan2 is at a high level, so that the data write transistor M2 and the compensation transistor M3 are both in an off state; the light emission control signal inputted from the light emission control signal line EM is also at a high level, so that both the first light emission control transistor M5 and the second light emission control transistor M6 are in an off state.

In the Data writing phase t12, the second Scan signal inputted from the second Scan signal line Scan2 is at a low level, so that the Data writing transistor M2 and the compensation transistor M3 are both turned on, and the Data signal inputted from the Data line Data is transmitted to the first pole of the driving transistor M1 through the Data writing transistor M2, and is written into the gate of the driving transistor M1 through the driving transistor M1 and the compensation transistor M3 in sequence, and the gate voltage of the driving transistor M1 gradually increases along with the writing of the Data signal until the gate voltage of the driving transistor M1 increases to Vdata + Vth. Vdata refers to a data voltage of the data signal, and Vth refers to a threshold voltage of the driving transistor M1.

In addition, in the data writing phase t12, the first Scan signal inputted from the first Scan signal line Scan1 is at a high level, so that the first reset transistor M4 and the second reset transistor M7 are both in an off state; the light emission control signal inputted from the light emission control signal line EM is also at a high level, so that both the first light emission control transistor M5 and the second light emission control transistor M6 are in an off state.

In the emission control period t13, the emission control signal inputted from the emission control signal line EM is at a low level, so that the first emission control transistor M5 and the second emission control transistor M6 are turned on, and then the driving current is supplied to the first electrode of the light emitting device EL through the first emission control transistor M5, the driving transistor M1 and the second emission control transistor M6. Drive current I ═ K (VgS-Vth) of light-emitting device EL²＝K(Vdata+Vth-Vdd-Vtt)²＝K(Vdata-Vdd)²。

Where K is a process and design related parameter, and once the size and process of the driving transistor M1 are determined, the parameter K may be determined, Vgs is a voltage difference between the gate and the source of the driving transistor M1, and Vdd is a power supply voltage provided by the first power supply signal line Vdd.

It can be seen that the magnitude of the driving current input to the light emitting device EL is related to the power supply voltage VDD supplied from the first power supply signal line VDD and the data voltage Vdata of the data signal, regardless of the threshold voltage of the driving transistor M1. Therefore, the threshold voltage of the driving transistor M1 can be compensated by providing the compensation transistor M3 to prevent the threshold voltage of the driving transistor M1 from drifting to cause instability of the driving current input to the light emitting device EL.

In addition, in the light emission control period t13, the first Scan signal inputted from the first Scan signal line Scan1 is at a high level, so that both the first reset transistor M4 and the second reset transistor M7 are in an off state; the second Scan signal inputted to the second Scan signal line Scan2 is at a high level, so that the data write transistor M2 and the compensation transistor M3 are both in an off state.

The driving process is described by taking as an example that the driving transistor M1, the data writing transistor M2, the compensation transistor M3, the first reset transistor M4, the first light emission control transistor M5, the second light emission control transistor M6, and the second reset transistor M7 are all P-type transistors, and they are turned on when the gate is at a low level and turned off when the gate is at a high level. Of course, the driving transistor M1, the data writing transistor M2, the compensation transistor M3, the first reset transistor M4, the first light emission control transistor M5, the second light emission control transistor M6, and the second reset transistor M7 in the embodiment of the present application may be N-type transistors, which are turned on when the gate is at a high level and turned off when the gate is at a low level. In addition, in order to distinguish two electrodes of a transistor except for a gate, a source thereof is referred to as a first electrode, and a drain thereof is referred to as a second electrode.

When the compensation transistor M3 leaks, the gate voltage of the driving transistor M1 changes, so that the output current provided by the driving transistor M1 to the light emitting device changes, which causes image quality problems such as flicker or crosstalk of the display panel.

In order to improve the image quality problem of the compensation transistor M3, such as flicker or crosstalk of the display panel caused by leakage, in the related art, as shown in fig. 3, a conductive structure 11 may be added in the second conductive layer of the display panel, the conductive structure 11 is electrically connected to the first power signal line VDD through a via penetrating through an interlayer dielectric layer, and the conductive structure 11 overlaps with a conductor portion in the active portion of the compensation transistor M3 to form a coupling capacitor, and the presence of the coupling capacitor may stabilize the potential of the conductor portion in the active portion of the compensation transistor M3, thereby improving the leakage phenomenon of the compensation transistor M3.

However, since the distance between the conductor portion of the compensation transistor M3 and the first power supply signal line VDD is large in the layout distribution of the pixel driving circuit, the area of the conductive structure 11 added in the second conductive layer is also large. When the area of the conductive structure 11 is large, the parasitic capacitance of the first power signal line VDD is increased, thereby causing an increase in power consumption of the display panel; in addition, when the area of the conductive structure 11 is large, the transmittance of the display panel is also reduced.

In view of the above technical problems, embodiments of the present application provide an array substrate and a display panel, in which a first connection portion is added in each pixel driving circuit, the first connection portion is electrically connected to a reference signal line, and the first connection portion overlaps with a conductor portion in an active portion of a compensation transistor to form a coupling capacitor, so that the potential stability of the conductor portion in the active portion of the compensation transistor can be improved, and the leakage phenomenon of the compensation transistor can be improved; in addition, since the added first connection portion and the first power signal line do not have an overlapping region, that is, the first connection portion and the first power signal line have a certain distance, the area of the added first connection portion in the second conductive layer can be smaller, so that parasitic capacitance is reduced, and transmittance of the display panel is improved.

In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below with reference to the accompanying drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are a subset of the embodiments in the present application and not all embodiments in the present application. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 4, an embodiment of the present application provides a schematic structural diagram of an array substrate. The array substrate includes a substrate 10 and a plurality of pixel driving circuits disposed on the substrate 10, each pixel driving circuit including a compensation transistor M3, a driving transistor M1 (not shown in fig. 4), a reference signal line REF, a first power signal line VDD, and a first connection portion 41. The first pole of the compensation transistor M3 is electrically connected to the second pole of the driving transistor M1, and the second pole of the compensation transistor M3 is electrically connected to the gate of the driving transistor M1.

Fig. 5 is a schematic structural diagram of an active layer in an array substrate according to an embodiment of the present disclosure. Referring to fig. 5, the active portion 21 of the compensation transistor M3 includes a first channel region 211, a second channel region 212, and a conductor portion 213 located between the first channel region 211 and the second channel region 212.

The first connection portion 41 is electrically connected to the reference signal line REF, an overlapping region exists between an orthogonal projection of the first connection portion 41 on the substrate 10 and an orthogonal projection of the conductor portion 213 on the substrate 10, and an overlapping region does not exist between an orthogonal projection of the first connection portion 41 on the substrate 10 and an orthogonal projection of the first power signal line VDD on the substrate 10.

In an actual product, the substrate 10 may be a rigid substrate, such as a glass substrate, and the substrate 10 may also be a flexible substrate, such as a Polyimide (PI) substrate. A plurality of pixel driving circuits are distributed on the substrate 10, and the pixel driving circuits are distributed in an array.

The driving transistor M1 refers to a transistor for driving the light emitting device to emit light, the compensation transistor M3 refers to a transistor for compensating for the threshold voltage of the driving transistor M1, and the compensation transistor M3 is connected between the gate and the second pole of the driving transistor M1.

In some embodiments, the compensation transistor M3 is a double-gate transistor, i.e., the compensation transistor has a double-gate structure including two channel regions and a gate corresponding to each channel region, and the two gates are connected to each other. When the compensation transistor M3 is a double-gate transistor, the leakage current of the compensation transistor M3 can be reduced, thereby improving the stability of the gate voltage of the driving transistor M1.

The reference signal line REF refers to a signal line for inputting a reference signal to the first reset transistor M4 to reset the gate of the driving transistor M1 through the first reset transistor M4 and for inputting a reference signal to the second reset transistor M7 to reset the first pole of the light emitting device EL through the second reset transistor M7 during the reset phase t 11. The first power supply signal line VDD refers to a signal line for supplying a power supply voltage VDD for inputting the power supply voltage VDD to the first light emission control transistor M5 during the light emission control period t 13.

As shown in fig. 5, the active portion 21 of the compensation transistor M3 includes a first channel region 211, a second channel region 212, and a conductor portion 213 located between the first channel region 211 and the second channel region 212, and the first channel region 211, the conductor portion 213, and the second channel region 212 are connected in sequence.

The first connection portion 41 is electrically connected to the reference signal line REF, and there is an overlapping region between the orthographic projection of the first connection portion 41 on the substrate 10 and the orthographic projection of the conductor portion 213 on the substrate 10, that is, there is an overlap between the first connection portion 41 and the conductor portion 213, so that the first connection portion 41 and the conductor portion 213 form a coupling capacitance. Since the first connection portion 41 is electrically connected to the reference signal line REF, and the reference signal provided by the reference signal line REF is a constant signal, based on the effect of the coupling capacitor, the potential of the conductor portion 213 is stable, so as to improve the leakage phenomenon of the compensation transistor M3, and the output current provided by the driving transistor M1 to the light emitting device is stable, thereby improving the image quality problems such as flicker or crosstalk of the display panel.

Further, since the first connection portion 41 is not electrically connected to the first power signal line VDD, the parasitic capacitance of the first power signal line VDD is not increased by adding the first connection portion 41. Although the first connection portion 41 is electrically connected to the reference signal line REF, the parasitic capacitance of the reference signal line REF may be increased to a certain extent, since there is no overlapping area between the orthographic projection of the first connection portion 41 on the substrate 10 and the orthographic projection of the first power signal line VDD on the substrate 10, that is, there is a certain distance between the first connection portion 41 and the first power signal line VDD, and the conductive structure 11 in fig. 3 extends to the position of the first power signal line VDD and overlaps the first power signal line VDD, it can be known that the extension length of the first connection portion 41 is smaller than the extension length of the conductive structure 11. Generally, the widths of the traces in the array substrate are not greatly different, and when the extension length of the first connection portion 41 is less than the extension length of the conductive structure 11, the area of the first connection portion 41 (i.e., the occupied area of the orthographic projection of the first connection portion 41 on the substrate 10) can be made smaller than the area of the conductive structure 11 (i.e., the occupied area of the orthographic projection of the conductive structure 11 on the substrate 10).

When the area of the first connection portion 41 is small, the lateral parasitic capacitance between the first connection portion 41 and other metal lines is small, so the parasitic capacitance added by the reference signal line REF is also small, and therefore, the parasitic capacitance of the array substrate can be reduced, and the power consumption of the display panel can be reduced. In addition, when the area of the first connection portion 41 is small, the light shielding area of the first connection portion 41 is also small, so that the transmittance of the display panel can be improved.

In some embodiments, the conductor portion 213 includes a first conductor portion and a second conductor portion connected to each other; the first conductor portion extends in a first direction X, and the second conductor portion extends in a second direction Y, the first direction X intersecting the second direction Y.

Specifically, the first conductor portion is connected to the first channel region 211, and the extending direction of the first channel region 211 is the same as the extending direction of the first conductor portion; the second conductor portion is connected to the second channel region 212, and the extending direction of the second channel region 212 is the same as the extending direction of the second conductor portion.

In some alternative embodiments, the reference signal line REF may extend in the first direction X. The first power signal line VDD may extend in the second direction Y. The first direction X may be perpendicular to the second direction Y. The first direction X may be a row direction of the array substrate, and the second direction Y may be a column direction of the array substrate. The active portion 21 of the compensation transistor M3 has an inverted "L" distribution.

The first direction X is perpendicular to the second direction Y, and is understood to be perpendicular within a process tolerance. For example, the included angle between the first direction X and the second direction Y is considered to be vertical when the included angle is within a predetermined included angle range, for example, the predetermined included angle may be in a range of 85 ° to 95 °.

Of course, in other embodiments, the first direction X and the second direction Y may not be perpendicular, and at this time, an included angle between the first direction X and the second direction Y may be greater than the first preset included angle or smaller than the second preset included angle. For example, the first predetermined included angle may be 95 °, and the second predetermined included angle may be 85 °.

In the array substrate shown in fig. 4, there is an overlapping region between the orthographic projection of the first connection portion 41 on the substrate 10 and the orthographic projection of the first conductor portion and the second conductor portion on the substrate 10, that is, the first connection portion 41 overlaps with both the first conductor portion and the second conductor portion. In this case, the area of the overlapping region between the first connection portion 41 and the conductor portion 213 can be made larger, and the capacitance value of the coupling capacitance formed between the first connection portion 41 and the conductor portion 213 can be made larger, so that the potential of the conductor portion 213 can be made more stable.

Of course, in some embodiments, there may be an overlapping region between the orthographic projection of the first connection portion 41 on the substrate 10 and the orthographic projection of the first conductor portion on the substrate 10, and there may be no overlapping region between the orthographic projection of the first connection portion 41 on the substrate 10 and the orthographic projection of the second conductor portion on the substrate 10. In this case, the area of the overlapping region between the first connection portion 41 and the conductor portion 213 can be made small, so that the capacitance value of the coupling capacitance formed between the first connection portion 41 and the conductor portion 213 can be made small, and the parasitic capacitance of the reference signal line REF can be reduced.

In other embodiments, there may be an overlapping region between the orthographic projection of the first connection portion 41 on the substrate 10 and the orthographic projection of the second conductor portion on the substrate 10, and there may be no overlapping region between the orthographic projection of the first connection portion 41 on the substrate 10 and the orthographic projection of the first conductor portion on the substrate 10. In this case, too, the area of the overlapping region between the first connection portion 41 and the conductor portion 213 is made smaller, and the capacitance value of the coupling capacitance formed between the first connection portion 41 and the conductor portion 213 is made smaller, so that the parasitic capacitance of the reference signal line REF can be reduced.

In the embodiment of the present application, as shown in fig. 4, each pixel driving circuit further includes a second connection portion 61, one end of the second connection portion 61 is electrically connected to the reference signal line REF, and the other end of the second connection portion 61 is electrically connected to the first connection portion 41.

That is, the first connection portion 41 may not be directly connected to the reference signal line REF but connected to the reference signal line REF through the second connection portion 61. The first connection portion 41 and the second connection portion 61 are disposed on different layers. In some embodiments, the reference signal line REF may be disposed in a different layer from the first power signal line VDD.

In some embodiments, the first connection portion 41 may be disposed at the same layer as the reference signal line REF.

In some embodiments, the second connection portion 61 may be disposed at the same layer as the first power signal line VDD.

Note that the "same layer" in the embodiment of the present application refers to a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then performing a patterning process once using the same mask. Depending on the specific pattern, the one-time patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights and/or have different thicknesses.

In addition, in some embodiments, each pixel driving circuit may further include a first Scan signal line Scan 1. The first Scan signal line Scan1 may extend in the first direction X.

In addition, in some embodiments, each pixel driving circuit may further include a second Scan signal line Scan 2. The second Scan signal line Scan2 may extend in the first direction X.

Further, in some embodiments, each pixel driving circuit may further include a light emission control signal line EM (not shown in fig. 4). The emission control signal line EM may extend in the first direction X.

In addition, in some embodiments, each pixel driving circuit may further include a Data line Data. The Data lines Data may extend in the second direction Y.

The reference signal line REF, the first Scan signal line Scan1, the second Scan signal line Scan2, and the light emission control signal line EM may extend in a first direction, and the first power signal line VDD and the Data line Data may extend in a second direction, the first direction intersecting the second direction. Optionally, the first direction is perpendicular to the second direction.

The first Scan signal line Scan1 can be located between the reference signal line REF and the second Scan signal line Scan2, and the second Scan signal line Scan2 can be located between the first Scan signal line Scan1 and the light-emitting control signal line EM.

In the embodiment of the present application, as shown in fig. 4, the gate of the compensation transistor M3 is controlled by the second Scan signal line Scan2, and the gate of the compensation transistor M3 is a portion of the second Scan signal line Scan2, which has an overlapping region with the first channel region 211 and the second channel region 212.

The second Scan signal line Scan2 can be directly used as the gate of the compensation transistor M3, so that the circuit arrangement of the pixel driving circuit is simpler; of course, it is also possible to additionally provide the gate of the compensation transistor M3 and electrically connect the gate of the compensation transistor M3 to the second Scan signal line Scan2, so that the gate of the compensation transistor M3 is controlled by the second Scan signal line Scan 2.

In some embodiments, each pixel driving circuit may further include: data is written to transistor M2.

The gate of the Data writing transistor M2 is controlled by the second Scan signal line Scan2, the first pole of the Data writing transistor M2 is electrically connected to the Data line Data, and the second pole of the Data writing transistor M2 is electrically connected to the first pole of the driving transistor M1.

The structure shown by reference numeral 22 in fig. 5 represents an active portion of the data write transistor M2. The gate of the data write transistor M2 is a portion of the second Scan signal line Scan2 that has an overlap region with the channel region of the active portion 22 of the data write transistor M2.

In some embodiments, each pixel driving circuit may further include: the first reset transistor M4.

The gate of the first reset transistor M4 is controlled by a first Scan signal line Scan1, the first pole of the first reset transistor M4 is electrically connected to the reference signal line REF through the second connection portion 61, and the second pole of the first reset transistor M4 is electrically connected to the gate of the driving transistor M1.

The first reset transistor M4 is also a double-gate transistor, and the leakage current of the first reset transistor M4 can be reduced by adopting a double-gate structure, so that the stability of the gate voltage of the first reset transistor M4 is improved. The structure shown by reference numeral 23 in fig. 5 represents the active portion of the first reset transistor M4, and it can be seen that the active portion of the first reset transistor M4 is distributed in an inverted "U" shape. The gate of the first reset transistor M4 is a portion of the first Scan signal line Scan1 that has an overlapping region with the two channel regions in the active portion 23 of the first reset transistor M4.

In some embodiments, each pixel driving circuit may further include: and a second reset transistor M7.

The gate of the second reset transistor M7 is controlled by the first Scan signal line Scan1, the first pole of the second reset transistor M7 is electrically connected to the reference signal line REF through the second connection portion 61, and the second pole of the second reset transistor M7 is electrically connected to the first pole of the light emitting device EL.

The structure indicated by reference numeral 24 in fig. 5 represents an active portion of the second reset transistor M7. The gate of the second reset transistor M7 may be a portion of the first Scan signal line Scan1 that has an overlap region with the channel region of the active portion 24 of the second reset transistor M7.

In some embodiments, each pixel driving circuit may further include: the first light emission controlling transistor M5.

A specific structure of the first light emitting control transistor M5 is not shown in fig. 4 to 8, and in each pixel driving circuit, the first light emitting control transistor M5 may be located at a side of the second Scan signal line Scan2 away from the first Scan signal line Scan 1. Further, the gate of the first light emission controlling transistor M5 may be a portion of the light emission controlling signal line EM that has an overlap region with the channel region in the active portion of the first light emission controlling transistor M5.

In some embodiments, each pixel driving circuit may further include: the second light emission controlling transistor M6.

A specific structure of the second light emission controlling transistor M6 is not shown in fig. 4 to 8, and in each pixel driving circuit, the second light emission controlling transistor M6 may be located at a side of the second Scan signal line Scan2 away from the first Scan signal line Scan 1. Further, the gate of the second emission control transistor M6 may be a portion of the emission control signal line EM where an overlap region exists with the channel region in the active portion of the second emission control transistor M6.

In some embodiments, each pixel driving circuit may further include: a storage capacitor C1.

A first plate of the storage capacitor C1 is electrically connected to the gate of the driving transistor M1, and a second plate of the storage capacitor C1 is electrically connected to the first power signal line VDD. The first plate and the second plate of the storage capacitor have an overlapping region, and both the first plate and the second plate are located between the second Scan signal line Scan2 and the emission control signal line EM.

In the actual manufacturing process, a patterning process is adopted to form an active layer of the array substrate on the substrate 10, and the active layer of each pixel driving circuit includes an active portion 21 of the compensation transistor M3, an active portion 22 of the data writing transistor M2, an active portion 23 of the first reset transistor M4, and an active portion 24 of the second reset transistor M7 as shown in fig. 5; in addition, the active layer of each pixel driving circuit further includes an active portion of the driving transistor M1, an active portion of the first light emission controlling transistor M5, and an active portion of the second light emission controlling transistor M6, which are not shown in fig. 5.

After the active layer is formed on the substrate 10, a first gate insulating layer covering the active layer and the substrate 10 is also formed, and then a first conductive layer of the array substrate is formed on the first gate insulating layer by using a patterning process. The first conductive layer may include a first Scan signal line Scan1 and a second Scan signal line Scan2 as shown in fig. 6; in addition, the first conductive layer may further include a light emission control signal line EM and a first plate of the storage capacitor C1, which are not shown in fig. 6.

That is, the first Scan signal line Scan1, the second Scan signal line Scan2, the light emission control signal line EM, and the first plate of the storage capacitor C1 are all located in a first conductive layer, which may also be referred to as a first gate layer.

After forming the first conductive layer on the first gate insulating layer, a second gate insulating layer covering the first conductive layer and the first gate insulating layer may be formed, and then, a second conductive layer of the array substrate may be formed on the second gate insulating layer using a patterning process. The second conductive layer may include the reference signal line REF and the first connection portion 41 as shown in fig. 7; in addition, the second conductive layer may also include a second plate of the storage capacitor C1, which is not shown in fig. 7.

That is, the reference signal line REF, the first connection portion 41, and the second plate of the storage capacitor C1 are all located in a second conductive layer, which may also be referred to as a second gate layer.

After forming the second conductive layer on the second gate insulating layer, an interlayer dielectric layer covering the second conductive layer and the second gate insulating layer may be formed, and then, a through via hole is formed by using an etching process. In fig. 8, a first via hole 51 penetrates through the interlayer dielectric layer, a second via hole 52 penetrates through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer, a third via hole 53 penetrates through the interlayer dielectric layer, a fourth via hole 54 penetrates through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer, and a fifth via hole 55 penetrates through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer. In the second direction, the third via 53 is located at a side of the first Scan signal line Scan1 away from the reference signal line REF.

Finally, a third conductive layer of the array substrate is formed on the interlayer dielectric layer using a patterning process, and the third conductive layer includes the first power signal line VDD, the Data line Data, the second connection portion 61, and the third connection portion 62 as shown in fig. 4.

That is, the first power supply signal line VDD, the Data line Data, the second connection portion 61, and the third connection portion 62 are all located on the third conductive layer, which may also be referred to as a source-drain electrode layer.

It is understood that, when the third conductive layer is formed, the conductive material of the third conductive layer may be correspondingly formed in the through via to form the array substrate as shown in fig. 4. Thus, the second connection portion 61 is electrically connected to the reference signal line REF through the first through via 51, and the second connection portion 61 is electrically connected to the active layer through the second through via 52 (specifically, the second connection portion 61 is electrically connected to the active portions of the first and second reset transistors M4 and M7 through the second through via 52, so that the second connection portion 61 is electrically connected to the first pole of the first reset transistor M4 through the second through via 52, and the second connection portion 61 is electrically connected to the first pole of the second reset transistor M7 through the second through via 52), and the second connection portion 61 is also electrically connected to the first connection portion 41 through the third through via 53; the third connection portion 62 is electrically connected to the active layer through the fourth through hole 54 (specifically, the third connection portion 62 is electrically connected to the second pole of the compensation transistor M3 through the fourth through hole 54), and the Data line Data is electrically connected to the active portion 22 of the Data writing transistor M2 through the fifth through hole 55 (specifically, the Data line Data is electrically connected to the first pole of the Data writing transistor M2 through the fifth through hole 55).

Since most of the wire segments (i.e., the wire segments between the first via 51 and the second via 52) in the second connection portion 61 shown in fig. 4 are possessed by themselves in the layout shown in fig. 3, the second connection portion 61 shown in fig. 4 is different from the corresponding conductive segments in fig. 3 in that the second connection portion 61 also extends toward one side of the second Scan signal line Scan2 and is electrically connected to the first connection portion 41 through the third via 53.

It can be seen that, compared to the layout shown in fig. 3, the newly added conductive segments in the layout shown in fig. 4 include: the wire segment extending in the second connection portion 61 and the first connection portion 41, and the conductive structure 11 in fig. 3 is removed. Since the extension length of the wire segment extending in the second connection portion 61 is short, and the first connection portion 41 and the first power signal line VDD have a certain distance, and the conductive structure 11 in fig. 3 extends to the position of the first power signal line VDD, it can be known that the sum of the extension length of the first connection portion 41 and the extension length of the wire segment extending in the second connection portion 61 is also smaller than the extension length of the conductive structure 11, so that the total area of the wire segments extending in the first connection portion 41 and the second connection portion 61 is smaller than the area of the conductive structure 11, thereby reducing the parasitic capacitance of the reference signal line REF and improving the transmittance of the display panel.

In addition, the orthogonal projection of the wire segment extending in the second connection portion 61 on the substrate 10 has no overlapping region with the orthogonal projection of the active pattern in the active layer (i.e., the active portion 23 of the first reset transistor M4 and the active portion 24 of the second reset transistor M7) on the substrate 10.

Optionally, there is an overlapping region between the orthographic projection of the first end of the second connection portion 61 on the substrate 10 and the orthographic projection of the reference signal line REF on the substrate 10. A first end of the second connection portion 61 is electrically connected to the reference signal line REF through a first via 51 passing therethrough. Optionally, there is an overlapping region between an orthogonal projection of the second end of the second connection portion 61 on the substrate 10 and an orthogonal projection of the first connection portion 41 on the substrate 10. A second end of the second connection portion 61 is electrically connected to the first connection portion 41 through a third through hole 53. An orthogonal projection of the second connection portion 61 on the substrate 10 and an orthogonal projection of the first Scan signal line Scan1 on the substrate 10 may be provided to intersect. The orthographic projections of the first and second ends of the second connection portion 61 on the substrate 10 may be located on both sides of the orthographic projection of the first Scan signal line Scan1 on the substrate, that is, the first connection portion 41 and the reference signal line REF are located on both sides of the first Scan signal line Scan1, respectively, in the second direction Y. The orthographic projections of the first and second via

holes

51 and 52 on the substrate may be located at both sides of the orthographic projection of the first Scan signal line Scan1 on the substrate.

Alternatively, the first connection portion 41 may be located on a side of the first Scan signal line Scan1 away from the reference signal line REF. An orthogonal projection of the first connection portion 41 on the substrate 10 and an orthogonal projection of the second Scan signal line Scan2 on the substrate 10 may not overlap. The orthographic projections of the first and

second connection portions

41 and 61 on the substrate 10 may be located on the same side as the orthographic projection of the first power supply signal line VDD on the substrate 10. There may be no wire segment between the conductor portion 213 and the first power signal line VDD, which forms a coupling capacitance.

As described above, a first gate insulating layer is disposed between the first conductive layer and the active layer, a second gate insulating layer is disposed between the second conductive layer and the first conductive layer, an interlayer dielectric layer is disposed between the third conductive layer and the second conductive layer, and the third conductive layer is located on a side of the interlayer dielectric layer away from the substrate 10.

The first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer may all be made of inorganic insulating materials, for example, the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer may be silicon nitride layers or silicon oxide layers, or the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer may also include silicon nitride layers and silicon oxide layers which are stacked. The material of the first conductive layer, the second conductive layer and the third conductive layer can be titanium, aluminum, molybdenum, copper and other metal materials.

It should be noted that the array substrate shown in fig. 4 only shows a circuit structure in one pixel driving circuit, and the circuit structure only includes a part of transistors and a part of signal lines in the pixel driving circuit shown in fig. 1.

In addition, the array substrate further comprises a passivation layer covering the third conductive layer and the interlayer dielectric layer, and a flat layer disposed on a side of the passivation layer away from the substrate 10. The passivation layer can be a silicon nitride layer or a silicon oxide layer, or the passivation layer can also comprise the silicon nitride layer and the silicon oxide layer which are arranged in a stacked mode; the material of the planarization layer may be an organic material, such as a resin.

In other embodiments, as shown in fig. 9, the compensation transistor M3 may also be a single-gate transistor including a channel region and a gate corresponding to the channel region.

Specifically, the active portion 21 of the compensation transistor M3 may include a channel region and a conductor portion, and the channel region may be the second channel region 212 shown in fig. 5, in this case, the active portion 21 of the compensation transistor M3 does not include the first channel region 211 shown in fig. 5, and a region corresponding to the first channel region 211 shown in fig. 5 is also subjected to a conductor processing to form a conductor portion, that is, the conductor portion in fig. 9 actually includes the conductor portion 213 shown in fig. 5, and the structure after the conductor processing of the first channel region 211 shown in fig. 5.

Therefore, as shown in fig. 9, the gate of the compensation transistor M3 is controlled by the second Scan signal line Scan2, and the gate of the compensation transistor M3 is located in the second Scan signal line Scan2 and has an overlapping region with the channel region (i.e., the second channel region 212).

In other embodiments, as shown in fig. 10, each pixel driving circuit further includes a second connection portion 61, the first connection portion 41 is disposed on the same layer as the second connection portion 61, and the first connection portion 41 is further disposed on the same layer as the first power signal line VDD. That is, the first connection portion 41, the second connection portion 61, and the first power supply signal line VDD are all provided in the same layer.

The first connection portion 41 and the second connection portion 61 may be formed using the same patterning process, so that the first connection portion 41 and the second connection portion 61 are an integral structure.

It should be noted that the layout shown in fig. 10 differs from the layout shown in fig. 4 in that, in the layout shown in fig. 4, the first connection portion 41 and the second connection portion 61 are arranged in different layers, and are electrically connected through the third through hole 53; in the layout shown in fig. 10, the first connection portion 41 and the second connection portion 61 are disposed on the same layer, and are not electrically connected through the third through hole 53, but are formed into an integral structure by using the same patterning process in the manufacturing process. Therefore, in the manufacturing process of the layout shown in fig. 10, a third via does not need to be formed, so that the process complexity in the via manufacturing process is reduced.

Therefore, the first connection portion is added in each pixel driving circuit, the first connection portion is electrically connected with the reference signal line, and the first connection portion and the conductor portion in the active portion of the compensation transistor are overlapped to form a coupling capacitor, so that the potential stability of the conductor portion in the active portion of the compensation transistor can be improved, and the leakage phenomenon of the compensation transistor can be improved; in addition, since the added first connection portion and the first power signal line do not have an overlapping region, that is, the first connection portion and the first power signal line have a certain distance, the area of the added first connection portion in the second conductive layer can be smaller, so that parasitic capacitance is reduced, and transmittance of the display panel is improved.

The embodiment of the present application further provides a display panel, which includes the array substrate described in the above technical solution. Therefore, the display panel provided in the embodiment of the present application also has the beneficial effects described in the above embodiments, and details are not repeated herein.

In addition, the display panel may further include a light emitting device layer and an encapsulation layer disposed on the array substrate. The light-emitting device layer comprises an anode, a pixel defining layer, a light-emitting layer, a cathode and the like. The light emitting device EL in fig. 1 includes an anode, a light emitting layer, and a cathode, which are stacked, and a first pole of the light emitting device EL is referred to as the anode and a second pole of the light emitting device EL is referred to as the cathode.

Specifically, the anode may be located on a side of the flat layer of the array substrate away from the substrate 10, the pixel defining layer is also located on a side of the flat layer of the array substrate away from the substrate 10, the pixel defining layer has a pixel opening exposing the anode, the light emitting layer is located in the pixel opening, and the cathode layer covers the pixel defining layer and the light emitting layer.

The encapsulation layer may be an organic encapsulation layer, an inorganic encapsulation layer, or a stacked structure of an organic encapsulation layer and an organic encapsulation layer.

The display panel may include a first display region and a second display region. The photosensitive element may be used to collect light transmitted through the second display region. The photosensitive element may comprise one or more of a camera and a fingerprint identification module. The transmittance of the second display region may be greater than or equal to the transmittance of the first display region. The second display region is provided with a pixel driving circuit having the same or similar structure as that of fig. 4, 9, 10, and the like. The pixel driving circuits of the first display area and the second display area can be the same or different. The display panel can be full-screen display, has no non-display area, and the width of the frame is almost zero.

It should be noted that the display panel provided in the embodiment of the present invention may be an organic light emitting display panel, and may also be a liquid crystal display panel. Illustratively, the display panel may be any product or component having a display function, such as a mobile phone, a tablet computer, a wearable device, a display, a notebook computer, and a navigator.

In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning a fixed connection, an indirect connection via an intermediary, a connection between two elements, or an interaction between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be configured in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. In the description of the present application, "a plurality" means two or more unless specifically stated otherwise.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, comprising: a substrate and a plurality of pixel driving circuits disposed on the substrate, each of the pixel driving circuits including a compensation transistor, a driving transistor, a reference signal line, a first power supply signal line, and a first connection portion;

the first pole of the compensation transistor is electrically connected with the second pole of the driving transistor, and the second pole of the compensation transistor is electrically connected with the grid electrode of the driving transistor; the active portion of the compensation transistor includes a conductor portion;

the first connection portion is electrically connected to the reference signal line, an orthogonal projection of the first connection portion on the substrate and an orthogonal projection of the conductor portion on the substrate have an overlapping region, and an orthogonal projection of the first connection portion on the substrate and an orthogonal projection of the first power signal line on the substrate do not have an overlapping region.

2. The array substrate of claim 1, wherein the active portion of the compensation transistor further comprises a first channel region and a second channel region, the conductor portion being located between the first channel region and the second channel region;

the conductor part comprises a first conductor part and a second conductor part which are connected with each other; the first conductor portion extends in a first direction, the second conductor portion extends in a second direction, and the first direction intersects the second direction;

an orthogonal projection of the first connection portion on the substrate and an orthogonal projection of the first conductor portion and/or the second conductor portion on the substrate have an overlapping region.

3. The array substrate of claim 1, wherein each of the pixel driving circuits further comprises a second connection portion, one end of the second connection portion is electrically connected to the reference signal line, and the other end of the second connection portion is electrically connected to the first connection portion.

4. The array substrate of claim 3, wherein the reference signal line is disposed in a different layer from the first power signal line, the first connection portion is disposed in a same layer as the reference signal line, and the second connection portion is disposed in a same layer as the first power signal line.

5. The array substrate of claim 3, wherein the first connection portion is disposed in the same layer as the second connection portion, and the first connection portion is further disposed in the same layer as the first power signal line.

6. The array substrate of claim 3, wherein the pixel driving circuit further comprises a first scan signal line and a first reset transistor;

a gate of the first reset transistor is controlled by the first scan signal line, a first electrode of the first reset transistor is electrically connected to the reference signal line through the second connection portion, and a second electrode of the first reset transistor is electrically connected to the gate of the driving transistor;

the orthographic projection of the second connecting part on the substrate is crossed with the orthographic projection of the first scanning signal line on the substrate; and, the first connection portion and the reference signal line are respectively located at both sides of the first scanning signal line in a second direction.

7. The array substrate of claim 6, wherein each of the pixel driving circuits further comprises a second scanning signal line, a light emission control signal line, and a data line;

the reference signal line, the first scanning signal line, the second scanning signal line, and the light emission control signal line extend in a first direction, the first power supply signal line and the data line extend in a second direction, and the first direction intersects the second direction;

preferably, the first scanning signal line is located between the reference signal line and the second scanning signal line, and the second scanning signal line is located between the first scanning signal line and the emission control signal line.

8. The array substrate of claim 7, wherein the gate of the compensation transistor is controlled by the second scan signal line, and the gate of the compensation transistor is a portion of the second scan signal line that overlaps with the channel region of the compensation transistor;

preferably, each of the pixel driving circuits further includes: a data writing transistor, a second reset transistor, a first light emitting control transistor, a second light emitting control transistor and a storage capacitor;

a gate of the data writing transistor is controlled by the second scanning signal line, a first pole of the data writing transistor is electrically connected to the data line, and a second pole of the data writing transistor is electrically connected to the first pole of the driving transistor;

a gate of the second reset transistor is controlled by the first scan signal line, a first electrode of the second reset transistor is electrically connected to the reference signal line through the second connection portion, and a second electrode of the second reset transistor is electrically connected to the first electrode of the light emitting device;

a gate of the first light emission control transistor is controlled by the light emission control signal line, a first pole of the first light emission control transistor is electrically connected to the first power signal line, and a second pole of the first light emission control transistor is electrically connected to the first pole of the driving transistor;

a gate electrode of the second emission control transistor is controlled by the emission control signal line, a first electrode of the second emission control transistor is electrically connected to a second electrode of the driving transistor, and the second electrode of the second emission control transistor is electrically connected to the first electrode of the light emitting device;

the first plate of the storage capacitor is electrically connected with the grid electrode of the driving transistor, and the second plate of the storage capacitor is electrically connected with the first power signal wire.

9. The array substrate of claim 8, wherein the active portion of the compensation transistor is located in an active layer; the first scanning signal line, the second scanning signal line, the light-emitting control signal line and the first polar plate of the storage capacitor are positioned on a first conductive layer; the reference signal line and the second polar plate of the storage capacitor are positioned on the second conducting layer; the first power signal line and the data line are located in a third conductive layer;

a first gate insulating layer is arranged between the first conducting layer and the active layer, a second gate insulating layer is arranged between the second conducting layer and the first conducting layer, an interlayer dielectric layer is arranged between the third conducting layer and the second conducting layer, and the third conducting layer is positioned on one side, far away from the substrate, of the interlayer dielectric layer.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.