WO2024066164A1

WO2024066164A1 - Display panel

Info

Publication number: WO2024066164A1
Application number: PCT/CN2023/075583
Authority: WO
Inventors: 刘大超; 曾勉; 孙亮
Original assignee: 武汉华星光电半导体显示技术有限公司
Priority date: 2022-09-29
Filing date: 2023-02-13
Publication date: 2024-04-04
Also published as: CN115631712A

Abstract

The present application discloses a display panel, comprising an active layer and a variable signal line. The active layer comprises a first channel portion, a second channel portion, and a coupling capacitance active portion connected between the first channel portion and the second channel portion; the first channel portion and the second channel portion have a first width and a second width in a first direction, respectively; the coupling capacitance active portion has a third width in a second direction; the third width is greater than the first width and the second width; and the variable signal line overlaps the coupling capacitance active portion to form a coupling capacitance transistor.

Description

Display Panel

Technical Field

The present application relates to the field of display technology, and in particular to a display panel.

Background technique

When the display panel is driven at a low frequency, the brightness of the light-emitting device changes greatly within a display cycle, causing flickering in the display panel. Although the display panel made of LTPO (Low Temperature Polycrystalline Oxide) backplane and adaptive refresh frequency technology can improve the low-frequency flicker problem, the structure and preparation process of the LTPO backplane are more complex than those of the LTPS (Low Temperature Poly-silicon) backplane, and the preparation cost is higher than that of the LTPS backplane.

technical problem

The embodiment of the present application provides a display panel that can improve the low-frequency flicker problem.

Technical Solutions

The embodiment of the present application provides a display panel, including a substrate, an active layer and a variable signal line. The active layer is located on the substrate, including a first channel portion, a second channel portion and a coupling-capacitive active portion connected between the first channel portion and the second channel portion. The variable signal line overlaps with the coupling-capacitive active portion. The first channel portion and the second channel portion have a first width and a second width in a first direction, respectively, and the coupling-capacitive active portion has a third width in a second direction intersecting the first direction, and the third width is greater than the first width and the second width.

Optionally, in some embodiments of the present application, the active coupling portion includes a connecting portion and an overlapping portion connected to each other, the overlapping portion and the first channel portion are respectively located on opposite sides of the connecting portion, and the first channel portion and the second channel portion are located on the same side of the connecting portion and are both connected to the connecting portion. The overlapping portion overlaps the variable signal line.

Optionally, in some embodiments of the present application, the ion doping concentration of the overlapping portion is less than the ion doping concentration of the connecting portion.

Optionally, in some embodiments of the present application, the display panel further includes a light-emitting device and a pixel driving circuit, wherein the pixel driving circuit includes a driving transistor and a compensation transistor. The driving transistor and the light-emitting device are connected in series between a first power line and a second power line; the compensation transistor includes a first sub-transistor and a second sub-transistor connected in series, one of the source and the drain of the first sub-transistor is electrically connected to the gate of the driving transistor, the other of the source and the drain of the first sub-transistor is electrically connected to one of the source and the drain of the second sub-transistor, the other of the source and the drain of the second sub-transistor is electrically connected to one of the source and the drain of the driving transistor, and the gate of the first sub-transistor and the gate of the second sub-transistor are both electrically connected to the first scan line. Wherein, the active layer further includes a first sub-active pattern of the first sub-transistor and a second sub-active pattern of the second sub-transistor, the first sub-active pattern includes the first channel portion, and the second sub-active pattern includes the second channel portion.

Optionally, in some embodiments of the present application, the first scan line extends along the first direction, the first scan line includes a first routing portion and a second routing portion located at both ends of the first routing portion and connected to the first routing portion, and the first routing portion overlaps with the first channel portion and the second channel portion. In the second direction, the distance between the first routing portion and the variable signal line is greater than the distance between the second routing portion and the variable signal line.

Optionally, in some embodiments of the present application, the pixel driving circuit further includes a reset transistor, the reset transistor includes a third sub-transistor and a fourth sub-transistor connected in series, one of the source and the drain of the third sub-transistor is electrically connected to the first reset line, one of the source and the drain of the fourth sub-transistor is electrically connected to the other of the source and the drain of the second sub-transistor, the other of the source and the drain of the fourth sub-transistor is electrically connected to the other of the source and the drain of the third sub-transistor, and the gate of the third sub-transistor and the gate of the fourth sub-transistor are both electrically connected to the second scan line. Wherein, the variable signal line is located between the first scan line and the second scan line.

Optionally, in some embodiments of the present application, the active layer further includes a third sub-active pattern of the third sub-transistor, a fourth sub-active pattern of the fourth sub-transistor and an electrical connection portion, the third sub-active pattern and the fourth sub-active pattern are connected through the electrical connection portion, and the third sub-active pattern and the fourth sub-active pattern are both spaced apart from the variable signal line. The third sub-active pattern and the second sub-active pattern are respectively located on opposite sides of the variable signal line, and the third sub-active pattern and the fourth sub-active pattern are located on the same side of the variable signal line.

Optionally, in some embodiments of the present application, the second sub-active pattern and the fourth sub-active pattern are electrically connected via a bridge portion that is in a different layer from the variable signal line.

Optionally, in some embodiments of the present application, the third sub-active pattern is electrically connected to the first reset line via a sixth conductive portion in a different layer from the first reset line, wherein the bridge portion and the sixth conductive portion are in the same layer and made of the same material.

Optionally, in some embodiments of the present application, the pixel driving circuit further includes a second transistor and a third transistor. The source and drain of the second transistor are electrically connected between one of the source and drain of the driving transistor and the data line, and the gate of the second transistor is electrically connected to the third scan line; the source and drain of the third transistor are electrically connected between the other of the source and drain of the driving transistor and the other of the source and drain of the second sub-transistor, and the gate of the third transistor is electrically connected to the third scan line. The third scan line is located on the side of the first scan line away from the variable signal line.

Optionally, in some embodiments of the present application, the active layer includes a first active pattern of the driving transistor, a second active pattern of the second transistor, and a third active pattern of the third transistor, and the first active pattern is connected between the second active pattern of the second transistor and the third active pattern. The third scan line partially overlaps with the second active pattern and the third active pattern of the second transistor, respectively, and the first active pattern is located on a side of the third scan line away from the variable signal line; the second active pattern is electrically connected to the data line through a second conductive portion in the same layer as the bridge portion; and the third active pattern is electrically connected to the fourth sub-active pattern through the bridge portion.

Optionally, in some embodiments of the present application, the display panel further includes:

A first conductive layer, located on the active layer, including the variable signal line;

A second conductive layer, located on the first conductive layer, including the first reset line;

a third conductive layer, located on the second conductive layer, comprising the bridge portion; and

The fourth conductive layer is located on the third conductive layer and includes the data line.

Optionally, in some embodiments of the present application, the data line includes a first main body portion and an extension portion. The first main body portion extends along the second direction, and the extension portion is connected to the first main body portion and overlaps with the second conductive portion. The extension portion is electrically connected to the second conductive portion.

Optionally, in some embodiments of the present application, the first reset line is located on a side of the second scan line away from the variable signal line, and the first reset line overlaps with the electrical connection portion.

Optionally, in some embodiments of the present application, the variable signal line is in the same layer and made of the same material as the first scan line and the second scan line.

Beneficial Effects

Compared with the prior art, the present application provides a display panel, including a substrate, an active layer and a variable signal line. The active layer is located on the substrate, including a first channel portion, a second channel portion and a coupling-capacitive active portion connected between the first channel portion and the second channel portion; the first channel portion and the second channel portion have a first width and a second width respectively in a first direction, and the coupling-capacitive active portion has a third width in a second direction intersecting the first direction, and the third width is greater than the first width and the second width. The variable signal line overlaps with the coupling-capacitive active portion to form a coupling-capacitive transistor with a capacitive characteristic, so as to improve the low-frequency flicker problem by using the variable signal transmitted by the coupling-capacitive transistor and the variable signal line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1A is a schematic diagram of a structure in which a variable signal line overlaps an active layer;

Fig. 1B is a cross-sectional view taken along the line p-p' in Fig. 1A;

Fig. 1C is a cross-sectional view taken along the line z-z' in Fig. 1A;

FIG2 is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present application;

FIG3 is a timing diagram of a pixel driving circuit provided in an embodiment of the present application;

FIG4 is a schematic diagram of display brightness change provided by an embodiment of the present application;

FIG5 is a schematic diagram of a film layer structure of a pixel driving circuit provided in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of an active layer provided in an embodiment of the present application;

FIG7 is a schematic diagram of the structure of a first conductive layer provided in an embodiment of the present application;

FIG8 is a schematic diagram of the structure of a second conductive layer provided in an embodiment of the present application;

FIG9 is a schematic structural diagram of a third conductive layer provided in an embodiment of the present application;

FIG. 10 is a schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present application.

Embodiments of the present invention

In order to make the purpose, technical solution and effect of the present application clearer and more specific, the present application is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described here are only used to explain the present application and are not used to limit the present application.

Fig. 1A is a schematic diagram of a structure in which a variable signal line overlaps an active layer; Fig. 1B is a cross-sectional view taken along line p-p' in Fig. 1A; and Fig. 1C is a cross-sectional view taken along line z-z' in Fig. 1A. The present application provides a display panel, including a substrate 100, an active layer 101, and a variable signal line EML1.

The substrate 100 includes a rigid substrate and a flexible substrate. Optionally, the substrate 100 includes glass, polyimide, quartz, etc. Optionally, a buffer layer 100 a is further disposed on the substrate 100 .

The active layer 101 is located on the substrate 100. Optionally, the active layer 101 includes a silicon semiconductor material or an oxide semiconductor material. Optionally, the silicon semiconductor material includes single crystal silicon, polycrystalline silicon, etc.; the oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO) or indium gallium zinc tin oxide (IGZTO), etc. Optionally, the active layer 101 is made using a low temperature polysilicon process.

Optionally, the active layer 101 includes a first channel portion CP1, a second channel portion CP2, and a coupling-capacitive active portion connected between the first channel portion CP1 and the second channel portion CP2. The first channel portion CP1 and the second channel portion CP2 have a first width W1 and a second width W2 in a first direction x, respectively, and the coupling-capacitive active portion has a third width W3 in a second direction y intersecting the first direction x, and the third width W3 is greater than the first width W1 and the second width W2.

The variable signal line EML1 and the active part of the coupling capacitor at least partially overlap to form a coupling capacitor transistor with capacitance characteristics, so as to improve the low-frequency flicker problem by using the coupling capacitor transistor and the variable signal EM1 transmitted by the variable signal line EML1.

Optionally, the coupling-capacitive active portion includes a connecting portion Cn1 and an overlapping portion Cn2 connected to each other, the overlapping portion Cn2 and the first channel portion CP1 are respectively located on opposite sides of the connecting portion Cn1, and the first channel portion CP1 and the second channel portion CP2 are located on the same side of the connecting portion Cn1 and are both connected to the connecting portion Cn1. The overlapping portion Cn2 overlaps with the variable signal line EML1 to form a coupling-capacitive transistor with capacitance characteristics.

Optionally, the active layer 101 can be doped using a self-alignment process in the process, that is, the variable signal line EML1 blocks the overlapping portion Cn2, so that the ion doping concentration of the overlapping portion Cn2 is lower than the ion doping concentration of the connecting portion Cn1, thereby saving the number of masks used in the process and thus saving preparation costs.

Optionally, the display panel further includes a first insulating layer 1001 located on the active layer 101. Optionally, the first insulating layer 1001 includes a silicon compound, a metal oxide, etc. Further, the first insulating layer 1001 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

Optionally, the display panel further includes a first conductive layer 102 located on the first insulating layer 1001, and the first conductive layer 102 includes a variable signal line EML1. Optionally, the first conductive layer 102 includes at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), etc. Optionally, the first conductive layer 102 can be a single-layer film structure, or a stacked structure such as Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Cu/Mo, Cu/Ti, Cu/MoTi or Cu/MoNb.

Optionally, the first conductive layer 102 may also be located between the substrate 100 and the active layer 101 , and the first insulating layer 1001 may be located between the first conductive layer 102 and the active layer 101 .

100b in FIG. 1B to FIG. 1C is a multi-layer composite insulating layer (ie, including a second insulating layer, an interlayer dielectric layer, a first planarizing layer, a second planarizing layer, and a pixel definition layer, etc.).

Figure 2 is a schematic diagram of the structure of the pixel driving circuit provided in the embodiment of the present application, and Figure 3 is a timing diagram of the pixel driving circuit provided in the embodiment of the present application. The display panel also includes a plurality of light emitting devices D, a plurality of pixel driving circuits and a plurality of signal lines.

The plurality of light emitting devices D are electrically connected to the plurality of pixel driving circuits, and the plurality of pixel driving circuits are used to drive the plurality of light emitting devices D to emit light. Optionally, the light emitting devices D include organic light emitting diodes, sub-millimeter light emitting diodes, micro light emitting diodes, and the like.

Optionally, the plurality of signal lines include a plurality of scan lines, a plurality of data lines DL, a plurality of light-emitting control lines EML, and a variable signal line EML1. The plurality of scan lines are used to transmit a plurality of scan signals, and the plurality of scan lines include a plurality of first scan lines SL1, a plurality of second scan lines SL22, a plurality of third scan lines SL21, and a plurality of fourth scan lines SL23. The first scan line SL1 is used to transmit a first scan signal S1, and the second scan line SL22, the third scan line SL21, and the fourth scan line SL23 are all used to transmit a second scan signal S2. The data line DL is used to transmit a data signal, the light-emitting control line EML is used to transmit a light-emitting control signal EM, and the variable signal line EML1 is used to transmit a variable signal EM1.

Optionally, the frequency of the first scanning signal S1 is less than the frequency of the second scanning signal S2. Optionally, the effective pulse of the first scanning signal S1 is located in a writing frame WF of a display cycle, and the effective pulse of the second scanning signal S2 is located in a writing frame WF and a holding frame HF of a display cycle. When a display cycle includes a holding frame HF, the display panel adopts a low refresh frequency driving mode.

Optionally, the display panel further includes a plurality of gate drive circuits, the plurality of gate drive circuits including a plurality of cascaded first gate drive circuits, a plurality of cascaded second gate drive circuits, and a plurality of cascaded third gate drive circuits. The plurality of cascaded first gate drive circuits are electrically connected to the plurality of first scan lines SL1 to provide a plurality of first scan signals S1 to the plurality of first scan lines SL1. The plurality of cascaded second gate drive circuits are electrically connected to the plurality of second scan lines SL22, the plurality of third scan lines SL21, and the plurality of fourth scan lines SL23 to provide a plurality of second scan signals S2 to the plurality of second scan lines SL22, the plurality of third scan lines SL21, and the plurality of fourth scan lines SL23. The plurality of cascaded third gate drive circuits are electrically connected to the plurality of light-emitting control lines EML to provide a plurality of light-emitting control signals EM to the plurality of light-emitting control lines EML.

Optionally, the plurality of gate drive circuits further include a plurality of cascaded fourth gate drive circuits, and the plurality of cascaded fourth gate drive circuits are electrically connected to the variable signal line EML1 to provide the variable signal EM1 to the variable signal line EML1. Optionally, the variable signal line EML1 may also be electrically connected to the driving chip to provide the variable signal EM1 through the driving chip.

Each pixel driving circuit is electrically connected to a corresponding scan line, a corresponding data line DL and a corresponding light emitting control line EML to control a corresponding light emitting device D to emit light according to a corresponding scan signal, a data signal and a light emitting control signal EM.

Please continue to refer to FIG. 2 , at least one pixel driving circuit includes a driving transistor T1 , a compensation transistor and a coupling capacitor transistor TC.

The driving transistor T1 and the light emitting device D are connected in series between the first power line VDD and the second power line VSS, and the driving transistor T1 is used to generate a driving current for driving the light emitting device D to emit light according to the data signal. The writing frame WF includes a stage in which the data signal is transmitted to the gate of the driving transistor T1, and the holding frame HF does not include a stage in which the data signal is transmitted to the gate of the driving transistor T1.

The compensation transistor includes a first sub-transistor TL1 and a second sub-transistor TL2 connected in series, and a connection node A is provided between the first sub-transistor TL1 and the second sub-transistor TL2. One of the source and the drain of the first sub-transistor TL1 is electrically connected to the gate of the driving transistor T1, the other of the source and the drain of the first sub-transistor TL1 is electrically connected to one of the source and the drain of the second sub-transistor TL2 through the connection node A, the other of the source and the drain of the second sub-transistor TL2 is electrically connected to one of the source and the drain of the driving transistor T1, and the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 are both electrically connected to the first scan line SL1. Optionally, when driving the light-emitting device D of the nth row, the first scan line SL1 to which the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 are electrically connected transmits the first scan signal S1(n) of the nth level. Wherein, n is greater than or equal to 1.

The gate of the coupling capacitor transistor TC is electrically connected to the variable signal line EML1, and the source and drain of the coupling capacitor transistor TC are electrically connected to the connection node A. The coupling capacitor transistor TC is used to couple the potential of the connection node A according to the variable signal EM1 transmitted by the variable signal line EML1 to change the difference between the connection node A and the gate potential of the driving transistor T1.

Please continue to refer to FIG. 2 , at least one pixel driving circuit further includes a reset transistor, and the reset transistor includes a third sub-transistor TL3 and a fourth sub-transistor TL4 connected in series. Optionally, one of the source and the drain of the third sub-transistor TL3 is electrically connected to the first reset line VL1, one of the source and the drain of the fourth sub-transistor TL4 is electrically connected to the other of the source and the drain of the second sub-transistor TL2, the other of the source and the drain of the fourth sub-transistor TL4 is electrically connected to the other of the source and the drain of the third sub-transistor TL3, and the gate of the third sub-transistor TL3 and the gate of the fourth sub-transistor TL4 are both electrically connected to the second scan line SL22.

Please continue to refer to FIG. 2 , the at least one pixel driving circuit further includes a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a storage capacitor Cst.

The source and drain of the second transistor T2 are electrically connected between one of the source and drain of the driving transistor T1 and the data line DL, and the gate of the second transistor T2 is electrically connected to the third scan line SL21. The second transistor T2 is used to transmit a data signal to the gate of the driving transistor T1 according to the second scan signal S2 transmitted by the third scan line SL21, so that the gate of the driving transistor T1 has a first potential.

The source and drain of the third transistor T3 are electrically connected between the other of the source and drain of the driving transistor T1 and the other of the source and drain of the second sub-transistor TL2, and the gate of the third transistor T3 is electrically connected to the third scan line SL21. The third transistor T3 is used to transmit the data signal to the gate of the driving transistor T1 in cooperation with the compensation transistor and the second transistor T2 according to the second scan signal S2 transmitted by the third scan line SL21. Among them, the second scan signal transmitted by the second scan line SL22 is effective before the second scan signal transmitted by the third scan line SL21. That is, when driving the light-emitting device D of the nth row, the third scan line SL21 to which the gate of the second transistor T2 and the gate of the third transistor T3 are electrically connected transmits the second scan signal S2(n) of the nth level, and the second scan line SL22 to which the gate of the third sub-transistor TL3 and the gate of the fourth sub-transistor TL4 are electrically connected transmits the second scan signal S2(n-1) of the n-1th level.

The source and drain of the fourth transistor T4 are electrically connected between one of the source and drain of the driving transistor T1 and the first power line VDD, the source and drain of the fifth transistor T5 are electrically connected between the other of the source and drain of the driving transistor T1 and the first node B, and the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are both electrically connected to the light emitting control line EML. The fourth transistor T4 and the fifth transistor T5 are used to enable the driving transistor T1 to drive the light emitting device D to emit light according to the light emitting control signal EM transmitted by the light emitting control line EML. Optionally, when driving the light emitting device D of the nth row, the light emitting control line EML to which the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are electrically connected transmits the light emitting control signal EM(n) of the nth level.

The source and drain of the sixth transistor T6 are electrically connected between the second reset line VL2 and the first node B, the gate of the sixth transistor T6 is electrically connected to the fourth scan line SL23, and the sixth transistor T6 is used to transmit the second reset signal transmitted by the second reset line VL2 to the first node B according to the second scan signal transmitted by the fourth scan line SL23. Optionally, when driving the light-emitting device D of the nth row, the fourth scan line SL23 electrically connected to the gate of the sixth transistor T6 transmits the second scan signal S2(n) of the nth level or transmits the second scan signal S2(n-1) of the n-1th level.

The light emitting device D is electrically connected between the first node B and the second power line VSS. The storage capacitor Cst is connected in series between the first power line VDD and the gate of the driving transistor T1 to maintain the gate potential of the driving transistor T1.

In the light emitting phase when the driving transistor T1 drives the light emitting device D to emit light, the variable signal EM1 has at least one jump from the second potential V2 to the third potential V3, wherein the first potential is between the second potential V2 and the third potential V3.

It is understandable that a pixel driving circuit can also drive multiple light-emitting devices D. The first reset signal and the second reset signal may be equal or unequal. The design in which the first reset signal and the second reset signal are unequal has a higher adjustability of the pixel driving circuit than the design in which the first reset signal and the second reset signal are equal. Each transistor included in the pixel driving circuit includes a silicon semiconductor material. Optionally, the silicon semiconductor material includes polycrystalline silicon, monocrystalline silicon, etc. When each transistor included in the pixel driving circuit includes a silicon semiconductor material, a simpler structure can be used to manufacture the display panel, thereby saving the manufacturing cost.

Please continue to refer to Figures 2 and 3, and take the case where each transistor included in the pixel driving circuit is a P-type transistor and the pixel driving circuit drives the light-emitting device D in the nth row to emit light as an example to explain the working principle of the pixel driving circuit. The pixel driving circuit includes: a reset phase t1, a data writing phase t2, and a light-emitting phase t3.

In the reset stage t1, the first scan signal S1(n) transmitted by the first scan line SL1 and the second scan signal S2(n-1) transmitted by the second scan line SL22 are valid, the first sub-transistor TL1, the second sub-transistor TL2, the third sub-transistor TL3 and the fourth sub-transistor TL4 are turned on, and the first reset signal transmitted by the first reset line VL1 is transmitted to the gate of the driving transistor T1 via the third sub-transistor TL3, the fourth sub-transistor TL4, the second sub-transistor TL2 and the first sub-transistor TL1 to reset the gate potential of the driving transistor T1.

In the data writing phase t2, the first scanning signal S1(n) transmitted by the first scanning line SL1 and the second scanning signal S2(n) transmitted by the third scanning line SL21 and the fourth scanning line SL23 are valid, the first sub-transistor TL1 and the second sub-transistor TL2 are turned on, the second transistor T2, the third transistor T3 and the sixth transistor T6 are all turned on in response to the second scanning signal S2(n), and the data signal transmitted by the data line DL is transmitted to the gate of the driving transistor T1 via the second transistor T2, the third transistor T3, the second sub-transistor TL2 and the first sub-transistor TL1, so that the gate of the driving transistor T1 has a first potential. The second reset signal transmitted by the second reset line VL2 is transmitted to the first node B via the sixth transistor T6 to reset the anode potential of the light emitting device D.

In the light emitting stage t3, the light emitting control signal EM(n) transmitted by the light emitting control line EML is valid, the fourth transistor T4 and the fifth transistor T5 are turned on in response to the light emitting control signal EM(n), and the driving transistor T1 generates a driving current for driving the light emitting device D to emit light. Optionally, the frequency of the light emitting control signal EM(n) is greater than the frequency of the first scanning signal S1(n), so as to improve the low-frequency flicker problem by switching the light emitting device D between bright and dark states.

In a writing frame WF of a display cycle, at least a reset phase t1 and a data writing phase t2 are included. When a low frequency is used for driving display, a display cycle includes at least a holding frame HF, and the data displayed in the holding frame HF is consistent with the data displayed in the writing frame WF. Therefore, it can be understood that the light-emitting phase t3 continues from the writing frame WF to the holding frame HF. The second scanning signal S2 still has a valid pulse in the holding frame, which can correct the gate potential of the driving transistor T1 and compensate for the brightness change of the light-emitting device D. The jump time of the variable signal EM1 (n) is located after the data signal is transmitted to the gate of the driving transistor T1. For example, the variable signal EM1 (n) can jump in the light-emitting phase t3 of the writing frame, and can also jump in the holding frame HF. Among them, in order to prevent the brightness change of the light-emitting device D caused by the jump of the variable signal EM1 (n) from being perceived by the human eye, the jump time of the variable signal EM1 (n) is located within the invalid pulse action time of the light-emitting control signal EM (n), or the jump time of the variable signal EM1 (n) is the same as the jump time of the light-emitting control signal EM (n).

For example, in the light-emitting stage t3 of the writing frame WF, the moment when the variable signal EM1(n) jumps from the second potential V2 to the third potential V3 is the same as the moment when the light-emitting control signal EM(n) jumps from the high level to the low level; or, the moment when the variable signal EM1(n) jumps from the third potential V3 to the second potential V2 is the same as the moment when the light-emitting control signal EM(n) jumps from the high level to the low level. Optionally, the first potential is greater than the third potential V3 and less than the second potential V2. Since the source and drain of the coupling capacitor transistor TC are electrically connected, the coupling capacitor transistor exhibits a capacitance characteristic. In the first time period t11, the gate of the driving transistor T1 is mainly affected by the first reset signal and the data signal, and the variable signal EM1(n) is the third potential V3 or the second potential V2 and does not affect the gate potential of the driving transistor T1. After the variable signal EM1(n) has a jump in the light-emitting stage t3, the potential of the connection node A changes accordingly due to the coupling effect, so that the gate potential of the driving transistor T1 also changes accordingly.

For example, when each transistor in the pixel driving circuit is still a P-type transistor, the variable signal EM1(n) jumps from the third potential V3 to the second potential V2, the potential of the connection node A is coupled to be increased to be greater than the gate potential of the driving transistor T1, and the connection node A leaks electricity to the gate of the driving transistor T1, so that the gate potential of the driving transistor T1 becomes higher accordingly, thereby reducing the driving current, causing the luminous brightness of the light-emitting device D to decrease. When the variable signal EM1(n) jumps from the second potential V2 to the third potential V3, the potential of the connection node A is coupled to be reduced to be less than the gate potential of the driving transistor T1, and the gate of the driving transistor T1 leaks electricity to the connection node A, so that the gate potential of the driving transistor T1 is reduced accordingly, thereby increasing the driving current, causing the luminous brightness of the light-emitting device D to increase. Therefore, the jump of the variable signal EM1(n) can cause the brightness of the light-emitting device D to change, and by continuously jumping the variable signal EM1(n) between the second potential V2 and the third potential V3, the average value of the gate potential of the driving transistor T1 can be basically stabilized at the first potential.

Optionally, the time length during which the variable signal EM1(n) maintains the second potential V2 is the first time period t11, and the time length during which the variable signal EM1(n) maintains the third potential V3 is the second time period t12. The time length of the first time period t11 may be equal to or unequal to the time length of the second time period t12. It can be understood that the time length of the first time period t11 and the time length of the second time period t12 can be set according to actual needs, and the time length during which the variable signal EM1(n) maintains the second potential V2 each time may be equal or unequal, and the time length during which the variable signal EM1(n) maintains the third potential V3 each time may also be equal or unequal. The shorter the time length of the first time period t11 and the time length of the second time period t12, the more times the variable signal EM1(n) jumps, and the higher the frequency of the variable signal EM1(n).

Theoretically, the potential of the connection node A and the gate potential of the driving transistor T1 are always equal, and the brightness of the light-emitting device D changes minimally. However, since the gate potential of the driving transistor T1 is different at different grayscales, and the potential of the connection node A is not much different, therefore, without changing the potential of the connection node A, only individual grayscales can have a better display effect, and the improvement effect of the display of most of the remaining grayscales is not good due to the difference between the potential of the connection node A and the gate potential of the driving transistor T1. Therefore, the present application utilizes the light-emitting stage t3, which is inevitably a long period of time when low-frequency driving exists, to make the potential of the connection node A variable within the light-emitting stage t3, so as to comprehensively combine the influence of the second potential V2 and the third potential V3 on the gate potential of the driving transistor T1, so that the average value of the gate potential of the driving transistor T1 is basically stable at the first potential, so that the light-emitting brightness of the light-emitting device D is basically maintained at the initial light-emitting brightness, which can improve the flicker problem existing in low-frequency driving, thereby improving the display quality.

FIG4 is a schematic diagram of display brightness change provided by an embodiment of the present application; wherein L1 represents a display brightness change curve obtained by driving a light-emitting device using the pixel driving circuit of the present application with the gate potential of the driving transistor T1, and L2 represents a display brightness change curve obtained by driving a light-emitting device using a pixel driving circuit in the prior art (a pixel driving circuit in the prior art is designed without a coupling capacitor transistor) with the gate potential of the driving transistor. By comparison, it can be seen that within the duration of a display cycle (1 Display), the luminous brightness of the light-emitting device D corresponding to L1 will change multiple times, and the change amplitude of the luminous brightness of the light-emitting device D is significantly smaller than the brightness change amplitude of the light-emitting device corresponding to L2. Since the duration of a display cycle (1 Display) is greater than the duration of each luminous brightness change. Therefore, even if the number of times the second potential V2 is greater than the gate potential of the driving transistor T1 is not equal to the number of times the third potential V3 is less than the gate potential of the driving transistor T1, it only manifests as a difference in the number of brightness change switches in L1. From the perspective of the duration of a display cycle (1 Display), the difference in the number of brightness change switches has little effect on the overall brightness change. It can be understood that one display cycle (1 Display) may include only one writing frame WF, or may include one writing frame WF and at least one holding frame HF.

FIG5 is a schematic diagram of the film structure of the pixel driving circuit provided in an embodiment of the present application, and FIG6 is a schematic diagram of the structure of the active layer provided in an embodiment of the present application. Please continue to refer to FIG5 and FIG6, the active layer includes a first sub-active pattern of the first sub-transistor TL1, a second sub-active pattern of the second sub-transistor TL2, a coupling capacitor active pattern of the coupling capacitor transistor TC, a first active pattern of the driving transistor T1, a second active pattern of the second transistor T2, a third active pattern of the third transistor T3, a fourth active pattern of the fourth transistor T4, a fifth active pattern of the fifth transistor T5, and a sixth active pattern of the sixth transistor T6.

Optionally, the first sub-active pattern includes a first channel portion CP1, the second sub-active pattern includes a second channel portion CP2, and the coupling-capacitive active pattern includes a coupling-capacitive active portion. Optionally, the coupling-capacitive active portion is connected between the first doped portion STL1 of the first sub-active pattern and the second doped portion DTL2 of the second sub-active pattern to serve as a connection node A, and the conductive performance of the coupling-capacitive active portion is higher than that of the first sub-active pattern and the second sub-active pattern, so that the first sub-active pattern and the second sub-active pattern are electrically connected by the coupling-capacitive active portion.

The part where the variable signal line EML1 overlaps with the active part of the coupling capacitor is used as the gate of the coupling capacitor transistor TC, and the active part of the coupling capacitor can be used as the source and drain of the coupling capacitor transistor TC, so that the coupling capacitor transistor TC has a capacitance characteristic. Since the source and drain of the coupling capacitor transistor TC are electrically connected to the connection node A, and the active part of the coupling capacitor is a semiconductor material, when the gate potential of the coupling capacitor transistor TC changes, the capacitance characteristic of the coupling capacitor transistor TC will change due to the difference in the accumulation of hole carriers at the semiconductor interface. Therefore, the coupling capacitor transistor TC can show the characteristics of a variable capacitor, and accordingly, the adjustability of the pixel driving circuit using the coupling capacitor transistor TC is more flexible. It can be understood that the capacitance value of the capacitor shown by the coupling capacitor transistor TC can be determined by factors such as the overlapping area of the variable signal line EML1 and the active part of the coupling capacitor, the potential of the variable signal EM1, etc.

Optionally, the two ends of the connection portion Cn1 included in the coupling-capacitive active portion are respectively connected to the first doping portion STL1 of the first sub-active pattern and the second doping portion DTL2 of the second sub-active pattern; the first channel portion Cp1 is located on the side of the first doping portion STL1 of the first sub-active pattern away from the coupling-capacitive active portion, and the second channel portion Cp2 is located on the side of the second doping portion STL2 of the second sub-active pattern away from the coupling-capacitive active portion. The first sub-active pattern and the second sub-active pattern are located on the same side of the connection portion Cn1, and the overlapping portion Cn2 is located on the side of the connection portion Cn1 away from the second doping portion DTL1 of the first sub-active pattern and the first doping portion STL2 of the second sub-active pattern.

The first doping part ST1 of the first active pattern is connected to the second doping part DT2 of the second active pattern and the second doping part DT4 of the fourth active pattern; the second doping part DT1 of the first active pattern is connected to the first doping part ST3 of the third active pattern and the first doping part ST5 of the fifth active pattern, and the second doping part DT5 of the fifth active pattern is connected to the first doping part ST6 of the sixth active pattern. The second active pattern and the third active pattern both extend along the second direction y and are arranged at intervals, and the second doping part DT3 of the third active pattern is connected to the first doping part STL2 of the second sub-active pattern.

Optionally, the active layer 101 further includes an electrical connection portion Cn3, a third sub-active pattern of the third sub-transistor TL3, and a fourth sub-active pattern of the fourth sub-transistor TL4. Optionally, the third sub-active pattern includes a third channel portion CP3, and the fourth sub-active pattern includes a fourth channel portion CP4.

The electrical connection portion Cn3 is connected between the third sub-active pattern and the fourth sub-active pattern and overlaps with the first reset line VL1 to form a coupling capacitor, thereby maintaining the potential of the middle node (i.e., point C in FIG. 2 ) between the third sub-transistor TL3 and the fourth sub-transistor TL4, and reducing the influence of the potential of the middle node of the third sub-transistor TL3 and the fourth sub-transistor TL4 on the gate potential of the driving transistor T1. Optionally, the electrical connection portion Cn3 extends along the first direction x, and the electrical conductivity of the electrical connection portion Cn3 is higher than that of the third sub-active pattern and the fourth sub-active pattern. The first doped portion STL3 of the third sub-active pattern and the second doped portion DTL4 of the fourth sub-active pattern are connected through the electrical connection portion Cn3, and the third sub-active pattern and the fourth sub-active pattern are both spaced apart from the coupling capacitor active portion.

Optionally, the second sub-active pattern and the fourth sub-active pattern are electrically connected via a bridge portion F3 in a different layer from the variable signal line EML1 to achieve electrical connection between the fourth sub-transistor TL4 and the second sub-transistor TL2 .

Optionally, the variable signal line EML1 and the first scan line SL1 are in the same layer and made of the same material.

7 is a schematic diagram of the structure of the first conductive layer provided in an embodiment of the present application. Optionally, the variable signal line EML1 is in the same layer and made of the same material as the first scan line SL1. Optionally, the first conductive layer further includes a first scan line SL1. The first scan line SL1 extends along a first direction x. Optionally, the first scan line SL1 includes a first routing portion and a second routing portion located at both ends of the first routing portion and connected to the first routing portion, and the first routing portion overlaps with the first channel portion Cp1 and the second channel portion Cp2. In the second direction y, the distance P1 between the first routing portion and the variable signal line EML1 is greater than the distance P2 between the second routing portion and the variable signal line EML1, so that the first scan line SL1 and the connecting portion Cn1 do not overlap.

Optionally, the variable signal line EML1 is in the same layer and made of the same material as the second scan line SL22. The first conductive layer 102 further includes a second scan line SL22, and the second scan line SL22 overlaps with the third channel portion CP3 and the fourth channel portion CP4. The variable signal line EML1 is located between the first scan line SL1 and the second sub-scan line SL22, the third sub-active pattern and the second sub-active pattern are located on opposite sides of the variable signal line EML1, and the third sub-active pattern and the fourth sub-active pattern are located on the same side of the variable signal line to avoid the formation of a transistor between the variable signal line EML1 and the first scan line SL1 and the bridge portion F3 that realizes the electrical connection between the fourth sub-transistor TL4 and the second sub-transistor TL2 when the fourth sub-transistor TL4 and the second sub-transistor TL2 are electrically connected, thereby affecting the normal operation of the pixel driving circuit.

Optionally, the first conductive layer 102 further includes a third scan line SL21, a fourth scan line SL23, a light emitting control line EML, and a first electrode portion E1 overlapping the first active pattern, so as to reduce the thickness of the display panel and save process steps. The third scan line SL21 is located on a side of the first scan line SL1 away from the variable signal line EML1, the light emitting control line EML is located on a side of the third scan line SL21 away from the variable signal line EML1, the fourth scan line SL23 is located on a side of the light emitting control line EML away from the third scan line SL21, and the first electrode portion E1 is located between the light emitting control line EML and the third scan line SL21.

The first electrode portion E1 is used as the gate of the driving transistor T1; the portion where the third scan line SL21 overlaps with the second active pattern is used as the gate of the second transistor T2, and the portion where the third scan line SL21 overlaps with the third active pattern is used as the gate of the third transistor T3; the portion where the light emitting control line EML overlaps with the fourth active pattern is used as the gate of the fourth transistor T4, the portion where the light emitting control line EML overlaps with the fifth active pattern is used as the gate of the fifth transistor T5, and the portion where the fourth scan line SL23 overlaps with the sixth active pattern is used as the gate of the sixth transistor T6.

Optionally, the connection portion Cn1 is located between the first scan line SL1 and the variable signal line EML1. The first active pattern is located between the third scan line SL21 and the light emitting control line EML. Optionally, the first active pattern is u-shaped. The second doping portion DT2 of the second active pattern and the first doping portion ST3 of the third active pattern are both located on the side of the third scan line SL21 away from the first scan line SL1. The first doping portion ST2 of the second active pattern, the second doping portion DT3 of the third active pattern, the second doping portion DTL1 of the first sub-active pattern, and the first doping portion STL2 of the second sub-active pattern are all located between the third scan line SL21 and the first scan line SL1. The second doping portion DTL3 of the third sub-active pattern and the first doping portion STL4 of the fourth sub-active pattern are both located between the variable signal line EML1 and the second scan line SL22.

Optionally, the display panel further includes a second insulating layer and a second conductive layer. The second insulating layer is located on the first conductive layer, and the second conductive layer is located on the second insulating layer. FIG8 is a schematic diagram of the structure of the second conductive layer provided in an embodiment of the present application; please continue to refer to FIG5 to FIG8, the second conductive layer includes a first reset line VL1, a second reset line VL2, a first power line VDD, and a second electrode portion E2 connected to the first power line VDD, and the first electrode portion E1 and the second electrode portion E2 overlap to serve as two electrodes of the storage capacitor Cst.

The first power line VDD is located between the third scan line SL21 and the light emission control line EML, the second reset line VL2 is located between the light emission control line EML and the fourth scan line SL23, and the first reset line VL1 is located on a side of the second scan line SL22 away from the variable signal line EML1. The first doped portion ST4 of the fourth active pattern and the second doped portion DT5 of the fifth active pattern are both located between the light emission control line EML and the second reset line VL2, and the second doped portion DT6 of the sixth active pattern is located on a side of the fourth scan line SL23 away from the second reset line VL2.

FIG9 is a schematic diagram of the structure of the third conductive layer provided in an embodiment of the present application; please continue to refer to FIG5 to FIG9, the display panel also includes an interlayer dielectric layer and a third conductive layer located on the second conductive layer. The third conductive layer includes a first conductive portion F1, a second conductive portion F2, a bridge portion F3, a fourth conductive portion F4, a fifth conductive portion F5, a sixth conductive portion F6, and a seventh conductive portion F7.

The first conductive portion F1 extends along the second direction y, and is electrically connected between the first electrode portion E1 and the second doped portion DTL1 of the first sub-active pattern, so as to realize the electrical connection between the gate of the driving transistor T1 and the first sub-transistor TL1. Specifically, the second electrode portion E2 includes a first opening exposing the first electrode portion E1, and the first conductive portion F1 is electrically connected to the first electrode portion E1 through the first opening and a via penetrating the interlayer dielectric layer and the second insulating layer (such as CNT1 in FIG. 9), and is electrically connected to the second doped portion DTL1 of the first sub-active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer and the first insulating layer (such as CNT2 in FIG. 9).

The second conductive portion F2 overlaps with the first doped portion ST2 of the second active pattern to serve as the source of the second transistor T2. Specifically, the second conductive portion F2 is electrically connected to the first doped portion ST2 of the second active pattern through a via hole penetrating the interlayer dielectric layer, the second insulating layer and the first insulating layer (such as CNT3 in FIG. 9 ) to serve as the source of the second transistor T2.

The bridge portion F3 extends along the second direction y, and is electrically connected between the first doped portion STL2 of the second sub-active pattern and the first doped portion STL4 of the fourth sub-active pattern, so as to realize the electrical connection between the second sub-transistor TL2 and the fourth sub-transistor TL4. Specifically, the bridge portion F3 is electrically connected to the first doped portion STL2 of the second sub-active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer and the first insulating layer (such as CNT4 in FIG. 9 ), and is electrically connected to the first doped portion STL4 of the fourth sub-active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer and the first insulating layer (such as CNT5 in FIG. 9 ). Optionally, the bridge portion F3 is also electrically connected between the second doped portion DT3 of the third active pattern and the first doped portion STL4 of the fourth sub-active pattern, so as to realize the electrical connection between the third transistor T3 and the fourth sub-transistor TL4.

The fourth conductive portion F4 extends along the second direction y, and is electrically connected between the second electrode portion E2 and the first doped portion ST4 of the fourth active pattern, so as to realize the electrical connection between the fourth transistor T4 and the first power line VDD. Specifically, the fourth conductive portion F4 is electrically connected to the second electrode portion E2 through a via hole penetrating the interlayer dielectric layer (such as CNT6 in FIG. 9 ), and is electrically connected to the first doped portion ST4 of the fourth active pattern through a via hole penetrating the interlayer dielectric layer, the second insulating layer, and the first insulating layer (such as CNT7 in FIG. 9 ).

The fifth conductive portion F5 extends along the second direction y, overlaps the second electrode portion E2, the light emitting control line EML, and the fifth active pattern portion, and is electrically connected to the second doped portion DT5 of the fifth active pattern to serve as the first node B. Specifically, the fifth conductive portion F5 is electrically connected to the second doped portion DT5 of the fifth active pattern through a via hole penetrating the interlayer dielectric layer, the second insulating layer, and the first insulating layer (such as CNT8 in FIG. 9 ).

The sixth conductive portion F6 is electrically connected between the second doped portion DTL3 of the third sub-active pattern and the first reset line VL1 to achieve electrical connection between the third sub-transistor TL3 and the first reset line VL1. Specifically, the sixth conductive portion F6 is electrically connected to the second doped portion DTL3 of the third sub-active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer and the first insulating layer (such as CNT9 in FIG. 9 ), and is electrically connected to the first reset line VL1 through a via penetrating the interlayer dielectric layer (such as CNT10 in FIG. 9 ).

The seventh conductive portion F7 is electrically connected between the second doped portion DT6 of the sixth active pattern and the second reset line VL2 to achieve electrical connection between the sixth transistor T6 and the second reset line VL2. Specifically, the seventh conductive portion F7 is electrically connected to the second doped portion DT6 of the sixth active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer and the first insulating layer (such as CNT11 in FIG. 9 ), and is electrically connected to the second reset line VL2 through a via penetrating the interlayer dielectric layer (such as CNT12 in FIG. 9 ).

10 is a schematic structural diagram of the fourth conductive layer provided in an embodiment of the present application; please continue to refer to FIGS. 5 to 10 , the driving circuit layer further includes a first planar layer and a fourth conductive layer located on the third conductive layer, and the fourth conductive layer includes a data line DL and a third power line VDD1.

The data line DL includes a first main body portion DL1 and an extension portion DL2 connected to each other, wherein the first main body portion DL1 extends along the second direction y; the extension portion DL2 overlaps with the second conductive portion F2 and is electrically connected to the second conductive portion F2. Specifically, the extension portion DL2 is electrically connected to the second conductive portion F2 through a via hole penetrating the first planar layer (such as PLN1 in FIG. 10 ).

The third power line VDD1 is arranged at intervals from the data line DL, and includes a second main body VD1 extending along the second direction y, a third main body VD2, and a avoidance portion VD3 located between the second main body VD1 and the third main body VD2 and arranged corresponding to the extension portion DL2. A portion of the third main body VD2 overlaps with the fourth conductive portion F4 and is electrically connected to the fourth conductive portion F4, so that one of the source and the drain of the fourth transistor T4 is electrically connected to the first power line VDD and the third power line VDD1. Specifically, the third main body VD2 is electrically connected to the fourth conductive portion F4 through a via hole penetrating the first planar layer (such as PLN2 in FIG. 10).

Optionally, the fourth conductive layer further includes a node connection portion B1, which is located on a side of the third power line VDD1 away from the data line DL, overlaps with the fifth conductive portion F5 and is electrically connected to the fifth conductive portion F5. Specifically, the node connection portion B1 is electrically connected to the fifth conductive portion F5 through a via hole penetrating the first planar layer (such as PLN3 in FIG. 10).

Optionally, the light emitting device is located on the second flat layer, and the second flat layer is located on the fourth conductive layer. Optionally, the display panel further includes an anode layer located on the second flat layer, a pixel definition layer located on the anode layer, a light emitting layer located in a pixel definition region of the pixel definition layer, a cathode layer located on the light emitting layer, etc.; the pixel definition region exposes the anode layer.

Optionally, the first power line VDD is electrically connected between the first voltage terminal and one of the source and the drain of the driving transistor T1, and the second power line VSS is electrically connected between the cathode of the light emitting device and the second voltage terminal.

It can be understood that the size of the portion corresponding to the via hole in each conductive layer and the active layer may be larger than the size of the portion not corresponding to the via hole in each conductive layer and the active layer.

The present application also provides a display device, the display device comprising any of the above-mentioned drive circuits or any of the above-mentioned display panels. It can be understood that the display device includes a movable display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), etc.

Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of the present application, and the content of this specification should not be understood as a limitation on the present application.

Claims

A display panel, comprising:

substrate;

an active layer, located on the substrate, comprising a first channel portion, a second channel portion, and a coupling-capacitive active portion connected between the first channel portion and the second channel portion; and

A variable signal line overlaps with the active portion of the coupling capacitor;

The first channel portion and the second channel portion have a first width and a second width respectively in a first direction, and the coupling active portion has a third width in a second direction intersecting the first direction, and the third width is greater than the first width and the second width.
The display panel according to claim 1, wherein the coupling active portion comprises a connecting portion and an overlapping portion connected to each other, the overlapping portion and the first channel portion are respectively located on two opposite sides of the connecting portion, and the first channel portion and the second channel portion are located on the same side of the connecting portion and are both connected to the connecting portion;

Wherein, the overlapping portion overlaps with the variable signal line.
The display panel according to claim 2, wherein the ion doping concentration of the overlapping portion is lower than the ion doping concentration of the connecting portion.
The display panel according to claim 1, further comprising a light emitting device and a pixel driving circuit, wherein the pixel driving circuit comprises:

a driving transistor connected in series with the light emitting device between the first power line and the second power line; and

a compensation transistor, comprising a first sub-transistor and a second sub-transistor connected in series, wherein one of a source and a drain of the first sub-transistor is electrically connected to a gate of the driving transistor, the other of the source and the drain of the first sub-transistor is electrically connected to one of a source and a drain of the second sub-transistor, the other of the source and the drain of the second sub-transistor is electrically connected to one of a source and a drain of the driving transistor, and the gate of the first sub-transistor and the gate of the second sub-transistor are both electrically connected to a first scan line;

The active layer further includes a first sub-active pattern of the first sub-transistor and a second sub-active pattern of the second sub-transistor, the first sub-active pattern includes the first channel portion, and the second sub-active pattern includes the second channel portion.
The display panel according to claim 4, wherein the first scan line extends along the first direction, the first scan line comprises a first routing portion and a second routing portion located at two ends of the first routing portion and connected to the first routing portion, and the first routing portion overlaps with the first channel portion and the second channel portion;

Wherein, in the second direction, the distance between the first routing portion and the variable signal line is greater than the distance between the second routing portion and the variable signal line.
The display panel according to claim 4, wherein the pixel driving circuit further comprises a reset transistor, the reset transistor comprising a third sub-transistor and a fourth sub-transistor connected in series, one of a source and a drain of the third sub-transistor being electrically connected to a first reset line, one of a source and a drain of the fourth sub-transistor being electrically connected to the other of a source and a drain of the second sub-transistor, the other of a source and a drain of the fourth sub-transistor being electrically connected to the other of a source and a drain of the third sub-transistor, and a gate of the third sub-transistor and a gate of the fourth sub-transistor being electrically connected to a second scan line;

Wherein, the variable signal line is located between the first scan line and the second scan line.
The display panel according to claim 6, wherein the active layer further comprises a third sub-active pattern of the third sub-transistor, a fourth sub-active pattern of the fourth sub-transistor and an electrical connection portion, the third sub-active pattern and the fourth sub-active pattern are connected via the electrical connection portion, and the third sub-active pattern and the fourth sub-active pattern are both spaced apart from the variable signal line;

The third sub-active pattern and the second sub-active pattern are respectively located on two opposite sides of the variable signal line, and the third sub-active pattern and the fourth sub-active pattern are located on the same side of the variable signal line.
The display panel according to claim 7, wherein the second sub-active pattern and the fourth sub-active pattern are electrically connected via a bridge portion in a different layer from the variable signal line.
The display panel according to claim 8, wherein the third sub-active pattern is electrically connected to the first reset line through a sixth conductive portion in a different layer from the first reset line;

The bridge portion and the sixth conductive portion are in the same layer and made of the same material.
The display panel according to claim 8, wherein the pixel driving circuit further comprises:

a second transistor, wherein a source and a drain of the second transistor are electrically connected between one of the source and the drain of the driving transistor and the data line, and a gate of the second transistor is electrically connected to a third scan line;

a third transistor, wherein a source and a drain of the third transistor are electrically connected between the other of the source and the drain of the driving transistor and the other of the source and the drain of the second sub-transistor, and a gate of the third transistor is electrically connected to the third scan line;

The third scan line is located at a side of the first scan line away from the variable signal line.
The display panel according to claim 10, wherein the active layer comprises a first active pattern of the driving transistor, a second active pattern of the second transistor, and a third active pattern of the third transistor, and the first active pattern is connected between the second active pattern of the second transistor and the third active pattern;

Among them, the third scan line partially overlaps with the second active pattern and the third active pattern of the second transistor respectively, and the first active pattern is located on the side of the third scan line away from the variable signal line; the second active pattern is electrically connected to the data line through a second conductive part on the same layer as the bridge part; the third active pattern is electrically connected to the fourth sub-active pattern through the bridge part.
The display panel according to claim 11, further comprising:

A first conductive layer, located on the active layer, including the variable signal line;

A second conductive layer, located on the first conductive layer, including the first reset line;

a third conductive layer, located on the second conductive layer, comprising the bridge portion; and

The fourth conductive layer is located on the third conductive layer and includes the data line.
The display panel according to claim 12, wherein the data line comprises:

A first main body portion extending along the second direction; and

an extension portion connected to the first main body portion and overlapping the second conductive portion;

Wherein, the extending portion is electrically connected to the second conductive portion.
The display panel according to claim 7, wherein the first reset line is located on a side of the second scan line away from the variable signal line, and the first reset line overlaps the electrical connection portion.
The display panel according to claim 6, wherein the variable signal line is in the same layer and made of the same material as the first scan line and the second scan line.