CN115696988A

CN115696988A - Display panel

Info

Publication number: CN115696988A
Application number: CN202211415787.9A
Authority: CN
Inventors: 刘大超; 曾勉; 孙亮
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2023-02-03
Also published as: WO2024098564A1

Abstract

The invention provides a display panel, which comprises an active layer, a first scanning line and a variable signal line. The first scan line extends in a first direction, and the first scan line overlaps with a first channel portion and a second channel portion which are oppositely disposed in the active layer. The variable signal line comprises a routing part and an overlapping part which are mutually connected, the overlapping part is positioned on one side of the routing part close to the first electric connection part, and the overlapping part is at least partially overlapped with the first electric connection part in the active layer, which is connected between the first channel part and the second channel part, so as to form a coupling capacitor, thereby realizing the scheme of improving the low-frequency flicker problem by utilizing the variable signal and the coupling capacitor transmitted by the variable signal line when the display panel adopts low-frequency driving.

Description

Display panel

Technical Field

The invention relates to the technical field of display, in particular to a display panel.

Background

In the existing display panel, an LTPO (Low Temperature Polycrystalline Oxide) backplane and an LTPS (Low Temperature Poly-silicon) backplane are often used, but the leakage current of a transistor in the LTPS backplane is large, which causes the change of the driving current flowing through the light emitting device, resulting in the flicker problem of the display panel during Low frequency driving; the LTPO back plate has a complex structure and a complex preparation process, and the preparation cost is high.

Disclosure of Invention

The embodiment of the invention provides a display panel, which can realize a scheme for improving the problem of low-frequency drive flicker of the display panel.

An embodiment of the invention provides a display panel, which includes an active layer, a first scan line and a variable signal line. The active layer comprises a first channel part and a second channel part which are oppositely arranged, and a first electric connection part connected between the first channel part and the second channel part; the first scanning line extends along the first direction and is overlapped with the first channel part and the second channel part; the variable signal line comprises a routing part and an overlapping part which are mutually connected, the overlapping part is positioned on one side of the routing part close to the first electric connection part, and the overlapping part is at least partially overlapped with the first electric connection part.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1A is a schematic diagram of a structure in which a variable signal line overlaps an active layer;

FIG. 1B is a cross-sectional view taken along p-p' in FIG. 1A;

FIG. 1C is a cross-sectional view taken along z-z' in FIG. 1A;

fig. 2A to fig. 2B are schematic diagrams illustrating a connection between a first gate driving circuit and a sub-pixel according to an embodiment of the invention;

FIG. 3 is a schematic structural diagram of a sub-pixel according to an embodiment of the present invention;

FIG. 4 is a timing diagram provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a variation of display brightness according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a film structure of a sub-pixel according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of an active layer provided in an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a first conductive layer according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a second conductive layer provided in an embodiment of the invention;

fig. 10 is a schematic structural diagram of a third conductive layer provided in an embodiment of the invention;

fig. 11 is a schematic structural diagram of a fourth conductive layer according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Furthermore, it should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, and are not intended to limit the present invention. In the present invention, unless otherwise specified, the use of directional terms such as "upper" and "lower" generally means upper and lower in the actual use or operation of the device, particularly in the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.

Specifically, fig. 1A is a schematic structural view in which a variable signal line overlaps an active layer, fig. 1B is a sectional view taken along p-p 'in fig. 1A, and fig. 1C is a sectional view taken along z-z' in fig. 1A. The present application provides a display panel, which includes a substrate 100, an active layer 101, a first scan line SL1, and a variable signal line EML1.

The substrate 100 includes a rigid substrate and a flexible substrate. Alternatively, the substrate 100 includes glass, polyimide, quartz, or the like. Optionally, a buffer layer 100a is further disposed on the substrate 100.

The active layer 101 is located on the substrate 100. Alternatively, the active layer 101 includes a silicon semiconductor material or an oxide semiconductor material. Alternatively, the silicon semiconductor material includes single crystal silicon, polycrystalline silicon, or the like; the oxide semiconductor material may include Indium Gallium Zinc Oxide (IGZO), indium Gallium Tin Oxide (IGTO), indium Gallium Zinc Tin Oxide (IGZTO), or the like. Alternatively, the active layer 101 is manufactured using a low temperature polysilicon process.

The active layer 101 includes a first channel portion CP1 and a second channel portion CP2 which are oppositely disposed, and a first electrical connection Cn1 connected between the first channel portion CP1 and the second channel portion CP 2.

The first scan line SL1 extends in the first direction x, and overlaps the first and second channel portions CP1 and CP 2.

The variable signal line EML1 includes a routing portion EML11 and an overlapping portion EML12 connected to each other, the overlapping portion EML12 is located on a side of the routing portion EML11 close to the first electrical connection portion Cn1, and the overlapping portion EML12 and the first electrical connection portion Cn1 are at least partially overlapped, so that the overlapping portion EML12 and the first electrical connection portion Cn1 form two electrodes of a coupling capacitor Co, and the problem of low-frequency flicker is improved by the coupling capacitor Co and the variable signal EM1 transmitted by the variable signal line EML1.

Alternatively, when the display panel adopts a high-resolution design, the overlapping area of the variable signal line EML1 and the first electrical connection portion Cn1 may be greater than 0 micrometers and less than or equal to 100 micrometers, depending on the design space.

Optionally, with continued reference to fig. 1A, the routing portion EML11 includes a first sub-portion EML11A, a second sub-portion EML11b, and a third sub-portion EML11c, the first sub-portion EML11A and the first electrical connection portion Cn1 are disposed at intervals, the second sub-portion EML11b and the third sub-portion EML11c are respectively connected to two ends of the first sub-portion EML11A, and an extension line between the second sub-portion EML11b and the third sub-portion EML11c overlaps with the first electrical connection portion Cn1. The distance from the second sub-section EML11b to the second end of the first electrical connection section Cn1 is smaller than the distance from the third sub-section EML11c to the second end of the first electrical connection section Cn1, and the overlapping section EML12 is connected to a portion of the first sub-section EML11a close to the second sub-section EML11b, so that when the capacitance value of the required coupling capacitor Co is small, only the overlapping section EML12 overlaps with the first electrical connection section Cn1.

Alternatively, the overlapping portion EML12 protrudes toward the first scan line SL1 with respect to the second sub-portion EML11b, and the first scan line SL1 has a recess corresponding to the overlapping portion EML12 so that there is no overlap between the first scan line SL1 and the overlapping portion EML 12.

Alternatively, with continued reference to fig. 1B to fig. 1C, the variable signal line EML1 is located on the active layer 101 or below the active layer 101. Optionally, the display panel further includes a first conductive layer 102 on the active layer 101, and the first conductive layer 102 includes the variable signal line EML1. Alternatively, the first conductive layer 102 includes at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), and the like. Alternatively, the first conductive layer 102 may have a single-layer film structure, or a stacked structure of Ti/Al/Ti, mo/Al/Mo, mo/AlGe/Mo, cu/Ti, cu/MoTi, or Cu/MoNb.

Optionally, the display panel further comprises an insulating layer between the first conductive layer 102 and the active layer 101. Optionally, the insulating layer comprises a first insulating layer 1001 and a second insulating layer 1002. Alternatively, the first insulating layer 1001 and the second insulating layer 1002 may include a silicon compound, a metal oxide, or the like, respectively. Further, the first insulating layer 1001 and the second insulating layer 1002 may include silicon oxide, silicon nitride oxide, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like, respectively.

Fig. 1B to fig. 1C show a multilayer composite insulating layer 100B (i.e., including an interlayer dielectric layer, a first planarization layer, a second planarization layer, a pixel defining layer, and the like).

Fig. 2A to fig. 2B are schematic diagrams illustrating connection between a first gate driving circuit and a sub-pixel according to an embodiment of the invention. The display panel further includes a plurality of signal lines and a plurality of sub-pixels.

Alternatively, the plurality of signal lines include a plurality of scan lines, a plurality of data lines DL, a plurality of light emission control lines EML, a plurality of reset lines, and a plurality of variable signal lines EML1.

The plurality of scan lines are used for transmitting a plurality of scan signals, and include a plurality of first scan lines SL1, a plurality of second scan lines SL22, a plurality of third scan lines SL21, and a plurality of fourth scan lines SL23. The first scan line SL1 is used for transmitting a first scan signal S1, and the second scan line SL22, the third scan line SL21, and the fourth scan line SL23 are all used for transmitting a second scan signal S2. Among the third scan line SL21, the second scan line SL22 and the fourth scan line SL23 electrically connected to the same pixel driving circuit, the second scan signal transmitted by the second scan line SL22 is valid before the second scan signal transmitted by the third scan line SL21, and the second scan signal transmitted by the fourth scan line SL23 is the same as the second scan signal transmitted by the second scan line SL22 or the second scan signal transmitted by the third scan line SL21.

The data line DL is used for transmitting data signals; the emission control line EML is used to transmit an emission control signal EM; the reset lines include a first reset line VL1 and a second reset line VL2, the first reset line VL1 is used to transmit a first reset signal, the second reset line VL2 is used to transmit a second reset signal, and the first reset signal and the second reset signal may be equal or unequal. The variable signal line EML1 is used to transmit the variable signal EM1.

Optionally, the frequency of the first scanning signal S1 is smaller than the frequency of the second scanning signal S2. Alternatively, the effective pulse of the first scan signal S1 is located in the write frame WF of a display period, and the effective pulse of the second scan signal S2 is located in the write frame WF and the hold frame HF of a display period. When a display period includes the hold frame HF, a driving method with a low refresh frequency is adopted for the display panel.

Optionally, the sub-pixels in the same row are electrically connected to the same variable signal line EML1, so that the sub-pixels in the same row are all under the action of the same variable signal EM1 to improve the flicker.

Optionally, the display panel further includes a plurality of gate driving circuits, and the plurality of gate driving circuits includes at least a first gate driving circuit EMG1, a plurality of cascaded second gate driving circuits, a plurality of cascaded third gate driving circuits, and a plurality of cascaded fourth gate driving circuits EMG2.

Optionally, the display panel includes a first gate driving circuit EMG1, the plurality of variable signal lines EML1 are electrically connected to the first gate driving circuit EMG1, and the first gate driving circuit EMG1 is configured to output the variable signal EM1 to the plurality of variable signal lines EM1, as shown in fig. 2A, so that the plurality of sub-pixels arranged in the array are all under the action of the same variable signal EM1 to achieve the problem of improving the flicker.

Optionally, the display panel includes a plurality of cascaded first gate driving circuits EMG1, each first gate driving circuit EMG1 is electrically connected to two variable signal lines EML1, and each first gate driving circuit EMG1 is configured to output a variable signal EM1 to two variable signal lines EM1, as shown in fig. 2B, so that a plurality of sub-pixels located in two rows are under the effect of the same variable signal EM1 to achieve the problem of improving flicker.

In the design that a first gate driving circuit EMG1 as shown in fig. 2A outputs a variable signal EM1 to a plurality of variable signal lines EM1, it is beneficial to implement a narrow frame design of a display panel; the design that a first gate driving circuit EMG1 outputs a variable signal EM1 to two variable signal lines EM1 as shown in fig. 2B has low requirements on the design of the driving chip, and is easy to implement control.

Optionally, the variable signal line EML1 may also be electrically connected to the driving chip to provide a variable signal through the driving chip.

The plurality of cascaded second gate driving circuits are electrically connected with the plurality of first scanning lines SL1 to provide a plurality of first scanning signals S1 to the plurality of first scanning lines SL 1; the plurality of cascaded third gate driving circuits are electrically connected with the plurality of second scanning lines SL22, the plurality of third scanning lines SL21 and the plurality of fourth scanning lines SL23 to provide a plurality of second scanning signals S2 to the plurality of second scanning lines SL22, the plurality of third scanning lines SL21 and the plurality of fourth scanning lines SL 23; the cascaded fourth gate driving circuits EMG2 are electrically connected to the light emission control lines EML to provide a plurality of light emission control signals to the light emission control lines EML.

Optionally, the topology of the fourth gate driving circuit EMG2 is the same as the topology of the first gate driving circuit EMG1 to follow the existing design, thereby saving design costs.

Alternatively, the plurality of cascaded fourth gate driving circuits EMG2 and the plurality of cascaded first gate driving circuits EMG1 are disposed at positions symmetrical with respect to a central axis of the display area of the display panel to facilitate wiring and reducing a bezel of the display panel.

Fig. 3 is a schematic structural diagram of a sub-pixel according to an embodiment of the present invention, and fig. 4 is a timing diagram according to an embodiment of the present invention. Each of the sub-pixels includes a light emitting device D and a pixel driving circuit. Each sub-pixel is electrically connected to a corresponding scan line, a corresponding data line DL and a corresponding emission control line EML, so that the pixel driving circuit controls the corresponding light emitting device D to emit light according to the corresponding scan signal, data signal and emission control signal EM. Optionally, the light emitting device D includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, or the like.

The at least one pixel driving circuit comprises a driving transistor T1, a compensation transistor and a coupling capacitor Co.

The source and drain of the driving transistor T1 and the corresponding light emitting device D are connected in series between the first power line VDD and the second power line VSS, and the driving transistor T1 is configured to generate a driving current for driving the light emitting device D to emit light according to a data signal transmitted to the gate of the driving transistor T1.

The compensation transistor includes a first sub-transistor TL1 and a second sub-transistor TL2 connected in series, the first sub-transistor TL1 and the second sub-transistor TL2 having a connection node a. One of a source and a drain of the first sub-transistor TL1 is electrically connected to the gate of the driving transistor T1, the other of the source and the drain of the first sub-transistor TL1 is electrically connected to one of a source and a drain of the second sub-transistor TL2 through a connection node a, the other of the source and the drain of the second sub-transistor TL2 is electrically connected to one of the source and the drain of the driving transistor T1, and both the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 are electrically connected to the first scan line SL1.

The coupling capacitor Co is connected in series between the variable signal line EML1 and the connection node a, and is configured to couple a potential of the connection node a according to the variable signal EM1 transmitted by the variable signal line EML1 to change a difference between the connection node a and a gate potential of the driving transistor T1.

With reference to fig. 3, at least one of the pixel driving circuits further includes a data transistor T2, a source and a drain of the data transistor T2 are electrically connected between the other of the source and the drain of the driving transistor T1 and the data line DL, and a gate of the data transistor T2 is electrically connected to the third scan line SL21. The data transistor T2 is used for transmitting a data signal to the gate of the driving transistor T1 according to the second scan signal S2 transmitted by the corresponding third scan line SL21, so that the gate of the driving transistor T1 has the first potential.

In the light emitting stage when the driving transistor T1 drives the light emitting device D to emit light, the variable signal EM1 has at least one level jump, so that the potential of the connection node a is coupled and accordingly changed in the light emitting stage, and thus the gate potential of the driving transistor T1 is also accordingly changed, so as to improve the flicker problem.

Alternatively, when the display panel includes a plurality of cascaded first gate driving circuits EMG1, and each first gate driving circuit EMG1 is configured to output the variable signal EM1 to two variable signal lines EM1, timings at which levels of the plurality of variable signals EM1 jump are different, as shown by EM1 (n) and EM1 (n + 1) in fig. 4, so that the plurality of sub-pixels can adjust the gate potentials of the respective driving transistors T1 at different timings, thereby substantially stabilizing the average value of the gate potentials of the driving transistors T1 of the plurality of sub-pixels at the first potential during the light emission period. When the display panel includes a first gate driving circuit EMG1 and the first gate driving circuit EMG1 is configured to output the variable signal EM1 to the plurality of variable signal lines EM1, the timing of the variable signal EM1 may be as shown in EM1 of fig. 4.

Optionally, the variable signal EM1 has at least one transition from the second potential V2 to the third potential V3 during a light emitting period in which the driving transistor T1 drives the light emitting device D to emit light, and the first potential is between the second potential V2 and the third potential V3, so that an average value of the gate potential of the driving transistor T1 is substantially stabilized at the first potential during the light emitting period.

Alternatively, in order to make the first potential between the second potential V2 and the third potential V3, the capacitance value of the coupling capacitor Co may be greater than 0 femtofarad and less than or equal to 10 femtofarads.

With reference to fig. 3, the at least one pixel driving circuit further includes a compensation transistor T3, a first switching transistor T4, a second switching transistor T5, an initialization transistor T6, a reset transistor, and a storage capacitor Cst.

The source and the drain of the compensation transistor T3 are electrically connected between one of the source and the drain of the driving transistor T1 and the other of the source and the drain of the second sub-transistor TL2, and the gate of the compensation transistor T3 is electrically connected to the third scan line SL21. The compensation transistor T3 is used for transmitting a data signal to the gate of the driving transistor T1 according to the second scan signal S2 transmitted by the third scan line SL21 in cooperation with the compensation transistor and the data transistor T2.

The source and the drain of the first switching transistor T4 are electrically connected between the other of the source and the drain of the driving transistor T1 and the first power line, the source and the drain of the second switching transistor T5 are electrically connected between one of the source and the drain of the driving transistor T1 and the first node B, and the gate of the first switching transistor T4 and the gate of the second switching transistor T5 are both electrically connected to the emission control line EML. The first and second switching transistors T4 and T5 are used to make the driving transistor T1 drive the light emitting device D to emit light according to the light emission control signal EM transmitted by the light emission control line EML.

The source and the drain of the initialization transistor T6 are electrically connected between the second reset line VL2 and the first node B, the gate of the initialization transistor T6 is electrically connected to the fourth scan line SL23, and the initialization transistor T6 is configured to transmit the second reset signal transmitted by the second reset line VL2 to the first node B according to the second scan signal transmitted by the fourth scan line SL23. The light emitting device D is electrically connected between the first node B and the second power line VSS.

The source and the drain of the reset transistor are electrically connected between the first reset line VL1 and the other of the source and the drain of the second sub-transistor TL2, and the gate of the reset transistor is electrically connected to the second scan line SL22. Alternatively, the reset transistor includes a third sub-transistor TL3 and a fourth sub-transistor TL4 connected in series, one of a source and a drain of the third sub-transistor TL3 is electrically connected to the first reset line VL1, one of a source and a drain of the fourth sub-transistor TL4 is electrically connected to the other of the source and the drain of the second sub-transistor TL2, the other of the source and the drain of the fourth sub-transistor TL4 is electrically connected to the other of the source and the drain of the third sub-transistor TL3, and a gate of the third sub-transistor TL3 and a gate of the fourth sub-transistor TL4 are both electrically connected to the second scan line SL22.

The storage capacitor Cst is connected in series between the first power line and the gate of the driving transistor T1, and is used to maintain the gate potential of the driving transistor T1.

Alternatively, each transistor included in the pixel drive circuit includes a silicon semiconductor material or an oxide semiconductor. Wherein the silicon semiconductor material comprises polycrystalline silicon, monocrystalline silicon and the like; the oxide semiconductor material includes Indium Gallium Zinc Oxide (IGZO), indium Gallium Tin Oxide (IGTO), indium Gallium Zinc Tin Oxide (IGZTO), or the like.

With reference to fig. 3 to 4, the first scan line SL1, in which the gates of the first sub-transistor TL1 and the second sub-transistor TL2 are electrically connected, transmits the nth stage of the first scan signal S1 (n); the second scan line SL22, which electrically connects the gate of the third sub-transistor TL3 and the gate of the fourth sub-transistor TL4, transmits the second scan signal S2 (n-1) of the (n-1) th stage; the light emission control line EML, in which the gate of the first switching transistor T4 and the gate of the second switching transistor T5 are electrically connected, transmits the light emission control signal EM (n) of the nth stage; the third scan line SL21 electrically connecting the gate of the data transistor T2 and the gate of the compensation transistor T3, and the fourth scan line SL23 electrically connecting the gate of the initialization transistor T6 both transmit the second scan signal S2 (n) of the nth stage, for example, and the operation principle of the pixel driving circuit will be described. Wherein n is more than or equal to 1.

In the reset phase T1, the first scan signal S1 (n) transmitted by the first scan line SL1 and the second scan signal S2 (n-1) transmitted by the second scan line SL22 are asserted, the first sub-transistor TL1, the second sub-transistor TL2, the third sub-transistor TL3, and the fourth sub-transistor TL4 are turned on, and the first reset signal transmitted by the first reset line VL1 is transmitted to the gate of the driving transistor T1 through the third sub-transistor TL3, the fourth sub-transistor TL4, the second sub-transistor TL2, and the first sub-transistor TL1 to reset the gate potential of the driving transistor T1.

In the data writing phase T2, the first scan signal S1 (n) transmitted by the first scan line SL1 and the second scan signal S2 (n) transmitted by the third scan line SL21 and the fourth scan line SL23 are asserted, the first sub-transistor TL1, the second sub-transistor TL2, the data transistor T2, the compensation transistor T3, and the initialization transistor T6 are turned on in response to the second scan signal S2 (n), and the data signal transmitted by the data line DL is transmitted to the gate of the driving transistor T1 through the data transistor T2, the compensation transistor T3, the second sub-transistor TL2, and the first sub-transistor TL1, so that the gate of the driving transistor T1 has the first potential. The second reset signal transmitted from the second reset line VL2 is transmitted to the first node B via the initialization transistor T6 to reset the anode potential of the light emitting device D.

In the light emitting period T3, the light emitting control signal EM (n) transmitted by the light emitting control line EML is asserted, the first switching transistor T4 and the second switching transistor T5 are turned on in response to the light emitting control signal EM (n), and the driving transistor T1 generates a driving current for driving the light emitting device D to emit light. Alternatively, the frequency of the emission control signal EM (n) is greater than the frequency of the first scan signal S1 (n), and the low frequency flicker problem can be improved by the continuous bright and dark states of the light emitting device D.

The write frame WF includes a stage where the data signal is transmitted to the gate of the driving transistor T1, and the hold frame HF does not include a stage where the data signal is transmitted to the gate of the driving transistor T1. When the display is driven with a low frequency, a display period includes at least one hold frame HF, and the data displayed in the hold frame HF is kept consistent with the data displayed in the write frame WF. Therefore, it can be understood that the light emission period t3 continues from the write frame WF to the hold frame HF. The second scan signal S2 still has an active pulse in the sustain frame, and can correct the gate potential of the driving transistor T1 to compensate for the luminance variation of the light emitting device D.

The transition timing of the variable signal EM1 (n) is after the data signal is transmitted to the gate of the driving transistor T1. For example, the variable signal EM1 (n) may be toggled during the light-emitting period t3 of the write frame or during the hold frame HF. In order to prevent the brightness variation of the light emitting device D from being perceived by human eyes due to the transition of the variable signal EM1 (n), the transition time of the variable signal EM1 (n) is within the inactive pulse action time of the emission control signal EM (n), or the transition time of the variable signal EM1 (n) is the same as the transition time of the emission control signal EM (n). In the light emission period t3 in which the frame WF is written, the timing at which the variable signal EM1 (n) transitions from the second potential V2 to the third potential V3 is the same as the timing at which the light emission control signal EM (n) transitions from the high level to the low level; alternatively, the timing at which the variable signal EM1 (n) transitions from the third potential V3 to the second potential V2 is the same as the timing at which the emission control signal EM (n) transitions from the high level to the low level. Optionally, the first potential is greater than the third potential V3 and less than the second potential V2.

The variable signal EM1 (n) holds the second potential V2 for a first period t11, and the variable signal EM1 (n) holds the third potential V3 for a second period t12. In the first period T11 of writing the frame WF, the gate of the driving transistor T1 is mainly affected by the first reset signal and the data signal, and the gate potential of the driving transistor T1 is not affected by the variable signal EM1 (n) being the third potential V3 or the second potential V2. After the variable signal EM1 (n) has a transition in the light-emitting period T3, the potential of the connection node a is coupled to change accordingly, so that the gate potential of the driving transistor T1 changes accordingly. As described by taking the transistors of the pixel driving circuit as P-type transistors as an example, when the variable signal EM1 (n) jumps from the third potential V3 to the second potential V2, the potential of the connection node a is coupled and raised to be greater than the gate potential of the driving transistor T1 by the coupling capacitor Co, and the connection node a leaks to the gate of the driving transistor T1, so that the gate potential of the driving transistor T1 is correspondingly raised, and the driving current is reduced, which causes the light-emitting luminance of the light-emitting device D to be reduced. When the variable signal EM1 (n) jumps from the second potential V2 to the third potential V3, the potential of the connection node a is coupled and reduced to be less than the gate potential of the driving transistor T1 by the coupling capacitor Co, and the gate of the driving transistor T1 leaks electricity to the connection node a, so that the gate potential of the driving transistor T1 is correspondingly reduced, and thus the driving current is increased, and the light-emitting brightness of the light-emitting device D is increased. Therefore, the transition of the variable signal EM1 (n) may cause the luminance of the light emitting device D to vary, and the average value of the gate potential of the driving transistor T1 may be substantially stabilized at the first potential by continuously transitioning the variable signal EM1 (n) between the second potential V2 and the third potential V3.

Alternatively, the duration of the first time period t11 may be equal to or different from the duration of the second time period t12. It can be understood that the duration of the first time period t11 and the duration of the second time period t12 can be set according to actual requirements, the durations of the variable signal EM1 (n) for maintaining the second potential V2 each time can be equal or different, and the durations of the variable signal EM1 (n) for maintaining the third potential V3 each time can be equal or different. The shorter the duration of the first time period t11 and the duration of the second time period t12, the greater the number of transitions of the variable signal EM1 (n), and the higher the frequency of the variable signal EM1 (n).

The potential of the connection node a and the gate potential of the driving transistor T1 are theoretically always equal, and the luminance variation of the light emitting device D is minimized. However, since the gate potentials of the driving transistor T1 are different in different gray scales and the potential difference of the connection node a is not large, only individual gray scales can have a better display effect without changing the potential of the connection node a, and the display improvement effect is not good for most of the remaining gray scales due to the difference between the potential of the connection node a and the gate potential of the driving transistor T1. Therefore, the application utilizes the light-emitting stage T3 which is inevitably existed in the low-frequency driving and has a longer time period to enable the potential of the connection node A to be variable in the light-emitting stage T3 through the action of the coupling capacitor Co so as to synthesize the influence of the second potential V2 and the third potential V3 on the grid potential of the driving transistor T1 and enable the average value of the grid potential of the driving transistor T1 to be basically stabilized at the first potential, thereby enabling the light-emitting brightness of the light-emitting device D to be basically maintained at the initial light-emitting brightness, being capable of improving the flicker problem existing in the low-frequency driving and improving the display quality.

It is to be understood that, when the display panel includes a plurality of cascaded first gate driving circuits EMG1, and each first gate driving circuit EMG1 is configured to output the variable signal EM1 to two variable signal lines EM1, the second potentials V2 of the plurality of variable signals EM1 may be the same or different, the third potentials V3 of the plurality of variable signals EM1 may be the same or different, the duration of each time the plurality of variable signals EM1 maintain the second potential V2 may be the same or different, and the duration of each time the plurality of variable signals EM1 maintain the third potential V3 may be the same or different.

FIG. 5 is a schematic diagram illustrating a variation of display brightness according to an embodiment of the present invention; where L1 denotes a display luminance change curve with a change in gate potential of the driving transistor T1 obtained by driving the light emitting device with the pixel driving circuit of the present application, and L2 denotes a display luminance change curve with a change in gate potential of the driving transistor obtained by driving the light emitting device with the pixel driving circuit in the related art (the pixel driving circuit in the related art has no coupling capacitor Co). By contrast, within the duration of one Display period (1 Display), the luminance of the light emitting device D driven by the pixel driving circuit of the present application changes many times, but the variation range of the luminance of the light emitting device D is significantly smaller than that of the light emitting device driven by the pixel driving circuit in the prior art.

In addition, the duration of one Display period (1 Display) is longer than the variation duration of each light emitting luminance. Therefore, even if the number of times that the second potential V2 is greater than the gate potential of the driving transistor T1 is not equal to the number of times that the third potential V3 is less than the gate potential of the driving transistor T1, only the difference in the number of times of switching of the luminance change in L1 appears, and the difference in the number of times of switching of the luminance change does not greatly affect the entire luminance change as viewed in the duration of one Display period (1 Display). It is understood that a Display period (1 Display) may comprise only one write frame WF, and may also comprise one write frame WF and at least one hold frame HF.

Fig. 6 is a schematic view of a film structure of a sub-pixel according to an embodiment of the present invention, and fig. 7 is a schematic view of a structure of an active layer according to an embodiment of the present invention. With reference to fig. 6 to 7, the active layer 101 includes a first sub-active pattern of the first sub-transistor TL1, a second sub-active pattern of the second sub-transistor TL2, a first active pattern of the driving transistor T1, a second active pattern of the data transistor T2, a third active pattern of the compensation transistor T3, a fourth active pattern of the first switching transistor T4, a fifth active pattern of the second switching transistor T5, a sixth active pattern of the initialization transistor T6, and a first electrical connection Cn1.

Alternatively, the first sub-active pattern includes a first channel portion CP1, the second sub-active pattern includes a second channel portion CP2, and the first electrical connection Cn1 is connected between the first sub-active pattern and the second sub-active pattern to serve as a connection node a. Alternatively, the first electrical connection Cn1 extends in a first direction x, and the first and second sub-active patterns extend in a second direction y, the first and second directions x and y crossing each other. The first sub-active pattern and the second sub-active pattern are located at the same side of the first electrical connection Cn1. A first end of the first electrical connection Cn1 is connected to the first end STL1 of the first sub-active pattern, and a second end of the first electrical connection Cn1 is connected to the second end DTL2 of the second sub-active pattern.

Optionally, the overlapping portion EML12 overlaps the junctions of the second end of the first electrical connection Cn1 and the second end DTL2 of the second sub-active pattern, so that the junctions of the overlapping portion EML12 and the second ends of the first electrical connection Cn1 and the second end DTL2 of the second sub-active pattern form two electrodes of the coupling capacitance Co.

Optionally, the ion doping concentration of the first electrical connection Cn1 is greater than the ion doping concentrations of the first and second channel portions CP1 and CP2, so that the conductive performance of the first electrical connection Cn1 is higher than the conductive performance of the first and second channel portions CP1 and CP2, thereby electrically connecting the first and second sub-active patterns with the first electrical connection Cn1.

The first end ST1 of the first active pattern is connected to the second end DT2 of the second active pattern and the second end DT4 of the fourth active pattern; the second end DT1 of the first active pattern is connected to the first ends ST3 and ST5 of the third and fifth active patterns, and the second end DT5 of the fifth active pattern is connected to the first end ST6 of the sixth active pattern. The second active pattern, the third active pattern, the fourth active pattern and the fifth active pattern all extend along the second direction y, the second active pattern and the third active pattern are arranged at intervals, the fourth active pattern and the fifth active pattern are arranged at intervals, and the second end DT3 of the third active pattern is connected to the first end STL2 of the second sub-active pattern.

Optionally, the active layer 101 further includes a third sub-active pattern of the third sub-transistor TL3, a fourth sub-active pattern of the fourth sub-transistor TL4, and a second electrical connection Cn2 connected between the third sub-active pattern and the fourth sub-active pattern, the third sub-active pattern including a third channel portion CP3, the fourth sub-active pattern including a fourth channel portion CP4, and the second scan line SL22 overlaps the third channel portion CP3 and the fourth channel portion CP4, so that the display panel can still be manufactured using the existing manufacturing process, and thus, a lower manufacturing cost than the LTPO backplane can be realized.

Alternatively, the first end STL3 of the third sub-active pattern and the second end DTL4 of the fourth sub-active pattern are connected by a second electrical connection Cn2, and the second electrical connection Cn2 extends along the first direction x and overlaps the first reset line VL1, so that the overlapping portion of the second electrical connection Cn2 and the first reset line VL1 forms two electrodes of another coupling capacitor, thereby maintaining the electric potential of the intermediate node (i.e., the point C in fig. 3) of the third sub-transistor TL3 and the fourth sub-transistor TL4, and reducing the influence of the intermediate node electric potential of the third sub-transistor TL3 and the fourth sub-transistor TL4 on the gate electric potential of the driving transistor T1.

Optionally, the third sub-active pattern and the fourth sub-active pattern are both located between the variable signal line EML1 and the first reset line VL1, and the third sub-active pattern and the fourth sub-active pattern are both spaced apart from the variable signal line EML1, so as to prevent the variable signal line EML1 and the first scan line SL1 from forming unnecessary transistors when the connection between the second sub-active pattern and the fourth sub-active pattern is achieved, thereby affecting the normal display of the sub-pixels.

Alternatively, the second sub-active pattern and the fourth sub-active pattern are electrically connected to the variable signal line EML1 and the bridge portion F3 of the first scan line SL1.

Alternatively, the variable signal line EML1 is the same layer and material as the first reset line VL 1. As shown in fig. 8, which is a schematic structural diagram of the first conductive layer according to an embodiment of the present invention, the first conductive layer 102 further includes a first reset line VL1, a second reset line VL2, and a first electrode portion E1. The first reset line VL1 is located on a side of the variable signal line EML1 away from the second reset line VL 2; the first electrode portion E1 is located between the second reset line VL2 and the variable signal line EML1, and the first electrode portion E1 overlaps the first active pattern.

Optionally, the first power line VDD includes a first sub power line VDD1 and a second sub power line VDD2 electrically connected to each other, and the first sub power line VDD1 extends along the second direction y; the second sub power line VDD2 extends along the first direction x, and the first sub power line VDD1 and the second sub power line VDD2 are different layers. Optionally, the first conductive layer 102 further includes a second sub power line VDD2, the second sub power line VDD2 is located between the first electrode portion E1 and the variable signal line EML1, and the second sub power line VDD2 is connected to the first electrode portion E1.

Optionally, the variable signal line EML1 is different from the first scan line SL1 and the second scan line SL22, and fig. 9 is a schematic structural diagram of the second conductive layer according to the embodiment of the present invention; the display panel further includes a second conductive layer between the first conductive layer 102 and the active layer 101. Further, a second conductive layer is located between the first insulating layer 1001 and the second insulating layer 1002. Alternatively, the second conductive layer includes first scan lines SL1, third scan lines SL21, second scan lines SL22, fourth scan lines SL23, light emission control lines EML, and second electrode portions E2.

The variable signal line EML1 is located between the first scan line SL1 and the second scan line SL22, the first reset line VL1 is located on a side of the second scan line SL22 away from the variable signal line EML1, the third scan line SL21 is located between the first scan line SL1 and the second sub power line VDD2, the light emitting control line EML is located between the second sub power line VDD2 and the second reset line VL2, and the fourth scan line SL23 is located on a side of the second reset line VL2 away from the light emitting control line EML.

A portion of the first scan line SL1 overlapping the first channel portion CP1 serves as a gate of the first sub-transistor TL1, and a portion of the first scan line SL1 overlapping the second channel portion CP2 serves as a gate of the second sub-transistor TL2. A portion of the second scan line SL22 overlapping the third channel portion CP3 serves as a gate of the third sub-transistor TL3, and a portion of the second scan line SL22 overlapping the fourth channel portion CP4 serves as a gate of the fourth sub-transistor TL 4. The third scanning line SL21 partially overlaps the second active pattern and the third active pattern, a portion of the third scanning line SL21 overlapping the second active pattern serves as a gate of the data transistor T2, and a portion of the third scanning line SL21 overlapping the third active pattern serves as a gate of the compensation transistor T3. The emission control line EML partially overlaps the fourth and fifth active patterns, a portion of the emission control line EML overlapping the fourth active pattern serves as a gate of the first switching transistor T4, and a portion of the emission control line EML overlapping the fifth active pattern serves as a gate of the second switching transistor T5. The fourth scan line SL23 partially overlaps the sixth active pattern, and a portion of the fourth scan line SL23 overlapping the sixth active pattern serves as a gate of the preliminary transistor T6. The second electrode part E2 overlaps the first active pattern to serve as a gate electrode of the driving transistor T1; the first electrode portion E1 and the second electrode portion E2 overlap to form two electrodes of the storage capacitor Cst.

Alternatively, the first end ST2 of the second active pattern, the second end DTL1 of the first sub-active pattern, the first end STL2 of the second sub-active pattern, and the second end DT3 of the third active pattern are all located between the third scan line SL21 and the first scan line SL1. The second end DTL3 of the third sub-active pattern and the first end STL4 of the fourth sub-active pattern are positioned between the variable signal line EML1 and the second scan line SL22. The first end ST4 of the fourth active pattern and the second end DT5 of the fifth active pattern are both located between the light emission control line EML and the second reset line VL2, and the second end DT6 of the sixth active pattern is located at a side of the fourth scan line SL23 away from the second reset line VL 2. Optionally, the first active pattern is u-shaped.

Fig. 10 is a schematic structural diagram of a third conductive layer according to an embodiment of the present invention, and the display panel further includes an interlayer dielectric layer and the third conductive layer over the first conductive layer. The third conductive layer includes a first conductive portion F1, a second conductive portion F2, a bridge portion F3, a fourth conductive portion F4, a fifth conductive portion F5, a sixth conductive portion F6, and a seventh conductive portion F7.

The first conductive part F1 extends along the second direction y and is electrically connected between the second electrode part E2 and the second end DTL1 of the first sub-active pattern, so as to electrically connect the gate of the driving transistor T1 and the first sub-transistor TL 1. Specifically, the first electrode portion E1 includes a first opening exposing the second electrode portion E2, and the first conductive portion F1 is electrically connected to the second electrode portion E2 (at CNT1 in fig. 10) through the first opening and a via hole penetrating through the interlayer dielectric layer and the second insulating layer 1002, and is electrically connected to the second end DTL1 of the first sub-active pattern (at CNT2 in fig. 10) through a via hole penetrating through the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001.

The second conductive portion F2 overlaps the first end ST2 of the second active pattern and is electrically connected to the first end ST2 of the second active pattern to serve as a source of the data transistor T2. Specifically, the second conductive portion F2 is electrically connected to the first end ST2 of the second active pattern (as at CNT3 in fig. 10) through a via hole penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 to serve as a source of the data transistor T2.

The bridge portion F3 extends along the second direction y and is electrically connected between the first end STL2 of the second sub-active pattern and the first end STL4 of the fourth sub-active pattern, so as to electrically connect the second sub-transistor TL2 and the fourth sub-transistor TL 4. Specifically, the bridge portion F3 is electrically connected to the first end STL2 of the second sub-active pattern (e.g., at CNT4 in fig. 10) through a via hole penetrating through the interlayer dielectric layer, the second insulating layer 1002 and the first insulating layer 1001, and is electrically connected to the first end STL4 of the fourth sub-active pattern (e.g., at CNT5 in fig. 10) through a via hole penetrating through the interlayer dielectric layer, the second insulating layer 1002 and the first insulating layer 1001.

The fourth conductive portion F4 extends along the second direction y and is electrically connected between the first electrode portion E1 and the first end ST4 of the fourth active pattern, so as to electrically connect the first switching transistor T4 and the second sub power line VDD 2. Specifically, the fourth conductive part F4 is electrically connected to the first electrode part E1 through a via hole penetrating the interlayer dielectric layer (as at CNT6 in fig. 10), and is electrically connected to the first end ST4 of the fourth active pattern through a via hole penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (as at CNT7 in fig. 10).

The fifth conductive part F5 is electrically connected between the second end DTL3 of the third sub-active pattern and the first reset line VL1 to electrically connect the third sub-transistor TL3 and the first reset line VL 1. Specifically, the fifth conductive portion F5 is electrically connected to the second end DTL3 of the third sub-active pattern (at CNT8 in fig. 10) through a via hole penetrating through the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001, and is electrically connected to the first reset line VL1 (at CNT9 in fig. 10) through a via hole penetrating through the interlayer dielectric layer.

The sixth conductive portion F6 extends along the second direction y, partially overlaps the second electrode portion E2, the light emission control line EML, and the fifth active pattern, and is electrically connected to the second end DT5 of the fifth active pattern to serve as the first node B. Specifically, the sixth conductive portion F6 is electrically connected to the second end DT5 of the fifth active pattern (e.g., at CNT10 in fig. 10) through a via hole penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001.

The seventh conductive part F7 is electrically connected between the second end DT6 of the sixth active pattern and the second reset line VL2 to electrically connect the initial transistor T6 and the second reset line VL 2. Specifically, the seventh conductive portion F7 is electrically connected to the second end DT6 of the sixth active pattern (e.g., at CNT11 in fig. 10) through a via hole penetrating through the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001, and is electrically connected to the second reset line VL2 (e.g., at CNT12 in fig. 10) through a via hole penetrating through the interlayer dielectric layer.

Fig. 11 is a schematic structural diagram of a fourth conductive layer provided in an embodiment of the invention; the display panel further includes a first planarization layer and a fourth conductive layer on the third conductive layer, the fourth conductive layer including the data line DL and the first sub power line VDD1.

The data line DL includes a first body portion DL1 and an extension portion DL2. The first main body portion DL1 extends along the second direction y, the extension portion DL2 is located on a side of the first main body portion DL1 close to the first sub-active pattern, the extension portion DL2 overlaps with the first end ST2 of the second active pattern and the second conductive portion F2, the extension portion DL2 is electrically connected to the second conductive portion F2, and the extension portion DL2 is electrically connected to the first end ST2 of the second active pattern through the second conductive portion F2. Specifically, the extension portion DL2 is electrically connected to the second conductive portion F2 through a via penetrating through the first planar layer (as shown at PLN1 in fig. 11).

The first sub power line VDD1 and the data line DL are arranged at intervals, and the first sub power line VDD1 includes a second main body portion VD1, a third main body portion VD2, and an avoiding portion VD3 located between the second main body portion VD1 and the third main body portion VD2 and arranged corresponding to the extension portion DL2. The second and third body portions VD1 and VD2 each extend in the second direction y. The evasion portion VD3 overlaps the joint of the first sub-portion EML11a and the third sub-portion EML11c, and is spaced from the overlapping portion EML12, so that there is no overlap between the evasion portion VD3 and the overlapping portion EML12, and there is no parasitic capacitance between the evasion portion VD3 and the overlapping portion EML 12.

Optionally, the second sub-power line VDD2 is electrically connected to the first sub-power line VDD1 through the fourth conductive part F4. Specifically, a portion of the third main body portion VD2 overlaps with the fourth conductive portion F4 and is electrically connected to the fourth conductive portion F4, and in addition, the fourth conductive portion F4 is electrically connected between the first electrode portion E1 and the first end ST4 of the fourth active pattern, and the first electrode portion E1 is electrically connected to the second sub power line VDD2, so that the fourth conductive portion F4 can achieve electrical connection between the second sub power line VDD2 and the first sub power line VDD1, and can enable one of the source and the drain of the first switching transistor T4 to be electrically connected to the second sub power line VDD2 and the first sub power line VDD1. The third body portion VD2 is electrically connected to the fourth conductive portion F4 through a via penetrating through the first planar layer (as shown in fig. 11 at PLN 2).

Optionally, the fourth conductive layer further includes a node connection portion B1, and the node connection portion B1 is located on a side of the first sub power line VDD1 away from the data line DL, and overlaps the sixth conductive portion F6 and is electrically connected to the sixth conductive portion F6. Specifically, the node connecting portion B1 is electrically connected to the sixth conductive portion F6 through a via penetrating the first flat layer (as at PLN3 in fig. 11).

It is understood that the size of the conductive layer and the active layer corresponding to the via may be larger than the size of the conductive layer and the active layer not corresponding to the via.

Optionally, the plurality of light emitting devices are electrically connected to the plurality of pixel driving circuits at the first node B correspondingly. The light emitting device and the source and the drain of the driving transistor T1 in the corresponding pixel driving circuit are electrically connected between the first voltage terminal and the second voltage terminal. Alternatively, the first power line is electrically connected between the first voltage terminal and one of the source and the drain of the driving transistor T1, and the second power line is electrically connected between the cathode of the light emitting device and the second voltage terminal.

The invention also provides a display device, which comprises any one of the driving circuits or any one of the display panels.

It is understood that the display device includes a movable display device (e.g., a notebook computer, a mobile phone, etc.), a fixed terminal (e.g., a desktop computer, a television, etc.), a measuring device (e.g., a sports bracelet, a temperature measuring instrument, etc.), and the like.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A display panel, comprising:

an active layer including a first channel portion and a second channel portion which are oppositely disposed, and a first electrical connection portion connected between the first channel portion and the second channel portion;

a first scan line extending in a first direction and overlapping the first channel portion and the second channel portion; and

the variable signal wire comprises a routing part and an overlapping part which are connected with each other, wherein the overlapping part is positioned on one side of the routing part close to the first electric connection part, and the overlapping part is at least partially overlapped with the first electric connection part.

2. The display panel of claim 1, further comprising a plurality of sub-pixels, each of the sub-pixels comprising a light emitting device and a pixel driving circuit, the pixel driving circuit comprising:

a driving transistor connected in series with the light emitting device between a first power line and a second power line; and

a compensation transistor including a first sub-transistor and a second sub-transistor connected in series, one of a source and a drain of the first sub-transistor being electrically connected to the gate of the driving transistor, the other of the source and the drain of the first sub-transistor being electrically connected to one of a source and a drain of the second sub-transistor, the other of the source and the drain of the second sub-transistor being electrically connected to one of the source and the drain of the driving transistor, the gate of the first sub-transistor and the gate of the second sub-transistor being electrically connected to the first scan line;

wherein the active layer further includes a first sub-active pattern of the first sub-transistor and a second sub-active pattern of the second sub-transistor, the first sub-active pattern including the first channel portion, the second sub-active pattern including the second channel portion.

3. The display panel according to claim 2, wherein the display panel includes a plurality of the variable signal lines, and a plurality of the sub-pixels in a same row are electrically connected to a same one of the variable signal lines.

4. The display panel according to claim 3, further comprising:

a first gate driving circuit electrically connected to the plurality of variable signal lines and configured to output variable signals to the plurality of variable signal lines;

wherein the variable signal has at least one level jump during a light emitting period in which the driving transistor drives the light emitting device to emit light.

5. The display panel according to claim 3, further comprising:

a plurality of cascaded first gate driving circuits, each of which is electrically connected to the two variable signal lines and configured to output a variable signal to the two variable signal lines;

wherein, in the light emitting stage of the driving transistor driving the light emitting device to emit light, each of the variable signals has at least one level jump, and the time of the level jump of the variable signals is different.

6. The display panel according to claim 2, wherein the pixel driving circuit further comprises a reset transistor comprising a third sub-transistor and a fourth sub-transistor connected in series, wherein one of a source and a drain of the third sub-transistor is electrically connected to a first reset line, one of a source and a drain of the fourth sub-transistor is electrically connected to the other of the source and the drain of the second sub-transistor, the other of the source and the drain of the fourth sub-transistor is electrically connected to the other of the source and the drain of the third sub-transistor, and a gate of the third sub-transistor and a gate of the fourth sub-transistor are both electrically connected to a second scan line;

the variable signal line is positioned between the first scanning line and the second scanning line, and is different from the first scanning line and the second scanning line.

7. The display panel according to claim 6, wherein the active layer further comprises a third sub-active pattern of the third sub-transistor, a fourth sub-active pattern of the fourth sub-transistor, and second electrical connections connected between the third sub-active pattern and the fourth sub-active pattern; the third sub-active pattern includes a third channel portion, and the fourth sub-active pattern includes a fourth channel portion;

wherein the second scan line overlaps with the third channel portion and the fourth channel portion, and the first reset line overlaps with the second electrical connection portion; the third sub-active pattern and the fourth sub-active pattern are both located between the variable signal line and the first reset line, and the third sub-active pattern and the fourth sub-active pattern are both spaced apart from the variable signal line.

8. The display panel according to claim 7, wherein the second sub-active pattern and the fourth sub-active pattern are electrically connected to the variable signal line and the bridge portion of the first scan line different layer.

9. The display panel of claim 6, wherein the variable signal line is of the same layer and material as the first reset line.

10. The display panel according to claim 1, wherein an ion doping concentration of the first electrical connection portion is greater than that of the first channel portion and that of the second channel portion.