KR102059368B1 - Organic light emitting display device with compensation function - Google Patents

Abstract

The present invention relates to an organic light emitting display device that accurately and efficiently compensates for a threshold voltage and mobility of a driving transistor.

Description

Organic light emitting display device with compensation function {ORGANIC LIGHT EMITTING DISPLAY DEVICE WITH COMPENSATION FUNCTION}

The present invention relates to an organic light emitting display device having a compensation function.

Recently, an organic light emitting display device, which has been in the spotlight as a display device, has an advantage in that the response speed is high by using an organic light emitting diode (OLED) which emits light by itself, and the luminous efficiency, luminance, and viewing angle are great.

The organic light emitting display device arranges pixels including the organic light emitting diode in a matrix form and controls brightness of pixels selected by the scan signal according to the gray level of the data.

In addition to the organic light emitting diode, each pixel of the organic light emitting diode display includes data lines and gate lines that cross each other, transistors and storage capacitors having a connection structure therewith.

The transistor included in each pixel of the organic light emitting diode display includes a driving transistor for driving the organic light emitting diode, and the driving transistor has unique characteristics such as a threshold voltage and mobility.

The threshold voltage and mobility of the driving transistor may vary depending on the driving time, and deviations may occur between pixels. This may seriously degrade the image quality of the organic light emitting display device.

Therefore, there is an urgent need for a technology capable of accurately and efficiently compensating the threshold voltage and mobility of the driving transistor.

In this background, it is an object of the present invention to provide an organic light emitting display device capable of accurately and efficiently compensating the threshold voltage and mobility of a driving transistor.

Another object of the present invention is to provide an organic light emitting display device having a pixel structure capable of internally compensating a threshold voltage and mobility of a driving transistor in real time.

It is still another object of the present invention to provide an organic light emitting display device having a pixel structure that can accurately and efficiently compensate for the threshold voltage and mobility of a driving transistor while increasing the aperture ratio.

To achieve the above object, in one aspect, the present invention provides a display panel in which a data line is formed in a first direction (vertical direction) and a gate line is formed in a second direction (horizontal direction) to define a plurality of pixels. ; A data driver supplying a data voltage through the data line; A gate driver supplying a scan signal through the gate line; And a timing controller for controlling driving timing of the data driver and the gate driver, wherein each of the plurality of pixels includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, and a scan signal. And a first transistor connected between the reference voltage supply node Nref to which the reference voltage Vref is supplied and the first node of the driving transistor, and the scan signal and controlled by the scan signal and the second of the data line and the driving transistor. A switching element for switching the supply of the reference voltage (Vref) to the reference voltage supply node, including a second transistor connected between the node, a storage capacitor connected between the first node and the second node of the driving transistor It provides an organic light emitting display device further comprising.

As described above, according to the present invention, there is an effect of providing an organic light emitting display device capable of accurately and efficiently compensating the threshold voltage and mobility of a driving transistor.

In addition, according to the present invention, there is an effect of providing an organic light emitting display device having a pixel structure capable of internally compensating the threshold voltage and mobility of the driving transistor in real time.

In addition, according to the present invention, there is an effect of providing an organic light emitting display device having a pixel structure capable of accurately and efficiently compensating the threshold voltage and mobility of a driving transistor and increasing the aperture ratio.

1 is a system configuration diagram of an organic light emitting display device to which embodiments are applied.
2 is a diagram illustrating a pixel structure to which embodiments are applied.
3 is an equivalent circuit diagram of a pixel structure according to the first embodiment.
4 is a timing diagram for mobility compensation driving of a pixel having a pixel structure according to the first embodiment.
5 is a timing diagram for driving the threshold voltage and mobility compensation of a pixel having a pixel structure according to the first embodiment.
6 is a layout view of signal lines of the organic light emitting diode display having the pixel structure according to the first embodiment.
FIG. 7 is a layout view illustrating signal lines of an organic light emitting display device having a pixel structure according to a first exemplary embodiment together with elements in a pixel.
8 and 9 are diagrams illustrating an equivalent circuit and a compensator of two pixel structures according to the second embodiment.
10 is a diagram for describing a driving mode type of a pixel having a pixel structure according to a second exemplary embodiment.
FIG. 11 is a diagram for describing a driving method for a threshold voltage external compensation process when a pixel having a pixel structure according to a second embodiment operates in a hybrid type driving mode.
12 and 13 illustrate two threshold voltage sensing schemes for the threshold voltage external compensation process when the pixel having the pixel structure according to the second embodiment operates in the hybrid type driving mode.
FIG. 14 is a diagram for describing a driving method for a mobility internal compensation process when a pixel having a pixel structure according to a second embodiment operates in a hybrid type driving mode.
FIG. 15 is a diagram for describing a driving method for a threshold voltage internal compensation and mobility internal compensation process when a pixel having a pixel structure according to a second embodiment operates in a full type driving mode.
16 illustrates a threshold voltage sensing capability according to embodiments.
17 is a diagram illustrating mobility compensation capability according to embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are shown in different drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the component of this invention, terms, such as 1st, 2nd, A, B, (a), (b), can be used. These terms are only to distinguish the components from other components, and the terms are not limited in nature, order, order, or number of the components. If a component is described as being "connected", "coupled" or "connected" to another component, that component may be directly connected to or connected to that other component, but between components It is to be understood that the elements may be "interposed" or each component may be "connected", "coupled" or "connected" through other components.

1 is a system configuration diagram of an organic light emitting display device 100 to which embodiments are applied.

Referring to FIG. 1, an organic light emitting display device 100 to which the embodiments are applied includes a display panel 110, a data driver 120, a gate driver 130, a timing controller 140, and the like.

Referring to FIG. 1, in the display panel 100, 4M data lines DL1 to DL4M are formed in a first direction (for example, a vertical direction) and 2N gate lines GL1 in a second direction (eg, a horizontal direction). GL2N) is formed to define a plurality of pixels (P: Pixel).

The data driver 120 supplies corresponding data voltages Vdata through 4M data lines DL1 to DL4M.

The gate driver 130 sequentially supplies the scan signal SCAN through the 2N gate lines GL1 to GL2N.

The timing controller 140 outputs various control signals to control the driving timing of the data driver 120 and the gate driver 130.

The gate driver 130 described above may be located on only one side of the display panel 110 as shown in FIG. 1, or may be divided into two and positioned on both sides of the display panel 110 according to a driving scheme.

In addition, the gate driver 130 may include a plurality of gate driver integrated circuits, and the gate driver integrated circuits may include a tape automated bonding (TAB) method or a chip on glass (COG) method. For example, the display panel 110 may be connected to a bonding pad of the display panel 110 or may be implemented as a GIP (Gate In Panel) type to be directly formed on the display panel 110.

In addition, the data driver 120 may include a plurality of data driving integrated circuits (also referred to as source driving integrated circuits), and the plurality of data driving integrated circuits may include a tape automated bonding (TAB) method or the like. The chip may be connected to a bonding pad of the display panel 110 in a chip on glass (COG) manner or may be directly formed on the display panel 110.

Hereinafter, the pixel structure of each of the plurality of pixels defined in the display panel 100 will be described with reference to FIG. 2, and two embodiments of the pixel structure and the driving method corresponding thereto will be described in detail. Explain.

2 is a diagram illustrating a pixel structure to which embodiments are applied.

Referring to FIG. 2, each of the plurality of pixels of the display panel 110 to which the embodiments are applied, basically, an organic light emitting diode OLED, a driving transistor DT, a first transistor T1, and a second transistor T2. ), And a storage capacitor Cstg.

In the organic light emitting diode OLED, a first electrode (for example, an anode or a cathode) is connected to a driving transistor DT, and a second electrode (for example, a cathode or an anode) is connected to a supply terminal for supplying a ground voltage VSS. Can be.

The driving transistor DT is a transistor for driving the organic light emitting diode OLED, and is controlled by a voltage applied to the second node N2, which is a gate node, and is driven from a driving voltage line DVL. The driving voltage (VDD) is applied to the third node N3, and a current may be supplied to the organic light emitting diode OLED to emit light of the organic light emitting diode OLED.

The first transistor T1 is a transistor connected between a reference voltage supply node (Nref: Reference Node) to which a reference voltage (Vref: Reference Voltage) is supplied and a first node (N1) of the driving transistor (DT). Controlled by the scan signal SCAN supplied through the line GL, the reference voltage Vref applied to the reference voltage supply node Nref may be applied to the first node N1 of the driving transistor DT. have.

The second transistor T2 is a transistor connected between the data line DL and the second node N2 of the driving transistor DT. The scan signal SCAN is applied to the gate node of the first transistor T2. Is controlled by being applied to the gate node, and supplies the data voltage Vdata supplied through the data line to the second node N2 which is the gate node of the driving transistor DT.

The storage capacitor Cstg is connected between the first node N1 and the second node N2 of the driving transistor DT to maintain a voltage for one frame.

As described above, the first transistor T1 and the second transistor T2 receive the scan signal SCAN simultaneously through one gate line GL. Therefore, the gate nodes of the first transistor T1 and the second transistor T2 are circuitly connected to each other.

In the present specification and drawings, all transistors are described as N types, but all transistors or some transistors may be designed as P types according to a circuit design scheme.

On the other hand, the display panel 110 of the organic light emitting display device 100 having the pixel structure according to the first embodiment is referred to as a reference voltage supply node Nref corresponding to a node to which a reference voltage Vref is supplied from each pixel. It may further include a switching device 200 for switching the supply of the voltage (Vref).

For example, one switching element 200 may be disposed for each pixel in the display panel 100, one pixel column for one pixel column, one pixel column for one pixel column, or one pixel column for one pixel column. One pixel may be disposed in each pixel row or one pixel may be disposed in several pixels in one pixel row.

As described above, in order to control whether the reference voltage is supplied to the reference voltage supply node Nref, two embodiments of the pixel structure capable of implementing a switching operation performed by the switching element 200 (first embodiment and first embodiment) are described. Embodiment 2) will be described below.

Briefly describing the two embodiments, the first embodiment adds " third transistor T3 " between the reference voltage supply node Nref and the reference voltage line RVL, through the reference voltage line RVL. In this embodiment, the reference voltage Vref is controlled to be supplied to the reference voltage supply node Nref. Meanwhile, the second embodiment adds a "switch SW" between the reference voltage line RVL connected to the reference voltage supply node Nref and the reference voltage supply unit, so that the reference voltage line is changed according to the switching operation of the switch SW. In this embodiment, the reference voltage Vref is controlled to be supplied to the reference voltage supply node Nref through RVL.

First, the first embodiment will be described.

3 is an equivalent circuit diagram of a pixel structure according to the first embodiment.

Referring to FIG. 3, each pixel having a pixel structure according to the first exemplary embodiment is controlled by a reference control signal (RCS) and includes a reference voltage line RVL for supplying a reference voltage Vref. A third transistor T3 is connected between the reference voltage supply node Nref as a switching element and connected to the reference voltage supply node Nref.

On the other hand, one third transistor T3 is disposed for each pixel, one pixel for each pixel column, one pixel for each of two or more pixels in each pixel column, or One pixel may be disposed for each pixel row, or one pixel may be disposed for two or more pixels in each pixel row.

On the other hand, in order to control the presence or absence of the reference voltage to the reference voltage supply node (Nref), it is possible to control the ON (OFF)-off (OFF) of the third transistor (T3). To this end, the reference control signal line RCSL for supplying the reference control signal RCS for controlling the ON-OFF of the third transistor T3 to the gate node of the third transistor T3: Reference control signal line) may be formed on the display panel 110.

As shown in FIG. 3, the reference control signal line RCSL may be formed and disposed in a second direction (eg, a pixel row direction and a horizontal direction).

In this case, as an example, one reference control signal line RCSL is disposed in a second direction (for example, a pixel row direction and a horizontal direction) for each pixel row, or for each of two or more pixel rows. It can be arranged in common one by one in the direction.

The reference control signal line RCSL may be formed in a first direction (eg, the pixel column direction and the vertical direction).

In this case, as an example, one reference control signal line RCSL is disposed in a first direction (for example, in a pixel column direction and a vertical direction) for each pixel column, or for each of two or more pixel columns. It may be arranged in common one by one in the direction.

Hereinafter, a driving method of a pixel having a pixel structure according to the first embodiment as shown in FIG. 3 will be described with reference to FIGS. 4 and 5.

Referring to FIG. 4, a driving method for compensating for mobility of a pixel having a pixel structure according to a first embodiment will be described. Referring to FIG. 5, a threshold of a pixel having a pixel structure according to a first embodiment will be described. A method of compensating driving of voltage (Vth: Threshold Voltage) and mobility will be described. However, the mobility compensation and the threshold voltage compensation described with reference to FIGS. 4 and 5 are internal compensation schemes that can be performed in real time without using an additional configuration outside the pixel.

4 is a timing diagram for mobility compensation driving of a pixel having a pixel structure according to the first embodiment.

Referring to FIG. 4, each pixel having the pixel structure according to the first embodiment includes an initialization step (S410), a writing step (S420), and a mobility compensation step (μ) for mobility compensation. Compensation step (S430) and the emission step (Emission Step, S440) and the like is operated in the first driving mode.

3 and 4, when each pixel having the pixel structure according to the first embodiment operates in the first driving mode, each step for driving mobility compensation will be described in detail.

3 and 4, in the initialization step S410 for mobility compensation driving, the reference control signal RCS supplied through the reference control signal line RCSL is at a high level and has a gate line. The scan signal SCAN supplied through GL is at a high level. In this case, the data voltage Vdata supplied through the data line DL is an initial level. Here, the data voltage Vdata of the initialization level may be the same as or different from the initialization voltage Vref.

Accordingly, the first transistor T1, the second transistor T2, and the third transistor T3 are in an ON state.

Therefore, the reference voltage Vref supplied to the reference voltage line RVL is connected to the first node N1 of the driving transistor DT through the third transistor T3 and the first transistor T1 in the on state. Is approved. In addition, the data voltage Vdata of the initialization level supplied to the data line DL is applied to the second node N2 of the driving transistor DT through the second transistor T2 in the on state. do.

Accordingly, the first node N1 and the second node N2 of the driving transistor DT are initialized to the data voltage Vdata of the reference voltage Vref and the initialization level, respectively.

That is, in the initialization step S410 of the first driving mode, the reference control signal RCS is supplied, that is, the reference control signal RCS is at a high level, so that the third transistor T3 is turned on to drive the transistor. The first node N1 of the DT may be initialized to the reference voltage Vref.

Meanwhile, in the initialization step S410, the data voltage Vdata supplied through the data line DL may be supplied at a level higher than the initial level (for example, a write level), and in this case, driving The second node N2 of the transistor DT may be initialized to a data voltage of a level higher than the initialization level.

3 and 4, in the recording step S420 which is performed after the initialization step S410 for mobility compensation driving, the reference control signal RCS is maintained at a high level, and the scan signal ( SCAN is maintained at a high level, but the data voltage Vdata is changed to a writing level higher than the initial level.

Accordingly, the reference voltage Vref is continuously applied to the first node N1 of the driving transistor DT, but the data voltage of the initial level is applied to the second node N2 of the driving transistor DT. A data voltage Vdata of a writing level higher than Vdata is applied.

3 and 4, in the mobility compensation step S430 that is performed after the recording step S420 for mobility compensation driving, the scan signal SCAN is maintained at a high level. The data voltage Vdata is maintained at the writing level, but the reference control signal RCS is changed to the low level.

Therefore, while the first transistor T1 and the second transistor T2 are kept in an ON state, the third transistor T3 is turned into an OFF state.

As described above, since the first transistor T1 and the second transistor T2 are kept in an ON state, the data voltage of the writing level at the second node N2 of the driving transistor DT is recorded. Vdata is still applied, but as the third transistor T3 is turned off, the reference voltage Vref is not supplied to the reference voltage supply node Nref, so that the first transistor of the driving transistor DT is not present. The node N1 is floating, and the voltage of the first node N1 of the driving transistor DT starts to rise from the reference voltage Vref.

As described above, the voltage of the first node N1 of the driving transistor DT rising from the reference voltage Vref is the voltage of the second node N2 of the driving transistor DT (that is, the data voltage writing at the write level). Level Vdata)) and the threshold voltage Vth, that is, the voltage of the first node N1 of the driving transistor DT is driven at the voltage of the second node N2 of the driving transistor DT. Before reaching the value obtained by subtracting the threshold voltage Vth of the transistor DT, the light emission step S440 is started as the scan signal SCAN is changed to a low level.

Here, when the first node N1 of the driving transistor DT is referred to as a source node, the voltage of the first node N1 of the driving transistor DT is the second node of the driving transistor DT. An operation of increasing the voltage of N2) to approach the value obtained by subtracting the threshold voltage Vth of the driving transistor DT is referred to as a "source following" operation.

Meanwhile, the rising slope (ΔV / Δt, Δt: voltage rise time of N1) or the rising width (ΔV) of the voltage of the first node N1 of the driving transistor DT according to the source following operation may be It depends on the magnitude of the mobility μ of the driving transistor DT. That is, as the mobility μ of the driving transistor DT increases, the voltage of the first node N1 of the driving transistor DT according to the source following operation may increase or increase much.

On the other hand, after the mobility compensation step, in the light emission step S440, the reference control signal RCS is maintained at a low level, but the scan signal SCAN is changed to a low level. The data voltage Vdata is changed to an initial level or a low level.

Accordingly, the first transistor T1, the second transistor T2, and the third transistor T3 are all turned off, so that the first node N1 and the second node N2 of the driving transistor DT are turned off. Are all floating.

Accordingly, due to the capacitor coupling phenomenon associated with the capacitor component of the organic light emitting diode OLED, the voltages of the first node N1 and the second node N2 of the driving transistor DT maintain the potential difference. Boost together.

The voltages of the first node N1 and the second node N2 of the driving transistor DT increase together, and the voltage of the first node N1 of the driving transistor DT is increased at the base voltage VSS. When the voltage becomes as high as the threshold voltage OLED Vth of the diode OLED, a current flows from the driving transistor DT to the organic light emitting diode OLED, and the organic light emitting diode OLED emits light.

As described with reference to FIG. 4, the mobility μ may be internally compensated in real time for each pixel having the pixel structure according to the first exemplary embodiment.

Meanwhile, referring to FIG. 5, a driving operation capable of compensating the threshold voltage Vth and the mobility μ of the driving transistor DT in each pixel having the pixel structure according to the first embodiment is described below. Will be explained.

5 is a timing diagram for threshold voltage and mobility compensation driving of each pixel having the pixel structure according to the first embodiment.

Referring to FIG. 5, each pixel having the pixel structure according to the first embodiment includes an initialization step S510, a threshold voltage compensation step S520, a writing and mobility compensation step Writing and Mobility Compensation Step S530 and Emission Step S540.

3 and 5, a second driving mode in which each of the plurality of pixels can compensate for the threshold voltage Vth and the mobility μ of the driving transistor DT will be described in detail.

3 and 5, the reference control signal RCS is at a high level, the data voltage Vdata is at an initial level, and the scan signal SCAN is at a high level. to be.

Accordingly, the first transistor T1, the second transistor T2, and the third transistor T3 are in an ON state, and the reference voltage Vref is applied to the first node N1 of the driving transistor DT. When the data voltage Vdata of the initialization level is applied to the second node N2 of the driving transistor DT, the first node N1 and the second node N2 of the driving transistor DT are applied. ) Is initialized. Here, the data voltage Vdata of the initialization level may be the same as or different from the initialization voltage Vref.

In the initializing step S510 of the second driving mode, the reference control signal RCS is supplied, that is, the reference control signal RCS becomes high level, thereby turning on the third transistor T3 to drive the drive transistor DT. The first node N1 of) may be initialized to the reference voltage Vref.

3 and 5, in the threshold voltage compensation step S520 performed after the initialization step S510 described above, the data voltage Vdata is maintained at an initial level, and the scan signal SCAN is Although maintained at a high level, the reference control signal RCS is changed to a low level.

Accordingly, the first transistor T1 and the second transistor T2 remain in the ON state, but the third transistor is turned OFF.

Accordingly, although the data voltage Vdata of the initial level is continuously applied to the second node N2 of the driving transistor DT, the first node N1 of the driving transistor DT is floated and driven. The voltage of the first node N1 of the transistor DT starts to rise from the initialization voltage Vref.

The voltage rise of the first node N1 of the driving transistor DT is such that the voltage of the first node N1 of the driving transistor DT is equal to the voltage of the second node N2 of the driving transistor DT. ) And until the difference between the threshold voltage Vth of the driving transistor DT is reached.

Meanwhile, in the timing diagram of FIG. 5, the timing of the data voltage Vdata and the voltage timing diagram of the first node N1 of the driving transistor DT are the data voltage Vdata and the reference voltage (Initial Level). Vref) shows different voltage values. If the data voltage Vdata and the reference voltage Vref of the initial level are set to the same voltage value, the data voltage Vdata is initialized at the threshold voltage compensation step S520. The voltage should be higher than the level and lower than the writing level.

That is, when the data voltage Vdata and the reference voltage Vref of the initial level are different, the data voltage Vdata is adjusted to two levels of the initial level and the writing level. When the data voltage Vdata and the reference voltage Vref of the initialization level are the same, the data voltage Vdata is equal to 3 of the initial level, the medium level, and the writing level. The level can be adjusted.

3 and 5, in the recording and mobility compensation step S530, which is performed after the threshold voltage compensation step S520, the reference control signal RCS is maintained at a low level, and the scan signal ( SCAN is maintained at a high level, but the data voltage Vdata is changed to a writing level.

As a result, the third transistor T3 is maintained in an OFF state, the first node N1 of the driving transistor DT is continuously floating, and the data voltage Vdata is raised to the write level, thereby driving. The voltage of the second node N2 of the transistor DT is increased to the data voltage Vdata of the write level. Therefore, the voltage of the first node N1 of the driving transistor DT rises again.

On the other hand, before the voltage of the first node N1 of the driving transistor DT rises and becomes saturated, the second transistor T2 is turned off, that is, the scan signal SCAN is turned low. By stopping the source following operation, the recording and mobility compensating step S530 is completed and the light emitting step S540 proceeds.

3 and 5, in the light emitting step S540, the reference control signal RCS is maintained at a low level, and the scan signal SCAN is changed to a low level.

Meanwhile, in the light emitting step S540, the data voltage Vdata may be maintained at the writing level, and may be changed from the writing level to a low level or an initial level.

As a result, the first transistor T1, the second transistor T2, and the third transistor T3 are all turned off, and as a result of the capacitor coupling phenomenon described above, the first transistor T1 is driven. The voltages of the node N1 and the second node N2 rise together, and the organic light emitting diode OLED emits light.

Meanwhile, as described above, in the organic light emitting display device 100 having the pixel structure according to the first embodiment, the reference control signal line RVL is formed in a second direction (for example, the pixel row direction and the horizontal direction). Can be. In this case, as an example, one reference control signal line RCSL is disposed in a second direction (for example, a pixel row direction and a horizontal direction) for each pixel row, or for each of two or more pixel rows. It can be arranged in common one by one in the direction.

The reference control signal line RCSL may be formed in a first direction (eg, the pixel column direction and the vertical direction). In this case, as an example, one reference control signal line RCSL is disposed in a first direction (for example, in a pixel column direction and a vertical direction) for each pixel column, or for each of two or more pixel columns. It may be arranged in common one by one in the direction.

Hereinafter, when the reference control signal line RVL is disposed in the second direction (horizontal direction), and one in common for each of two or more pixel rows, the organic light emitting display device 100 having the pixel structure according to the first embodiment will be described. ) Will be described with reference to FIGS. 6 and 7.

6 is a layout view of signal lines of the organic light emitting diode display 100 having the pixel structure according to the first embodiment. FIG. 7 is a layout view illustrating signal lines of an organic light emitting display device 100 having a pixel structure according to a first exemplary embodiment together with elements in a pixel.

6 and 7, the pixels Pr, Pw, Pg, Pb, ... that can receive scan signals from the 2n-1th gate line GL2n-1 in the 2n-1th pixel row. Is placed. In the 2n-th pixel row, pixels Pr ', Pw', Pg ', Pb', ... which can receive scan signals from the 2n-th gate line GL2n are disposed.

6 and 7, pixels Pr, Pr ′,..., Which can receive a data voltage from the 4m-3rd data line DL4m-3 are disposed in the 4m-3rd pixel column. Pixels Pw, Pw ', ... that can receive data voltages from the 4m-2nd data line DL4m-2 are arranged in the 4m-2nd pixel column, and 4m are arranged in the 4m-1th pixel column. Pixels Pg, Pg ', ... that can receive a data voltage from the -1th data line DL4m-1 are arranged, and the data voltage is applied from the 4mth data line DL4m in the 4mth pixel column. Pixels Pb, Pb ', ... which can be supplied are arranged.

6 and 7 illustrate a case in which the display panel 110 has an R (red) W (white) G (green) B (blue) pixel structure. Pr and Pr 'are red pixels, Pw and Pw 'are white pixels, Pg and Pg' are green pixels, and Pb and Pb 'are blue pixels. Of course, the plurality of pixels defined in the display panel 110 may have an RGB pixel structure instead of the four-color pixel structure.

As illustrated in FIG. 7, one driving voltage line DVL may be disposed every four pixel columns. That is, all the pixels in the 4m-3rd pixel column, the 4m-2nd pixel column, the 4m-1th pixel column, and the 4mth pixel column receive the driving voltage VDD together from one driving voltage line DVLm. Can be.

On the other hand, one reference control signal line RCSLn is disposed between the 2n-1st pixel rows and the 2nth pixel rows, and the third transistor T3 has four pixels Pr, Pw, One for each of Pg and Pb, and one for every four pixels Pr ', Pw', Pg ', and Pb' in the 2nth pixel row.

The third transistor T3 arranged one by one for every four pixels Pr, Pw, Pg, and Pb in the 2n-1th pixel row is controlled by the reference control signal RCS supplied from the reference control signal line RCSLn. It is controlled to supply the reference voltage Vref supplied from the reference voltage line RVLm to the reference voltage supply node Nref in each of the four pixels Pr, Pw, Pg, and Pb in the 2n-1th pixel row. .

The third transistor T3 arranged one by one for every four pixels Pr ', Pw', Pg ', and Pb' in the 2nth pixel row is the reference control signal RCS supplied from the reference control signal line RCSLn. The reference voltage supply node Nref of each of the four pixels Pr ', Pw', Pg ', and Pb' is controlled by the reference voltage line Vref supplied from the reference voltage line RVLm. ).

Hereinafter, as another method for implementing a switching operation for controlling whether the switching element 200 in the pixel structure of FIG. 2 controls the presence or absence of a reference voltage to the reference voltage supply node Nref, the switching element 200 is connected to the reference voltage supply node Nref. A "switch SW" is added between the reference voltage line RVL and the reference voltage supply unit to convert the reference voltage Vref through the reference voltage line RVL according to the switching operation of the switch SW. A second embodiment for controlling supply to Nref) will be described.

8 and 9 are diagrams illustrating an equivalent circuit and a compensator of two pixel structures according to the second embodiment.

8 and 9, a reference voltage line RVL is connected to a reference voltage supply node Nref Nref to which a reference voltage Vref is supplied from each pixel, and the reference voltage line RVL is analogized. An analog digital converter (ADC) 820 or a switch (SW) 810 connected to the reference voltage supply unit 830 is included as the switching element 200.

Here, the switch 810 and the analog-to-digital converter 820 and the like, the threshold voltage of the driving transistor DT with the first node N1 and the second node N2 of the driving transistor DT under a specific voltage condition. Configurations for sensing (Vth).

The switch 810 is configured to drive the transistor through the reference voltage supply node Nref in order to emit light of a pixel or to create a specific condition for compensating the threshold voltage Vth or mobility of the driving transistor DT. When the reference voltage Vref is to be supplied to the first node N1 of the DT, the reference voltage supply unit 840 and the reference voltage line RVL are connected to each other.

In addition, the switch 810 allows the analog-to-digital converter 820 to be connected to the reference voltage line RVL when a specific condition for sensing the threshold voltage Vth of the driving transistor DT is reached. Accordingly, the analog to digital converter 820 senses the voltage of the first node N1 of the driving transistor DT. The threshold voltage Vth of the driving transistor DT may be checked from the sensed voltage, and information about the sensed voltage or the checked threshold voltage Vth may be stored in the memory 830.

Based on the information on the sensing voltage or the threshold voltage Vth stored in the memory 830, the data voltage to be supplied to the data line DL of the corresponding pixel or digital data before the data voltage is converted into an analog value is changed. Can be.

That is, referring to FIGS. 8 and 9, the data change based on the information about the sensing voltage or the threshold voltage Vth stored in the memory 830 may be performed by the timing controller 140 or the data driver 120. For the data source 850, a digital value of the threshold voltage Vth stored in the memory 830 may be added or subtracted in the digital domain. In addition, the data driver 120 may change the data in the analog domain in such a manner that the data driver 120 adds or subtracts the analog value of the threshold voltage Vth stored in the memory 830 with respect to the analog data source 850. have.

The data change may be made in the timing controller 140 or the data driver 120, or may be made by other components outside the timing controller 140 and the data driver 120.

In connection with such data change, the configuration 810 and 820 for sensing the voltage of the reference voltage line RVL, that is, the voltage of the first node N1 of the driving transistor DT, and the sensing voltage or threshold voltage. It may be referred to as a compensation unit 800 including a memory 830 for storing information about the information, and a configuration for performing data change processing (the timing controller 140 or the data driver 120 or a separate configuration).

Meanwhile, as shown in FIG. 8, the reference voltage line RVL through which the reference voltage Vref supplied from the reference voltage supply unit 8201 is transferred to the reference voltage supply node Nref in the pixel is the second direction (horizontal direction). As shown in FIG. 9, the display panel 110 may be formed in the display panel 110 in a first direction (vertical direction). However, although the direction in which the reference voltage line RVL is formed is different, the sensing and compensation operation principles described above are the same.

10 is a diagram for describing a driving mode type of a pixel having a pixel structure according to a second exemplary embodiment.

Referring to FIG. 10, in the pixel having the pixel structure according to the second exemplary embodiment, both the hybrid type and the threshold voltage and the mobility of which the threshold voltage compensates externally and the mobility compensates internally (real time compensation) It can operate in one of the driving modes (Full Type) that performs the internal compensation (real time compensation).

Referring to FIG. 10, when the pixel operates in the hybrid type driving mode, the reference voltage line RVL may be formed on the display panel 110 in a first direction (vertical direction) or in a second direction (horizontal direction). Can be. In contrast, when the pixel operates in the full type driving mode, the reference voltage line RVL should be formed in the display panel 110 in the second direction (horizontal direction).

Therefore, when the reference voltage line RVL is formed in the display panel 110 in the second direction (horizontal direction) as shown in FIG. 8, the pixel is in one of the hybrid type driving mode and the full type driving mode. I can drive it. However, when the reference voltage line RVL is formed in the display panel 110 in the first direction (vertical direction) as shown in FIG. 9, the pixel may be driven only in the hybrid type driving mode.

Meanwhile, the driving mode type may be determined according to the mobility of the backplane of the organic light emitting display device 100. For example, when the mobility of the backplane of the organic light emitting display device 100 is high, both the hybrid type driving mode and the full type driving mode may operate, so that any type may be determined. On the other hand, when the mobility of the backplane of the organic light emitting display device 100 is low, the hybrid type driving mode is more advantageous for the pixel, and thus the driving mode may be set as the hybrid type.

Hereinafter, the hybrid type driving mode will be described with reference to FIGS. 11 to 14, and the full type driving mode will be described with reference to FIG. 15.

Before describing the hybrid type driving mode in detail with reference to FIGS. 11 to 14, the hybrid type driving mode will be briefly described.

Each of the plurality of pixels includes a "threshold voltage external compensation process" in which the threshold voltage Vth of the driving transistor DT is compensated by voltage sensing by the analog-digital converter 820 and data change processing according to the voltage sensing result; When the data voltage Vdata of the writing level is applied to the second node N2 of the driving transistor DT, the mobility internal compensation process is compensated for the mobility μ of the driving transistor DT. It operates in a hybrid type drive mode consisting of ".

In the hybrid type driving mode, the reference voltage line RVL may be formed in the display panel 110 in a first direction (vertical direction) or a second direction (horizontal direction).

Hereinafter, referring to FIG. 11, a driving method for a threshold voltage external compensation process when a pixel having a pixel structure according to the second embodiment operates in a hybrid type driving mode will be described.

FIG. 11 is a diagram for describing a driving method for a threshold voltage external compensation process when a pixel having a pixel structure according to a second embodiment operates in a hybrid type driving mode.

FIG. 11A is an equivalent circuit diagram of a pixel structure satisfying both the pixel structures of FIGS. 8 and 9, and FIG. 11B shows a hybrid type driving of a pixel having the pixel structure of FIG. 11A. The driving timing diagram for the threshold voltage external compensation process when operating the mode.

Referring to FIGS. 11A and 11B, in the hybrid type driving mode operation, the threshold voltage external compensation process may include an initialization step S1110, a threshold voltage sensing step S1120, and the like.

Referring to FIGS. 11A and 11B, in the initialization step S1110 of the threshold voltage external compensation process, the scan signal SCAN is at a high level, and thus, the first transistor T1 and the second transistor are accordingly. (T2) is turned on.

In addition, the switch 810 is turned on, and the reference voltage supply unit 840 and the reference voltage line RVL are connected. Accordingly, the reference voltage Vref is changed from the reference voltage supply unit 840 to the reference voltage supply node Nref. The reference voltage Vref is applied to the first node N1 of the driving transistor DT through the supplied first transistor T1. In this case, the high level data voltage Vdata is applied to the second node N2 of the driving transistor DT through the second transistor T2 in the on state.

That is, in the initialization step S1110 of the threshold voltage external compensation process, the first node N1 and the second node N2 of the driving transistor DT are the initialization voltage Vref and the high level data voltage Vdata. Is initialized to

Referring to FIGS. 11A and 11B, in the threshold voltage sensing step S1120 performed after the initialization step S1110, the switch 810 is turned off, and the analog-to-digital converter 820 and the reference voltage line are turned off. (RVL) is connected.

In addition, as the switch 810 is turned off, the reference voltage is not supplied to the reference voltage supply node Nref, and the first node N1 of the driving transistor DT is floated. Therefore, the voltage of the first node N1 of the driving transistor DT increases from the reference voltage Vref by the above-described source following phenomenon.

The voltage of the first node N1 of the driving transistor DT is a value Vdata obtained by subtracting the threshold voltage Vth of the driving transistor DT from the voltage Vdata of the second node N2 of the driving transistor DT. Rise until -Vth), and then saturation.

In this case, the analog-to-digital converter 820 may sense the voltage of the first node N1 of the driving transistor DT.

After the threshold voltage sensing step S1120, a compensation step (not shown) in which data change processing is performed is performed. That is, when the voltage of the first node N1 of the driving transistor DT is sensed by the analog-to-digital converter 820, the difference value ΔV between the sensed voltages Vdata-Vth and the data voltage Vdata. Vdata- (Vdata-Vth) = Vth) is stored in the memory 830 as the threshold voltage Vth. Subsequently, when the display panel 110 is driven, the threshold voltage Vth stored in the memory 830 is added to the data voltage value of the gamma curve, thereby compensating the threshold voltage.

Meanwhile, the threshold voltage sensing time tsense is from the time when the switch 810 is turned off to the time when the scan signal SCAN falls to the low level. The threshold voltage sensing time tsense is the first time of the driving transistor DT. It must be sufficient time for the voltage at node N1 to rise and saturate.

Therefore, the on-off timing of the switch 810 and the timing of the scan signal SCAN should be controlled to enable the threshold voltage sensing, which may be performed according to the control signal of the timing controller 140.

Meanwhile, the threshold voltage external compensation process described with reference to FIG. 11 includes whether the reference voltage line RVL is disposed in the horizontal direction parallel to the gate line GL or in the vertical direction parallel to the data line DL. Accordingly, the threshold voltage sensing scheme may vary.

A threshold voltage sensing method according to the arrangement direction of the reference voltage line RVL will be described with reference to FIGS. 12 and 13.

12 and 13 illustrate two threshold voltage sensing schemes for the threshold voltage external compensation process when the pixel having the pixel structure according to the second embodiment operates in the hybrid type driving mode.

12 illustrates a case in which the reference voltage lines RVL1, RVL2, RVL3,..., RVL2N are arranged in a horizontal direction parallel to the gate line GL.

Referring to FIG. 12, when the reference voltage lines RVL1, RVL2, RVL3,..., RVL2N are arranged in the horizontal direction parallel to the gate line GL, the gate driver 130 may include all the gate lines GL1. Scan signals SCAN1, SCAN2, ..., SCAN2N are outputted as ~ GL2N).

In addition, the data driver 120 outputs the data voltage for threshold voltage sensing only to the first data line DL1, and the black data voltage (that is, the driving transistor DT) to the remaining data lines DL2 to DL4M. Output voltage lower than the threshold voltage).

Accordingly, only pixels arranged in the first pixel column corresponding to the sensing column receive the data voltage for the threshold voltage sensing through the first data line DL1.

Accordingly, the voltages Vsen (1), Vsen (2), ..., Vsen of the first node N1 of all the driving transistors DT included in each of the pixels arranged in the first pixel column. (2N)) can be sensed at the same time, and from the difference between the sensed voltages Vsen (1), Vsen (2), ..., Vsen (2N) and the data voltage, the first pixel column Threshold voltages of all driving transistors DT included in each of the pixels may be simultaneously sensed.

In this way, after the threshold voltages of all the driving transistors DT included in each of the pixels arranged in the first pixel column are sensed at the same time, the pixels arranged in the second pixel column in the same manner. In order to sense threshold voltages of all driving transistors DT included in each of the gate transistors, the gate driver 130 outputs scan signals SCAN1, SCAN2,..., SCAN2N to all gate lines GL1 to GL2N. The data driver 120 outputs the data voltage for threshold voltage sensing only to the first data line DL2, and the black data voltage (that is, the driving transistor) to the remaining data lines DL1, DL3 to DL4M. A threshold voltage lower than the threshold voltage of DT) may be output to simultaneously sense the threshold voltages of all the driving transistors DT included in each of the pixels arranged in the second pixel column.

According to this sensing method, the threshold voltages of all the driving transistors DT included in each of the pixels arranged in all the pixel columns may be sensed.

As described above, when the reference voltage line RVL is disposed in a direction parallel to the gate line GL, threshold voltage sensing is performed for each pixel column. This is called a "column by column method".

Meanwhile, referring to FIG. 13, when the reference voltage line RVL is disposed in a direction parallel to the data line DL, the scan signal SCAN is sequentially supplied for each pixel row, so that the scan signal SCAN is supplied. The threshold voltages of the driving transistors DT included in all the pixels arranged in the pixel rows may be sensed at the same time.

That is, referring to FIG. 13, the gate driver 130 outputs the scan signal SCAN1 to the first gate line GL1. Accordingly, all pixels arranged in the first pixel row corresponding to the sensing row receive the scan signal SCAN1 through the first gate line GL1. The data driver 120 outputs a data voltage for threshold voltage sensing to all data lines DL1 to DL4M.

Accordingly, the sensing row is performed by the analog-to-digital converter 820 connected to all reference voltage lines (..., RVLi, ..., RVLj, ...) arranged in parallel with the data line DL. The voltages (..., Vsen (i), ..., Vsen (1) of the first node N1 of the driving transistor DT included in all pixels arranged in the first pixel row corresponding to (Sensing Row). j), ...) are sensed at the same time, the threshold voltage can be sensed at the same time.

Subsequently, the threshold voltage of the driving transistor DT included in all the pixels arranged in the second pixel row may be simultaneously sensed using the second pixel row as the sensing row. In this manner, the threshold voltages of the driving transistors DT included in all the pixels arranged in all the pixel rows are sensed.

As described above, when the reference voltage line RVL is disposed in a direction parallel to the data line DL, the threshold voltage sensing is performed for each pixel row. This is called a "row by row" method.

After the threshold voltage external compensation process of the hybrid type driving mode described with reference to FIGS. 11 to 13, the mobility internal compensation process may proceed, which will be described with reference to FIG. 14.

FIG. 14 is a diagram for describing a driving method for a mobility internal compensation process when a pixel having a pixel structure according to a second embodiment operates in a hybrid type driving mode.

FIG. 14A is an equivalent circuit diagram of a pixel structure to which the concept of the pixel structure of FIGS. 8 and 9 is applied to explain the mobility internal compensation process of the hybrid type driving mode, and FIG. 14B is a diagram of FIG. The mobility of a pixel having the pixel structure of Fig. 14A is a drive timing diagram for an internal compensation process.

Referring to FIGS. 14A and 14B, the mobility internal compensation process may include an initialization step S1410, a recording step S1420, a mobility compensation step S1430, a light emission step S1440, and the like. Is done.

Referring to (a) and (b) of FIG. 14, in the initialization step S1410 of the mobility internal compensation process, the first transistor T1 and the second transistor T2 are applied to the high level of the scan signal SCAN. ) Is turned on, the switch 810 is turned on, the first node N1 of the driving transistor DT is initialized to the reference voltage Vref, and the second node N2 of the driving transistor DT is reset. Initialize to data voltage Vdata of Initial Level.

Here, the data voltage Vdata of the initial level may be equal to the reference voltage Vref.

Referring to FIGS. 14A and 14B, in the writing step S1420 of the mobility internal compensation process, the scan signal SCAN is maintained at a high level, and the data voltage is raised to the writing level. At this time, the switch 810 is continuously turned on to connect the reference voltage line RVL and the reference voltage supply unit 840.

Accordingly, the voltage of the second node N2 of the driving transistor DT is increased from the data voltage Vdata of the initial level to the data voltage Vdata of the writing level. At this time, the voltage of the first node N1 of the driving transistor DT is maintained as the reference voltage Vref.

Referring to FIGS. 14A and 14B, in the mobility compensation step S1430 of the mobility internal compensation process, the scan signal SCAN is maintained at a high level, and the data voltage Vdata is maintained at a write level. maintain. In this case, the switch 810 is turned off to connect the reference voltage line RVL and the analog-digital converter 820.

Accordingly, the first node N1 of the driving transistor DT is floated, and the voltage of the first node N1 of the driving transistor DT rises due to a source following phenomenon.

Before the voltage of the first node N1 of the driving transistor DT rises and becomes saturated, the scan signal SCAN is dropped to a low level, so that the second node N2 of the driving transistor DT is also floated. .

Accordingly, the light emission step S1440 is performed to increase the voltages of the first node N1 and the second node N2 of the driving transistor DT at the same time by a capacitor coupling phenomenon. When the voltage of the first node N1 of the driving transistor DT becomes higher than the base voltage VSS by the threshold voltage OLED Vth of the organic light emitting diode OLED, from then on, the current is transmitted to the organic light emitting diode OLED. Begins to cloud, and the organic light emitting diode OLED emits light.

Hereinafter, a case in which the pixel having the pixel structure according to the second embodiment operates in a full type driving mode that performs internal compensation (real time compensation) for both threshold voltage and mobility will be described with reference to FIG. 15. do.

In the full type driving mode, when the data voltage Vdata of the initial level is applied to the second node N2 of the driving transistor DT, the threshold voltage Vth of the driving transistor DT is compensated. When the threshold voltage internal compensation process and the data voltage Vdata of the writing level are applied to the second node N2 of the driving transistor DT, the mobility μ of the driving transistor DT is applied. Is made up of a "mobility internal compensation process" in which is compensated.

For this full type driving mode, the reference voltage line RVL should be formed in the display panel 110 in the second direction (horizontal direction).

FIG. 15 is a diagram for describing a driving method for a threshold voltage internal compensation and mobility internal compensation process when a pixel having a pixel structure according to a second embodiment operates in a full type driving mode.

FIG. 15A is an equivalent circuit diagram of a pixel structure to which both the pixel structures of FIGS. 8 and 9 are applied, and FIG. 15B is a full type pixel having the pixel structure of FIG. It is a drive timing diagram when operating in a drive mode.

Referring to FIGS. 15A and 15B, the "threshold voltage internal compensation process" and the "mobility internal compensation process" of the full-type driving mode may be performed together in real time with respect to data voltage application. Therefore, the following description will be given without distinguishing between the threshold voltage internal compensation process and the mobility internal compensation process.

Referring to FIGS. 15A and 15B, the full type driving mode proceeds to an initialization step S1510, a threshold voltage compensation step S1520, a recording and mobility compensation step S1530, and a light emission step S1540. do.

Referring to FIGS. 15A and 15B, in the initialization step S1510 of the full type driving mode, the scan signal SCAN is supplied at a high level, and the data voltage Vdata is supplied at an initialization level. In this case, the switch 810 is turned on, and the reference voltage line RVL and the reference voltage supply unit 840 are connected to supply the reference voltage Vref to the reference voltage supply node Nref.

As the scan signal SCAN is supplied at a high level, the first transistor T1 and the second transistor T2 are turned on, and the data voltage of the initialization level is transferred through the second transistor T2 to the driving transistor DT. Is applied to the second node N2.

In addition, the reference voltage Vref supplied to the reference voltage supply node Nref is applied to the first node N1 of the driving transistor DT through the first transistor T1 in the on state.

Therefore, the first node N1 and the second node N2 of the driving transistor DT are initialized with the reference voltage Vref and the data voltage Vdata of the initialization level. The reference voltage Vref and the data voltage Vdata of the initialization level may be different voltage values.

Referring to FIGS. 15A and 15B, after the initialization step S1510 of the full type driving mode, in the threshold voltage compensation step S1520, the scan signal SCAN is maintained at a high level so that the first transistor T1) and the second transistor T2 remain on. Therefore, the voltage of the second node N2 of the driving transistor DT is maintained at the data voltage of the initialization level.

However, since the switch 810 is turned off and the reference voltage Vref is not supplied to the reference voltage supply node Nref, the first node N1 of the driving transistor DT is floated.

Accordingly, the voltage of the first node N1 of the driving transistor DT rises due to a source following phenomenon.

The voltage rise of the first node N1 of the driving transistor DT is made up to a voltage value obtained by subtracting the threshold voltage of the driving transistor DT from the voltage of the second node N2 of the driving transistor DT. After that, the saturation state is performed, and the threshold voltage compensation operation is performed.

Referring to FIGS. 15A and 15B, after the threshold voltage compensation step S1520 of the full type driving mode, in the recording and mobility compensation step S1530, the scan signal SCAN is maintained at a high level. The switch 810 is also kept off, but the data voltage Vdata is raised from the initialization level to the writing level.

Accordingly, the voltage of the second node N2 of the driving transistor DT is increased from the data voltage of the initialization level to the data voltage of the writing level, and the voltage of the first node N1 of the floating driving transistor DT is floated. It rises by this source following phenomenon.

Before the voltage of the first node N1 of the driving transistor DT rises to saturate, the scan signal SCAN is dropped to the low berel to allow the light emitting step S1540 to proceed.

The voltage rising width? V of the first node N1 of the driving transistor DT is increased in proportion to the mobility of the driving transistor DT.

Referring to FIGS. 15A and 15B, since the first transistor T1 and the second transistor T2 are both turned off in the light emitting step S1540, the first node of the driving transistor DT may be formed. N1) and the second node N2 are both floating, so that the voltages of the first node N1 and the second node N2 of the driving transistor DT rise together due to the capacitor coupling phenomenon, The light emitting diode OLED emits light.

Meanwhile, in the first and second embodiments, the threshold voltage sensing time tsense for sensing the threshold voltage is a time at which the threshold voltage is sensed, and the first node N1 of the driving transistor DT is floated. It should be at least longer than the time (critical time) from the time when the voltage of the first node N1 of the driving transistor DT rises to the time when the voltage is saturated.

Therefore, when the threshold voltage sensing time tsense is shorter than the threshold time, the accurate threshold voltage is not sensed, and when the threshold voltage sensing time tsense is longer than the threshold time, it takes a long time that is unnecessary to sense the threshold voltage.

Accordingly, the threshold voltage sensing and compensation capability may vary depending on how to adjust the threshold voltage sensing time tsense.

On the other hand, the threshold voltage sensing time is the time when the reference control signal RCS falls to the low level in order to turn off the third transistor T3 in the full type driving mode of the first embodiment and the second embodiment, or From the time when the switch 810 is turned off until the time when the data voltage rises to the write level.

In addition, in the hybrid type driving mode of the second embodiment, the threshold voltage sensing time is from the time when the switch 810 is turned off to the time when the scan signal SCAN falls to a low level.

Accordingly, in order to sense the threshold voltage accurately and quickly, the application timing of the reference control signal RCS (ie, the voltage level change timing) or the on / off timing of the switch 810 and the application timing of the scan signal SCAN (ie, Voltage level change timing).

16 illustrates a threshold voltage sensing capability according to embodiments.

In the graph of FIG. 16, the x axis represents five cases of threshold voltage deviation, and the y axis represents the deviation of the actually sensed threshold voltage with respect to the actual threshold voltage.

Referring to FIG. 16, when the threshold voltage sensing time is sufficiently controlled according to the present embodiments, it can be seen that the threshold voltage deviation ΔVth between pixels can be sensed at approximately 99%. Accordingly, threshold voltage deviation compensation may be enabled at the same time as 99% or more.

17 is a diagram showing mobility compensation capability.

In the graph of FIG. 17, the x-axis is a mobility variation value, and the y-axis is a current deviation (%) of how much current actually flows with respect to the reference current (2.160 μA) to which the driving transistor DT is to flow.

Referring to FIG. 17, it can be seen that mobility compensation can be performed with a variation within ± 3% for a 20% mobility change.

As described above, according to the present invention, there is an effect of providing an organic light emitting display device capable of accurately and efficiently compensating the threshold voltage and mobility of a driving transistor.

In addition, according to the present invention, there is an effect of providing an organic light emitting display device having a pixel structure capable of internally compensating the threshold voltage and mobility of the driving transistor in real time.

In addition, according to the present invention, the scan signal is applied to the gate nodes of the first transistor T1 and the second transistor T2 through one gate line while compensating the threshold voltage and mobility of the driving transistor accurately and efficiently. By supplying, there is an effect of providing an organic light emitting display device having a pixel structure in which the number of gate lines is reduced and the aperture ratio is increased accordingly.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may combine the configurations without departing from the essential characteristics of the present invention. Various modifications and variations may be made, including separation, substitution, and alteration. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: organic light emitting display device 110: display panel
120: data driver 130: gate driver
140: timing controller

Claims (13)

A display panel in which a data line is formed in a first direction and a gate line is formed in a second direction to define a plurality of pixels;
A data driver supplying a data voltage through the data line;
A gate driver supplying a scan signal through the gate line; And
A timing controller configured to control driving timing of the data driver and the gate driver;
Each of the plurality of pixels includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a reference voltage supply node controlled by the scan signal and supplied with a reference voltage, and a first node of the driving transistor. A first transistor to be connected, a second transistor controlled by the scan signal and connected between the data line and a second node of the driving transistor, and storage connected between the first node and the second node of the driving transistor. Including a capacitor,
A switching device for switching the supply of the reference voltage to the reference voltage supply node, further controlled by a reference control signal, the third transistor between the reference voltage line and the reference voltage supply node for supplying the reference voltage And an organic light emitting display device connected to the reference voltage supply node as the switching element. delete The method of claim 1,
The third transistor,
One for each pixel, one for each pixel column, one for each two or more pixels in each pixel column, one for each pixel row, or one for each two or more pixels in each pixel row An organic light emitting display device, characterized in that. The method of claim 1,
And a reference control signal line for supplying the reference control signal to the gate node of the third transistor. The method of claim 4, wherein
The reference control signal line,
One pixel row is disposed one in the second direction, one pixel row is disposed one in the second direction, or one pixel column is disposed one in the first direction, or two The organic light emitting display device of claim 1, wherein one pixel column is disposed in common in the first direction. The method of claim 1,
Each of the plurality of pixels,
Operate in a first drive mode comprising an initialization step, a recording step, a mobility compensation step, and a light emission step, or operate in a second drive mode including an initialization step, a threshold voltage compensation step, a recording and mobility compensation step, and a light emission step,
The reference control signal is supplied in an initialization step of the first driving mode or the second driving mode to turn on the third transistor to initialize the first node of the driving transistor to the reference voltage. Device. delete The method of claim 1,
The reference voltage line,
The organic light emitting display device of claim 1, wherein the display panel is formed in the display panel in the first direction or the second direction. A display panel in which a data line is formed in a first direction and a gate line is formed in a second direction to define a plurality of pixels;
A data driver supplying a data voltage through the data line;
A gate driver supplying a scan signal through the gate line; And
A timing controller configured to control driving timing of the data driver and the gate driver;
Each of the plurality of pixels includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a reference voltage supply node controlled by the scan signal and supplied with a reference voltage, and a first node of the driving transistor. A first transistor to be connected, a second transistor controlled by the scan signal and connected between the data line and a second node of the driving transistor, and storage connected between the first node and the second node of the driving transistor. Including a capacitor,
Further comprising a switching device for switching the supply of the reference voltage to the reference voltage supply node,
A reference voltage line is connected to the reference voltage supply node, and includes a switch for connecting the reference voltage line with an analog-digital converter or a reference voltage supply unit as the switching element,
Each of the plurality of pixels,
A threshold voltage external compensation process for compensating the threshold voltage of the driving transistor through a threshold voltage sensing by the analog-to-digital converter and a data change process according to the voltage sensing result; And a hybrid type driving mode comprising a mobility internal compensation process in which the mobility of the driving transistor is compensated when a voltage is applied. The method of claim 9,
The reference voltage line,
And an organic light emitting display device disposed in a direction parallel to the gate line or in a direction parallel to the data line. The method of claim 10,
When the reference voltage line is disposed in a direction parallel to the gate line, threshold voltage sensing is sequentially performed for each pixel column.
When the reference voltage line is arranged in a direction parallel to the data line, the threshold voltage sensing is sequentially performed for each pixel row unit. A display panel in which a data line is formed in a first direction and a gate line is formed in a second direction to define a plurality of pixels;
A data driver supplying a data voltage through the data line;
A gate driver supplying a scan signal through the gate line; And
A timing controller configured to control driving timing of the data driver and the gate driver;
Each of the plurality of pixels includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a reference voltage supply node controlled by the scan signal and supplied with a reference voltage, and a first node of the driving transistor. A first transistor to be connected, a second transistor controlled by the scan signal and connected between the data line and a second node of the driving transistor, and storage connected between the first node and the second node of the driving transistor. Including a capacitor,
Further comprising a switching device for switching the supply of the reference voltage to the reference voltage supply node,
A reference voltage line is connected to the reference voltage supply node, and includes a switch for connecting the reference voltage line with an analog-digital converter or a reference voltage supply unit as the switching element,
Each of the plurality of pixels,
When the data voltage of the initialization level is applied to the second node of the drive transistor, a threshold voltage internal compensation process for compensating the threshold voltage of the drive transistor, and the data voltage of the write level is applied to the second node of the drive transistor. The organic light emitting display device of claim 1, wherein the organic light emitting display device is operated in a full type driving mode including a mobility internal compensation process in which the mobility of the driving transistor is compensated. The method of claim 12,
The reference voltage line,
And an organic light emitting display device disposed in a direction parallel to the gate line.

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