KR102390477B1 - Organic Light Emitting Diode display device and method for driving the same - Google Patents

Abstract

The present invention relates to an OLED display device capable of realizing peak luminance and realizing peak luminance with a lower data voltage and a driving method thereof, wherein the OLED display device includes a plurality of gate lines and data lines. A display panel including a plurality of defined sub-pixels, a timing controller outputting a sensing time control signal varying a sensing time according to an average image level (APL) of input image data, and the sensing time from the timing controller It is configured to include a gate driver that varies and outputs the sensing time of each sub-pixel in response to a control signal.

Description

OLED display device and driving method thereof {Organic Light Emitting Diode display device and method for driving the same}

The present invention relates to an organic light emitting diode (OLED) display device and a driving method thereof.

Recently, as a flat panel display device that displays an image using digital data, a liquid crystal display (LCD) using liquid crystal, an OLED display using an organic light emitting diode (OLED), etc. are representative. .

Among the flat panel displays, each pixel of the OLED display includes an OLED including an organic light emitting layer between an anode and a cathode, and a pixel circuit independently driving the OLED.

The pixel circuit may be configured in various ways, but in the case of the 3T1C configuration, it includes first and second switching thin film transistors (Thin Film Transistors; hereafter referred to as TFTs), a capacitor, and a driving TFT.

The first switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor. The second switching TFT senses a threshold voltage and mobility of the driving TFT in response to a sensing signal.

However, in such an OLED display device, the difference in characteristics such as the threshold voltage (Vth) and mobility of the driving TFT occurs for each pixel due to process deviation, etc. will occur

In general, the difference in the characteristics of the driving TFT in the initial stage causes spots or patterns on the screen, and the characteristic difference due to the deterioration of the driving TFT that occurs while driving the OLED reduces the lifespan of the OLED display panel or causes an afterimage. there is.

To solve this problem, the timing controller senses the threshold voltage and mobility of the driving TFT of each pixel using the data driver, and compensates the data supplied to each pixel according to the sensed threshold voltage and mobility of the driving TFT How to do it has been introduced.

FIG. 1 is a circuit diagram of a 3T1C pixel of a general OLED display device, and FIG. 2 is a driving timing diagram of the pixel configured as in FIG. 1 .

As shown in FIG. 1 , each pixel of a conventional OLED display includes an organic light emitting diode (OLED) and a pixel circuit driving the organic light emitting diode.

The pixel circuit includes first and second switching TFTs T1 and T2, a storage capacitor Cst, and a driving TFT DT.

The first switching TFT T1 charges a data voltage to the storage capacitor Cst in response to a scan pulse Scan. The driving TFT DT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst. The second switching TFT T2 senses a threshold voltage and mobility of the driving TFT DT in response to a sensing signal.

The organic light emitting diode (OLED) may include a first electrode (eg, an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (eg, a cathode electrode or an anode electrode).

The storage capacitor Cst is electrically connected between a gate electrode and a source electrode of the driving TFT DT, and applies a data voltage corresponding to an image signal voltage or a voltage corresponding thereto for one frame time. can keep you

The operation of each pixel of the conventional OLED display configured as described above will be described as follows.

As shown in FIG. 2 , at the beginning of the frame, the scan pulse SCAN maintains a low state and outputs the sense pulse SENSE to a high state to initialize the driving TFT DT and the capacitor Cst. .

When the sense pulse SENSE is maintained in a high state and the scan pulse SCAN is output in a high state, the data voltage DATA of the data line is charged (stored) in the capacitor Cst. That is, the data voltage is written (data writing).

When the scan pulse SCAN maintains a high state and the sense pulse SENSE is output in a low state, the mobility of the driving TFT DT is sensed and compensated. That is, when the mobility of the driving TFT DT is high, the gate-source voltage Vgs of the driving TFT DT is low. Conversely, when the mobility of the driving TFT DT is low, the driving TFT DT Since the gate-source voltage Vgs of , the mobility of the driving TFT DT is compensated.

And, when both the scan pulse SCAN and the sense pulse SENSE are output in a low state, the driving TFT DT is turned on according to the data voltage stored in the capacitor Cst, and the light emitting diode ( The amount of current supplied to the OLED) is controlled to control the amount of light emitted by the OLED.

Also, although not shown in FIG. 2 , the sense pulse SENSE and the scan pulse SCAN are output to a high state before power-on or after power-off to sense the threshold voltage Vth of the driving TFT DT. This compensates the data supplied to each pixel from the outside, thereby compensating the threshold voltage Vth of the driving TFT DT.

As described above, a driving method for compensating for the threshold voltage and mobility of the driving TFT of each pixel is referred to as a hybrid external compensation (HYB) method.

However, in this hybrid external compensation (HYB) driving method, peak luminance is realized in comparison with a normal driving method in which the scan pulse SCAN and the sense pulse SENSE are driven in the same phase. There was this disadvantageous problem.

That is, in the normal driving method, since the falling edge times of the scan pulse SCAN and the sense pulse SENSE are the same, there is no loss of the gate-source voltage Vgs of the driving TFT DT. Therefore, the luminance is not dropped. However, since the hybrid external compensation (HYB) driving method compensates for the mobility of the driving TFT DT in a source follow method, the luminance is dropped, so that the implementation of the peak luminance is disadvantageous. .

The present invention has been devised to solve this problem, and sets the peak luminance level by analyzing the average picture level of the input image signal, and the sensing time according to the peak luminance level It is an object of the present invention to provide an OLED display device capable of realizing peak luminance by varying , and realizing peak luminance with a lower data voltage, and a method of driving the same.

An OLED display device according to the present invention for achieving the above object includes a display panel having a plurality of sub-pixels defined by a plurality of gate lines and data lines, and an average image level ( APL) comprising a timing controller that outputs a sensing time control signal that varies the sensing time, and a gate driver that varies and outputs the sensing time of each sub-pixel in response to the sensing time control signal from the timing controller. has its characteristics.

Here, the timing controller includes the image data APL analyzer that analyzes the image data input from the outside to analyze the average image level, and relatively sets the peak luminance level when the average image analyzed by the image data APL analyzer is low. A peak luminance setting unit that sets high and sets the peak luminance level relatively low when the average image level is high, and sets a data voltage according to the peak luminance level set by the peak luminance setting unit and provides data to the data driver When the voltage setting unit and the peak luminance level set by the peak luminance setting unit are high, the rising edge time of the GOE signal is delayed relatively long, and when the peak luminance level is low, the rising edge time of the GOE signal is delayed relatively short. and a GOE time setting unit provided to the gate driver, wherein the gate driver masks the sensing pulse with the time-set GOE signal to vary the sensing time of each sub-pixel.

In addition, the timing controller includes the image data APL analyzer that analyzes the image data input from the outside to analyze the average image level, and the peak luminance level is relatively adjusted when the average image analyzed by the image data APL analyzer is low. A peak luminance setting unit that sets high and sets the peak luminance level relatively low when the average image level is high, and sets a data voltage according to the peak luminance level set by the peak luminance setting unit and provides data to the data driver When the voltage setting unit and the peak luminance level set by the peak luminance setting unit are high, the clock pulse width is set to be relatively long, and when the peak luminance level is low, the clock pulse width is set relatively short and provided to the gate driver A GIP clock pulse width setting unit is provided, and the gate driver outputs the variable sensing time of each sub-pixel by using the clock pulse of which the width is variable.

In addition, the timing controller includes the image data APL analyzer that analyzes the image data input from the outside to analyze the average image level, and the peak luminance level is relatively adjusted when the average image analyzed by the image data APL analyzer is low. A peak luminance setting unit that sets high and sets the peak luminance level relatively low when the average image level is high, and sets a data voltage according to the peak luminance level set by the peak luminance setting unit and provides data to the data driver When the voltage setting unit and the peak luminance level set by the peak luminance setting unit are high, the rising edge time of the DOE signal is delayed relatively long, and when the peak luminance level is low, the rising edge time of the DOE signal is delayed relatively short. and a DOE time setting unit provided to the data driver, wherein the data driver varies the data voltage application time according to the DOE signal to vary the sensing time of each sub-pixel.

Meanwhile, in the method of driving an OLED display device according to the present invention for achieving the above object, the OLED display device includes a display panel having a plurality of sub-pixels defined by a plurality of gate lines and data lines. A driving method of a method comprising: analyzing an average image level (APL) of input image data; outputting a sensing time control signal for varying a sensing time according to an average image level (APL) of the image data; It is characterized in that it comprises the step of varying the sensing time of each sub-pixel in response to the sensing time control signal.

Here, the outputting of the sensing time control signal for varying the sensing time according to the average image level (APL) of the image data includes setting a relatively high peak luminance level when the average image level of the image data is low, and setting the peak luminance level to be relatively low when the average image level of the image data is high; when the peak luminance level is high, delaying the rising edge time of the GOE signal relatively long, and when the peak luminance level is low, the GOE signal and outputting a GOE signal with a relatively short delay of a rising edge time of , and varying the sensing time of each sub-pixel includes masking a sensing pulse with the GOE signal to increase the sensing time of each sub-pixel. It is characterized by variability.

In addition, the outputting of the sensing time control signal for varying the sensing time according to the average image level (APL) of the image data includes setting a relatively high peak luminance level when the average image level of the image data is low, and Setting the peak luminance level to be relatively low when the average image level of the image data is high, and when the peak luminance level set by the peak luminance setting unit is high, setting the clock pulse width to be relatively long, and when the peak luminance level is low and outputting a clock pulse having a relatively short clock pulse width, wherein varying the sensing time of each sub-pixel includes varying the sensing time of each sub-pixel by using the clock pulse. characterized.

In addition, the outputting of the sensing time control signal for varying the sensing time according to the average image level (APL) of the image data includes setting a relatively high peak luminance level when the average image level of the image data is low, and Setting the peak luminance level relatively low when the average image level of the image data is high; when the peak luminance level is high, delaying the rising edge time of the DOE signal relatively long, and when the peak luminance level is low, the DOE signal outputting a DOE signal with a relatively short delay of a rising edge time of do.

The OLED display device and the driving method thereof according to the present invention having the above characteristics have the following effects.

That is, the average image level is analyzed by analyzing the image data input from the outside. When the analyzed average image level is low, the peak luminance level is set relatively high, and when the average image level is high, the peak luminance level is set relatively low. When the set peak luminance level is high, the rising edge time of the GOE signal is delayed relatively long, and when the peak luminance level is low, the rising edge time of the GOE signal is delayed relatively short, thereby reducing the sensing time of each sub-pixel. When the peak luminance level is variable or the peak luminance level set by the peak luminance setting unit is high, the clock pulse width is set to be relatively long, and when the peak luminance level is low, the clock pulse width is set relatively short to determine the sensing time of each sub-pixel. When variable or the peak luminance level set by the peak luminance setting unit is high, the rising edge time of the DOE signal is delayed relatively long, and when the peak luminance level is low, the rising edge time of the DOE signal is delayed relatively short. Since the sensing time of the sub-pixel is varied, peak luminance driving is possible, and peak luminance driving is possible with a lower data voltage.

1 is a circuit diagram of a 3T1C pixel of a typical OLED display device;
FIG. 2 is a driving timing diagram of a pixel configured as in FIG. 1 ;
3 is a block diagram schematically illustrating an OLED display device according to an embodiment of the present invention;
4 is a block diagram illustrating an internal configuration of a data processing unit built in the timing controller according to the first embodiment in the OLED display of the present invention shown in FIG. 3;
5 is a block diagram illustrating an internal configuration of a data processing unit built in the timing controller according to the second embodiment in the OLED display device of the present invention shown in FIG. 3;
6 is a graph showing the relationship between the average image level and the peak luminance level according to the OLED display device of the present invention;
7 is a driving timing diagram of a pixel having a 3T1C structure in an OLED display device of the present invention;
8 is a circuit diagram of a 4T1C pixel of an OLED display device according to another embodiment of the present invention;
9 is a driving timing diagram of a pixel configured as in FIG. 8;
10 is a block diagram illustrating an internal configuration of a data processing unit built in the timing controller according to the third embodiment in the OLED display device of the present invention configured as in FIG. 8;
11 is a graph showing a gamma curve according to a gate-source voltage (Vgs) of each driving TFT and a current (Ids) flowing through the driving TFT in the present invention, the prior art, and normal driving.

An OLED display device and a driving method thereof according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

3 is a block diagram schematically illustrating an OLED display device according to an embodiment of the present invention.

The OLED display shown in FIG. 3 includes a timing controller 10 , a data driver 20 , a gate driver 30 , a gamma voltage generator 40 , and a display panel 50 .

The timing controller 10 generates a data control signal and a gate control signal for controlling driving timings of the data driver 20 and the gate driver 30, respectively, using a plurality of synchronization signals input from the outside to generate the data driver 20 ) and the gate driver 30 .

The timing controller 10 analyzes an average picture level (average value of one frame image) of input image data to set a peak luminance level, and sets a data voltage according to the peak luminance level. setting and outputting a data control signal to the data driver 20 , and outputting a sensing time control signal for varying a sensing time according to the peak luminance level to the gate driver 30 .

The timing controller 10 senses information including a threshold voltage Vth and a mobility characteristic of a driving TFT DT of each sub-pixel through the data driver 20, and uses the sensed information (sensed data) to Accordingly, it is possible to compensate the characteristic deviation of the driving TFT of each sub-pixel by compensating the data.

The gamma voltage generator 40 generates a gamma voltage set including a plurality of gamma voltages having different levels and supplies it to the data driver 20 .

The data driver 20 converts digital data from the timing controller 10 into analog data signals in response to a data control signal from the timing controller 10 and supplies them to a plurality of data lines of the display panel 50 . do.

In this case, the data driver 20 subdivides the gamma voltage set from the gamma voltage generator 40 into gray voltages respectively corresponding to gray values of the data, and then converts digital data into an analog data signal using the subdivided gray voltages. convert to The data driver 20 is driven in a sensing mode for external compensation and a display mode for display driving under the control of the timing controller 10 .

The data driver 20 drives each subpixel through a data line using a data signal in the display mode. The data driver 20 drives each sub-pixel using the pre-charge voltage in the sensing mode, and then senses a sensing voltage or a sensing current from each driven sub-pixel through a sensing channel (data line or reference line). It is converted into data, and the sensed data is transmitted to the timing controller 10 .

The gate driver 30 sequentially drives a plurality of gate lines of the display panel 50 in response to a gate control signal from the timing controller 10 . The gate driver 30 varies and outputs the sensing time of each sub-pixel in response to the sensing time control signal of the timing controller 10 .

The gate driver 30 receives the gate control signal and the sensing time control signal directly from the timing controller 10 or receives the gate control signal and the sensing time control signal from the timing controller 10 via the data driver 20 . The sensing time control signal may be supplied.

The gate driver 30 is composed of at least one gate drive IC, is mounted on a circuit film such as TCP, COF, FPC, etc. and is attached to the display panel 50 in a TAB method, or in a COG method. It may be mounted on the display area. In contrast, the gate driver 30 is formed in the non-display area of the TFT substrate together with the TFT array formed in the pixel array of the display panel 50 to be a GIP (Gate In Panel) type built into the display panel 50 . can be formed.

The display panel 50 includes a matrix-type pixel array. Each pixel of the pixel array implements a desired color by a combination of red (R), green (G), and blue (B) sub-pixels, and may additionally include a white (W) sub-pixel for improving luminance.

Each of the sub-pixels includes an OLED element and a pixel circuit for driving the OLED element. The pixel circuit has a 3T1C structure and includes first and second switching TFTs T1 and T2 , a driving TFT DT, and a storage capacitor Cst. The pixel circuit includes first and second gate lines Scan and Sense for controlling the first and second switching TFTs T1 and T2, respectively, and a data line for supplying a data signal to the first switching TFT T1. DATA), a reference line ref for supplying a reference voltage Vref to the second switching TFT T2, an ELVDD line for supplying a high potential power ELVDD to the driving TFT DT, and the cathode of the OLED It is connected to the ELVSS line that supplies the low potential power supply (ELVSS) to the

Also, although not shown in the drawings, the pixel circuit of the display panel 50 may be formed in a 4T1C structure.

FIG. 4 is a block diagram illustrating an internal configuration of a data processing unit built in the timing controller 10 according to the first embodiment in the OLED display device of the present invention shown in FIG. 3 , and FIG. 5 is the diagram shown in FIG. In the OLED display device of the present invention, it is a block diagram showing the internal configuration of the data processing unit built in the timing controller 10 according to the second embodiment.

6 is a graph showing the relationship between the average image level and the peak luminance level according to the OLED display of the present invention, and FIG. 7 is a driving timing diagram of a pixel having a 3T1C structure in the OLED display of the present invention.

4 and 5 illustrate only the data processing unit that varies the sensing time according to the peak luminance level to achieve the object of the present invention, omitting the general data processing unit.

In the OLED display device of the present invention, the data processing unit embedded in the timing controller 10 according to the first embodiment includes an image data APL analysis unit 11 and a peak luminance setting unit 12 as shown in FIG. 4 . ), a data voltage setting unit 13 and a GOE time (Gate Output Enable Time) setting unit 14 are provided.

The image data APL analyzer 11 analyzes an average value of an image (brightness of image) of one frame by analyzing image data input from the outside.

The peak luminance setting unit 12 sets the peak luminance level according to the average image level analyzed by the image data APL analyzing unit 11 . That is, the peak luminance setting unit 12 sets the peak luminance level to be high when the average image level analyzed by the image data APL analyzer 11 is low, and the average analyzed by the image data APL analyzer 11 . If the image level is high, the peak luminance level is set low.

6, when the average image level is about 25%, the peak luminance level is set to about 450 nits, and when the average image level is about 100%, the peak luminance level is set to about 150 nits.

The data voltage setting unit 13 sets a data voltage according to the peak luminance level set by the peak luminance setting unit 12 and provides it to the data driver 20 .

For example, when the peak luminance level is set to about 450 nits, the data voltage is set to 17V, and when the peak luminance level is about 150 nits, the data voltage is set to about 13V and provided to the data driver 20 .

The GOE time (Gate Output Enable Time) setting unit 14 sets the GOE time according to the peak luminance level set in the peak luminance setting unit 12 and provides it to the gate driver 30 .

For example, when the peak luminance level is set to about 450 nits, the rising edge time of the GOE signal is delayed relatively long, and when the peak luminance level is about 150 nits, the rising edge time of the GOE signal is relatively set It is provided to the gate driver 30 by performing a short delay.

Accordingly, the data driver 20 converts digital data from the timing controller 10 into an analog data signal using the set data voltage and supplies it to a plurality of data lines of the display panel 50 .

The gate driver 30 changes the on-time of the second switching TFT T2 of the pixel circuit by masking the sensing pulse Sense with the time-set GOE signal.

Meanwhile, in the OLED display device of the present invention, the data processing unit built in the timing controller 10 according to the second embodiment includes an image data APL analysis unit 11 and a peak luminance setting unit, as shown in FIG. 5 . (12), a data voltage setting unit 13 and a GIP clock pulse width setting unit 15 are provided.

The image data APL analyzer 11 analyzes an average value of an image (brightness of image) of one frame by analyzing image data input from the outside.

The peak luminance setting unit 12 sets the peak luminance level according to the average image level analyzed by the image data APL analyzing unit 11 . That is, the peak luminance setting unit 12 sets the peak luminance level to be high when the average image level analyzed by the image data APL analyzer 11 is low, and the average analyzed by the image data APL analyzer 11 . If the image level is high, the peak luminance level is set low.

6, when the average image level is about 25%, the peak luminance level is set to about 450 nits, and when the average image level is about 100%, the peak luminance level is set to about 150 nits.

The data voltage setting unit 13 sets a data voltage according to the peak luminance level set by the peak luminance setting unit 12 and provides it to the data driver 20 .

For example, when the peak luminance level is set to about 450 nits, the data voltage is set to 17V, and when the peak luminance level is about 150 nits, the data voltage is set to about 13V and provided to the data driver 20 .

The GIP clock pulse width setting unit 15 sets the pulse width supplied to the gate driver 30 according to the peak luminance level set by the peak luminance setting unit 12 and provides it to the gate driver 30 .

For example, when the peak luminance level is set as high as about 450 nits, the clock pulse width is set to be relatively long, and when the peak luminance level is set as low as about 150 nits, the clock pulse width is set relatively short to set the gate driver ( 30) is provided.

Accordingly, the data driver 20 converts digital data from the timing controller 10 into an analog data signal using the set data voltage and supplies it to a plurality of data lines of the display panel 50 .

The gate driver 30 varies the on-time of the second switching TFT T2 of the pixel circuit by using the clock pulse of which the width is variable.

The variable on-time of the second switching TFT T2 of the pixel circuit in the gate driver 30 will be described in more detail with reference to FIGS. 6 and 7 as follows.

As shown in FIG. 7 , at the beginning of the frame, the scan pulse SCAN maintains a low state and outputs the sense pulse SENSE to a high state to initialize the driving TFT DT and the capacitor Cst. .

When the sense pulse SENSE is maintained in a high state and the scan pulse SCAN is output in a high state, the data voltage DATA of the data line is charged (stored) in the capacitor Cst. That is, the data voltage is written (data writing).

When the scan pulse SCAN maintains a high state and the sense pulse SENSE is output in a low state, the mobility of the driving TFT DT is sensed and compensated. That is, when the mobility of the driving TFT DT is high, the gate-source voltage Vgs of the driving TFT DT is low. Conversely, when the mobility of the driving TFT DT is low, the driving TFT DT Since the gate-source voltage Vgs of , the mobility of the driving TFT DT is compensated.

And, when both the scan pulse SCAN and the sense pulse SENSE are output in a low state, the driving TFT DT is turned on according to the data voltage stored in the capacitor Cst, and the light emitting diode ( The amount of current supplied to the OLED) is controlled to control the amount of light emitted by the OLED.

The scan pulse SCAN is in a high state and the sense pulse SENSE is in a low state. The mobility sensing and compensation period of the driving TFT DT varies according to the set feed luminance level.

In order to vary the mobility compensation period of the driving TFT DT, it is necessary to adjust the falling edge time of the sense pulse Sense.

According to the first embodiment of the present invention, when the data processing unit built in the timing controller 10 is configured as shown in FIG. 4 , the GOE time setting unit 14 sets the peak luminance setting unit 12 in the When the peak luminance level is set high, the rising edge time of the GOE signal is delayed relatively long, and when the peak luminance level is set low, the rising edge time of the GOE signal is delayed relatively short.

Accordingly, when the rising edge time of the GOE signal is delayed for a relatively long time, the gate driver 30 delays the falling edge time of the sense pulse for a long time so that the second switching TFT T2 of the pixel circuit Since the on-time is lengthened, the movement sensing and compensation period of the driving TFT DT is shortened.

Conversely, when the rising edge time of the GOE signal is delayed relatively short, the gate driver 30 delays the falling edge time of the sense pulse for a short time so that the second switching TFT T2 of the pixel circuit Since the on-time is shortened, the movement sensing and compensation period of the driving TFT DT becomes long.

That is, as shown in FIG. 6 , when the average image level is relatively high, the mobility sensing and compensation period of the driving TFT DT is shortened (Short Tsen), and when the average image level is relatively low, the driving The movement sensing and compensation period of the TFT (DT) becomes longer (Long Tsen).

According to the second embodiment of the present invention, when the data processing unit built in the timing controller 10 is configured as shown in FIG. 5 , the GIP clock pulse width setting unit 15 is configured to be the peak luminance setting unit 12 . When the peak luminance level is set high, the scan pulse width is set relatively long, and when the peak luminance level is set low in the peak luminance setting unit 12, the scan pulse width is set relatively short.

Accordingly, when the width of the scan pulse is set to be relatively long, the gate driver 30 increases the width of the sense pulse to increase the on time of the second switching TFT T2 of the pixel circuit. time), as a result, the mobility sensing and compensation period of the driving TFT DT is shortened.

Conversely, when the width of the scan pulse is set to be relatively short, the gate driver 30 shortens the width of the sense pulse to enable the on-time (On-) of the second switching TFT T2 of the pixel circuit. time) is shortened, so that the movement sensing and compensation period of the driving TFT DT is lengthened.

That is, as shown in FIG. 6 , when the average image level is relatively high, the mobility sensing and compensation period of the driving TFT DT is shortened (Short Tsen), and when the average image level is relatively low, the driving The movement sensing and compensation period of the TFT (DT) becomes longer (Long Tsen).

Meanwhile, when the sub-pixel is configured as 4T1C to be driven by the internal compensation method, the mobility sensing and compensation period of the driving TFT can be adjusted by adjusting the application time of the data voltage.

8 is a circuit diagram of a 4T1C pixel of an OLED display device according to another embodiment of the present invention, and FIG. 9 is a driving timing diagram of the pixel configured as in FIG. 8 .

As shown in FIG. 8 , a 4T1C pixel of an OLED display according to another exemplary embodiment includes an organic light emitting diode (OLED) and a pixel circuit driving the organic light emitting diode.

The pixel circuit includes first to third switching TFTs SW1 , SW2 , and SW3 , a storage capacitor Cst, and a driving TFT DT.

The first switching TFT SW1 charges a data voltage to the storage capacitor Cst in response to the scan pulse SW1 . The driving TFT DT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst.

The second switching TFT SW2 initializes the driving TFT DT and the storage capacitor Cst in response to the sense pulse SW2.

The third switching TFT SW3 initializes the driving TFT DT and the storage capacitor Cst together with the second switching TFT SW2 in response to the initialization pulse SW3, and Senses and compensates for the threshold voltage.

The organic light emitting diode (OLED) may include a first electrode (eg, an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (eg, a cathode electrode or an anode electrode).

The storage capacitor Cst is electrically connected between a gate electrode and a source electrode of the driving TFT DT, and applies a data voltage corresponding to an image signal voltage or a voltage corresponding thereto for one frame time. can keep you

An operation of each pixel of the OLED display according to another exemplary embodiment of the present invention configured as described above will be described below.

As shown in FIG. 9 , at the beginning of the frame, the scan pulse SW1 is output in a low state, and the sense pulse SW2 and the initialization pulse SW3 are output in a high state at the same time to output the second and second 3 Since the switching TFTs SW2 and SW3 are turned on, the driving TFT DT and the capacitor Cst are initialized.

Then, when the initialization pulse SW3 is maintained in a high state and the sense pulse SENSE is output in a low state, the threshold voltage Vth of the driving TFT DT is sensed, and the initialization pulse SW3 is output to the low state, the threshold voltage Vth of the driving TFT DT is internally compensated.

When the second and third switching TFTs SW2 and SW3 are turned off by maintaining the sense pulse SW2 and the initialization pulse SW3 in a low state, and the scan pulse SW1 is output to a high state, The data DATA voltage of the data line is charged (stored) in the capacitor Cst. That is, the data voltage is written (data writing).

At this time, as the data voltage is written, the mobility of the driving TFT DT is sensed and the mobility of the driving TFT DT is internally compensated.

In addition, when all of the scan pulse SW1 , the sense pulse SW2 , and the initialization pulse SW3 are output in a low state, the driving TFT DT turns according to the voltage of the data DATA stored in the capacitor Cst. It is turned on and controls the amount of current supplied to the light emitting diode (OLED) to control the amount of light emitted by the OLED.

As described above, as shown in FIG. 8 , even when the sub-pixels are configured as 4T1C, the threshold voltage and mobility of the driving TFT DT are compensated by the source follow method, so that the peak is Luminance implementation becomes disadvantageous.

Accordingly, even when the sub-pixels are composed of 4T1C as described above and the threshold voltage and mobility of the driving TFT DT are compensated for by the source follow method, the average picture level of the input image signal Accordingly, the peak luminance may be realized by varying the sensing time.

10 is a block diagram illustrating an internal configuration of a data processing unit built in the timing controller 10 according to the third embodiment in the OLED display device of the present invention configured as shown in FIG. 8 .

In the OLED display device of the present invention, the data processing unit embedded in the timing controller 10 according to the third embodiment includes an image data APL analysis unit 11 and a peak luminance setting unit 12 as shown in FIG. 10 . ), a data voltage setting unit 13 and a DOE time (Data Output Enable Time) setting unit 16 .

The functions of the image data APL analyzer 11, the peak luminance setting unit 12, and the data voltage setting unit 13 are the same as those described in the first and second embodiments of the present invention, and thus will be omitted.

The DOE time setting unit 16 sets the DOE time according to the peak luminance level set by the peak luminance setting unit 12 and provides it to the data driver 20 .

For example, when the peak luminance level is set as high as about 450 nits, the rising edge time of the DOE signal is delayed for a relatively long time, and when the peak luminance level is set as low as about 150 nits, the rising edge time of the DOE signal is provided to the data driver 20 by a relatively short delay.

Accordingly, the data driver 20 converts digital data from the timing controller 10 into an analog data signal using the set data voltage and supplies it to a plurality of data lines of the display panel 50 .

In addition, when the rising edge time of the DOE signal is delayed for a relatively long time, the data driver 20 delays the data voltage application time for a relatively long time based on the rising edge of the scan pulse SW1 and outputs it. The mobility sensing and compensation period of the driving TFT DT is shortened.

Conversely, when the rising edge time of the DOE signal is delayed relatively short, the data driver 20 delays the data voltage application time relatively short based on the rising edge of the scan pulse SW1 and outputs it. The mobility sensing and compensation period of the driving TFT DT is lengthened.

As described above, in the OLED display device and the driving method thereof according to the present invention, since the sensing time varies according to the average screen level (APL) of the input image signal, it is possible to realize peak luminance and achieve peak luminance with a lower data voltage. can be implemented.

11 is a graph showing a gamma curve according to the gate-source voltage (Vgs) of each driving TFT and the current (Ids) flowing through the driving TFT during normal driving, according to the present invention and the prior art.

11 , the OLED display device and the driving method thereof according to the present invention are inferior to normal driving in terms of peak luminance driving, but enable peak luminance driving compared to the prior art.

In addition, the OLED display device and the driving method thereof according to the present invention enable peak luminance driving with a lower data voltage.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

10: Timing controller 11: Video data APL analysis unit
12: peak luminance setting unit 13: data voltage setting unit
14: GOE time setting unit 15: GIP clock pulse width setting unit
16: DOE time setting unit 20: data driver
30: gate driver 40: gamma voltage generator
50: display panel

Claims (14)

a display panel including a plurality of sub-pixels defined by a plurality of gate lines and data lines;
By analyzing the average image level (APL) of input image data, when the analyzed average image level is low, the peak luminance level is set relatively high, and when the average image level is high, the peak luminance level is set relatively low, a timing controller outputting a sensing time control signal for varying a sensing time according to a peak luminance level; and
and a gate driver that varies and outputs the sensing time of each sub-pixel in response to the sensing time control signal from the timing controller. The method of claim 1,
The timing controller is
An image data APL analysis unit that analyzes the image data input from the outside to analyze the average image level;
a peak luminance setting unit for setting a relatively high peak luminance level when the average image analyzed by the image data APL analysis unit is low, and setting the peak luminance level relatively low when the average image level is high;
a data voltage setting unit that sets a data voltage according to the peak brightness level set by the peak brightness setting unit and provides it to the data driver;
When the peak luminance level set in the peak luminance setting unit is high, the rising edge time of the GOE signal is delayed relatively long, and when the peak luminance level is low, the rising edge time of the GOE signal is delayed relatively short and provided to the gate driver and a GOE time setting unit to
The gate driver masks the sensing pulse with the time-set GOE signal to vary the sensing time of each sub-pixel and output the variable. The method of claim 1,
The timing controller is
An image data APL analysis unit that analyzes the image data input from the outside to analyze the average image level;
a peak luminance setting unit for setting a relatively high peak luminance level when the average image analyzed by the image data APL analysis unit is low, and setting the peak luminance level relatively low when the average image level is high;
a data voltage setting unit that sets a data voltage according to the peak brightness level set by the peak brightness setting unit and provides it to the data driver;
When the peak luminance level set by the peak luminance setting unit is high, the clock pulse width is set relatively long, and when the peak luminance level is low, the clock pulse width is set relatively short and provided to the gate driver. to have wealth,
The gate driver varies the sensing time of each sub-pixel by using the clock pulse of which the width is variable and outputs the variable. The method of claim 1,
The timing controller is
An image data APL analysis unit that analyzes the image data input from the outside to analyze the average image level;
a peak luminance setting unit for setting a relatively high peak luminance level when the average image analyzed by the image data APL analysis unit is low, and setting the peak luminance level relatively low when the average image level is high;
a data voltage setting unit that sets a data voltage according to the peak brightness level set by the peak brightness setting unit and provides it to the data driver;
When the peak luminance level set in the peak luminance setting unit is high, the rising edge time of the DOE signal is delayed relatively long, and when the peak luminance level is low, the rising edge time of the DOE signal is delayed relatively short and provided to the data driver and a DOE time setting unit to
The data driver varies the data voltage application time according to the DOE signal to vary the sensing time of each sub-pixel. The method of claim 1,
An OLED display device in which the pixel circuit of each sub-pixel is composed of three transistors and one capacitor for compensating for the mobility of the driving TFT in a source-following manner. The method of claim 1,
An OLED display device in which the pixel circuit of each sub-pixel is composed of four transistors and one capacitor that compensate for the mobility of the driving TFT in a source-following manner. A method of driving an OLED display device having a display panel having a plurality of sub-pixels defined by a plurality of gate lines and data lines, the method comprising:
analyzing an average image level (APL) of input image data;
When the analyzed average image level (APL) is low, the peak luminance level is set relatively high, and when the average image level is high, the peak luminance level is set relatively low, and the sensing time is varied according to the set peak luminance level. outputting a time control signal; And
and varying the sensing time of each sub-pixel in response to the sensing time control signal. 8. The method of claim 7,
The step of outputting a sensing time control signal for varying the sensing time according to the average image level (APL) of the image data includes:
setting a relatively high peak luminance level when the average image level of the image data is low, and setting the peak luminance level relatively low when the average image level of the image data is high;
When the peak luminance level is high, the rising edge time of the GOE signal is delayed relatively long, and when the peak luminance level is low, the GOE signal in which the rising edge time of the GOE signal is relatively short. How the device is driven. 9. The method of claim 8,
Varying the sensing time of each sub-pixel includes:
A method of driving an OLED display device for varying a sensing time of each sub-pixel by masking a sensing pulse with the GOE signal. 8. The method of claim 7,
The step of outputting a sensing time control signal for varying the sensing time according to the average image level (APL) of the image data includes:
setting a relatively high peak luminance level when the average image level of the image data is low, and setting the peak luminance level relatively low when the average image level of the image data is high;
An OLED display device comprising: outputting a clock pulse having a relatively long clock pulse width when the peak luminance level set by the peak luminance setting unit is high, and having a relatively short clock pulse width when the peak luminance level is low driving method. 11. The method of claim 10,
Varying the sensing time of each sub-pixel includes:
A method of driving an OLED display for varying the sensing time of each sub-pixel by using the clock pulse. 8. The method of claim 7,
The step of outputting a sensing time control signal for varying the sensing time according to the average image level (APL) of the image data includes:
setting a relatively high peak luminance level when the average image level of the image data is low, and setting the peak luminance level relatively low when the average image level of the image data is high;
When the peak luminance level is high, the rising edge time of the DOE signal is delayed relatively long, and when the peak luminance level is low, the DOE signal in which the rising edge time of the DOE signal is relatively short. How the device is driven. 13. The method of claim 12,
Varying the sensing time of each sub-pixel includes:
A method of driving an OLED display for varying an application time of a data voltage by using the DOE signal. 13. The method of any one of claims 8, 10 and 12,
The method of driving an OLED display device further comprising the step of setting a data voltage according to the peak luminance level set by the peak luminance setting unit.

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