KR20190057564A - Organic light emitting display device and driving method of the same - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of preventing flickers, and a driving method thereof. The device of the present invention comprises: a display panel which has a plurality of pixels connected to a gate line and a data line; a gate driving unit which outputs a first scan signal, a second scan signal and a light emitting control signal to the gate line; and a data driving unit which outputs a data voltage to the data line during refresh sections, and outputs a reference voltage during a horizontal holding section. When the first scan signal is high, the data voltage is applied to a plurality of pixels, and the second scan signal is high, an initial voltage is applied to the plurality of pixels. After the first scan signal falls to a low state, the second scan signal rises to a high state such that an output luminance delay phenomenon may be prevented.

Description

Technical Field [0001] The present invention relates to an organic light emitting diode (OLED) display device,

And more particularly, to an organic light emitting display capable of preventing flicker and a driving method thereof.

Recently, as the information age has come to the age of information, a display field for visually expressing electrical information signals has been rapidly developed. In response to this, various display devices having excellent performance in thinning, light weighting, Is being developed.

Specific examples of such a display device include a liquid crystal display device (LCD), a field emission display device (FED), and an organic light emitting display device (OLED) have.

Each of the plurality of pixels constituting the organic light emitting display includes an organic light emitting element composed of an organic light emitting layer between the anode and the cathode and a pixel circuit for independently driving the organic light emitting element. The pixel circuit includes a switching thin film transistor (hereinafter referred to as TFT), a driving TFT, and a capacitor. Here, the switching TFT charges the data voltage in the capacitor in response to the scan pulse, and the driving TFT controls the amount of current supplied to the organic light emitting element according to the data voltage charged in the capacitor to control the amount of light emitted from the organic light emitting element.

The organic light emitting display device is a self-emission type display device, unlike a liquid crystal display device, a separate light source is not required, and thus it can be manufactured in a light and thin shape. In addition, the organic light emitting display device is not only advantageous in terms of power consumption by low voltage driving, but also has excellent hue, response speed, viewing angle, and contrast ratio (CR), and has been studied as a next generation display device in various fields. Further, since the organic light emitting element has a surface light emitting structure, it is easy to realize a flexible form.

In the OLED display device having the above advantages, a characteristic difference such as a threshold voltage (Vth) and a mobility of a driving TFT is generated for each pixel due to a process variation or the like, and a voltage drop of the high potential voltage (VDD) And the amount of current for driving the organic light emitting diode is changed, so that a luminance deviation occurs between the pixels. In general, there is a problem in that unevenness or pattern that is unintended on the screen is generated due to the difference in characteristics of the initial driving TFTs, and a characteristic difference due to the deterioration of the driving TFTs generated while driving the organic light emitting elements, And there is a problem that afterimage is generated. Thus, attempts have been made to improve image quality by reducing the luminance deviation between pixels by introducing a compensation circuit that compensates for the characteristic deviation of the drive TFT and compensates for the voltage drop of the high-potential voltage (VDD).

Accordingly, various attempts have been made to reduce the power consumption of the OLED display by variously changing the driving method of the OLED display. One of such driving methods is to control the driving frequency of the organic light emitting display device to be smaller than the basic driving frequency and to control the horizontal holding period of the light emitting state.

However, when a low gray level is expressed in such a driving method, there is a problem that a certain time is delayed until the normal luminance output due to the threshold voltage of the organic light emitting element. This output luminance lag phenomenon causes flicker on the display panel.

The inventors of the present invention have recognized that, when performing low-speed driving in an organic light emitting diode display, it is possible to suppress a decrease in luminance during a refresh interval by an internal compensation circuit or an external voltage compensation method for each pixel of the organic light emitting diode display . Accordingly, the present inventors have invented an organic light emitting display device capable of preventing the output luminance delay phenomenon of the organic light emitting display device.

Accordingly, it is an object of the present invention to provide an organic light emitting display device capable of preventing an output luminance delay phenomenon at a low gray level.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an OLED display device including a display panel including a plurality of pixels connected to a gate line and a data line, And a data driver for outputting a data voltage during a refresh interval and outputting a reference voltage during a horizontal holding interval, wherein when a first scan signal is in a high state, a plurality of When a data voltage is applied to a pixel and a second scan signal is in a high state, an initialization voltage is applied to a plurality of pixels, a first scan signal is polled to a low state, and then a second scan signal is raised to a high state , It is possible to prevent the output luminance delay phenomenon.

According to an exemplary embodiment of the present invention, a refresh period includes an initialization period, a sampling period, a programming period, a compensation period, and a light emission period, The second scan signal is raised to the high state to prevent the output luminance delay phenomenon.

The details of other embodiments are included in the detailed description and drawings.

The time required for the voltage of the source node of the driving TFT provided in each pixel of the organic light emitting diode display according to the embodiment of the present invention to reach the threshold voltage of the organic light emitting diode can be reduced. Accordingly, the OLED display according to an exemplary embodiment of the present invention can output the target luminance without delay, and it is possible to prevent a video defect such as a flicker.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

FIG. 1 is a schematic block diagram for explaining an organic light emitting display according to an embodiment of the present invention. Referring to FIG.
2 is a waveform diagram illustrating a gate signal according to a low-speed driving mode of an OLED display according to an embodiment of the present invention.
3 is a circuit diagram illustrating a 4T2C pixel circuit included in an OLED display according to an embodiment of the present invention.
4 is a waveform diagram showing a signal input to the pixel circuit shown in FIG. 3 during the refresh period.
FIG. 5 is a graph illustrating an initial luminance reduction amount of an OLED display according to an exemplary embodiment of the present invention. Referring to FIG.
6 is a waveform diagram illustrating a signal input to a pixel circuit during a refresh period of the OLED display according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

An element or layer is referred to as being another element or layer " on ", including both intervening layers or other elements directly on or in between.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

In the present invention, the TFT may be configured as a P type or an N type. In the following embodiments, for convenience of description, the TFT is formed as an N type. In describing the pulse-shaped signal, the gate high voltage (VGH) state is defined as a "high state", and the gate low voltage (VGL) state is defined as a "low state".

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram for explaining an organic light emitting display according to an embodiment of the present invention. Referring to FIG.

1, an organic light emitting diode display 100 includes a display panel 110 including a plurality of pixels P connected to a gate line GL and a data line DL, A data driver 140 for supplying a data signal to each of the data lines DL and a timing controller 120 for controlling the gate driver 130 and the data driver 140 .

The timing controller 120 processes image data (RGB) input from the outside in accordance with the size and the resolution of the display panel 110 and supplies the data to the data driver 140. The timing controller 120 receives the synchronization signals SYNC input from the outside, for example, a dot clock signal DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync ) To generate a plurality of gate and data control signals (GCS, DCS). And controls the gate driver 130 and the data driver 140 by supplying the generated gate and data control signals GCS and DCS to the gate driver 130 and the data driver 140, respectively.

The gate driver 130 supplies a gate signal to the gate line GL in accordance with the gate control signal GCS supplied from the timing controller 120. [ Here, the gate signal includes a first scan signal SCAN1, a second scan signal SCAN2, and a light emission control signal EM. In FIG. 1, the gate driver 130 is shown as being disposed on one side of the display panel 110, but the number and arrangement of the gate drivers 130 are not limited thereto. That is, the gate driver 130 may be disposed on one side or both sides of the display panel 110 in a GIP (Gate In Panel) manner.

The data driver 140 converts the image data RGB to a data voltage Vdata according to the data control signal DCS supplied from the timing controller 120 and supplies the converted data voltage Vdata to the data line DL. To the pixel P.

A plurality of gate lines GL and a plurality of data lines DL are intersected with each other in the display panel 110 and each of the plurality of pixels P is connected to a gate line GL and a data line DL.

Here, one pixel P receives a gate signal from the gate driver 130 through the gate line GL, receives a data signal from the data driver 140 through the data line DL, To provide various power sources.

Specifically, one pixel P receives the first scan signal SCAN1, the second scan signal SCAN2 and the emission control signal EM through the gate line GL, Receives the data voltage Vdata and the reference voltage Vref and receives the high potential voltage VDD, the low potential voltage VSS and the initialization voltage Vinit through the power supply line.

Each of the pixels P includes a pixel circuit for controlling driving of the organic light emitting diode OD and the organic light emitting diode OD. Here, the organic light emitting diode OD comprises an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The pixel circuit includes a switching TFT, a driving TFT, and a capacitor. Specifically, in the pixel circuit, the driving TFT controls the amount of light to be supplied to the organic light emitting diode OD according to the data voltage (Vdata) charged in the capacitor to control the amount of light emitted from the organic light emitting diode OD, (SCAN) supplied through the scan line (GL) and charges the capacitor with the data voltage (Vdata).

As described above, the organic light emitting diode display 100 includes the driving TFT and the switching TFT in the pixel circuit, and the active layer constituting each of the driving TFT and the switching TFT may be composed of different materials. As described above, in one pixel circuit, each of the driving TFT and the switching TFT is made of a TFT having different characteristics, and the organic light emitting display 100 may include a multi-type TFT.

Specifically, in the organic light emitting diode display 100 including a multi-type TFT, an LTPS TFT using low temperature poly-silicon (hereinafter referred to as LTPS) is used as a TFT having a polycrystalline semiconductor material as an active layer do. Since the polysilicon material has high mobility (100 cm 2 / Vs or more), low energy consumption power and excellent reliability, the polysilicon material is applied to the gate driver 130 and / or the multiplexer (MUX) for driving the display element TFTs can do. Or the driving TFT in the pixel P in the organic light emitting diode display 100 is preferable.

In the organic light emitting diode display 100 including a multi-type TFT, an oxide semiconductor TFT using an oxide semiconductor material as an active layer is used. Since the oxide semiconductor material has a low off-current, it is suitable for a switching TFT having a short turn-on time and a long turn-off time.

In particular, the organic light emitting diode display 100 including the multi-type TFT according to the embodiment of the present invention includes a pixel circuit in which the switching TFT is made of an oxide semiconductor TFT and the driving TFT is made of an LTPS TFT. However, in the organic light emitting diode display device 100 of the present invention, the switching TFT is not limited to the oxide semiconductor TFT and the driving TFT is not limited to the LTPS TFT, and the multi-type TFT may be variously configured. In the organic light emitting diode display device 100 of the present invention, the pixel circuit may include a single type of TFT instead of a multi-type TFT.

The OLED display 100 may be driven while varying the driving frequency. In more detail, the timing controller 120 of the OLED display 100 adjusts a frame rate through a refresh rate control signal to adjust the driving method of the OLED display 100 have. For example, the organic light emitting display 100 can be driven at a refresh rate higher or lower than the reference refresh rate. In particular, driving the organic light emitting display 100 to a level lower than the reference refresh rate is referred to as 'low speed driving' (also referred to as 'low refresh rate driving'), 100) is referred to as " high-speed driving ".

Here, the low-speed driving means driving at a refresh rate lower than the reference refresh rate of 60 Hz, which drives the organic light emitting display 100 to output fewer than 60 frames for one second . That is, when the refresh rate is 60 Hz, it is driven by 60 frames for one second, and driving at a refresh rate lower than 60 Hz is called low-speed driving. For example, a low-speed drive may have a refresh rate of 1 Hz, and a 1 Hz low-speed drive may output only one frame per second.

Hereinafter, low-speed driving in the organic light emitting display will be described in detail with reference to FIG.

2 is a waveform diagram illustrating a gate signal according to a low-speed driving mode of an OLED display according to an embodiment of the present invention.

Referring to FIG. 2, in order to reduce the power consumption of the OLED display device, the low-speed driving mode can control the horizontal holding period Ph to be long and the refresh period Pr to be short for a unit time.

Here, the horizontal holding period Ph is a period in which the data voltage Vdata is not supplied through the data lines DL connected to the organic light emitting diodes OD and the organic light emitting diode OD is applied even if the reference voltage Vref is applied. Emitting period. The refresh period Pr is an initialization period for applying an initialization voltage Vinit to the organic light emitting diode OD so that the organic light emitting diode OD can emit light during the horizontal holding period Ph, A sampling period for sampling or sensing the threshold voltage Vth of the TFT and a programming period for storing the data voltage Vdata in the capacitor connected to the organic light emitting diode OD.

For example, in the low-speed driving mode, the refresh period Pr during one second can be maintained for 16.6 milliseconds (msec), and the horizontal holding period Ph can be maintained for 983.4 msec. However, the present invention is not limited to this, and the refresh period Pr in the low-speed drive mode may be a period corresponding to a plurality of frames.

Referring to FIG. 2, the gate signal is sequentially shifted to each of the gate lines GL during the refresh period Pr to be supplied to the pixel P. Specifically, the gate signal is sequentially shifted and supplied from the first gate line GL1 to the nth gate line GLn during the refresh period Pr. Here, n denotes the total number of gate lines in the OLED display.

Accordingly, the organic light emitting diode OD emits light during the horizontal holding period Ph by the data voltage Vdata sampled and programmed in the refresh period Pr.

Hereinafter, the operation of the pixel circuit in the refresh period and the horizontal holding period when the organic light emitting display according to the embodiment of the present invention includes the pixel circuit of 4T2C will be described in detail.

3 is a circuit diagram illustrating a 4T2C pixel circuit included in an OLED display according to an embodiment of the present invention.

Referring to Fig. 3, the pixel circuit includes a driving TFT DT, three switching TFTs T1, T2, and T3, and two capacitors C1 and C2.

The driving TFT DT includes a gate node which is a first node N1 connected to the first switching TFT T1, a source node which is a second node N2 connected to the second switching TFT T2 and a source node which is connected to the third switching TFT T3 And a drain node which is a third node N3 connected to the second node N3.

Specifically, the gate node of the driving TFT DT is electrically connected to the data line supplying the data voltage Vdata and the reference voltage Vref. Thus, the gate node of the driving TFT DT is connected to the source node of the first switching TFT Tl to receive the data voltage Vdata and the reference voltage Vref. The drain node of the driving TFT DT is electrically connected to the high potential voltage (VDD) line. Thus, the drain node of the driving TFT DT is connected to the source node of the third switching TFT T3 and is supplied with the high-potential voltage VDD. The source node of the driving TFT DT is electrically connected to the organic light emitting element OD. Specifically, the source node of the driving TFT DT is connected to the anode of the organic light emitting element OD, and is connected to the source node of the second switching TFT T2.

Thus, when the third switching TFT T3 is turned on by the emission control signal EM and the driving TFT DT is also turned on, the driving TFT DT is turned on based on the voltages applied to the gate node and the source node The brightness of the organic light emitting diode OD is controlled by controlling the magnitude of the current flowing through the organic light emitting diode OD.

The first switching TFT Tl includes a gate node connected to the first scan signal SCAN1, a drain node connected to the data line, and a source node N1 connected to the driving TFT DT. Specifically, the gate node of the first switching TFT T1 is connected to the first scan signal SCAN1 and is turned on or off by the first scan signal SCAN1. The drain node of the first switching TFT (T1) is connected to the data line to transfer the data voltage (Vdata) and the reference voltage (Vref) to the gate node of the driving TFT (DT).

Accordingly, when the first scan signal SCAN1 is in the high state, the first switching TFT T1 is turned on to supply the data voltage Vdata and the reference voltage Vref to the gate node of the driving TFT DT .

The second switching TFT T2 includes a gate node connected to the second scan signal SCAN2 line, a drain node connected to the initialization voltage Vinit line, and a source node connected to the source node of the driving TFT DT. Specifically, when the second scan signal SCAN2 is in a high state, the gate node of the second switching TFT T2 turns on the second switching TFT T2. The second switching TFT T2 supplies the initializing voltage Vinit to the second node N2. Accordingly, when the second scan signal SCAN2 is in the high state, the second switching TFT T2 is turned on to supply the initialization voltage Vinit to the second node N2, Thereby initializing the written data voltage Vdata.

The third switching TFT T3 includes a gate node connected to the emission control signal EM line, a drain node connected to the high potential voltage (VDD) line, and a source node connected to the drain node of the driving TFT DT. Specifically, the gate node of the third switching TFT T3 is connected to the emission control signal EM line, and when the emission control signal EM is in a high state, the third switching TFT T3 is turned on. The drain node of the third switching TFT T3 is directly connected to the high potential voltage (VDD) line. The third switching TFT T3 is turned on to supply the high potential voltage VDD to the drain node of the driving TFT DT so that the driving TFT DT is turned on, Adjusts the amount of current of the organic light emitting diode OD by the data voltage Vdata.

The two capacitors may be storage capacitors that store the voltages applied to the gate node or the source node of the driving TFT DT. Further, two capacitors are connected in series at the source node of the driving TFT DT.

Specifically, the first capacitor C1 is electrically connected to the first node N1 which is the gate node of the drive TFT DT and the second node N2 which is the source node of the drive TFT DT. The first capacitor C1 stores a voltage corresponding to the difference between the voltages applied to the first node N1 and the second node N2. The second capacitor C2 is electrically connected to the second node N2 which is the source node of the driving TFT DT and the high potential voltage (VDD) line. Also, the second capacitor C2 is connected in series with the first capacitor C1 at the second node N2. Thus, the second capacitor C2 stores the voltage by the voltage division together with the first capacitor C1.

For example, the first capacitor C1 stores and samples the threshold voltage of the driving TFT DT with a voltage difference between the first node N1 and the second node N2. Further, when the data voltage Vdata is applied, the first capacitor C1 stores and programs the voltage determined by the voltage division with the second capacitor C2. That is, the first capacitor C1 and the second capacitor C2 sample the threshold voltage of the driving TFT DT in a source-follower manner. The first capacitor C1 and the second capacitor C2 are connected to the first node N1 and the second node N2 through a voltage distribution when the potentials of the first node N1 and the second node N2 change, Respectively.

4 is a waveform diagram showing a signal input to the pixel circuit shown in FIG. 3 during the refresh period. Will be described later with reference to Fig. 3 for convenience of explanation.

Referring to FIG. 4, the refresh period Pr includes an initialization period p1, a sampling period p2, a programming period p3, a compensation period p4, and a light emission period p5. The refresh period Pr may be set to approximately one horizontal period (1H), and in some embodiments, the light emitting period p5 may not be included in one horizontal period (1H). That is, the initialization period p1, the sampling period p2, the programming period p3, and the compensation period p4 may be included in one horizontal period 1H.

Data is written to the pixels arranged in one horizontal line of the pixel array during the refresh period (Pr). Specifically, the threshold voltage of the driving TFT DT of the pixel circuit is sampled during the refresh period Pr, and the data voltage Vdata is compensated by the threshold voltage. Accordingly, the data voltage Vdata is compensated and written into the pixel so that the amount of current of the organic light emitting diode OD can be determined regardless of the threshold voltage.

In FIG. 4, the initialization interval p1, the sampling interval p2, the programming interval p3, the compensation interval p4, and the light emission interval p5 are shown to be maintained for the same time, The time interval p2, the programming interval p3, the compensation interval p4, and the light emission interval p5 may vary according to the embodiment.

First, the first scan signal SCAN1 and the second scan signal SCAN2 are rising and go high as soon as the initialization period p1 starts. Simultaneously, the emission control signal EM is polled to a low state. Thus, during the initialization period p1, the first switching TFT (T1) and the second switching TFT (T2) are turned on and the third switching TFT (T3) is turned off. Thus, the reference voltage Vref is supplied from the data line to the first node N1 by the first switching TFT (T1). Further, the initializing voltage Vinit is supplied from the initializing voltage (Vinit) line to the second node N2 by the second switching TFT T2. That is, as the initialization voltage Vinit is supplied to the second node N2 which is the source node of the driving TFT DT, the data voltage Vdata written in the organic light emitting element OD is initialized.

During the sampling period p2, the first scan signal SCAN1 is held in a high state and the second scan signal SCAN2 is held in a low state. The emission control signal EM rises as soon as the sampling period p2 starts and maintains the high state during the sampling period p2. Thus, the first switching TFT (T1) and the third switching TFT (T3) are turned on and the second switching TFT (T2) is turned off during the sampling period (p2). Accordingly, the reference voltage Vref is supplied to the first node N1 through the turned-on first switching TFT Tl and the high-potential voltage VDD is supplied to the driving TFT Tl through the third switching TFT T3, Is supplied to the drain node of the transistor DT. That is, the voltage of the first node N1 is maintained at the reference voltage Vref during the sampling period p2, and the voltage of the second node N2 is maintained at the drain-source current of the driver TFT DT Quot;). Here, the gate-source voltage (hereinafter referred to as Vgs) of the driving TFT DT is sampled at the threshold voltage of the driving TFT DT by the source-follower method. The threshold voltage of the driver TFT DT thus sampled is stored in the first capacitor C1. The voltage of the first node N1 is the reference voltage Vref and the voltage of the second node N2 is Vref-Vth during the sampling period p2.

During the programming period p3, the first scan signal SCAN1 is maintained in a high state and the second scan signal SCAN2 is maintained in a low state. The emission control signal EM is polled at the moment when the programming period p3 is started and held low during the programming period p3. Thus, during the programming period p3, only the first switching TFT (T1) is turned on, and the second switching TFT (T2) and the third switching TFT (T3) are turned off. Accordingly, the data voltage Vdata is supplied to the first node N1 through the turned-on first switching TFT T1, and the drain node and the source node of the driving TFT DT are floated.

The data voltage Vdata is supplied to the first node N1 during the programming period p3 so that the voltage variation of the first node N1 is voltage-divided between the first capacitor C1 and the second capacitor C2 , The voltage of the second node N2 is determined as the voltage-divided voltage value. Specifically, the voltage change amount of the first node N1 is Vdata-Vref, and due to the voltage distribution between the first capacitor C1 and the second capacitor C2 connected in series, during the programming period p3, The amount of change in voltage at the node N2 is C1 / (C1 + C2) * (Vdata-Vref). That is, the voltage of the second node N2 is changed from Vref-Vth determined in the sampling period p2 to C1 / (C1 + C2) * (Vdata-Vth) which is the voltage variation amount in the second node N2 during the programming period p3, Vref). In other words, the voltage of the second node N2 in the programming period p3 is (Vref-Vth) + C1 / (C1 + C2) * (Vdata-Vref), and Vgs of the driving TFT DT is C1 / (C1 + C2)) * (Vdata-Vref) + Vth.

During the compensation period p4, the first scan signal SCAN1 is polled to a low state, and then the second scan signal SCAN2 is raised to a high state. Thereafter, before the end of the compensation period p4, the second scan signal SCAN2 is polled to a low state. During the compensation period p4, the emission control signal EM maintains the low state and the initialization voltage Vinit rises to the high state. That is, during the compensation period p4 during which the first scan signal SCAN1 is in a low state and the second scan signal SCAN2 is in a high state, the initialization voltage Vinit is raised to a high state.

Thus, during the compensation period p4, the first switching TFT T1 and the third switching TFT T3 are turned off, and the second switching TFT T2 is turned on. Thus, the initialization voltage Vinit in the high state is supplied to the second node N2, which is the source node of the driving TFT DT, through the turned-on second switching TFT T2. Accordingly, the voltages of the first node N1 and the second node N2 are polled by the polling of the first scan signal SCAN1 at the start of the compensation period p4 by a predetermined voltage, The voltage of the second node N2 is increased by a predetermined voltage and the voltage of the first node N1 coupled to the second node N2 through the first capacitor C1 is also increased by the second node N2 ) Voltage rise. That is, the voltages of the first node N1 and the second node N2 all rise by a constant voltage due to the initialization voltage Vinit of the high state.

During the light emitting period p5, the first scan signal SCAN1 maintains a low state and the second scan signal SCAN2 maintains a low state. The emission control signal EM is raised at the instant when the emission period p5 starts and is maintained in the high state during the emission period p5. Thus, during the light emitting period p5, the first switching TFT (T1) and the second switching TFT (T2) are turned off, and the third switching TFT (T3) is turned on. Accordingly, the high-potential voltage VDD is supplied to the drain node of the driving TFT DT through the turned-on third switching TFT T3, Vds> Vgs> Vth, (OD). Specifically, the current Ioled flowing through the organic light emitting element OD is controlled by Vgs of the driving TFT DT during the light emitting period p5, and the luminance of the organic light emitting element OD is raised by the Ioled do. The current Ioled flowing through the organic light emitting diode OD during the light emitting period p5 is expressed by the following equation (1).

[Equation 1]

Here, k is a proportional constant reflecting various factors of the pixel circuit, and C '= C1 / (C1 + C2). Considering the expression (1), Vth is canceled in the expression (1), and the current Ioled flowing through the organic light emitting element OD is not affected by the threshold voltage of the driving TFT DT.

Since the general organic light emitting display device immediately shifts from the programming period p3 to the light emitting period p5 without the compensation period p4, the first scan signal SCAN1 generated at the end of the programming period p3, The voltage of the second node N2 is lowered to the threshold voltage of the organic light emitting diode OD connected to the second node N2 due to the voltage drop of the first node N1 and the second node N2, A certain time is required to reach the organic light emitting display device, and the luminance output delay of the organic light emitting display device has occurred.

However, the organic light emitting diode display 100 according to an embodiment of the present invention further includes a compensation period p4 between the programming period p3 and the light emitting period p5, and is generated at the end of the programming period p3 The voltage of the first node N1 and the voltage of the second node N2 due to the polling of the first scan signal SCAN1 is compensated by using the initialization voltage Vinit of high state, To reach the threshold voltage of the organic light emitting diode OD connected to the second node N2. Accordingly, the organic light emitting diode display 100 according to the embodiment of the present invention can output the target luminance without delay, and it is possible to prevent a video defect like a flicker.

FIG. 5 is a graph illustrating an initial luminance reduction amount of an OLED display according to an exemplary embodiment of the present invention. Referring to FIG.

That is, in FIG. 5, the reduction amount of the initial luminance of light emission is expressed as a percentage in accordance with the potential of the initialization voltage (Vinit) in a high state.

The initialization voltage Vinit in the high state is lower in potential than the threshold voltage of the organic light emitting diode OD and the voltage Vin2 in the second node N2 increases as the initialization voltage Vinit in the high state approaches the threshold voltage of the organic light emitting diode. The time for reaching the threshold voltage of the organic light emitting diode OD connected to the second node N2 is reduced, so that the initial luminance reduction of light emission can be mitigated.

Specifically, when the initialization voltage Vinit of high state is 0V, the initial luminance of light emission is reduced by about 10%, and when the initialization voltage Vinit of high state is 1V to 1.5V, the initial luminance of light emission is reduced by about 6% And when the initialization voltage Vinit of the high state was 2V, the initial luminance of the light emission decreased by about 4%.

In other respects, Table 1 shows the flicker level according to the potential of the initialization voltage (Vinit) in a high state.

[Table 1]

When the initialization voltage Vinit in the high state is 0V, the flicker level is 3, and the initialization voltage Vinit in the high state is 1V. The initialization voltage Vinit is relaxed to the flicker level 2 and then the initialization voltage Vinit ) Is 1.5V, the flicker level is relaxed to 1, and when the initialization voltage (Vinit) at the high state is 0V, the flicker level is completely improved to zero.

That is, referring to FIG. 5 and Table 1, when the initialization voltage (Vinit) in the high state is set to be equal to or less than the threshold voltage of the organic light emitting element and close to the threshold voltage of the organic light emitting element, The degree of improvement was found to be the highest. The higher the initialization voltage Vinit of the high state, the higher the flicker improvement degree. However, the initialization voltage Vinit of the high state should be increased within the driving voltage range of the organic light emitting diode OD.

6 is a waveform diagram illustrating a signal input to a pixel circuit during a refresh period of the OLED display according to another embodiment of the present invention. The pixel circuit of the embodiment of the present invention and the pixel circuit of another embodiment of the present invention are the same, but the signals applied to the pixel circuit are different from each other, so the pixel conception will be described later with reference to Fig.

As shown in FIG. 6, the refresh of the OLED display according to another embodiment of the present invention may be performed during two horizontal periods (H1, H2).

Here, each of the two horizontal periods H1 and H2 may be a period corresponding to one horizontal period (1H) in the description of the OLED display according to an embodiment of the present invention.

That is, the initialization period p1 may be included in the first horizontal period H1, and the sampling period p2, the programming period p3, and the compensation period p4 may be included in the second horizontal period H2. Here, the first horizontal period H1 may be a period during which data is written to the pixels P arranged in the front-end horizontal line, and the second horizontal period H2 may be a period during which data is written to the pixels P arranged in the horizontal line It may be a period of time written.

Specifically, since the initialization period p1 is included in the first horizontal period H1, the first scan signal SCAN1 and the second scan signal SCAN2 are in a high state. Simultaneously, the emission control signal EM is polled to a low state. Thus, during the initialization period p1, the first switching TFT (T1) and the second switching TFT (T2) are turned on and the third switching TFT (T3) is turned off. Thus, the reference voltage Vref is supplied from the data line to the first node N1 by the first switching TFT (T1). Further, the initializing voltage Vinit is supplied from the initializing voltage (Vinit) line to the second node N2 by the second switching TFT T2. That is, as the initialization voltage Vinit is supplied to the second node N2 which is the source node of the driving TFT DT, the data voltage Vdata written in the organic light emitting element OD is initialized.

The first scan signal SCAN1 and the second scan signal SCAN2 are sequentially polled in the first horizontal period p1 'except for the initialization period p1 to be in a low state. Thus, the first switching TFT (T1), the second switching TFT (T2), and the third switching TFT (T3) are turned off. Therefore, the data voltage Vdata corresponding to the pixel P of the front-end horizontal line is not applied to the driving TFT DT of the pixel P of the horizontal line in question, The first node N1 and the second node N2 are maintained in the initialized state.

The second horizontal interval H2 may include a sampling interval p2, a programming interval p3, and a compensation interval p4. One embodiment of the present invention and another embodiment of the present invention may be different with respect to the length of the sampling interval p2. That is, the sampling period p2 of the organic light emitting diode display according to another embodiment of the present invention may be longer, and the operation in each section is the same as that described above, so duplicate explanation is omitted.

Thus, since the organic light emitting display according to another embodiment of the present invention refreshes over two horizontal periods, the initialization period and the sampling period can be set long.

Thus, the initialization of the first node and the second node of the gate node source node of the driving TFT can be performed more accurately, and the threshold voltage sampling of the driving TFT can be performed more accurately, Can be performed accurately.

According to an aspect of the present invention, there is provided an OLED display device including a display panel including a plurality of pixels connected to a gate line and a data line, And a data driver for outputting a data voltage during a refresh interval and outputting a reference voltage during a horizontal holding interval, wherein when a first scan signal is in a high state, a plurality of When a data voltage is applied to a pixel and a second scan signal is in a high state, an initialization voltage is applied to a plurality of pixels, a first scan signal is polled to a low state, and then a second scan signal is raised to a high state , It is possible to prevent the output luminance delay phenomenon.

According to another aspect of the present invention, the second scan signal in a high state is polled to a low state before the emission control signal is raised to a high state.

According to still another aspect of the present invention, while the first scan signal is in the low state and the second scan signal is in the high state, the initialization voltage is maintained in the high state.

According to another aspect of the present invention, the initialization voltage in the high state is 0V to 2V.

According to still another aspect of the present invention, a pixel circuit disposed in a plurality of pixels includes: a driving TFT for controlling a current flowing to the organic light emitting element, based on a voltage applied to the gate node and the source node; A first switching TFT for applying a data voltage and a reference voltage to the gate node of the driving TFT, a second switching TFT for applying an initialization voltage to the source node of the driving TFT based on the second scanning signal, And a third switching TFT for applying a high potential voltage to the drain node of the driving TFT.

According to still another aspect of the present invention, the pixel circuit further includes a first capacitor connected to a gate node and a source node of the driving TFT, and a second capacitor connected to a source node of the driving TFT and a voltage line to which a high potential voltage is applied do.

According to an exemplary embodiment of the present invention, a refresh period includes an initialization period, a sampling period, a programming period, a compensation period, and a light emission period, The second scan signal is raised to the high state to prevent the output luminance delay phenomenon.

According to another aspect of the present invention, the initialization voltage is raised to the high state in the compensation period.

According to another aspect of the present invention, the initialization voltage in the high state is lower than the threshold voltage of the organic light emitting element.

According to another aspect of the present invention, the initialization period, the sampling period, the programming period, and the compensation period are included in one horizontal period.

According to another aspect of the present invention, the initialization period, the sampling period, the programming period, and the compensation period are included in one horizontal period.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: organic light emitting display
110: Display panel
120: Timing controller
130: gate driver
140: Data driver
Vdata: data voltage
Vref: Reference voltage
Scan: scan signal
EM: emission control signal
P1: Initialization interval
P2: Sampling interval
P3: Programming section
P4: Compensation section
P5: Light emitting section

Claims (11)

A display panel having a plurality of pixels connected to a gate line and a data line;
A gate driver for outputting a first scan signal, a second scan signal, and a light emission control signal to the gate line;
And a data driver for outputting a data voltage during the refresh interval to the data line and outputting a reference voltage during the horizontal hold interval,
The data voltage is applied to the plurality of pixels when the first scan signal is in a high state,
An initialization voltage is applied to the plurality of pixels when the second scan signal is in a high state,
And the second scan signal is rising to a high state after the first scan signal is polled to a low state. The method according to claim 1,
And the second scan signal in a high state is polled to a low state before the emission control signal is raised to a high state. The method according to claim 1,
Wherein the initialization voltage is maintained in a high state while the first scan signal is in a low state and the second scan signal is in a high state. The method according to claim 1,
Wherein the pixel circuit arranged in the plurality of pixels includes:
A driving TFT for controlling a current flowing to the organic light emitting element based on a voltage applied to the gate node and the source node;
A first switching TFT for applying the data voltage and the reference voltage to a gate node of the driving TFT based on the first scan signal;
A second switching TFT for applying the initializing voltage to the source node of the driving TFT based on the second scanning signal,
And a third switching TFT for applying a high potential voltage to the drain node of the driving TFT based on the light emission control signal. 5. The method of claim 4,
The pixel circuit includes:
A first capacitor connected to the gate node and the source node of the driving TFT,
And a second capacitor connected to a source node of the driving TFT and a voltage line to which the high potential voltage is applied. 5. The method of claim 4,
And the initialization voltage of the high state is lower than the threshold voltage of the organic light emitting element. A driving TFT for controlling a current flowing to the organic light emitting element based on a voltage applied to the gate node and the source node;
A first switching TFT for applying a data voltage and a reference voltage to a gate node of the driving TFT based on a first scanning signal;
A second switching TFT for applying an initialization voltage to the source node of the driving TFT based on the second scan signal,
And a third switching TFT for applying a high potential voltage to a drain node of the driving TFT on the basis of the light emission control signal, the organic light emitting display device comprising: a plurality of pixels, each of which includes a refresh period and a horizontal holding period; , The method comprising:
Wherein the refresh period includes an initialization period, a sampling period, a programming period, a compensation period, and a light emitting period,
And the second scan signal is raised to a high state during the compensation period. 8. The method of claim 7,
And the initialization voltage is increased to a high state during the compensation period. 9. The method of claim 8,
Wherein the initialization voltage of the high state is lower than the threshold voltage of the organic light emitting element. 8. The method of claim 7,
Wherein the initialization period, the sampling period, the programming period, and the compensation period are included in one horizontal period. 8. The method of claim 7,
The initialization period is included in the first horizontal period,
Wherein the sampling period, the programming period, and the compensation period are included in a second horizontal period subsequent to the first horizontal period.

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