KR102385833B1 - Organic light emitting display device and driving method of the same - Google Patents

Abstract

The present invention relates to an organic light emitting diode display and a driving method thereof. The present invention provides a display panel including a gate line and a plurality of pixels connected to the data line, a data driver outputting a data voltage to the data line during a refresh period, a reference voltage during a horizontal holding period, and a first gate during the refresh period and a gate driver that receives a control signal and receives a second gate control signal during the horizontal holding period, and outputs a first scan signal, a second scan signal, and a light emission control signal to a gate line; By setting the control timing to be slower than the control timing of the second gate control signal, it is possible to prevent a luminance increase due to low-speed driving.

Description

Organic light emitting display device and driving method thereof

The present invention relates to an organic light emitting display device and a driving method thereof, and more particularly, to an organic light emitting display device capable of preventing a luminance increase during low-speed driving and a driving method thereof.

Recently, as we enter the information age, the field of display that visually expresses electrical information signals has developed rapidly, and in response to this, various display devices with excellent performance of thinness, light weight, and low power consumption have been developed. is being developed

Specific examples of such a display device include a liquid crystal display device (LCD), a field emission display device (FED), an organic light emitting display device (OLED), and the like. there is.

Each of the plurality of pixels constituting the organic light emitting diode display includes an organic light emitting device including an organic light emitting layer between an anode and a cathode, and a pixel circuit independently driving the organic light emitting device. The pixel circuit includes a switching thin film transistor (hereinafter referred to as a TFT), a driving TFT, and a capacitor. Here, the switching TFT charges the capacitor with a data voltage in response to the scan pulse, and the driving TFT controls the amount of current supplied to the organic light emitting device according to the data voltage charged in the capacitor to control the amount of light emitted from the organic light emitting device.

The organic light emitting display device is a self-emission type display device, and unlike a liquid crystal display device, it does not require a separate light source, so it can be manufactured in a lightweight and thin form. In addition, the organic light emitting display device is being studied as a next-generation display device in various fields because it is advantageous in terms of power consumption due to low voltage driving and excellent in color realization, response speed, viewing angle, and contrast ratio (CR). In addition, since the organic light emitting diode has a surface light emitting structure, it is easy to implement a flexible form.

In the organic light emitting diode display having the above advantages, differences in characteristics such as threshold voltage Vth and mobility of the driving TFT occur for each pixel due to process variation, etc., and a voltage drop of the high potential voltage VDD occurs. Accordingly, the amount of current for driving the organic light emitting diode varies, thereby causing a luminance deviation between pixels. In general, there is a problem in that unintended spots or patterns are generated on the screen due to the difference in characteristics of the driving TFT in the initial stage, and the characteristic difference due to deterioration of the driving TFT that occurs while driving the organic light emitting diode is the lifespan of the organic light emitting display panel. There is a problem of reducing the image or generating an afterimage. Accordingly, attempts to improve image quality by reducing luminance deviation between pixels by introducing a compensation circuit for compensating for the characteristic deviation of the driving TFT and for compensating for the voltage drop of the high potential voltage VDD are continuing.

Accordingly, it was attempted to reduce power consumption of the organic light emitting diode display by variously changing the driving method of the organic light emitting display device. One of the driving methods capable of reducing power consumption is a low-speed driving method in which a driving frequency of the organic light emitting diode display is reduced from a basic driving frequency. In the low-speed driving method, the refresh period in which data is written is controlled to be short, and the horizontal holding period in which the light emission state is maintained is controlled to be long.

Accordingly, in the low-speed driving method, the display panel is temporarily turned off only in the refresh period, and the display panel is maintained in an on state in the horizontal holding period. In this case, since the time for the display panel to emit light increases, the luminance perceived by the viewer increases.

The inventors of the present invention have recognized that when the organic light emitting diode display is driven at a low speed, an increase in luminance of the organic light emitting diode display can be suppressed. Accordingly, the present inventors have invented an organic light emitting diode display capable of preventing an increase in luminance of the organic light emitting diode display.

Accordingly, an object of the present invention is to provide an organic light emitting diode display capable of preventing a luminance increase in low-speed driving.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, an organic light emitting diode display according to an embodiment of the present invention outputs a data voltage during a refresh period to a display panel including a plurality of pixels connected to a gate line and a data line, a data line, and , a data driver that outputs a reference voltage during a horizontal holding period, receives a first gate control signal during a refresh period, and receives a second gate control signal during a horizontal holding period, a first scan signal and a second scan signal on the gate line and a gate driver outputting a light emission control signal, wherein the control timing of the first gate control signal is slower than the control timing of the second gate control signal, thereby preventing a luminance increase due to low-speed driving.

In order to solve the above problems, according to a method of driving an organic light emitting diode display according to an embodiment of the present invention, the control timing of the first gate control signal is slower than the control timing of the second gate control signal, so that the low-speed driving is performed. It is possible to prevent a luminance increase caused by this.

Details of other embodiments are included in the detailed description and drawings.

In the organic light emitting diode display according to an embodiment of the present invention, the luminance of the organic light emitting diode can be decreased by extending the threshold voltage sampling period of the driving TFT by modulation of the control clock signal, so that the luminance increases due to low-speed driving can prevent

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a schematic block diagram illustrating an organic light emitting diode display according to an exemplary embodiment.
2 is a schematic block diagram illustrating a timing controller of an organic light emitting diode display according to an exemplary embodiment.
3 is a waveform diagram illustrating a gate signal in a low-speed driving mode of an organic light emitting diode display according to an exemplary embodiment.
4 is a view for explaining a plurality of frame periods according to an embodiment of the present invention.
5 is a circuit diagram illustrating a pixel circuit included in an organic light emitting diode display according to an exemplary embodiment.
6 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 5 during a refresh period.
7A and 7B are diagrams for explaining an initialization section, a sampling section, and a programming section included in the refresh section.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of the other device or layer.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

In the present invention, the TFT may be configured as a P-type or an N-type, and in the following embodiments, the TFT is configured as an N-type for convenience of description. Also, in describing the pulse-shaped signal, a state of the gate high voltage VGH is defined as a “high state” and a state of the gate low voltage VGL is defined as a “low state”.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram illustrating an organic light emitting diode display according to an exemplary embodiment.

Referring to FIG. 1 , the organic light emitting diode display 100 includes a display panel 110 including a plurality of pixels P connected to a gate line GL and a data line DL and a gate to each of the gate lines GL. It includes a gate driver 130 for supplying a signal, a data driver 140 for supplying a data signal to each of the data lines DL, and a timing controller 120 for controlling the gate driver 130 and the data driver 140 . .

The timing controller 120 processes image data RGB input from the outside to be suitable for the size and resolution of the display panel 110 , and supplies it to the data driver 140 . In addition, the timing controller 120 controls the synchronization signals SYNC input from the outside, for example, the main clock signal mCLK, the data enable signal DE, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync. ) to generate a plurality of gate and data control signals (GCS, DCS). By supplying the generated plurality of gate and data control signals GCS and DCS to the gate driver 130 and the data driver 140 , respectively, the gate driver 130 and the data driver 140 are controlled.

2 is a schematic block diagram illustrating a timing controller of an organic light emitting diode display according to an exemplary embodiment.

Referring to FIG. 2 , the timing controller 120 receives a main clock signal mCLK and generates a first control clock signal cCLK1 and a second control clock signal cCLK2, and a clock modulator 121 and a first and a signal generator 123 for generating gate and data control signals GCS and DCS based on timings of the control clock signal cCLK1 and the second control clock signal cCLK2 .

The clock modulator 121 modulates the main clock signal mCLK to generate a first control clock signal cCLK1 and a second control clock signal cCLK2 having different frequencies. Here, the frequency of the first control clock signal cCLK1 is modulated to be lower than the frequency of the second control clock signal cCLK2.

In addition, the signal generator 123 controls the gate and data in the refresh period Pr and the horizontal holding period Ph, which will be described later, based on the timings of the first control clock signal cCLK1 and the second control clock signal cCLK2 . Outputs the signals GCS and DCS.

Specifically, in the refresh period Pr, the signal generator 123 outputs the first gate control signal GCS1 and the first data control signal DCS1 based on the timing of the first control clock signal cCLK1, and horizontally During the holding period Ph, the signal generator 123 outputs the second gate control signal GCS2 and the second data control signal DCS2 based on the timing of the second control clock signal cCLK2 .

That is, the gate and data control signals GCS and DCS include the first gate control signal GCS1 and the first data control signal DCS1 outputted to the refresh period Pr and the second outputted to the horizontal holding period Ph. and a gate control signal GCS2 and a second data control signal DCS2.

Since the frequency of the first control clock signal cCLK1 is lower than the frequency of the second control clock signal cCLK2, the first gate control signal GCS1 and the first data based on the timing of the first control clock signal cCLK1 Control timing of the control signal DCS1 is later than that of the second gate control signal GCS2 and the second data control signal DCS2 based on the timing of the second control clock signal cCLK2 . Here, the control timing means a rising timing and a falling timing of the gate and data control signals GCS and DCS.

The gate driver 130 supplies a gate signal to the gate line GL according to the gate control signal GCS supplied from the timing controller 120 . Here, the gate signal includes a first scan signal SCAN1 , a second scan signal SCAN2 , and an emission control signal EM. Although it is illustrated in FIG. 1 that the gate drivers 130 are spaced apart from one side of the display panel 110 , the number and arrangement positions of the gate drivers 130 are not limited thereto. That is, the gate driver 130 may be disposed on one side or both sides of the display panel 110 in a GIP (Gate In Panel) method.

The data driver 140 converts the image data RGB into the data voltage Vdata according to the data control signal DCS supplied from the timing controller 120 , and converts the converted data voltage Vdata into the data line DL. is supplied to the pixel P through

In the display panel 110 , the plurality of gate lines GL and the plurality of data lines DL cross each other, and each of the plurality of pixels P is connected to the gate line GL and the data line DL.

Here, one pixel P receives a gate signal from the gate driver 130 through a gate line GL, receives a data signal from the data driver 140 through a data line DL, and a power supply line A variety of power sources are supplied through

Specifically, one pixel P receives the first scan signal SCAN1 , the second scan signal SCAN2 , and the emission control signal EM through the gate line GL, and receives the light emission control signal EM through the data line DL. The data voltage Vdata and the reference voltage Vref are received, and the high potential voltage VDD, the low potential voltage VSS, and the initialization voltage Vinit are received through the power supply line.

In addition, each of the pixels P includes an organic light emitting device OD and a pixel circuit controlling driving of the organic light emitting device OD. Here, the organic light emitting device OD includes an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The pixel circuit includes a switching TFT, a driving TFT, and a capacitor. Specifically, in the pixel circuit, the driving TFT controls the amount of light emitted by the organic light emitting device OD by controlling the amount of current supplied to the organic light emitting device OD according to the data voltage Vdata charged in the capacitor, and the switching TFT controls the amount of light emitted by the gate line. The data voltage Vdata is charged in the capacitor by receiving the scan signal SCAN supplied through the GL.

As described above, the organic light emitting diode display 100 may include a driving TFT and a switching TFT in a pixel circuit, and an active layer constituting each of the driving TFT and the switching TFT may be made of different materials. As described above, in one pixel circuit, each of the driving TFT and the switching TFT is formed of TFTs having different characteristics, so that the organic light emitting diode display 100 may include multiple types of TFTs.

Specifically, in the organic light emitting display device 100 including a multi-type TFT, a LTPS TFT using a low temperature poly-silicon (hereinafter referred to as LTPS) is used as a TFT using a polycrystalline semiconductor material as an active layer. do. Polysilicon material has high mobility (100 cm 2 /Vs or more), low energy consumption, and excellent reliability. can do. Alternatively, it is preferable to apply it as a driving TFT in the pixel P in the organic light emitting diode display 100 .

Also, in the organic light emitting diode display 100 including multi-type TFTs, an oxide semiconductor TFT using an oxide semiconductor material as an active layer is used. Since the oxide semiconductor material has a low off-current, it is suitable for a switching TFT that has a short turn-on time and a long turn-off time.

In particular, the organic light emitting diode display 100 including multi-type TFTs according to an embodiment of the present invention includes a pixel circuit in which a switching TFT is formed of an oxide semiconductor TFT and a driving TFT is formed of a LTPS TFT. However, in the organic light emitting diode display 100 of the present invention, the switching TFT is not limited to an oxide semiconductor TFT and the driving TFT is not limited to an LTPS TFT, and a multi-type TFT may be variously configured. In addition, in the organic light emitting diode display 100 of the present invention, the pixel circuit may include one type of TFT instead of multiple types of TFTs.

The organic light emitting diode display 100 may be driven while varying a driving frequency. Specifically, in the organic light emitting diode display 100 , the timing controller 120 may control a driving method of the organic light emitting display 100 by adjusting a frame rate through a refresh rate control signal. there is. For example, the organic light emitting diode display 100 may be driven at a refresh rate higher or lower than the reference refresh rate. In particular, driving the organic light emitting diode display 100 at a lower than the reference refresh rate is referred to as 'low-speed driving' (also referred to as 'low refresh rate driving'), and driving the organic light emitting diode display 100 at a higher than the reference refresh rate (also referred to as 'low refresh rate driving'). 100) is called 'high-speed driving'.

Here, the low-speed driving refers to driving at a refresh rate lower than 60 Hz, which is a reference refresh rate, which drives the organic light emitting diode display 100 to output fewer than 60 frames for 1 second. means that That is, when the refresh rate is 60 Hz, 60 frames are driven for 1 second, and driving at a refresh rate lower than 60 Hz is called low-speed driving. For example, the low-speed driving may have a refresh rate of 1 Hz, and the 1 Hz low-speed driving may output only one frame for 1 second.

Hereinafter, low-speed driving in the organic light emitting diode display will be described in detail with reference to FIG. 3 .

3 is a waveform diagram illustrating a gate signal in a low speed driving mode of an organic light emitting diode display according to an exemplary embodiment.

Referring to FIG. 3 , in order to reduce power consumption of the organic light emitting diode display, in the low-speed driving mode, the horizontal holding period Ph may be lengthened for a unit time, and the refresh period Pr may be controlled short.

Here, the horizontal holding period Ph refers to the organic light emitting diode OD even though the data voltage Vdata is not supplied and the reference voltage Vref is applied through the data lines DL connected to each of the organic light emitting diodes OD. It is the period in which they emit light. The refresh period Pr is an initialization period in which the initialization voltage Vinit is applied to the organic light emitting element OD so that the organic light emitting element OD emits light during the horizontal holding period Ph, and the organic light emitting element OD is driven. It includes a sampling period for sampling or sensing the threshold voltage Vth of the TFT and a programming period for storing the data voltage Vdata in a capacitor connected to the organic light emitting diode OD.

Referring to FIG. 3 , the gate signal is sequentially shifted to each of the gate lines GL and supplied to the pixel P during the refresh period Pr. Specifically, the gate signal is sequentially shifted and supplied from the first gate line GL1 to the n-th gate line GLn during the refresh period Pr. Here, n denotes the total number of gate lines in the organic light emitting diode display.

Accordingly, the organic light emitting diode OD emits light during the horizontal holding period Ph by the data voltage Vdata sampled and programmed in the refresh period Pr.

And, based on 60Hz, which is the reference refresh rate, the refresh period Pr may include a first frame period Frame 1 for refreshing the frame with a new frame, and the horizontal holding period Ph is the second frame for maintaining the previously refreshed frame. The second frame period Frame 2 to the 60th frame period Frame 60 may be included.

In addition, the control timings of the first gate control signal GCS1 and the first data control signal DCS1 output in the refresh period Pr are the second gate control signal GCS2 and the second gate control signal output in the horizontal holding period Ph. Since it is slower than the control timing of the second data control signal DCS2, the first frame period Frame 1 is in each of the second frame period Frame 2 to the 60th frame period Frame 60 of the horizontal holding period Ph. will be longer than

4 is a view for explaining a plurality of frame periods according to an embodiment of the present invention.

Referring to FIG. 4 , as described above, the first frame period Frame 1 of the refresh period Pr may be controlled to be longer than the second frame period Frame 2 of the horizontal holding period Ph.

In addition, the first frame period Frame 1 may include n first horizontal periods H1 corresponding to the number of gate lines GL, and the second frame period Frame 1 may also include the number of gate lines GL. It may include n second horizontal periods H2.

As described above, since the first frame period Frame 1 is controlled to be longer than the second frame period Frame 2 , the first horizontal period H1 may also be controlled to be longer than the second horizontal period H2 .

For example, when the first horizontal period H1 and the second horizontal period H2 have a time difference by Δt, the first frame period Frame 1 and the second frame period Frame 2 have a time difference of n*Δt fly

Hereinafter, when the organic light emitting diode display according to an exemplary embodiment includes a 4T2C pixel circuit, an operation of the pixel circuit will be described in detail.

5 is a circuit diagram illustrating a pixel circuit included in an organic light emitting diode display according to an exemplary embodiment.

Referring to FIG. 5 , the pixel circuit includes a driving TFT DT, three switching TFTs T1 , T2 , and T3 , and two capacitors C1 and C2 .

The driving TFT DT includes a gate node that is a first node N1 connected to the first switching TFT T1 , a source node that is a second node N2 connected with the second switching TFT T2 , and a third switching TFT T3 . ) and a drain node that is a third node N3 connected to the drain node.

Specifically, the gate node of the driving TFT DT is electrically connected to a data line that supplies the data voltage Vdata and the reference voltage Vref. Accordingly, the gate node of the driving TFT DT is connected to the source node of the first switching TFT T1 to receive the data voltage Vdata and the reference voltage Vref. A drain node of the driving TFT DT is electrically connected to the high potential voltage VDD line. Accordingly, the drain node of the driving TFT DT is connected to the source node of the third switching TFT T3 to receive the high potential voltage VDD. A source node of the driving TFT DT is electrically connected to the organic light emitting diode OD. Specifically, the source node of the driving TFT DT is connected to the anode of the organic light emitting diode OD and is connected to the source node of the second switching TFT T2 .

Accordingly, when the third switching TFT T3 is turned on by the emission control signal EM and the driving TFT DT is also turned on, the driving TFT DT is turned on based on the voltage applied to the gate node and the source node. The luminance of the organic light emitting device OD is controlled by controlling the magnitude of the current flowing through the organic light emitting device OD.

The first switching TFT T1 includes a gate node connected to the first scan signal SCAN1 line, a drain node connected to the data line, and a source node that is a first node N1 connected to the driving TFT DT. Specifically, the gate node of the first switching TFT T1 is connected to the first scan signal SCAN1 line and is turned on or off by the first scan signal SCAN1 . The drain node of the first switching TFT T1 is connected to the data line to transmit the data voltage Vdata and the reference voltage Vref to the gate node of the driving TFT DT.

Accordingly, when the first scan signal SCAN1 is in a high state, the first switching TFT T1 is turned on to supply the data voltage Vdata and the reference voltage Vref to the gate node of the driving TFT DT. .

The second switching TFT T2 includes a gate node connected to the second scan signal line SCAN2 , a drain node connected to the initialization voltage Vinit line, and a source node connected to the source node of the driving TFT DT. Specifically, in the gate node of the second switching TFT T2 , when the second scan signal SCAN2 is in a high state, the second switching TFT T2 is turned on. The second switching TFT T2 supplies the initialization voltage Vinit to the second node N2 . Accordingly, when the second scan signal SCAN2 is in the high state, the second switching TFT T2 is turned on to supply the initialization voltage Vinit to the second node N2 to the organic light emitting diode OD. The written data voltage Vdata is initialized.

The third switching TFT T3 includes a gate node connected to the emission control signal EM line, a drain node connected to the high potential voltage VDD line, and a source node connected to the drain node of the driving TFT DT. Specifically, the gate node of the third switching TFT T3 is connected to the emission control signal EM line, and when the emission control signal EM is in a high state, the third switching TFT T3 is turned on. The drain node of the third switching TFT T3 is directly connected to the high potential voltage VDD line. Accordingly, when the emission control signal EM is in a high state, the third switching TFT T3 is turned on to supply the high potential voltage VDD to the drain node of the driving TFT DT, and the driving TFT DT is turned on. The amount of current of the organic light emitting diode OD is controlled by the data voltage Vdata.

The two capacitors may be storage capacitors for storing a voltage applied to a gate node or a source node of the driving TFT DT. Also, two capacitors are connected in series at the source node of the driving TFT (DT).

Specifically, the first capacitor C1 is electrically connected to a first node N1 serving as a gate node of the driving TFT DT and a second node N2 serving as a source node of the driving TFT DT. Accordingly, the first capacitor C1 stores a voltage equal to the difference between the voltages applied to the first node N1 and the second node N2 . The second capacitor C2 is electrically connected to the second node N2 serving as the source node of the driving TFT DT and the high potential voltage VDD line. In addition, the second capacitor C2 is connected in series with the first capacitor C1 at the second node N2 . Accordingly, the second capacitor C2 stores a voltage by voltage division together with the first capacitor C1.

For example, the first capacitor C1 stores and samples the threshold voltage of the driving TFT DT as a voltage difference between the first node N1 and the second node N2 . Also, when the data voltage Vdata is applied, the first capacitor C1 stores and programs a voltage determined by voltage division with the second capacitor C2. That is, the first capacitor C1 and the second capacitor C2 sample the threshold voltage of the driving TFT DT in a source-follower manner. When the potentials of the first node N1 and the second node N2 change, the first capacitor C1 and the second capacitor C2 divide the voltage between the first node N1 and the second node N2. Store the potentials of each.

6 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 5 during a refresh period. For convenience of description, it will be described later with reference to FIG. 5 .

Referring to FIG. 6 , the refresh period Pr includes an initialization period p1 , a sampling period p2 , a programming period p3 , and an emission period p4 . The refresh period Pr may be set as the first horizontal period H1 . That is, the initialization period p1 , the sampling period p2 , the programming period p3 , and the light emission period p4 may be included in the first horizontal period H1 .

During the refresh period Pr, data is written to the pixels arranged in one horizontal line of the pixel array. Specifically, during the refresh period Pr, the threshold voltage of the driving TFT DT of the pixel circuit is sampled, and the data voltage Vdata is compensated for by the threshold voltage. Accordingly, the data voltage Vdata is compensated and written in the pixel so that the amount of current of the organic light emitting diode OD can be determined regardless of the threshold voltage.

First, when the initialization period p1 starts, the first scan signal SCAN1 and the second scan signal SCAN2 rise to a high state. At the same time, the light emission control signal EM is polled to be in a low state. Accordingly, during the initialization period p1 , the first switching TFT T1 and the second switching TFT T2 are turned on, and the third switching TFT T3 is turned off. Accordingly, the reference voltage Vref is supplied to the first node N1 from the data line by the first switching TFT T1 . In addition, the initialization voltage Vinit is supplied to the second node N2 from the initialization voltage Vinit line by the second switching TFT T2 . That is, as the initialization voltage Vinit is supplied to the second node N2 that is the source node of the driving TFT DT, the data voltage Vdata written in the organic light emitting diode OD is initialized.

During the sampling period p2 , the first scan signal SCAN1 maintains a high state and the second scan signal SCAN2 maintains a low state. At the moment the sampling period p2 starts, the emission control signal EM rises and maintains a high state during the sampling period p2 . Accordingly, during the sampling period p2 , the first switching TFT T1 and the third switching TFT T3 are turned on, and the second switching TFT T2 is turned off. Accordingly, the reference voltage Vref is supplied to the first node N1 through the turned-on first switching TFT T1 , and the high potential voltage VDD is applied to the driving TFT through the turned-on third switching TFT T3 . It is supplied to the drain node of (DT). That is, during the sampling period p2, the voltage of the first node N1 is maintained as the reference voltage Vref, and the voltage of the second node N2 is the drain-source current (hereinafter, Ids) of the driving TFT DT. ) is raised by Here, a gate-source voltage (hereinafter, referred to as Vgs) of the driving TFT DT is sampled as a threshold voltage of the driving TFT DT by a source-follower method. The threshold voltage Vth (sampling) of the driving TFT DT sampled as described above is stored in the first capacitor C1. Accordingly, during the sampling period p2 , the voltage of the first node N1 is the reference voltage Vref, and the voltage of the second node N2 is Vref-Vth(sampling).

During the programming period p3 , the first scan signal SCAN1 maintains a high state, and the second scan signal SCAN2 maintains a low state. At the moment the programming period p3 starts, the light emission control signal EM is polled and maintains a low state during the programming period p3. Accordingly, during the programming period p3, only the first switching TFT T1 is turned on, and the second switching TFT T2 and the third switching TFT T3 are turned off. Accordingly, the data voltage Vdata is supplied to the first node N1 through the turned-on first switching TFT T1 , and the drain node and the source node of the driving TFT DT float.

As the data voltage Vdata is supplied to the first node N1 during the programming period p3, the voltage change amount of the first node N1 is divided between the first capacitor C1 and the second capacitor C2, and , the voltage of the second node N2 is determined as a voltage-divided voltage value. Specifically, the voltage change amount of the first node N1 is Vdata-Vref, and due to voltage distribution between the first capacitor C1 and the second capacitor C2 connected in series, the second node during the programming period p3 The voltage change amount at (N2) is C1/(C1+C2)*(Vdata-Vref). That is, the voltage of the second node N2 is Vref-Vth(sampling) determined in the sampling period p2 and C1/(C1+C2)* which is the amount of voltage change at the second node N2 during the programming period p3 (Vdata-Vref) is added. In other words, in the programming period p3, the voltage of the second node N2 is (Vref-Vth(sampling))+C1/(C1+C2)*(Vdata-Vref), and Vgs of the driving TFT DT is It is programmed as (1- C1/(C1+C2))*(Vdata-Vref)+Vth(sampling).

During the emission period p4 , the first scan signal SCAN1 maintains a low state, and the second scan signal SCAN2 also maintains a low state. At the moment when the emission period p4 starts, the emission control signal EM rises and maintains a high state during the emission period p4 . Accordingly, during the emission period p4 , the first switching TFT T1 and the second switching TFT T2 are turned off, and the third switching TFT T3 is turned on. Accordingly, the high potential voltage VDD is supplied to the drain node of the driving TFT DT through the turned-on third switching TFT T3 , and Vds>Vgs>Vth becomes Vds>Vgs>Vth through the driving TFT DT. (OD) current flows. Specifically, during the light emitting period p4, the current Ioled flowing through the organic light emitting device OD is controlled by Vgs of the driving TFT DT, and the organic light emitting device OD emits light by Ioled to increase the luminance. do. As described above, the current Ioled flowing through the organic light emitting device OD during the light emitting period p4 is expressed by the following [Equation 1].

[Equation 1]

Here, k is a proportional constant reflecting various factors of the pixel circuit, and C'=C1/(C1+C2). Examining [Equation 1], since Vgs in [Equation 1] is (1-C')×(Vdata-Vref)+Vth(sampling), Vth is erased in Ioled's equation, and the organic light emitting diode (OD) The current Ioled flowing through the polarizer is not affected by the threshold voltage of the driving TFT DT.

7A and 7B are diagrams for explaining an initialization section, a sampling section, and a programming section included in the refresh section.

7A and 7B, the end points of the initialization section p1, the sampling section p2, and the programming section p3 in a typical organic light emitting diode display are shown with dotted lines, and in the organic light emitting diode display according to an embodiment of the present invention End points of the initialization section p1, the sampling section p2, and the programming section p3 are indicated by solid lines.

As described above, since the first horizontal period H1 may be controlled to be longer than the second horizontal period H2, the first horizontal period H1 may be controlled to be longer than the horizontal period in a general organic light emitting diode display. .

That is, in the organic light emitting diode display according to an embodiment of the present invention, the refresh period Pr itself may be lengthened.

Specifically, as shown in FIG. 7A , the initialization period p1 , the sampling period p2 , and the programming period p3 of the refresh period Pr may all be extended by a predetermined period, respectively.

In this way, by extending the initialization period p1, the data voltage Vdata written in the organic light emitting diode OD can be sufficiently initialized to the initialization voltage Vinit, and by extending the sampling period p2, the driving TFT ( By sufficiently sampling the threshold voltage of DT) to the first capacitor C1, as will be described later, a luminance increase phenomenon during low-speed driving can be prevented, and by extending the programming period p3, the data voltage Vdata is converted into organic light emission. It allows sufficient writing to the device OD.

As another method, as shown in FIG. 7B , only the sampling period p2 of the refresh period Pr may be extended by a predetermined period.

For this reason, as shown in FIG. 6 , the length of the sampling section p2 may be longer than the length of the programming section p3 .

Accordingly, as the length of the sampling period p2 is extended, the threshold voltage Vth(smpling) of the driving TFT DT sampled by a source-follower method is the actual threshold voltage Vth of the driving TFT DT. ) is lower than

According to [Equation 1], since the Vgs value of the driving TFT is (1-C')×(Vdata-Vref)+Vth(sampling), the value of Vth(sampling) decreases and the current ( Ioled) will decrease.

As an example, with reference to Table 1, the relationship of the decrease in luminance according to the extension of the length of the sampling section p2 will be described as follows.

[Table 1]

Specifically, when 63 grayscales are output to output 10 nits without extending the sampling period p2, the luminance is increased to 10.81 nits in the low-speed driving method and output.

Accordingly, when the sampling period p2 is extended by 0.2 μs, a luminance of 10.80 nits is output, and the luminance is reduced by 0.06% compared to the existing low-speed driving method. And, when the sampling section (p2) is extended by 0.3 μs, a luminance of 10.69 nits is output, and the luminance is reduced by 1.11% compared to the existing low-speed driving method. When the sampling section (p2) is extended by 0.4 μs, 10.58 nits is output, the luminance is reduced by 2.16% compared to the existing low-speed driving method, and when the sampling section (p2) is extended by 0.5 μs, a luminance of 10.46 nits is output, which increases the luminance by 3.21% compared to the existing low-speed driving method will be reduced

As described above, by extending the sampling period, the luminance of the organic light emitting diode can be reduced, and thus, it is possible to prevent a luminance increase during the low-speed driving due to the low-speed driving.

In order to solve the above problems, an organic light emitting diode display according to an embodiment of the present invention outputs a data voltage during a refresh period to a display panel including a plurality of pixels connected to a gate line and a data line, a data line, and , a data driver that outputs a reference voltage during a horizontal holding period, receives a first gate control signal during a refresh period, and receives a second gate control signal during a horizontal holding period, a first scan signal and a second scan signal on the gate line and a gate driver outputting a light emission control signal, wherein the control timing of the first gate control signal is slower than the control timing of the second gate control signal, thereby preventing a luminance increase caused by the low-speed driving.

According to another aspect of the present invention, a main clock signal of one frequency applied from an external host system is modulated into a plurality of control clock signals of a plurality of frequencies, and based on the plurality of control clock signals, a first gate control signal and A timing controller for outputting a second gate control signal is further included.

According to another aspect of the present invention, the timing controller includes a clock modulator configured to modulate the main clock signal to generate a first control clock signal having a first frequency and a second control clock signal having a second frequency higher than the first frequency. do.

According to another feature of the present invention, the pixel circuit arranged in the plurality of pixels is based on the voltage applied to the gate node and the source node, based on the driving TFT first scan signal for controlling the current flowing through the organic light emitting device, Based on a first switching TFT that applies a data voltage and a reference voltage to a gate node of the driving TFT, a second scan signal, a second switching TFT that applies an initialization voltage to a source node of the driving TFT, and a light emission control signal; and a third switching TFT for applying a high potential voltage to the drain node of the driving TFT.

According to another feature of the present invention, the pixel circuit further includes a first capacitor connected to the gate node and the source node of the driving TFT, and a second capacitor connected to the source node of the driving TFT and a voltage line to which a high potential voltage is applied. include

In order to solve the above problems, according to a method of driving an organic light emitting diode display according to an exemplary embodiment of the present invention, the control timing of the first gate control signal is slower than the control timing of the second gate control signal, so that the low-speed driving is performed. It is possible to prevent a luminance increase caused by this.

According to another feature of the present invention, the first gate control signal is output based on a first control clock signal of a first frequency, and the second gate control signal is outputted based on a second control clock signal of a second frequency higher than the first frequency. output based on

According to another feature of the present invention, one horizontal period of the horizontal holding period is shorter than one horizontal period of the refresh period.

According to another feature of the present invention, the refresh period includes an initialization period for applying an initialization voltage to the organic light emitting diode, a sampling period for sampling a threshold voltage of a driving TFT of the organic light emitting element, and a capacitor connected to the organic light emitting element. It includes a programming section to

According to another feature of the present invention, the length of the sampling section is the longest among the initialization section, the sampling section, and the programming section.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: organic light emitting display device
110: display panel
120: timing controller
130: gate driver
140: data driver
Vdata: data voltage
Vref: reference voltage
Scan: scan signal
EM: light emission control signal
P1: Initialization section
P2: sampling interval
P3: programming section
P4: luminous section

Claims (10)

a display panel including a plurality of pixels connected to a gate line and a data line;
a data driver outputting a data voltage to the data line during a refresh period and outputting a reference voltage during a horizontal holding period;
a gate driver configured to receive a first gate control signal during the refresh period and a second gate control signal during the horizontal holding period to output a first scan signal, a second scan signal, and a light emission control signal to the gate line including,
and a control timing of the first gate control signal is slower than a control timing of the second gate control signal.
According to claim 1,
modulates a main clock signal of one frequency applied from an external host system into a plurality of control clock signals of a plurality of frequencies;
and a timing controller configured to output the first gate control signal and the second gate control signal based on the plurality of control clock signals.
3. The method of claim 2,
The timing control
and a clock modulator configured to modulate the main clock signal to generate a first control clock signal having a first frequency and a second control clock signal having a second frequency higher than the first frequency.
According to claim 1,
A pixel circuit disposed in the plurality of pixels,
a driving TFT for controlling a current flowing through the organic light emitting device based on a voltage applied to the gate node and the source node;
a first switching TFT for applying the data voltage and the reference voltage to a gate node of the driving TFT based on the first scan signal;
a second switching TFT for applying an initialization voltage to a source node of the driving TFT based on the second scan signal; and
and a third switching TFT configured to apply a high potential voltage to a drain node of the driving TFT based on the light emission control signal.
5. The method of claim 4,
The pixel circuit is
a first capacitor connected to a gate node and a source node of the driving TFT; and
and a second capacitor connected to a source node of the driving TFT and a voltage line to which the high potential voltage is applied.
Split driving into refresh section and horizontal holding section,
a driving TFT for controlling a current flowing through the organic light emitting device based on a voltage applied to the gate node and the source node;
a first switching TFT for applying a data voltage and a reference voltage to a gate node of the driving TFT based on a first scan signal;
a second switching TFT for applying an initialization voltage to a source node of the driving TFT based on a second scan signal; and
a display panel including a plurality of pixels each including a third switching TFT for applying a high potential voltage to a drain node of the driving TFT based on a light emission control signal;
A gate receiving a first gate control signal during the refresh period and receiving a second gate control signal during the horizontal holding period to output the first scan signal, the second scan signal, and the emission control signal to a gate line A method of driving an organic light emitting diode display including a driving unit, the method comprising:
and a control timing of the first gate control signal is slower than a control timing of the second gate control signal.
7. The method of claim 6,
the first gate control signal is output based on a first control clock signal of a first frequency, and the second gate control signal is output based on a second control clock signal of a second frequency higher than the first frequency; A method of driving an organic light emitting diode display.
7. The method of claim 6,
One horizontal period of the horizontal holding period is shorter than one horizontal period of the refresh period.
7. The method of claim 6,
The refresh period includes an initialization period for applying the initialization voltage to the organic light emitting element, a sampling period for sampling a threshold voltage of the driving TFT of the organic light emitting element, and programming for storing the data voltage in a capacitor connected to the organic light emitting element A method of driving an organic light emitting diode display including a section.
10. The method of claim 9,
The method of claim 1 , wherein the sampling period has the longest length among the initialization period, the sampling period, and the programming period.

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