KR102470085B1 - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device, and more particularly, to an organic light emitting display device capable of reducing flicker. The present invention relates to a display panel having a plurality of pixels connected to a gate line and a data line, a gate driver outputting a scan signal and an emission control signal to the gate line, receiving image data, and outputting a data voltage to the data line during a refresh period. and a data driver outputting a reference voltage during the horizontal holding period. In the horizontal holding period, the emission control signal polls from a high state to a low state at least once, so that a flicker phenomenon in driving with a low driving frequency may be reduced.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present invention relates to an organic light emitting display device, and more particularly, to an organic light emitting display device capable of reducing flicker.

Recently, as we enter the information age, the display field that visually expresses electrical information signals has developed rapidly. is being developed.

Specific examples of such a display device include a liquid crystal display device (LCD), a field emission display device (FED), and an organic light emitting display device (OLED). have.

Each of the plurality of pixels constituting the organic light emitting display device includes an organic light emitting element composed of an organic light emitting layer between an anode and a cathode, and a pixel circuit independently driving the organic light emitting element. The pixel circuit includes a switching thin film transistor (hereinafter referred to as TFT), a driving TFT, and a capacitor. Here, the switching TFT charges the capacitor with the data voltage in response to the scan pulse, and the driving TFT controls the amount of current supplied to the organic light emitting diode according to the data voltage charged in the capacitor to adjust the amount of light emitted from the organic light emitting diode.

An organic light emitting display device is a self-emissive display device and, unlike a liquid crystal display device, does not require a separate light source, and thus can be manufactured to be lightweight and thin. In addition, organic light emitting display devices are not only advantageous in terms of power consumption due to low voltage driving, but also excellent in color implementation, response speed, viewing angle, and contrast ratio (CR), and are being studied as next-generation display devices in various fields. In addition, since the organic light emitting device has a surface light emitting structure, it is easy to implement a flexible form.

In the organic light emitting diode display having the above advantages, differences in characteristics such as the threshold voltage (Vth) and mobility of the driving TFT occur for each pixel due to process variation, and a voltage drop of the high potential voltage (VDD) occurs. As the amount of current driving the organic light emitting device is changed, a luminance deviation occurs between pixels. In general, there is a problem that unintended stains or patterns are generated on the screen due to the difference in characteristics of the initial driving TFT, and the difference in characteristics due to deterioration of the driving TFT that occurs while driving the organic light emitting device is the lifespan of the organic light emitting display panel. There is a problem of reducing or generating an afterimage. Accordingly, attempts are being made to improve image quality by reducing luminance deviation between pixels by introducing a compensation circuit that compensates for the characteristic deviation of the driving TFT and compensates for the voltage drop of the high potential voltage (VDD).

Accordingly, an attempt has been made to reduce power consumption of the organic light emitting display device by variously changing the driving method of the organic light emitting display device. In one of these driving methods, the driving frequency of the organic light emitting display device is reduced from the basic driving frequency, and the period for horizontally holding the light emitting state is controlled to be long.

However, as the organic light emitting diode display is driven at a low driving frequency and the horizontally holding period of the light emitting state is controlled to be long, the luminance may decrease during a period in which a scan signal is applied or a period in which a horizontal holding period is applied. This decrease in luminance may also cause a flicker phenomenon, which is recognized by the human eye and flickers.

Accordingly, there is a need for a method capable of reducing a flicker phenomenon while driving an organic light emitting display device at a low driving frequency in order to reduce power consumption.

The inventors of the present invention have recognized that when the organic light emitting display is driven at a low speed, a phenomenon in which luminance is reduced during a refresh period can be suppressed by an internal compensation circuit or an external voltage compensation method for each pixel of the organic light emitting display. . Accordingly, the present inventors have invented an organic light emitting display device capable of reducing flicker while reducing power consumption of the organic light emitting display device.

Accordingly, an object to be solved by the present invention is to provide an organic light emitting display device that maintains an emission control signal in a low state for a certain period of time even in a horizontal holding period in which data is not written during low-speed driving.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, an organic light emitting display device according to an exemplary embodiment of the present invention includes a display panel having a plurality of pixels connected to gate lines and data lines, and outputting scan signals and emission control signals to the gate lines. It includes a gate driver and a data driver that receives image data, outputs a data voltage to the data line during a refresh period, and outputs a reference voltage during a horizontal holding period. In the horizontal holding period, the emission control signal polls from a high state to a low state at least once, so that a flicker phenomenon in driving with a low driving frequency may be reduced.

Other embodiment specifics are included in the detailed description and drawings.

The organic light emitting display device according to an embodiment of the present invention maintains the emission control signal in a low state for a certain period of time even in a horizontal holding period, outputs an average luminance corresponding to a predicted luminance value based on image data, and simultaneously uses a low driving frequency. The flicker phenomenon in furnace driving can also be reduced.

Effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a schematic block diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.
2 is a waveform diagram illustrating a gate signal according to a low-speed driving mode of an organic light emitting diode display according to an exemplary embodiment of the present invention.
3 is a circuit diagram illustrating a 4T2C pixel circuit included in an organic light emitting display device according to an exemplary embodiment of the present invention.
FIG. 4 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 3 and corresponding luminance during a refresh period.
FIG. 5 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 3 and corresponding luminance during a horizontal holding period.
6A and 6B are graphs showing the luminance of the organic light emitting device of the organic light emitting diode display according to the present invention according to a refresh period and a horizontal holding period.
7 is a circuit diagram illustrating a 6T1C pixel circuit included in an organic light emitting display device according to another exemplary embodiment of the present invention.
FIG. 8 is a waveform diagram illustrating signals input to the pixel circuit shown in FIG. 7 during a refresh period and luminance accordingly.
FIG. 9 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 7 and corresponding luminance during a horizontal holding period.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

When an element or layer is referred to as “on” another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

In the present invention, the TFT may be of the P type or the N type, and in the following embodiments, the TFT is configured of the N type for convenience of description. Also, in describing the pulse type signal, the gate high voltage (VGH) state is defined as a “high state” and the gate low voltage (VGL) state is defined as a “low state”.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , the organic light emitting display device 100 includes a display panel 110 including a plurality of pixels P connected to a gate line GL and a data line DL, and gates on each of the gate lines GL. It includes a gate driver 130 supplying a signal, a data driver 140 supplying a data signal to each of the data lines DL, and a timing controller 120 controlling the gate driver 130 and the data driver 140. .

The timing controller 120 processes image data (RGB) input from the outside to suit the size and resolution of the display panel 110 and supplies it to the data driver 140 . The timing controller 120 receives synchronizing signals SYNC input from the outside, for example, a dot clock signal DCLK, a data enable signal DE, a horizontal synchronizing signal Hsync, and a vertical synchronizing signal Vsync. to generate a plurality of gate and data control signals (GCS, DCS). The gate driver 130 and the data driver 140 are controlled by supplying the generated gate and data control signals GCS and DCS to the gate driver 130 and the data driver 140, respectively.

The gate driver 130 supplies a gate signal to the gate line GL according to the gate control signal GCS supplied from the timing controller 120 . Here, the gate signal includes at least one scan signal SCAN and an emission control signal EM. In FIG. 1 , the gate drivers 130 are illustrated as being spaced apart from one side of the display panel 110 , but the number and position of the gate drivers 130 are not limited thereto. That is, the gate driver 130 may be disposed on one side or both sides of the display panel 110 in a Gate In Panel (GIP) method.

The data driver 140 converts the image data RGB to data voltage Vdata according to the data control signal DCS supplied from the timing controller 120, and converts the converted data voltage Vdata to the data line DL. is supplied to the pixel P through

In the display panel 110, the plurality of gate lines GL and the plurality of data lines DL cross each other, and each of the plurality of pixels P is connected to the gate line GL and the data line DL. Specifically, one pixel P receives a gate signal from the gate driver 130 through the gate line GL, receives a data signal from the data driver 140 through the data line DL, and supplies power. Various power is supplied through the line. Specifically, one pixel (P) receives at least one scan signal (SCAN) and emission control signal (EM) through the gate line (GL), and receives the data voltage (Vdata) or reference through the data line (DL). It receives the voltage Vref, and receives a high potential voltage VDD, a low potential voltage VSS, and an initialization voltage Vinit through a power supply line.

Also, each of the pixels P includes an organic light emitting element and a pixel circuit that controls driving of the organic light emitting element. Here, the organic light emitting element is composed of an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The pixel circuit includes a switching TFT, a driving TFT and a capacitor. Specifically, in the pixel circuit, the driving TFT controls the amount of light emitted from the organic light emitting element by controlling the amount of current supplied to the organic light emitting element according to the data voltage charged in the capacitor, and the switching TFT controls the scan signal supplied through the gate line GL. (SCAN) is received and the data voltage (Vdata) is charged in the capacitor.

As described above, the organic light emitting display device 100 includes a driving TFT and a switching TFT in a pixel circuit, and active layers constituting the driving TFT and the switching TFT may be made of different materials. As such, since the driving TFT and the switching TFT are each composed of TFTs having different characteristics in one pixel circuit, the organic light emitting display device 100 may include multi-type TFTs.

Specifically, in the organic light emitting display device 100 including multi-type TFTs, LTPS TFTs using low temperature poly-silicon (hereinafter referred to as LTPS) are used as TFTs using polycrystalline semiconductor materials as active layers. do. Since polysilicon material has high mobility (more than 100 cm 2 /Vs), low energy consumption and excellent reliability, it is applied to the gate driver 130 for driving elements and/or multiplexer (MUX) that drives TFTs for display elements. can do. Alternatively, it is preferable to apply the driving TFT in the pixel P in the organic light emitting display device 100 .

Also, in the organic light emitting display device 100 including multi-type TFTs, an oxide semiconductor TFT using an oxide semiconductor material as an active layer is used. Since the oxide semiconductor material has a low off-current, it is suitable for a switching TFT having a short turn-on time and a long turn-off time.

In particular, the organic light emitting display device 100 including multi-type TFTs according to an embodiment of the present invention includes a pixel circuit in which a switching TFT is made of an oxide semiconductor TFT and a driving TFT is made of an LTPS TFT. However, in the organic light emitting diode display 100 of the present invention, the switching TFT is not limited to the oxide semiconductor TFT and the driving TFT to the LTPS TFT, and multi-type TFTs may be configured in various ways. Also, in the organic light emitting display device 100 of the present invention, the pixel circuit may include one type of TFT instead of multiple types of TFTs.

The organic light emitting display device 100 can be driven while varying the driving frequency. Specifically, in the organic light emitting display device 100, the timing controller 120 may adjust the driving method of the organic light emitting display device 100 by adjusting a frame rate through a refresh rate control signal. have. For example, the organic light emitting display device 100 may be driven at a higher or lower refresh rate than the reference refresh rate. In particular, driving the organic light emitting display device 100 lower than the reference refresh rate is referred to as 'low speed driving' (also referred to as 'low refresh rate driving'), and driving the organic light emitting display device 100 higher than the reference refresh rate ( 100) is called 'high-speed driving'.

Here, the low-speed driving means driving at a refresh rate lower than the reference refresh rate of 60 Hz, which drives the organic light emitting display device 100 to output fewer than 60 frames per second. means that That is, when the refresh rate is 60 Hz, 60 frames are driven for one second, and driving at a refresh rate lower than 60 Hz is referred to as low-speed driving. For example, the low-speed driving may have a refresh rate of 1Hz, and the 1Hz low-speed driving may output only one frame for 1 second.

Hereinafter, referring to FIG. 2 , low-speed driving in the organic light emitting diode display will be described in detail.

2 is a waveform diagram illustrating a gate signal according to a low-speed driving mode of an organic light emitting diode display according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , in order to reduce power consumption of the organic light emitting diode display, in the low-speed driving mode, the horizontal holding period Ph is controlled to be long and the refresh period Pr is controlled to be short during unit time. Here, the horizontal holding period Ph is a period in which the organic light emitting elements emit light even when the data voltage Vdata is not supplied and the reference voltage Vref is applied through the data lines DL connected to each of the organic light emitting elements. The refresh period (Pr) is an initialization period for applying the initialization voltage (Vini) to the organic light emitting diode so that the organic light emitting diode can emit light during the horizontal holding period (Ph), sampling the threshold voltage (Vth) of the organic light emitting diode's driving TFT. Alternatively, a sampling period for sensing and a programming period for storing the data voltage Vdata in a capacitor connected to the organic light emitting element are included.

For example, in the low-speed drive mode, the refresh period Pr may be maintained for 16.6 milliseconds (hereinafter referred to as msec) and the horizontal holding period Ph may be maintained for 983.4 msec during 1 second.

Referring to FIG. 2 , the gate signal is sequentially shifted to each of the gate lines GL and supplied to the pixel P during the refresh period Pr. Specifically, the gate signal is sequentially shifted and supplied from the first gate line GL1 to the nth gate line GLn during the refresh period Pr. Here, n means the total number of gate lines in the organic light emitting diode display.

Accordingly, the light is emitted during the horizontal holding period Ph by the data voltage sampled and programmed in the refresh period Pr.

Hereinafter, operations of the pixel circuit in the refresh period and the horizontal holding period when the organic light emitting display device according to an exemplary embodiment includes the 4T2C pixel circuit will be described in detail.

3 is a circuit diagram illustrating a 4T2C pixel circuit included in an organic light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , the pixel circuit includes a driving TFT (DT), three switching TFTs (T1, T2, T3) and two capacitors (C1, C2).

The driving TFT (DT) includes a gate node that is a first node (N1) connected to the first switching TFT (T1), a source node that is a second node (N2) connected to the second switching TFT (T2), and a third switching TFT (T3 ) and a third node N3 connected to the drain node.

Specifically, the gate node of the driving TFT DT is electrically connected to a data line supplying the data voltage Vdata or the reference voltage Vref. Accordingly, the gate node of the driving TFT (DT) is connected to the source node of the first switching TFT (T1) to receive the data voltage (Vdata) or the reference voltage (Vref). A drain node of the driving TFT (DT) is electrically connected to the high potential voltage (VDD) line. Accordingly, the drain node of the driving TFT (DT) is connected to the source node of the third switching TFT (T3) to receive the high potential voltage (VDD). A source node of the driving TFT DT is electrically connected to the organic light emitting diode OLED and the organic light emitting diode OD. Specifically, the source node of the driving TFT (DT) is connected to the anode of the organic light emitting diode (OLED) OD, and is connected to the source node of the second switching TFT (T2).

Accordingly, when the third switching TFT (T3) is turned on by the light emission control signal (EM) and the driving TFT (DT) is also turned on, the driving TFT (DT) is turned on based on the voltage applied to the gate node and the source node. The luminance of the organic light emitting diode (OLED) is controlled by controlling the amount of current flowing through the organic light emitting diode (OD).

The first switching TFT T1 includes a gate node connected to the first scan signal SCAN1 line, a drain node connected to the data line, and a source node, which is the first node N1 connected to the driving TFT DT. Specifically, the gate node of the first switching TFT T1 is connected to the first scan signal SCAN1 line and turned on or off by the first scan signal SCAN1. The drain node of the first switching TFT (T1) is connected to the data line to transfer the data voltage (Vdata) or the reference voltage (Vref) to the gate node of the driving TFT (DT). The source node of the first switching TFT (T1) is connected to the gate node of the driving TFT (DT).

Accordingly, when the first scan signal SCAN1 is in a high state, the first switching TFT T1 is turned on to supply the data voltage Vdata or the reference voltage Vref to the gate node of the driving TFT DT. .

The second switching TFT T2 includes a gate node connected to the second scan signal SCAN2 line, a drain node connected to the initialization voltage Vinit line, and a source node connected to the source node of the driving TFT DT. Specifically, when the second scan signal SCAN2 of the gate node of the second switching TFT T2 is in a high state, the second switching TFT T2 is turned on. The second switching TFT (T2) supplies the initialization voltage (Vinit) to the second node (N2). The source node of the second switching TFT T2 is directly connected to the second node N2 connected to the source node of the driving TFT DT and the anode of the OLED OD.

Accordingly, when the second scan signal SCAN2 is in a high state, the second switching TFT T2 is turned on and supplies the initialization voltage Vinit to the second node N2 so that the organic light emitting diode OLED The data voltage Vdata written to the light emitting device OD is initialized.

The third switching TFT (T3) includes a gate node connected to the emission control signal (EM) line, a drain node connected to the high potential voltage (VDD) line, and a source node connected to the drain node of the driving TFT (DT). Specifically, the gate node of the third switching TFT (T3) is connected to the emission control signal (EM) line, so that the third switching TFT (T3) is turned on when the emission control signal (EM) is in a high state. A drain node of the third switching TFT (T3) is directly connected to the high potential voltage (VDD) line.

Accordingly, when the emission control signal EM is in a high state, the third switching TFT T3 is turned on to supply the high potential voltage VDD to the drain node of the driving TFT DT, A current amount of the organic light emitting diode (OLED) organic light emitting diode (OD) is controlled by the data voltage (Vdata).

The two capacitors may be storage capacitors that store voltages applied to the gate node or source node of the driving TFT (DT). Also, two capacitors are connected in series at the source node of the driving TFT (DT).

Specifically, the first capacitor C1 is electrically connected to a first node N1 that is a gate node of the driving TFT DT and a second node N2 that is a source node of the driving TFT DT. Accordingly, the first capacitor C1 stores a voltage equal to the difference between the voltages applied to the first node N1 and the second node N2. The second capacitor C2 is electrically connected to the second node N2 that is the source node of the driving TFT DT and the high potential voltage VDD line. Also, the second capacitor C2 is connected in series with the first capacitor C1 at the second node N2. Accordingly, the second capacitor C2 stores the voltage by voltage division together with the first capacitor C1.

For example, the first capacitor C1 stores and samples the threshold voltage of the driving TFT DT as a voltage difference between the first node N1 and the second node N2. Also, when the data voltage Vdata is applied, the first capacitor C1 stores and programs a voltage determined by voltage division with the second capacitor C2. That is, the first capacitor C1 and the second capacitor C2 sample the threshold voltage of the driving TFT DT in a source-follower method. When the potentials of the first node N1 and the second node N2 change, the first and second capacitors C1 and C2 are connected to the first node N1 and the second node N2 through voltage division. Store the potential of each. Sampling and programming of the first capacitor C1 will be described later with reference to FIG. 4 .

FIG. 4 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 3 and corresponding luminance during a refresh period. For convenience of explanation, it will be described later with reference to FIG. 3 .

Referring to FIG. 4 , the refresh period Pr includes an initialization period t1, a sampling period t2, a programming period t3 and an emission period t4. The refresh period Pr may be set to approximately 1 horizontal period 1H, and in some embodiments, the emission period t4 may not be included in 1 horizontal period 1H. During the refresh period Pr, data is written to pixels arranged on one horizontal line of the pixel array. Specifically, the threshold voltage of the driving TFT (DT) of the pixel circuit is sampled during the refresh period Pr, and the data voltage Vdata is compensated by the threshold voltage. Accordingly, the data voltage Vdata is compensated and written to the pixel so that the amount of current of the organic light emitting diode (OLED) OD can be determined regardless of the threshold voltage. 4 shows that each of the initialization period t1, the sampling period t2, the programming period t3, and the emission period t4 are maintained for the same time, but the initialization period t1, the sampling period t2, and the programming period t2. The time of each of the period t3 and the emission period t4 may be variously changed according to the embodiment.

First, as soon as the initialization period t1 starts, the first scan signal SCAN1 and the second scan signal SCAN2 rise and become high. At the same time, the emission control signal EM is polled and becomes low. Accordingly, during the initialization period t1, the first switching TFT T1 and the second switching TFT T2 are turned on, and the third switching TFT T3 is turned off. Accordingly, the reference voltage Vref is supplied from the data line to the first node N1 by the first switching TFT T1. Also, the initialization voltage Vinit is supplied from the initialization voltage Vinit line to the second node N2 by the second switching TFT T2. That is, as the initialization voltage Vinit is supplied to the second node N2 which is the source node of the driving TFT DT, the data voltage Vdata written in the organic light emitting diode OD of the organic light emitting diode OLED is initialized. do. Further, as the emission control signal EM is polled and maintained in a low state, and the third switching TFT T3 is turned off, a current flowing through the organic light emitting device OLED and the organic light emitting device OD (hereinafter referred to as Ioled) is blocked, so the luminance of the organic light emitting diode (OLED) organic light emitting diode (OD) is reduced.

During the sampling period t2, the first scan signal SCAN1 is maintained in a high state, and the second scan signal SCAN2 is switched to a low state. As soon as the sampling period t2 starts, the emission control signal EM rises and maintains a high state during the sampling period t2. Accordingly, during the sampling period t2, the first switching TFT T1 and the third switching TFT T3 are turned on, and the second switching TFT T2 is turned off. Accordingly, the reference voltage Vref is supplied to the first node N1 through the turned-on first switching TFT T1, and the high potential voltage VDD is supplied to the driving TFT through the turned-on third switching TFT T3. is supplied to the drain node of (DT). That is, during the sampling period t2, the voltage of the first node N1 is maintained as the reference voltage Vref, and the voltage of the second node N2 is the drain-to-source current of the driving TFT DT (hereinafter, Ids called) rises by Here, the gate-to-source voltage (hereinafter referred to as Vgs) of the driving TFT (DT) is sampled as the threshold voltage of the driving TFT (DT) by a source-follower method. The threshold voltage of the driving TFT DT sampled in this way is stored in the first capacitor C1. Accordingly, during the sampling period t2, the voltage of the first node N1 is the reference voltage Vref, and the voltage of the second node N2 is Vref-Vth.

During the programming period t3, the first scan signal SCAN1 maintains a high state and the second scan signal SCAN2 maintains a low state. As soon as the programming period t3 starts, the emission control signal EM is polled and maintained in a low state during the programming period t3. Thus, during the programming period t3, only the first switching TFT (T1) is turned on, and the second switching TFT (T2) and the third switching TFT (T3) are turned off. Accordingly, the data voltage Vdata is supplied to the first node N1 through the turned-on first switching TFT T1, and the drain node and the source node of the driving TFT DT are floated.

As the data voltage Vdata is supplied to the first node N1 during the programming period t3, the voltage variation of the first node N1 is voltage-divided between the first capacitor C1 and the second capacitor C2. , the voltage of the second node N2 is determined as a voltage divided voltage value. Specifically, the amount of change in voltage of the first node N1 is Vdata-Vref, and due to voltage distribution between the first capacitor C1 and the second capacitor C2 connected in series, the second node during the programming period t3. The amount of change in voltage at (N2) is C1/(C1+C2)*(Vdata-Vref). That is, the voltage of the second node N2 is C1/(C1+C2)*(Vdata- Vref). In other words, in the programming period t3, the voltage of the second node N2 is (Vref-Vth)+C1/(C1+C2)*(Vdata-Vref), and the Vgs of the driving TFT (DT) is (1- It is programmed as C1/(C1+C2))*(Vdata-Vref)+Vth. Further, as the emission control signal EM is polled and maintained in a low state, and the third switching TFT T3 is turned off, the current Ioled flowing through the organic light emitting device OLED and the organic light emitting device OD is blocked. Organic Light-Emitting Device (OLED) The luminance of the organic light-emitting device (OD) is reduced.

During the emission period t4, the first scan signal SCAN1 is in a low state, and the second scan signal SCAN2 is also maintained in a low state. As soon as the emission period t4 starts, the emission control signal EM rises and maintains a high state during the emission period t4. Accordingly, during the light emission period t4, the first switching TFT T1 and the second switching TFT T2 are turned off, and the third switching TFT T3 is turned on. Accordingly, the high potential voltage VDD is supplied to the drain node of the driving TFT (DT) through the turned-on third switching TFT (T3), and Vds>Vgs>Vth becomes the organic light emitting element through the driving TFT (DT). Current flows through the (OLED) organic light emitting device (OD). Specifically, during the light emission period t4, the current Ioled flowing through the organic light emitting device OD is controlled by Vgs of the driving TFT DT, and the organic light emitting device OLED is controlled by Ioled. The light emitting element OD emits light, so that luminance increases. In this way, the current Ioled flowing through the organic light emitting diode OLED and the organic light emitting diode OD during the light emitting period t4 is as follows [Equation 1].

[Equation 1]

Here, k is a proportional constant in which various factors of the pixel circuit are reflected, and C'=C1/(C1+C2). Looking at [Equation 1], Vth is eliminated in [Equation 1], and the current Ioled flowing through the organic light emitting diode (OLED) organic light emitting diode (OD) is affected by the threshold voltage of the driving TFT (DT). do not receive

FIG. 5 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 3 and corresponding luminance during a horizontal holding period. For convenience of description, it will be described later with reference to FIG. 3 based on one horizontal period.

As shown in FIG. 5, during the horizontal holding period Ph, the first scan signal SCAN1 is in a low state, the second scan signal SCAN2 also maintains a low state, and the data line has a reference voltage (Vref ) is authorized. Accordingly, the first switching TFT (T1) and the second switching TFT (T2) are turned off during the horizontal holding period (Ph).

In the horizontal holding period Ph, the emission control signal EM polls from the high state to the low state at least once, and is maintained in the low state for a predetermined time.

As the light emitting control signal EM is polled and maintained in a low state, the third switching TFT T3 is turned off, so that the current Ioled flowing through the organic light emitting diode OLED and the organic light emitting diode OD is blocked. Organic Light-Emitting Device (OLED) The luminance of the organic light-emitting device (OD) is reduced.

Here, the gate driver 130 adjusts the time for which the emission control signal EM is maintained in a low state during the horizontal holding period Ph based on the image data RGB.

Specifically, as shown in Table 1, as the predicted luminance value calculated based on the image data RGB increases, the time during which the emission control signal EM is maintained in a low state during the horizontal holding period Ph is reduced.

[Table 1]

For example, when the predicted luminance value based on the image data RGB is 1 nit, the emission control signal EM is maintained in a low state for a total of 60 horizontal periods, and the larger the predicted luminance value, the lower the emission control signal EM becomes. The time maintained in the state is gradually decreased, and when the predicted luminance value is 300 nits, the emission control signal EM is maintained in the low state for a total of 6 horizontal periods.

6A and 6B are graphs showing the luminance of the organic light emitting device of the organic light emitting diode display according to the present invention according to a refresh period and a horizontal holding period.

Specifically, in FIG. 6A, the predicted luminance value is relatively high, showing the luminance when the emission control signal EM is maintained in a low state for a relatively short time. In contrast, in FIG. 6B, the predicted luminance value is relatively low, It shows the luminance when the emission control signal EM is maintained in a low state for a relatively long time.

In FIG. 6A , when the time for which the light emitting control signal EM is maintained in a low state is short, the amount of decrease in luminance of the organic light emitting diode (OLED) or the organic light emitting diode (OD) is relatively small. Accordingly, the average luminance of the organic light emitting diode (OLED) organic light emitting diode (OD) is relatively high. That is, the time during which the emission control signal EM is maintained in a low state is set to be short so that the average luminance of the organic light emitting diode (OLED) OD increases as the predicted luminance value based on the image data RGB increases. can

Contrary to this, in FIG. 6B , when the time for which the emission control signal EM is maintained in a low state is long, the decrease in luminance of the organic light emitting diode (OLED) or the organic light emitting diode (OD) is relatively large. Accordingly, the average luminance of the organic light emitting diode (OLED) organic light emitting diode (OD) is relatively low. That is, the time during which the emission control signal EM is maintained in a low state may be set longer so that the average luminance of the organic light emitting diode (OLED) OD decreases as the predicted luminance value based on the image data RGB decreases. can

In this way, the organic light emitting diode display device according to an embodiment of the present invention maintains the light emission control signal in a low state for a certain period of time even in the horizontal holding period, outputs an average luminance corresponding to a predicted luminance value based on image data, and simultaneously operates at a low level. The flicker phenomenon in driving with frequency can also be reduced.

7 is a circuit diagram illustrating a 6T1C pixel circuit included in an organic light emitting display device according to another exemplary embodiment of the present invention.

Referring to FIG. 7 , the pixel circuit includes a driving TFT (DT), five switching TFTs, and one capacitor.

The driving TFT (DT) has a gate node connected to one node of the capacitor, a drain node electrically connected to the second switching TFT (T2) and the third switching TFT (T3), and the first switching TFT (T1) and the fourth switching TFT ( T4) and a source node electrically connected.

Specifically, the gate node of the driving TFT (DT) stores the high potential voltage (VDD) when the second switching TFT (T2) and the third switching TFT (T3) are turned on. When the data voltage Vdata is supplied while the second switching TFT T2 is turned on, the data voltage Vdata is written to the gate node of the driving TFT DT by the source follower method. The driving TFT (DT) supplies driving current to the organic light emitting diode (OD) according to the emission control signal (EM), and adjusts the luminance of the organic light emitting diode (OLED) OD according to the amount of current. Control.

The first switching TFT T1 includes a gate node connected to the second scan signal SCAN2 line, a drain node connected to the data line, and a source node connected to the source node of the driving TFT DT. Accordingly, the first switching TFT (T1) is turned on or off by the second scan signal (SCAN2). That is, when the second scan signal SCAN2 is supplied in a high state to the gate node of the first switching TFT T1, the data voltage Vdata from the drain node of the first switching TFT T1 is applied to the driving TFT DT. It is supplied to the third node N3 as a source node.

The second switching TFT (T2) has a gate node connected to the first scan signal (SCAN1) line, a drain node connected to the drain node of the driving TFT (DT) and a source node of the third switching TFT (T3), and a driving TFT (DT). Includes a source node connected to the gate node of Accordingly, the second switching TFT T2 may be turned on by the first scan signal SCAN1. That is, when the first scan signal SCAN1 is in a high state, the second switching TFT T2 is turned on. Thus, the second switching TFT T2 transfers the voltage at the first node N1, which is the drain node of the driving TFT (DT), to the voltage at the second node N2, which is the gate node of the driving TFT (DT).

Accordingly, when the first scan signal SCAN1 is in a high state, the second switching TFT T2 transmits the high potential voltage VDD of the first node N1 or the sampled voltage of the driving TFT DT to the second switching TFT T2. It is supplied to the node N2 to initialize the data voltage Vdata written in the organic light emitting diode OLED or the organic light emitting diode OD, or to write the data voltage Vdata and set the threshold voltage of the driving TFT DT. sample

The third switching TFT (T3) includes a gate node connected to the nth emission control signal (EM[n]) line, a drain node connected to the high potential voltage (VDD) line, and a source node connected to the drain node of the driving TFT (DT). include Accordingly, the third switching TFT T3 may be turned on by the nth emission control signal EM[n]. That is, when the n th emission control signal EM[n] is in a high state, the third switching TFT T3 is turned on and applies the high potential voltage VDD from the source node to the drain node of the driving TFT DT. supplied to the first node N1.

Accordingly, when the emission control signal is in a high state, the third switching TFT (T3) supplies the high potential voltage (VDD) to the drain node of the driving TFT (DT). Accordingly, the driving TFT (DT) of the third switching TFT (T3) controls the amount of current of the organic light emitting diode (OLED) and the organic light emitting diode (OD) according to the data voltage (Vdata).

The fourth switching TFT (T4) has a gate node connected to the n−1 th light emitting control signal (EM[n−1]) line, a drain node connected to the source node of the driving TFT (DT), and an organic light emitting device (OLED). It includes a source node electrically connected to the device OD. Accordingly, the fourth switching TFT T4 may be turned on by the n−1 th emission control signal EM[n−1]. That is, when the n−1 th light emission control signal EM[n−1] is in a high state, the fourth switching TFT T4 is turned on, and the third node N3, which is the source node of the driving TFT DT, and a fourth node N4 which is a source node of the fourth switching TFT T4 is connected.

Accordingly, when the fourth switching TFT T4 is turned on by the n−1 th emission control signal EM[n−1], the voltage of the third node N3 is supplied to the fourth node N4. . When the fourth switching TFT (T4), the driving TFT (DT) and the third switching TFT (T3) are turned on, the high potential voltage (VDD) is supplied to the driving TFT (DT), and the organic light emitting diode (OLED) emits light. A driving current is supplied to the device OD so that the organic light emitting device OLED emits light.

The fifth switching TFT (T5) is a gate node connected to the first scan signal (SCAN1) line, a drain node connected to the initialization voltage (Vinit) line, and a fourth node that is an anode of the organic light emitting diode (OLED) OD. Contains the source node connected to (N4). Accordingly, the fifth switching TFT T5 may be turned on by the first scan signal SCAN1. That is, when the first scan signal SCAN1 is in a high state, the fifth switching TFT T5 is turned on and supplies the initialization voltage Vinit to the fourth node N4.

Accordingly, when the fifth switching TFT (T5) is turned on by the first scan signal (SCAN1), the initialization voltage (Vinit) is supplied to the fourth node (N4), so that the organic light emitting diode (OLED) organic light emitting diode ( The data voltage Vdata written to OD is initialized.

The capacitor may be a storage capacitor Cst that stores a voltage applied to a gate node of the driving TFT DT. Here, the capacitor is disposed between the second node N2 which is the gate node of the driving TFT DT and the fourth node N4 electrically connected to the anode of the organic light emitting diode OD. That is, the capacitor is electrically connected to the second node N2 and the fourth node N4 so that the voltage of the gate node of the driving TFT DT and the anode of the organic light emitting diode OLED are supplied. Store the difference in voltage.

FIG. 8 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 7 and corresponding luminance during a refresh period. For convenience of explanation, it will be described later with reference to FIG. 3 .

Referring to FIG. 8 , the data voltage is applied to each of the pixels disposed on one horizontal line through an initialization period t1, a sampling period t2, a voltage horizontal holding period t3, a connection period t4, and an emission period t5. (Vdata) is written, and each pixel emits light. 8 shows that each of the initialization period t1, sampling period t2, voltage horizontal holding period t3, connection period t4, and emission period t5 is maintained for the same time, but the initialization period t1 , The time of each of the sampling period t2, the voltage horizontal holding period t3, the connection period t4, and the emission period t5 may be variously changed according to the embodiment. For example, the voltage horizontal holding period t3 may be shorter than the other periods.

First, as soon as the initialization period t1 starts, the first scan signal SCAN1 rises to a high state, and the second scan signal SCAN2 maintains a low state. At the same time, the n−1 th emission control signal EM[n−1] also maintains a low state, and the n th emission control signal EM[n] is polled from a high state during the initialization period t1 to a low state. do. Accordingly, during the initialization period t1, the second switching TFT T2 and the fifth switching TFT T5 are turned on, and the first switching TFT T1 and the fourth switching TFT T4 are turned off. In addition, the third switching TFT (T3) is turned on only during a period in which the nth light emission control signal EM[n] is in a high state, and turns while the nth light emission control signal EM[n] is converted to a low state. goes off Accordingly, the initialization voltage Vinit is supplied to the fourth node N4 through the fifth switching TFT T5 and the high potential voltage VDD is applied to the second switching TFT T3 while the third switching TFT T3 is turned on. It is supplied to the second node N2 through the TFT T2. That is, as the initialization voltage Vinit is supplied to the fourth node N4 which is the source node of the driving TFT DT, the data voltage Vdata written in the organic light emitting diode OD of the organic light emitting diode OLED is initialized. and a high potential voltage (VDD) is supplied to the gate node of the driving TFT (DT). In addition, as the n th light emitting control signal EM[n] is polled and maintained in a low state, and the third switching TFT T3 is turned off, the current flowing through the organic light emitting device OLED (OD) Ioled is blocked, so the luminance of the organic light emitting diode (OLED) organic light emitting diode (OD) is reduced.

During the sampling period t2, the first scan signal SCAN1 is maintained in a high state, and the second scan signal SCAN2 rises to a high state. During the sampling period t2, both the nth emission control signal EM[n] and the n−1th emission control signal EM[n−1] are maintained at a low state. Accordingly, during the sampling period t2, the first switching TFT (T1), the second switching TFT (T2), and the fifth switching TFT (T5) are turned on, and the third switching TFT (T3) and the fourth switching TFT (T4) are turned on. ) is turned off. Accordingly, the data voltage Vdata is supplied to the third node N3 through the first switching TFT T1. In addition, as the second switching TFT (T2) is turned on, the first node (N1), which is the drain node of the driving TFT (DT), and the second node (N2), which is the gate node of the driving TFT (DT) are connected, thereby Vgs of the driving TFT (DT) is sampled as Vth of the driving TFT (DT) by the source follower method. Also, as the fifth switching TFT T5 is turned on, the initialization voltage Vinit is supplied to the fourth node N4 and Vdata+Vth-Vinit is stored in the capacitor. Accordingly, during the sampling period t2, the voltages of the first node N1 and the second node N2 are Vdata+Vth, the voltage of the third node N3 is Vdata, and the voltage of the fourth node N4 is This is the initialization voltage (Vinit). In addition, as the n th light emitting control signal EM[n] is polled and maintained in a low state, and the third switching TFT T3 is turned off, the current flowing through the organic light emitting diode OLED (OD) Ioled is blocked, so the luminance of the organic light emitting diode (OLED) organic light emitting diode (OD) is reduced.

At the moment when the voltage horizontal holding period t3 starts, the first scan signal SCAN1 and the second scan signal SCAN2 poll to become low, and the nth emission control signal EM[n] and the n−1th scan signal EM[n] The emission control signal EM[n-1] remains low. Thus, during the voltage horizontal holding period t3, all switching TFTs are turned off. Accordingly, each of the first node N1, the second node N2, the third node N3, and the fourth node N4 sampled or written in the sampling period t2 is floated, and the voltage of each node is It stays the same.

In particular, in an organic light emitting display device, when a switching TFT of a pixel is made of an oxide semiconductor TFT and a driving TFT (DT) of a pixel is made of an LTPS TFT, such a pixel circuit is advantageous for low-speed driving. Specifically, since the off-current of the switching TFT made of the oxide semiconductor TFT is very small, the first node N1, the second node N2, the third node N3, and the fourth node N1, the second node N2, the third node N3, and the fourth It is advantageous to hold the voltage of each node N4 horizontally. That is, in the switching TFT made of the oxide semiconductor TFT, the off-current is very small during the voltage horizontal holding period t3, so that the first node N1, the second node N2, the third node N3, and the fourth node N4 ) can be held horizontally without each voltage being reduced. Accordingly, when the switching TFT of the pixel is made of an oxide semiconductor TFT and the driving TFT (DT) of the pixel is made of an LTPS TFT, since the off-current is small even in low-speed driving, the voltage of each node during the voltage horizontal holding period (t3) is It can be held horizontally with little reduction. In addition, as the n th light emitting control signal EM[n] is polled and maintained in a low state, and the third switching TFT T3 is turned off, the current flowing through the organic light emitting diode OLED (OD) Ioled is blocked, so the luminance of the organic light emitting diode (OLED) organic light emitting diode (OD) is reduced.

During the connection period t4, the first scan signal SCAN1 and the second scan signal SCAN2 are maintained in a low state. At the moment when the connection period t4 starts, the n−1 th light emission control signal EM[n−1] rises to a high state, and the nth emission control signal EM[n] remains low. Accordingly, only the fourth switching TFT (T4) is turned on during the connection period (t4), and the first switching TFT (T1), the second switching TFT (T2), the third switching TFT (T3) and the fifth switching TFT (T5) are turned on. ) are all turned off. Accordingly, the fourth switching TFT (T4) is turned on so that the third node (N3) and the fourth node (N4) are connected, and Vdata horizontally held by the third node (N3) is connected to the fourth node (N4). are supplied In addition, as the n th light emitting control signal EM[n] is polled and maintained in a low state, and the third switching TFT T3 is turned off, the current flowing through the organic light emitting diode OLED (OD) Ioled is blocked, so the luminance of the organic light emitting diode (OLED) organic light emitting diode (OD) is reduced.

During the emission period t5, the first scan signal SCAN1 and the second scan signal SCAN2 are maintained in a low state. As soon as the emission period t5 starts, the nth emission control signal EM[n] rises and maintains a high state during the emission period t5. In addition, the n−1 th emission control signal EM[n−1] also maintains a high state. Accordingly, during the light emission period t5, the first switching TFT (T1), the second switching TFT (T2), and the fifth switching TFT (T5) are turned off, and the third switching TFT (T3) and the fourth switching TFT (T4) are turned off. ) is turned on. In addition, the driving TFT (DT) is also turned on by Vdata + Vth stored in the second node (N2) until the connection period (t4), and the organic light emitting diode (OLED) organic light emitting diode (OLED) is also turned on from the high potential voltage (VDD) line. OD), a path through which the driving current can flow is formed. That is, Ioled flows to the organic light emitting diode (OLED) organic light emitting diode (OD) through the turned-on driving TFT (DT), third switching TFT (T3) and fourth switching TFT (T4) during the emission period (t5). In addition, since the Vgs of the driving TFT (DT) is expressed as a voltage including Vdata in the emission period t5 and the Vth of the driving TFT (DT) is compensated, the size of Ioled is determined by the size of Vdata of the driving TFT (DT). is also controlled, and the organic light emitting device (OLED) organic light emitting device (OD) emits light by Ioled, so that the luminance increases.

FIG. 9 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 7 and corresponding luminance during a horizontal holding period. For convenience of description, it will be described later with reference to FIG. 7 based on one horizontal period.

As shown in FIG. 9, during the horizontal holding period Ph, the first scan signal SCAN1 is in a low state, the second scan signal SCAN2 also maintains a low state, and the data line has a reference voltage (Vref ) is authorized. Accordingly, the first switching TFT (T1) and the second switching TFT (T2) are turned off during the horizontal holding period (Ph).

In the horizontal holding period Ph, the n th light emission control signal EM[n] polls from the high state to the low state at least once, and is maintained in the low state for a predetermined period of time.

In this way, as the nth light emitting control signal EM[n] is polled and maintained in a low state, the third switching TFT T3 is turned off, and the current flowing through the organic light emitting device OLED (OD) Ioled is blocked, so the luminance of the organic light emitting diode (OLED) organic light emitting diode (OD) is reduced.

Here, the gate driver 130 adjusts the time for which the n th emission control signal EM[n] is maintained in a low state during the horizontal holding period Ph, based on the image data RGB.

Specifically, as shown in Table 1, as the predicted luminance value calculated based on the image data RGB is larger, the nth emission control signal EM[n] is maintained at a low state during the horizontal holding period Ph. reduce the time

For example, when the predicted luminance value based on the image data RGB is 1 nit, the n-th emission control signal EM[n] is maintained in a low state for a total of 60 horizontal periods, and the larger the predicted luminance value, the n-th emission The time for which the control signal EM[n] is maintained in a low state is gradually decreased, and when the predicted luminance value is 300 nit, the nth emission control signal EM[n] is maintained in a low state for a total of 6 horizontal periods. .

The organic light emitting display device according to an embodiment of the present invention maintains the emission control signal in a low state for a certain period of time even in a horizontal holding period, outputs an average luminance corresponding to a predicted luminance value based on image data, and simultaneously uses a low driving frequency. The flicker phenomenon in furnace driving can also be reduced.

An organic light emitting diode display device according to an exemplary embodiment of the present invention includes a display panel including a plurality of pixels connected to gate lines and data lines, a gate driver outputting scan signals and emission control signals to the gate lines, and receiving image data. and a data driver outputting a data voltage to the data line during a refresh period and outputting a reference voltage during a horizontal holding period. In the horizontal holding period, the emission control signal polls from a high state to a low state at least once, so that a flicker phenomenon in driving with a low driving frequency may be reduced.

According to another feature of the present invention, the gate driver adjusts the time the light emission control signal is maintained in a low state during the horizontal holding period based on the image data.

According to another feature of the present invention, the gate driver reduces the time for which the emission control signal is maintained in a low state during the horizontal holding period as the predicted luminance value based on the image data increases.

According to another feature of the present invention, a pixel circuit disposed in a plurality of pixels includes a driving TFT for controlling a current flowing in an organic light emitting device based on voltages applied to a gate node and a source node, and a first scan signal. Based on the first switching TFT for applying the data voltage and the reference voltage to the gate node of the driving TFT, the second switching TFT for applying the initialization voltage to the source node of the driving TFT based on the second scan signal, and the emission control signal and a third switching TFT for applying a high potential voltage to the drain node of the driving TFT.

According to another feature of the present invention, the gate driver adjusts the time for which the emission control signal is maintained in a low state during the horizontal holding period, based on the image data, to control the time for current to flow through the organic light emitting device.

According to another feature of the present invention, the gate driver reduces the time during which the emission control signal is maintained in a low state during the horizontal holding period as the predicted luminance value based on the image data increases, thereby reducing the time for current to flow through the organic light emitting device. increase

According to another feature of the present invention, the pixel circuit disposed in the plurality of pixels is based on the driving TFT second scan signal for controlling the current flowing in the organic light emitting element based on the voltage applied to the gate node and the source node, The first switching TFT for applying the data voltage and the reference voltage to the source node of the driving TFT and the second switching TFT for applying the voltage of the drain node of the driving TFT to the gate node of the driving TFT based on the first scan signal n-th light emission A third switching TFT for applying a high potential voltage to the drain node of the driving TFT based on the control signal, and a fourth switching TFT for applying the voltage of the source node of the driving TFT to the organic light emitting element based on the n-1 th light emission control signal. and a fifth switching TFT for applying an initialization voltage to the organic light emitting element based on the switching TFT and the first scan signal.

According to another feature of the present invention, the gate driver adjusts the time for each of the n−1 th light emission control signal and the n−1 th light emission control signal to be maintained in a low state during the horizontal holding period based on the image data, The time during which current flows through the organic light emitting element is controlled.

According to another feature of the present invention, the gate driver maintains a low state for each of the n−1 th light emission control signal and the n−1 th light emission control signal during the horizontal holding period as the predicted luminance value based on the image data increases time, thereby increasing the time during which current flows through the organic light emitting device.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: organic light emitting display device
110: display panel
120: timing controller
130: gate driver
140: data driver
Vdata: data voltage
Vref: reference voltage
Scan: scan signal
EM: emission control signal

Claims (9)

a display panel including a plurality of pixels connected to gate lines and data lines;
a gate driver outputting a scan signal and an emission control signal to the gate line; and
A data driver for receiving image data, outputting a data voltage to the data line during a refresh period, and outputting a reference voltage during a horizontal holding period;
In the horizontal holding period, the emission control signal polls from a high state to a low state at least once;
The gate driver,
The organic light emitting diode display device, wherein a time for which the emission control signal is maintained in a low state during the horizontal holding period decreases as the predicted luminance value based on the image data increases. delete delete According to claim 1,
The pixel circuit disposed in the plurality of pixels,
a driving TFT that controls a current flowing through the organic light emitting element based on voltages applied to the gate node and the source node;
a first switching TFT for applying the data voltage and the reference voltage to a gate node of the driving TFT based on a first scan signal;
a second switching TFT for applying an initialization voltage to a source node of the driving TFT based on a second scan signal; and
and a third switching TFT for applying a high potential voltage to a drain node of the driving TFT based on the emission control signal. According to claim 4,
The gate driver,
Based on the image data, a time period during which the emission control signal is maintained in a low state during the horizontal holding period is controlled to control a time period during which current flows through the organic light emitting element. According to claim 4,
The gate driver,
The organic light emitting diode display device, wherein as the predicted luminance value based on the image data increases, a time during which the light emitting control signal is maintained in a low state during the horizontal holding period is decreased to increase a time during which a current flows through the organic light emitting device. According to claim 1,
The pixel circuit disposed in the plurality of pixels,
a driving TFT that controls a current flowing through the organic light emitting element based on voltages applied to the gate node and the source node;
a first switching TFT for applying the data voltage and the reference voltage to a source node of the driving TFT based on a second scan signal;
a second switching TFT for applying the voltage of the drain node of the driving TFT to the gate node of the driving TFT based on the first scan signal;
a third switching TFT for applying a high potential voltage to a drain node of the driving TFT based on the nth emission control signal;
a fourth switching TFT for applying a voltage of a source node of the driving TFT to the organic light emitting element based on an n−1 th light emission control signal; and
and a fifth switching TFT configured to apply an initialization voltage to the organic light emitting element based on a first scan signal. According to claim 7,
The gate driver,
Based on the image data, a time period during which the n−1 th light emitting control signal and the n−1 th light emitting control signal are maintained in a low state during the horizontal holding period is controlled so that current flows through the organic light emitting device. An organic light emitting display device that controls a. According to claim 7,
The gate driver,
As the predicted luminance value based on the image data increases, the time during which the n−1 th light emitting control signal and the n−1 th light emitting control signal are maintained in a low state during the horizontal holding period is reduced, thereby reducing the organic light emitting element. An organic light emitting display device that increases a time during which current flows through the device.

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