KR20190046346A - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device and, more specifically, to an organic light emitting display device capable of reducing a flicker. The organic light emitting display device comprises: a display panel having a plurality of pixels connected to a gate line and a data line; a gate driving unit outputting a scan signal and a light emission control signal to the gate line; and a data driving unit receiving image data, outputting a data voltage to the data line for a refresh period, and outputting a reference voltage for a horizontal holding period. In the horizontal holding period, the light emission control signal is polled from a high state to a low state at least once, thereby reducing flicker phenomena in the driving with a low driving frequency.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

And more particularly, to an organic light emitting display device capable of reducing flicker.

Recently, as the information age has come to the age of information, a display field for visually expressing electrical information signals has been rapidly developed. In response to this, various display devices having excellent performance in thinning, light weighting, Is being developed.

Specific examples of such a display device include a liquid crystal display device (LCD), a field emission display device (FED), and an organic light emitting display device (OLED) have.

Each of the plurality of pixels constituting the organic light emitting display includes an organic light emitting element composed of an organic light emitting layer between the anode and the cathode and a pixel circuit for independently driving the organic light emitting element. The pixel circuit includes a switching thin film transistor (hereinafter referred to as TFT), a driving TFT, and a capacitor. Here, the switching TFT charges the data voltage in the capacitor in response to the scan pulse, and the driving TFT controls the amount of current supplied to the organic light emitting element according to the data voltage charged in the capacitor to control the amount of light emitted from the organic light emitting element.

The organic light emitting display device is a self-emission type display device, unlike a liquid crystal display device, a separate light source is not required, and thus it can be manufactured in a light and thin shape. In addition, the organic light emitting display device is not only advantageous in terms of power consumption by low voltage driving, but also has excellent hue, response speed, viewing angle, and contrast ratio (CR), and has been studied as a next generation display device in various fields. Further, since the organic light emitting element has a surface light emitting structure, it is easy to realize a flexible form.

In the OLED display device having the above advantages, a characteristic difference such as a threshold voltage (Vth) and a mobility of a driving TFT is generated for each pixel due to a process variation or the like, and a voltage drop of the high potential voltage (VDD) And the amount of current for driving the organic light emitting diode is changed, so that a luminance deviation occurs between the pixels. In general, there is a problem in that unevenness or pattern that is unintended on the screen is generated due to the difference in characteristics of the initial driving TFTs, and a characteristic difference due to the deterioration of the driving TFTs generated while driving the organic light emitting elements, And there is a problem that afterimage is generated. Thus, attempts have been made to improve image quality by reducing the luminance deviation between pixels by introducing a compensation circuit that compensates for the characteristic deviation of the drive TFT and compensates for the voltage drop of the high-potential voltage (VDD).

Accordingly, various attempts have been made to reduce the power consumption of the OLED display by variously changing the driving method of the OLED display. One of such driving methods is to control the driving frequency of the organic light emitting display device to be smaller than the basic driving frequency and to control the horizontal holding period of the light emitting state.

However, driving the organic light emitting display device with a low driving frequency and controlling the horizontal holding period of the light emitting state to be long may cause a problem that the luminance is lowered during a period in which a scan signal is applied or during a horizontal holding period. Such a luminance decline may cause a flickering phenomenon that is visible to the human eye and flickers.

Accordingly, there is a demand for a method capable of driving the organic light emitting display device at a low driving frequency and reducing the flicker phenomenon in order to reduce power consumption.

The inventors of the present invention have recognized that, when performing low-speed driving in an organic light emitting diode display, it is possible to suppress a decrease in luminance during a refresh interval by an internal compensation circuit or an external voltage compensation method for each pixel of the organic light emitting diode display . Accordingly, the present inventors have invented an organic light emitting display device capable of reducing the flicker phenomenon while reducing the power consumption of the organic light emitting display device.

Accordingly, it is an object of the present invention to provide an organic light emitting display device that maintains a light emission control signal in a low state for a predetermined period even during a horizontal holding period in which data is not written during low-speed driving.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an organic light emitting diode (OLED) display device including a display panel including a plurality of pixels connected to a gate line and a data line, a scan line driver And a data driver for receiving the gate driver and the image data, outputting the data voltage during the refresh interval to the data line, and outputting the reference voltage during the horizontal holding interval. In the horizontal holding period, the emission control signal is polled from the high state to the low state at least once, thereby reducing the flicker phenomenon in the driving with a low driving frequency.

The details of other embodiments are included in the detailed description and drawings.

The organic light emitting display according to an embodiment of the present invention maintains the emission control signal in a low state for a predetermined period even during the horizontal holding period to output an average luminance corresponding to the predicted luminance value based on the image data, The flicker phenomenon in driving can also be reduced.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

FIG. 1 is a schematic block diagram for explaining an organic light emitting display according to an embodiment of the present invention. Referring to FIG.
2 is a waveform diagram illustrating a gate signal according to a low-speed driving mode of an OLED display according to an embodiment of the present invention.
3 is a circuit diagram illustrating a 4T2C pixel circuit included in an OLED display according to an embodiment of the present invention.
FIG. 4 is a waveform diagram showing signals input to the pixel circuit shown in FIG. 3 during the refresh period and luminance according to the signals.
FIG. 5 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 3 during a horizontal holding period and luminance according to the signal.
6A and 6B are graphs showing the luminance of the organic light emitting diode of the OLED display according to the present invention, according to the refresh period and the horizontal holding period.
7 is a circuit diagram showing a 6T1C pixel circuit included in an OLED display according to another embodiment of the present invention.
8 is a waveform diagram showing a signal input to the pixel circuit shown in FIG. 7 during the refresh period and a luminance according to the signal.
FIG. 9 is a waveform diagram illustrating signals input to the pixel circuit shown in FIG. 7 during the horizontal holding period and luminance according to the signals.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

An element or layer is referred to as being another element or layer " on ", including both intervening layers or other elements directly on or in between.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

In the present invention, the TFT may be configured as a P type or an N type. In the following embodiments, for convenience of description, the TFT is formed as an N type. In describing the pulse-shaped signal, the gate high voltage (VGH) state is defined as a "high state", and the gate low voltage (VGL) state is defined as a "low state".

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram for explaining an organic light emitting display according to an embodiment of the present invention. Referring to FIG.

1, an organic light emitting diode display 100 includes a display panel 110 including a plurality of pixels P connected to a gate line GL and a data line DL, A data driver 140 for supplying a data signal to each of the data lines DL and a timing controller 120 for controlling the gate driver 130 and the data driver 140 .

The timing controller 120 processes image data RGB inputted from outside according to the size and the resolution of the display panel 110 and supplies the data to the data driver 140. The timing controller 120 outputs the synchronizing signals SYNC input from the outside, for example, a dot clock signal DCLK, a data enable signal DE, a horizontal synchronizing signal Hsync, and a vertical synchronizing signal Vsync To generate a plurality of gate and data control signals (GCS, DCS). And controls the gate driver 130 and the data driver 140 by supplying the generated gate and data control signals GCS and DCS to the gate driver 130 and the data driver 140, respectively.

The gate driver 130 supplies a gate signal to the gate line GL in accordance with the gate control signal GCS supplied from the timing controller 120. [ Here, the gate signal includes at least one scan signal SCAN and a light emission control signal EM. In FIG. 1, the gate driver 130 is shown as being disposed on one side of the display panel 110, but the number and arrangement of the gate drivers 130 are not limited thereto. That is, the gate driver 130 may be disposed on one side or both sides of the display panel 110 in a GIP (Gate In Panel) manner.

The data driver 140 converts the image data RGB to a data voltage Vdata according to the data control signal DCS supplied from the timing controller 120 and supplies the converted data voltage Vdata to the data line DL. To the pixel P.

A plurality of gate lines GL and a plurality of data lines DL are intersected with each other in the display panel 110 and each of the plurality of pixels P is connected to a gate line GL and a data line DL. Specifically, one pixel P receives a gate signal from the gate driver 130 through the gate line GL, receives a data signal from the data driver 140 through the data line DL, Various power sources are supplied through the line. Specifically, one pixel P receives at least one scan signal SCAN and a light emission control signal EM through the gate line GL and supplies the data voltage Vdata or the reference voltage Vdata through the data line DL, Receives the voltage Vref, and receives the high potential voltage VDD, the low potential voltage VSS, and the initialization voltage Vinit through the power supply line.

Each of the pixels P includes an organic light emitting element and a pixel circuit for controlling driving of the organic light emitting element. Here, the organic light emitting element comprises an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The pixel circuit includes a switching TFT, a driving TFT, and a capacitor. Specifically, in the pixel circuit, the driving TFT controls the amount of current supplied to the organic light emitting element according to the data voltage charged in the capacitor, thereby adjusting the amount of light emitted from the organic light emitting element, and the switching TFT supplies the scan signal (SCAN) and charges the capacitor with the data voltage (Vdata).

As described above, the organic light emitting diode display 100 includes the driving TFT and the switching TFT in the pixel circuit, and the active layer constituting each of the driving TFT and the switching TFT may be composed of different materials. As described above, in one pixel circuit, each of the driving TFT and the switching TFT is made of a TFT having different characteristics, and the organic light emitting display 100 may include a multi-type TFT.

Specifically, in the organic light emitting diode display 100 including a multi-type TFT, an LTPS TFT using low temperature poly-silicon (hereinafter referred to as LTPS) is used as a TFT having a polycrystalline semiconductor material as an active layer do. Since the polysilicon material has high mobility (100 cm 2 / Vs or more), low energy consumption power and excellent reliability, the polysilicon material is applied to the gate driver 130 and / or the multiplexer (MUX) for driving the display element TFTs can do. Or the driving TFT in the pixel P in the organic light emitting diode display 100 is preferable.

In the organic light emitting diode display 100 including a multi-type TFT, an oxide semiconductor TFT using an oxide semiconductor material as an active layer is used. Since the oxide semiconductor material has a low off-current, it is suitable for a switching TFT having a short turn-on time and a long turn-off time.

In particular, the organic light emitting diode display 100 including the multi-type TFT according to the embodiment of the present invention includes a pixel circuit in which the switching TFT is made of an oxide semiconductor TFT and the driving TFT is made of an LTPS TFT. However, in the organic light emitting diode display device 100 of the present invention, the switching TFT is not limited to the oxide semiconductor TFT and the driving TFT is not limited to the LTPS TFT, and the multi-type TFT may be variously configured. In the organic light emitting diode display device 100 of the present invention, the pixel circuit may include a single type of TFT instead of a multi-type TFT.

The OLED display 100 may be driven while varying the driving frequency. In more detail, the timing controller 120 of the OLED display 100 adjusts a frame rate through a refresh rate control signal to adjust the driving method of the OLED display 100 have. For example, the organic light emitting display 100 can be driven at a refresh rate higher or lower than the reference refresh rate. In particular, driving the organic light emitting display 100 to a level lower than the reference refresh rate is referred to as 'low speed driving' (also referred to as 'low refresh rate driving'), 100) is referred to as " high-speed driving ".

Here, the low-speed driving means driving at a refresh rate lower than the reference refresh rate of 60 Hz, which drives the organic light emitting display 100 to output fewer than 60 frames for one second . That is, when the refresh rate is 60 Hz, it is driven by 60 frames for one second, and driving at a refresh rate lower than 60 Hz is called low-speed driving. For example, a low-speed drive may have a refresh rate of 1 Hz, and a 1 Hz low-speed drive may output only one frame per second.

Hereinafter, low-speed driving in the organic light emitting display will be described in detail with reference to FIG.

2 is a waveform diagram illustrating a gate signal according to a low-speed driving mode of an OLED display according to an embodiment of the present invention.

Referring to FIG. 2, in order to reduce the power consumption of the OLED display device, the low-speed driving mode can control the horizontal holding period Ph to be long and the refresh period Pr to be short for a unit time. The horizontal holding period Ph is a period during which the organic light emitting elements emit light even when the reference voltage Vref is applied without supplying the data voltage Vdata through the data lines DL connected to the organic light emitting elements. The refresh period Pr is a period during which the initialization voltage Vini is applied to the organic light emitting device so that the organic light emitting device can emit light during the horizontal holding period Ph, Or a sampling period for sensing the voltage and a programming period for storing the data voltage (Vdata) in the capacitor connected to the organic light emitting element.

For example, in the low-speed driving mode, the refresh period Pr during one second can be maintained for 16.6 milliseconds (msec), and the horizontal holding period Ph can be maintained for 983.4 msec.

Referring to FIG. 2, the gate signal is sequentially shifted to each of the gate lines GL during the refresh period Pr to be supplied to the pixel P. Specifically, the gate signal is sequentially shifted and supplied from the first gate line GL1 to the nth gate line GLn during the refresh period Pr. Here, n denotes the total number of gate lines in the OLED display.

Thus, the data voltage is sampled and programmed in the refresh period Pr to emit light during the horizontal holding period Ph.

Hereinafter, the operation of the pixel circuit in the refresh period and the horizontal holding period when the organic light emitting display according to the embodiment of the present invention includes the pixel circuit of 4T2C will be described in detail.

3 is a circuit diagram illustrating a 4T2C pixel circuit included in an OLED display according to an embodiment of the present invention.

Referring to Fig. 3, the pixel circuit includes a driving TFT DT, three switching TFTs T1, T2, and T3, and two capacitors C1 and C2.

The driving TFT DT includes a gate node which is a first node N1 connected to the first switching TFT T1, a source node which is a second node N2 connected to the second switching TFT T2 and a source node which is connected to the third switching TFT T3 And a drain node which is a third node N3 connected to the second node N3.

Specifically, the gate node of the driving TFT DT is electrically connected to the data line supplying the data voltage Vdata or the reference voltage Vref. Thus, the gate node of the driving TFT DT is connected to the source node of the first switching TFT Tl to receive the data voltage Vdata or the reference voltage Vref. The drain node of the driving TFT DT is electrically connected to the high potential voltage (VDD) line. Thus, the drain node of the driving TFT DT is connected to the source node of the third switching TFT T3 and is supplied with the high-potential voltage VDD. The source node of the driving TFT DT is electrically connected to the organic light emitting diode OL. Specifically, the source node of the driving TFT DT is connected to the anode of the organic light emitting diode (OLED) organic light emitting diode OD, and is connected to the source node of the second switching TFT T2.

Thus, when the third switching TFT T3 is turned on by the emission control signal EM and the driving TFT DT is also turned on, the driving TFT DT is turned on based on the voltages applied to the gate node and the source node Organic Light Emitting Device OLED Controls the magnitude of the current flowing in the organic light emitting device OD to control the luminance of the organic light emitting device OD.

The first switching TFT Tl includes a gate node connected to the first scan signal SCAN1, a drain node connected to the data line, and a source node N1 connected to the driving TFT DT. Specifically, the gate node of the first switching TFT T1 is connected to the first scan signal SCAN1 and is turned on or off by the first scan signal SCAN1. The drain node of the first switching TFT Tl is connected to the data line to transfer the data voltage Vdata or the reference voltage Vref to the gate node of the driving TFT DT. The source node of the first switching TFT (T1) is connected to the gate node of the driving TFT (DT).

Accordingly, when the first scan signal SCAN1 is in the high state, the first switching TFT T1 is turned on to supply the data voltage Vdata or the reference voltage Vref to the gate node of the driving TFT DT .

The second switching TFT T2 includes a gate node connected to the second scan signal SCAN2 line, a drain node connected to the initialization voltage Vinit line, and a source node connected to the source node of the driving TFT DT. Specifically, when the second scan signal SCAN2 is in a high state, the gate node of the second switching TFT T2 turns on the second switching TFT T2. The second switching TFT T2 supplies the initializing voltage Vinit to the second node N2. The source node of the second switching TFT T2 is directly connected to the source node of the driving TFT DT and the second node N2 connected to the anode of the organic light emitting diode OD.

Accordingly, when the second scan signal SCAN2 is in the high state, the second switching TFT T2 is turned on to supply the initialization voltage Vinit to the second node N2, Thereby initializing the data voltage Vdata written in the light emitting element OD.

The third switching TFT T3 includes a gate node connected to the emission control signal EM line, a drain node connected to the high potential voltage (VDD) line, and a source node connected to the drain node of the driving TFT DT. Specifically, the gate node of the third switching TFT T3 is connected to the emission control signal EM line, and when the emission control signal EM is in a high state, the third switching TFT T3 is turned on. The drain node of the third switching TFT T3 is directly connected to the high potential voltage (VDD) line.

The third switching TFT T3 is turned on to supply the high potential voltage VDD to the drain node of the driving TFT DT so that the driving TFT DT is turned on, Adjusts the amount of current of the organic light emitting diode OD by the data voltage Vdata.

The two capacitors may be storage capacitors that store the voltages applied to the gate node or the source node of the driving TFT DT. Further, two capacitors are connected in series at the source node of the driving TFT DT.

Specifically, the first capacitor C1 is electrically connected to the first node N1 which is the gate node of the drive TFT DT and the second node N2 which is the source node of the drive TFT DT. The first capacitor C1 stores a voltage corresponding to the difference between the voltages applied to the first node N1 and the second node N2. The second capacitor C2 is electrically connected to the second node N2 which is the source node of the driving TFT DT and the high potential voltage (VDD) line. Also, the second capacitor C2 is connected in series with the first capacitor C1 at the second node N2. Thus, the second capacitor C2 stores the voltage by the voltage division together with the first capacitor C1.

For example, the first capacitor C1 stores and samples the threshold voltage of the driving TFT DT with a voltage difference between the first node N1 and the second node N2. Further, when the data voltage Vdata is applied, the first capacitor C1 stores and programs the voltage determined by the voltage division with the second capacitor C2. That is, the first capacitor C1 and the second capacitor C2 sample the threshold voltage of the driving TFT DT in a source-follower manner. The first capacitor C1 and the second capacitor C2 are connected to the first node N1 and the second node N2 through a voltage distribution when the potentials of the first node N1 and the second node N2 change, Respectively. Sampling and programming of the first capacitor C1 will be described later with reference to Fig.

FIG. 4 is a waveform diagram showing signals input to the pixel circuit shown in FIG. 3 during the refresh period and luminance according to the signals. Will be described later with reference to Fig. 3 for convenience of explanation.

Referring to FIG. 4, the refresh period Pr includes an initialization period t1, a sampling period t2, a programming period t3, and a light emission period t4. The refresh period Pr may be set to approximately one horizontal period (1H), and in some embodiments, the light emission period t4 may not be included in one horizontal period (1H). Data is written to the pixels arranged in one horizontal line of the pixel array during the refresh period (Pr). Specifically, the threshold voltage of the driving TFT DT of the pixel circuit is sampled during the refresh period Pr, and the data voltage Vdata is compensated by the threshold voltage. Accordingly, the data voltage Vdata is compensated and written into the pixel so that the amount of current of the organic light emitting diode OD can be determined regardless of the threshold voltage. Although the initialization period t1, the sampling period t2, the programming period t3 and the light emitting period t4 are shown as being maintained for the same time in FIG. 4, the initialization period t1, the sampling period t2, The duration of each of the period t3 and the luminescence period t4 may be variously changed according to the embodiment.

First, the first scan signal SCAN1 and the second scan signal SCAN2 are turned on at a moment when the initialization period t1 is started, and are brought into a high state. Simultaneously, the emission control signal EM is polled to a low state. Thus, during the initialization period t1, the first switching TFT (T1) and the second switching TFT (T2) are turned on and the third switching TFT (T3) is turned off. Thus, the reference voltage Vref is supplied from the data line to the first node N1 by the first switching TFT (T1). Further, the initializing voltage Vinit is supplied from the initializing voltage (Vinit) line to the second node N2 by the second switching TFT T2. That is, the initialization voltage Vinit is supplied to the second node N2, which is the source node of the driving TFT DT, so that the data voltage Vdata written in the organic light emitting diode OL is initialized do. The third switching TFT T3 is turned off so that the current flowing through the organic light emitting diode OD (hereinafter, referred to as Ioled) is applied to the organic light emitting diode OL as the emission control signal EM is polled and held in a low state. The brightness of the organic light emitting diode OD is reduced.

During the sampling period t2, the first scan signal SCAN1 is kept in a high state and the second scan signal SCAN2 is turned into a low state. At the instant when the sampling period t2 starts, the emission control signal EM is raised and maintained in the high state during the sampling period t2. Thus, during the sampling period t2, the first switching TFT T1 and the third switching TFT T3 are turned on and the second switching TFT T2 is turned off. Accordingly, the reference voltage Vref is supplied to the first node N1 through the turned-on first switching TFT Tl and the high-potential voltage VDD is supplied to the driving TFT Tl through the third switching TFT T3, Is supplied to the drain node of the transistor DT. That is, the voltage of the first node N1 is maintained at the reference voltage Vref during the sampling period t2, and the voltage of the second node N2 is maintained at the drain-source current of the driver TFT DT Quot;). Here, the gate-source voltage (hereinafter referred to as Vgs) of the driving TFT DT is sampled at the threshold voltage of the driving TFT DT by the source-follower method. The threshold voltage of the driver TFT DT thus sampled is stored in the first capacitor C1. Thus, during the sampling period t2, the voltage of the first node N1 is the reference voltage Vref and the voltage of the second node N2 is Vref-Vth.

During the programming period t3, the first scan signal SCAN1 is held in the high state and the second scan signal SCAN2 is held in the low state. The emission control signal EM is polled at the moment the programming period t3 starts and remains low during the programming period t3. Thus, during the programming period t3, only the first switching TFT (T1) is turned on, and the second switching TFT (T2) and the third switching TFT (T3) are turned off. Accordingly, the data voltage Vdata is supplied to the first node N1 through the turned-on first switching TFT T1, and the drain node and the source node of the driving TFT DT are floated.

The data voltage Vdata is supplied to the first node N1 during the programming period t3 so that the voltage variation amount of the first node N1 is voltage-divided between the first capacitor C1 and the second capacitor C2 , The voltage of the second node N2 is determined as the voltage-divided voltage value. Specifically, the voltage change amount of the first node N1 is Vdata-Vref, and due to the voltage distribution between the first capacitor C1 and the second capacitor C2 connected in series, during the programming period t3, The amount of change in voltage at the node N2 is C1 / (C1 + C2) * (Vdata-Vref). That is, the voltage of the second node N2 is changed from Vref-Vth determined in the sampling period t2 to C1 / (C1 + C2) * (Vdata-Vth) which is the voltage variation amount in the second node N2 during the programming period t3, Vref). In other words, the voltage of the second node N2 in the programming period t3 is (Vref-Vth) + C1 / (C1 + C2) * (Vdata-Vref), and Vgs of the driving TFT DT is C1 / (C1 + C2)) * (Vdata-Vref) + Vth. As the third switching TFT T3 is turned off, the current Ioled flowing through the OLED organic light emitting diode OD is cut off, as the emission control signal EM is polled and held in a low state, Organic Light Emitting Device OLED The luminance of the organic light emitting device OD is reduced.

During the light emitting period t4, the first scan signal SCAN1 is brought into a low state and the second scan signal SCAN2 is held in a low state. The light emission control signal EM is lifted as soon as the light emission period t4 is started and maintained high during the light emission period t4. Thus, during the light emitting period t4, the first switching TFT T1 and the second switching TFT T2 are turned off, and the third switching TFT T3 is turned on. Accordingly, the high-potential voltage VDD is supplied to the drain node of the driving TFT DT through the turned-on third switching TFT T3, Vds> Vgs> Vth, (OLED) An electric current flows to the organic light emitting diode (OD). Specifically, the current Ioled flowing in the organic light emitting diode OD is controlled by the Vgs of the driving TFT DT during the light emitting period t4, and the current Ioled flowing through the organic light emitting diode OLED The luminous means OD emits light and the luminance rises. The current Ioled flowing through the organic light emitting diode OD during the light emitting period t4 is expressed by the following equation (1).

[Equation 1]

Here, k is a proportional constant reflecting various factors of the pixel circuit, and C '= C1 / (C1 + C2). Vth is canceled in the expression (1), and the current Ioled flowing in the organic light emitting diode OD of the organic light emitting diode OLED is affected by the threshold voltage of the driving TFT DT I do not accept.

FIG. 5 is a waveform diagram illustrating a signal input to the pixel circuit shown in FIG. 3 during a horizontal holding period and luminance according to the signal. For ease of explanation, one horizontal period will be described later with reference to Fig.

5, during the horizontal holding period Ph, the first scan signal SCAN1 goes low, the second scan signal SCAN2 also goes low, and the data line receives the reference voltage Vref Is applied. Thus, the first switching TFT (T1) and the second switching TFT (T2) are turned off during the horizontal holding period (Ph).

In the horizontal holding period Ph, the emission control signal EM is polled at least once from a high state to a low state, and is maintained in a low state for a predetermined time.

The emission control signal EM is polled and held in the low state and the third switching TFT T3 is turned off so that the current Ioled flowing through the organic light emitting diode OL is blocked Organic Light Emitting Device OLED The luminance of the organic light emitting device OD is reduced.

Here, the gate driver 130 adjusts the time during which the emission control signal EM is kept in the low state during the horizontal holding period Ph, based on the image data RGB.

Specifically, as shown in Table 1, the larger the predicted luminance value calculated based on the image data (RGB), the shorter the time during which the emission control signal EM is held in the low state during the horizontal holding period Ph.

[Table 1]

For example, when the predicted luminance value based on the image data (RGB) is 1 nit, the emission control signal EM is kept in a low state for a total of 60 horizontal periods, and the emission control signal EM becomes low State, and when the predicted luminance value is 300 nits, the emission control signal EM is kept in a low state for a total of 6 horizontal periods.

6A and 6B are graphs showing the luminance of the organic light emitting diode of the OLED display according to the present invention, according to the refresh period and the horizontal holding period.

Specifically, FIG. 6A shows the luminance when the emission control signal EM is held in the low state for a relatively short time because the predicted luminance value is relatively high. On the other hand, in FIG. 6B, the predicted luminance value is relatively low, And the emission control signal EM is held in a low state for a relatively long time.

In FIG. 6A, when the time during which the emission control signal EM is kept low is short, the luminance reduction amount of the organic light emitting diode OD is relatively small. Accordingly, the average luminance of the organic light emitting diode OL is relatively high. That is, the time for which the emission control signal EM is kept in the low state is set to be short so that the average luminance of the OLED OL is higher as the predicted luminance value based on the image data RGB is higher. .

In contrast, in FIG. 6B, when the emission control signal EM is maintained at a low level for a long time, the reduction amount of the luminance of the organic light emitting diode OD is relatively large. Accordingly, the average luminance of the organic light emitting diode OL is relatively lowered. That is, the time for which the emission control signal EM is kept in the low state is set to be long so that the average luminance of the OLED OL is lowered as the predicted luminance value based on the image data RGB is lower .

The OLED display according to the exemplary embodiment of the present invention maintains the emission control signal in a low state for a predetermined period even during a horizontal holding period to output an average luminance corresponding to a predicted luminance value based on image data, The flicker phenomenon in driving by the frequency can also be reduced.

7 is a circuit diagram showing a 6T1C pixel circuit included in an OLED display according to another embodiment of the present invention.

Referring to Fig. 7, the pixel circuit includes a driving TFT DT, five switching TFTs, and one capacitor.

The driving TFT DT includes a gate node connected to one node of the capacitor, a drain node electrically connected to the second switching TFT T2 and the third switching TFT T3, and a first switching TFT T1 and a fourth switching TFT RTI ID = 0.0 > T4. ≪ / RTI >

Specifically, the gate node of the driving TFT DT stores the high-potential voltage VDD when the second switching TFT T2 and the third switching TFT T3 are turned on. When the data voltage Vdata is supplied in the state that the second switching TFT T2 is turned on, the data voltage Vdata is written to the gate node of the driving TFT DT by the source follower method. The driving TFT DT supplies a driving current to the OLED organic light emitting diode OD by the emission control signal EM so that the luminance of the organic light emitting diode OD .

The first switching TFT Tl includes a gate node connected to the second scan signal SCAN2 line, a drain node connected to the data line, and a source node connected to the source node of the driving TFT DT. Thus, the first switching TFT Tl is turned on or off by the second scan signal SCAN2. That is, when the second scan signal SCAN2 is supplied to the gate node of the first switching TFT T1 in a high state, the data voltage Vdata from the drain node of the first switching TFT T1 is applied to the gate of the driver TFT DT And is supplied to the third node N3 which is the source node.

The second switching TFT T2 includes a gate node connected to the first scan signal SCAN1 line, a drain node connected to the source node of the third switching TFT T3 and a drain node connected to the drive TFT DT, And a source node connected to the gate node. Thus, the second switching TFT T2 may be turned on by the first scan signal SCAN1. That is, when the first scan signal SCAN1 is in a high state, the second switching TFT T2 is turned on. Thus, the second switching TFT T2 transfers the voltage at the first node N1, which is the drain node of the driving TFT DT, to the voltage at the second node N2, which is the gate node of the driving TFT DT.

Accordingly, when the first scan signal SCAN1 is in a high state, the second switching TFT T2 supplies the sampled voltage of the driving TFT DT or the high-potential voltage VDD of the first node N1 to the second And supplies the data voltage Vdata to the node N2 to initialize the data voltage Vdata written to the OLED organic light emitting diode OD or to write the data voltage Vdata to the threshold voltage of the driving TFT DT Sampling.

The third switching TFT T3 is connected to the gate node connected to the nth emission control signal EM [n] line, the drain node connected to the high potential voltage (VDD) line, and the source node connected to the drain node of the driving TFT DT . Thus, the third switching TFT T3 can be turned on by the nth emission control signal EM [n]. That is, when the nth emission control signal EM [n] is in the high state, the third switching TFT T3 is turned on and the high potential voltage VDD is supplied from the source node to the drain node of the driving TFT DT And supplies it to the first node N1.

Thus, when the emission control signal is in the high state, the third switching TFT T3 supplies the high potential voltage VDD to the drain node of the driving TFT DT. Thus, the third switching TFT T3 controls the amount of current of the organic light emitting diode OL by the driving TFT DT by the data voltage Vdata.

The fourth switching TFT T4 includes a gate node connected to the n-1 emission control signal EM [n-1] line, a drain node connected to the source node of the driving TFT DT and an organic light emitting element OLED And a source node electrically connected to the device OD. Thus, the fourth switching TFT T4 can be turned on by the (n-1) -th emission control signal EM [n-1]. In other words, when the (n-1) -th emission control signal EM [n-1] is in a high state, the fourth switching TFT T4 is turned on and the third node N3, which is the source node of the driving TFT DT, And the fourth node N4 which is the source node of the fourth switching TFT T4.

Thereby, when the fourth switching TFT T4 is turned on by the (n-1) -th emission control signal EM [n-1], the voltage of the third node N3 is supplied to the fourth node N4 . When the fourth switching TFT T4, the driving TFT DT and the third switching TFT T3 are turned on, the high-potential voltage VDD is supplied to the driving TFT DT, and the organic EL element OLED A driving current is supplied to the device OD to cause the organic light emitting device OL to emit light.

The fifth switching TFT T5 includes a gate node connected to the first scan signal line SCAN1, a drain node connected to the initialization voltage Vinit line, and a fourth node N4, which is an anode of the organic light emitting diode OL. RTI ID = 0.0 > N4. ≪ / RTI > Thus, the fifth switching TFT T5 may be turned on by the first scan signal SCAN1. That is, when the first scan signal SCAN1 is in the high state, the fifth switching TFT T5 is turned on and supplies the initializing voltage Vinit to the fourth node N4.

Accordingly, when the fifth switching TFT T5 is turned on by the first scan signal SCAN1, the initializing voltage Vinit is supplied to the fourth node N4 to turn on the organic light emitting diode OLED The data voltage Vdata that has been written to the data line OD is initialized.

The capacitor may be a storage capacitor Cst that stores the voltage applied to the gate node of the driving TFT DT. Here, the capacitor is disposed between the second node N2 which is the gate node of the driving TFT DT and the fourth node N4 which is electrically connected to the anode of the organic light emitting diode OD. That is, the capacitor is electrically connected to the second node N2 and the fourth node N4 to supply the voltage of the gate node of the driving TFT DT and the anode of the organic light emitting diode OD Store the voltage difference.

8 is a waveform diagram showing a signal input to the pixel circuit shown in FIG. 7 during the refresh period and a luminance according to the signal. Will be described later with reference to Fig. 3 for convenience of explanation.

Referring to FIG. 8, data voltages V1 and V2 are applied to pixels arranged in one horizontal line through an initialization period t1, a sampling period t2, a voltage horizontal holding period t3, a connection period t4 and a light emission period t5. (Vdata) is written, and each pixel emits light. Although the initialization period t1, the sampling period t2, the voltage horizontal holding period t3, the connection period t4 and the light emitting period t5 are shown as being maintained for the same time in FIG. 8, The sampling period t2, the voltage horizontal holding period t3, the connection period t4 and the light emission period t5 may vary in various ways according to the embodiment. For example, the voltage horizontal holding period t3 may be shorter than the other intervals.

First, at the start of the initialization period t1, the first scan signal SCAN1 rises to be in a high state, and the second scan signal SCAN2 maintains a low state. At the same time, the n-1th emission control signal EM [n-1] is also kept in the low state, and the nth emission control signal EM [n] is polled in the high state during the initialization period t1, do. Thus, during the initialization period t1, the second switching TFT T2 and the fifth switching TFT T5 are turned on, and the first switching TFT T1 and the fourth switching TFT T4 are turned off. The third switching TFT T3 is turned on only during a period in which the nth emission control signal EM [n] is in the high state and is turned on while the nth emission control signal EM [n] Off. Thus, the initializing voltage Vinit is supplied to the fourth node N4 through the fifth switching TFT T5, and the high-potential voltage VDD is supplied to the second node N4 while the third switching TFT T3 is turned on. And is supplied to the second node N2 through the TFT T2. That is, the initialization voltage Vinit is supplied to the fourth node N4, which is the source node of the driving TFT DT, so that the data voltage Vdata written in the organic light emitting diode OL is initialized And the high potential voltage VDD is supplied to the gate node of the driving TFT DT. The nth emission control signal EM [n] is polled and held in a low state to turn off the current flowing through the organic light emitting diode OD (OLED) as the third switching TFT T3 is turned off. The brightness of the organic light emitting diode OD is reduced.

During the sampling period t2, the first scan signal SCAN1 is maintained in a high state and the second scan signal SCAN2 is rising in a high state. The n-th emission control signal EM [n] and the n-1th emission control signal EM [n-1] are all kept in a low state during the sampling period t2. Thus, during the sampling period t2, the first switching TFT T1, the second switching TFT T2 and the fifth switching TFT T5 are turned on and the third switching TFT T3 and the fourth switching TFT T4 Is turned off. Accordingly, the data voltage (Vdata) is supplied to the third node (N3) through the first switching TFT (T1). As the second switching TFT T2 is turned on, the first node N1, which is the drain node of the drive TFT DT, and the second node N2, which is the gate node of the drive TFT DT, Vgs of the driving TFT DT is sampled at Vth of the driving TFT DT by the source follower method. Further, as the fifth switching TFT T5 is turned on, the initializing voltage Vinit is supplied to the fourth node N4, and Vdata + Vth-Vinit is stored in the capacitor. Therefore, during the sampling period t2, the voltages of the first node N1 and the second node N2 are Vdata + Vth, the voltage of the third node N3 is Vdata, and the voltage of the fourth node N4 is Is the initialization voltage (Vinit). The nth emission control signal EM [n] is polled and held in the low state to turn off the current flowing to the OLED organic light emitting diode OD as the third switching TFT T3 is turned off. The brightness of the organic light emitting diode OD is reduced.

The first scan signal SCAN1 and the second scan signal SCAN2 are polled to be in a low state at the start of the voltage horizontal holding period t3 and the nth emission control signals EM [n] and n-1 The light emission control signal EM [n-1] remains in a low state. Thus, all the switching TFTs are turned off during the voltage horizontal holding period t3. Accordingly, the first node N1, the second node N2, the third node N3, and the fourth node N4 sampled or written in the sampling period t2 are floated, and the voltage of each node is .

Particularly, in the organic light emitting display device, when the switching TFT of the pixel is made of an oxide semiconductor TFT and the driving TFT (DT) of the pixel is made of the LTPS TFT, such a pixel circuit is advantageous for low speed driving. Specifically, since the switching TFT composed of the oxide semiconductor TFT has a very small off-current, the first node N1, the second node N2, the third node N3, and the fourth node N3 during the voltage horizontal holding period t3. It is advantageous to horizontally hold the voltage of each of the nodes N4. That is, in the switching TFT formed of the oxide semiconductor TFT, since the off-current is very small during the voltage holding period t3, the first node N1, the second node N2, the third node N3, and the fourth node N4 ) Can be held horizontally without reducing each voltage. Accordingly, when the switching TFT of the pixel is made of the oxide semiconductor TFT and the driving TFT DT of the pixel is made of the LTPS TFT, since the off-current is small even in the low speed driving, the voltage of each node during the voltage horizontal holding period t3 It can be horizontally held without substantially decreasing. The nth emission control signal EM [n] is polled and held in the low state to turn off the current flowing to the OLED organic light emitting diode OD as the third switching TFT T3 is turned off. The brightness of the organic light emitting diode OD is reduced.

During the connection period t4, the first scan signal SCAN1 and the second scan signal SCAN2 are held in a low state. The n-th emission control signal EM [n-1] is raised to a high state and the nth emission control signal EM [n] is maintained in a low state at the start of the connection period t4. Thus, during the connection period t4, only the fourth switching TFT T4 is turned on, and the first, second, and third switching TFTs T1, T2, T3, and T5 ) Are all turned off. Accordingly, the fourth switching TFT T4 is turned on to connect the third node N3 and the fourth node N4, and the Vdata horizontally held in the third node N3 is connected to the fourth node N4 . The nth emission control signal EM [n] is polled and held in the low state to turn off the current flowing to the OLED organic light emitting diode OD as the third switching TFT T3 is turned off. The brightness of the organic light emitting diode OD is reduced.

During the light emitting period t5, the first scan signal SCAN1 and the second scan signal SCAN2 are held in a low state. The nth emission control signal EM [n] rises and maintains a high state during the light emission period t5 at the start of the light emission period t5. Further, the (n-1) -th emission control signal EM [n-1] also maintains a high state. Thus, during the light emitting period t5, the first switching TFT T1, the second switching TFT T2 and the fifth switching TFT T5 are turned off, and the third switching TFT T3 and the fourth switching TFT T4 ) Is turned on. The driving TFT DT is also turned on by the Vdata + Vth stored in the second node N2 until the connection period t4 so that the driving TFT DT is turned on from the high potential voltage line to the organic light emitting diode OLED OD) is formed. That is, Ioled flows to the organic light emitting diode OD through the driving TFT DT, the third switching TFT T3, and the fourth switching TFT T4 turned on during the light emitting period t5. Vgs of the driving TFT DT is represented by a voltage including Vdata and Vth of the driving TFT DT is compensated at the light emitting period t5 so that the magnitude of the Ioled And the organic light emitting diode (OLED) OL is illuminated by the Ioled to increase the brightness.

FIG. 9 is a waveform diagram illustrating signals input to the pixel circuit shown in FIG. 7 during the horizontal holding period and luminance according to the signals. For convenience of explanation, one horizontal period will be described later with reference to Fig.

9, during the horizontal holding period Ph, the first scan signal SCAN1 goes low, the second scan signal SCAN2 also goes low, and the data line receives the reference voltage Vref Is applied. Thus, the first switching TFT (T1) and the second switching TFT (T2) are turned off during the horizontal holding period (Ph).

In the horizontal holding period Ph, the nth emission control signal EM [n] polls at least one time from a high state to a low state and remains in a low state for a predetermined time.

As the third switching TFT T3 is turned off, the nth emission control signal EM [n] is polled and held in the low state, and the current flowing in the organic light emitting diode OD The brightness of the organic light emitting diode OD is reduced.

Here, the gate driver 130 adjusts the time during which the nth emission control signal EM [n] is held in the low state during the horizontal holding period Ph, based on the image data RGB.

Specifically, as shown in Table 1, as the predictive luminance value calculated based on the image data (RGB) is larger, the nth emission control signal EM [n] remains in the low state during the horizontal holding period Ph Reduces time.

For example, when the predicted luminance value based on the image data (RGB) is 1 nit, the nth emission control signal EM [n] is held in the low state for a total of 60 horizontal periods, and the larger the predicted luminance value, The time during which the control signal EM [n] is held in the low state is gradually decreased, and when the predicted luminance value is 300 nit, the nth emission control signal EM [n] is held in the low state for a total of 6 horizontal periods .

The organic light emitting display according to an embodiment of the present invention maintains the emission control signal in a low state for a predetermined period even during the horizontal holding period to output an average luminance corresponding to the predicted luminance value based on the image data, The flicker phenomenon in driving can also be reduced.

An organic light emitting display according to an embodiment of the present invention includes a display panel having a plurality of pixels connected to a gate line and a data line, a gate driver for outputting a scan signal and a emission control signal to the gate line, And a data driver for outputting a data voltage during a refresh interval to the data line and outputting a reference voltage during a horizontal hold interval. In the horizontal holding period, the emission control signal is polled from the high state to the low state at least once, thereby reducing the flicker phenomenon in the driving with a low driving frequency.

According to another aspect of the present invention, the gate driver adjusts the time during which the emission control signal is kept in the low state during the horizontal holding period based on the image data.

According to still another aspect of the present invention, the larger the predicted luminance value based on the image data, the shorter the time during which the emission control signal is held in the low state during the horizontal holding period.

According to still another aspect of the present invention, a pixel circuit disposed in a plurality of pixels includes: a driving TFT for controlling a current flowing to the organic light emitting element, based on a voltage applied to the gate node and the source node; A first switching TFT for applying a data voltage and a reference voltage to the gate node of the driving TFT, a second switching TFT for applying an initialization voltage to the source node of the driving TFT based on the second scanning signal, And a third switching TFT for applying a high potential voltage to the drain node of the driving TFT.

According to still another aspect of the present invention, the gate driving unit controls the time during which the current flows through the organic light emitting diode by adjusting the time during which the emission control signal is held in the low state during the horizontal holding period based on the image data.

According to another aspect of the present invention, the gate driving unit reduces the time during which the emission control signal is held in the low state during the horizontal holding period as the predicted luminance value based on the image data increases, .

According to still another aspect of the present invention, a pixel circuit disposed in a plurality of pixels includes a plurality of pixel circuits, each pixel circuit including a plurality of pixels, A first switching TFT for applying a data voltage and a reference voltage to the source node of the driving TFT and a second switching TFT for applying the voltage of the drain node of the driving TFT to the gate node of the driving TFT based on the first scanning signal, A third switching TFT for applying a high potential voltage to the drain node of the driving TFT on the basis of the control signal, a fourth switching TFT for applying a voltage of the source node of the driving TFT to the organic light- And a fifth switching TFT for applying an initialization voltage to the organic light emitting element based on the switching TFT and the first scan signal.

According to another aspect of the present invention, the gate driver adjusts the time during which the n-1th emission control signal and the (n-1) th emission control signal are held in the low state during the horizontal holding period, Thereby controlling the time for current to flow through the organic light emitting element.

According to still another aspect of the present invention, the gate driver is maintained in a low state for each of the (n-1) th emission control signal and the (n-1) th emission control signal during the horizontal holding period as the predicted luminance value based on the image data is larger Time, thereby increasing the time for which the current flows through the organic light emitting element

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: organic light emitting display
110: Display panel
120: Timing controller
130: gate driver
140: Data driver
Vdata: data voltage
Vref: Reference voltage
Scan: scan signal
EM: emission control signal

Claims (9)

A display panel having a plurality of pixels connected to a gate line and a data line;
A gate driver for outputting a scan signal and a light emission control signal to the gate line; And
And a data driver receiving the image data and outputting a data voltage during the refresh interval to the data line and outputting a reference voltage during a horizontal holding interval,
Wherein the emission control signal is polled at least one time from a high state to a low state in the horizontal holding period. The method according to claim 1,
Wherein the gate driver comprises:
And controls a time during which the emission control signal is held in a low state during the horizontal holding period based on the image data. 3. The method of claim 2,
Wherein the gate driver comprises:
And decreases the time during which the emission control signal is held in the low state during the horizontal holding period as the predicted luminance value based on the image data is larger. The method according to claim 1,
Wherein the pixel circuit arranged in the plurality of pixels includes:
A driving TFT for controlling a current flowing to the organic light emitting element based on a voltage applied to the gate node and the source node;
A first switching TFT for applying the data voltage and the reference voltage to a gate node of the driving TFT based on a first scanning signal;
A second switching TFT for applying an initialization voltage to a source node of the driving TFT based on a second scanning signal; And
And a third switching TFT for applying a high potential voltage to the drain node of the driving TFT based on the light emission control signal. 5. The method of claim 4,
Wherein the gate driver comprises:
And controls the time during which the current flows through the organic light emitting diode by adjusting a time during which the emission control signal is maintained in a low state during the horizontal holding period based on the image data. 5. The method of claim 4,
Wherein the gate driver comprises:
Wherein the OLED display decreases the time during which the emission control signal is maintained in the low state during the horizontal holding period and increases the time during which current flows through the OLED as the predicted luminance value based on the image data increases. The method according to claim 1,
Wherein the pixel circuit arranged in the plurality of pixels includes:
A driving TFT for controlling a current flowing to the organic light emitting element based on a voltage applied to the gate node and the source node;
A first switching TFT for applying the data voltage and the reference voltage to a source node of the driving TFT based on a second scan signal;
A second switching TFT for applying a voltage of a drain node of the driving TFT to a gate node of the driving TFT based on a first scanning signal;
A third switching TFT for applying a high potential voltage to the drain node of the driving TFT based on the nth emission control signal;
A fourth switching TFT for applying a voltage of a source node of the driving TFT to the organic light emitting element based on an (n-1) -th emission control signal; And
And a fifth switching TFT for applying an initialization voltage to the organic light emitting element based on the first scan signal. 8. The method of claim 7,
Wherein the gate driver comprises:
The organic light emitting display device according to any one of claims 1 to 3, wherein the organic light emitting diode (OLED) includes a plurality of organic light emitting diodes (OLEDs) Of the organic light emitting display device. 8. The method of claim 7,
Wherein the gate driver comprises:
1) th emission control signal and the (n-1) th emission control signal during the horizontal holding period as the predicted luminance value based on the image data increases, The current flowing through the organic light emitting diode is increased.

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