KR102406707B1 - Gate driver and Organic Light Emitting Diode Display Device including the same - Google Patents

Abstract

The gate driver according to the present invention includes a plurality of GIPs for sequentially supplying a scan signal to each of a plurality of gate lines, each GIP outputs a first and a second scan pulse to a sub-pixel, and each GIP is a second scan pulse output unit configured to output the second scan pulse; and an inverter configured to output the first scan pulse to the sub-pixel by inverting the signal output from the second scan pulse output unit, wherein the inverter comprises: The second scan pulse is inverted using a clock signal according to an operation mode.

Description

Gate driver and OLED display device having same {Gate driver and Organic Light Emitting Diode Display Device including the same}

The present invention relates to a gate driving unit and an OLED display having the same, and more particularly, to a gate driving unit in which a GIP constituting the gate driving unit has only one scan pulse output unit, and to an OLED display having the same.

As the information society develops and various portable electronic devices such as high-resolution TVs, mobile communication terminals, and notebook computers develop, the demand for a flat panel display device that can be applied thereto is gradually increasing.

Representative examples of such a flat panel display include a liquid crystal display (LCD) using liquid crystal, an OLED display using an organic light emitting diode (hereinafter referred to as OLED), and the like.

The flat panel display devices as described above include a flat panel display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the flat panel display panel.

The driving circuit includes a gate driver for driving the plurality of gate lines, a data driver for driving the plurality of data lines, and a timing controller for supplying image data and various control signals to the gate driver and the data driver. .

The gate driver may be simultaneously formed on the non-display area of the display panel while forming the pixels with the plurality of gate lines and the plurality of data lines of the display panel.

That is, a gate-in-panel (hereinafter also referred to as “GIP”) method in which the gate driver is directly integrated into the display panel is applied. In addition, the GIP is configured to correspond to the plurality of gate lines in a 1:1 ratio.

In the OLED display panel of the OLED display device, a plurality of gate lines and a plurality of data lines are disposed to cross each other, and a plurality of sub-pixels are arranged in a matrix form in an area where the plurality of gate lines and the plurality of data lines cross each other. .

Each of the plurality of sub-pixels includes an OLED comprising an anode electrode, a cathode electrode, an organic light emitting layer formed between the anode electrode and the cathode electrode, and a pixel circuit independently driving the OLED.

The pixel circuit includes a 3T1C structure including a driving thin film transistor (hereinafter referred to as TFT), a storage capacitor and two switching TFTs, or a 4T1C structure consisting of a driving TFT, a storage capacitor and three switching TFTs, etc.; It can be configured in various ways.

However, in such an OLED display panel, a difference in characteristics such as a threshold voltage (Vth) and mobility of the driving TFT occurs for each sub-pixel due to process deviation, etc., so that the amount of current driving the OLED varies between pixels A luminance deviation occurs.

In general, the difference in the characteristics of the driving TFT in the initial stage causes spots or patterns on the screen, and the characteristic difference due to the deterioration of the driving TFT that occurs while driving the OLED reduces the lifespan of the OLED display panel or causes an afterimage. have.

In order to solve this problem, a method of sensing the threshold voltage and mobility of the driving TFT of each sub-pixel and compensating for data supplied to each pixel according to the sensed threshold voltage and mobility of the driving TFT has been introduced. .

1 is a circuit diagram of a 3T1C sub-pixel of a general OLED display device, FIG. 2 is a driving timing diagram of the pixel configured as in FIG. 1, and FIG. 3 is a conventional GIP configuration block diagram.

As shown in FIG. 1 , each pixel of a conventional OLED display includes an organic light emitting diode (OLED) and a pixel circuit driving the organic light emitting diode.

The pixel circuit includes first and second switching TFTs T1 and T2, a storage capacitor Cst, and a driving TFT DT.

The first switching TFT T1 is an N-type TFT, and a data voltage is charged to the storage capacitor Cst in response to a first scan pulse Scan1 . The driving TFT DT is a P-type TFT, and the amount of light emitted by the OLED is controlled by controlling the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst. The second switching TFT T2 is a P-type TFT and senses a threshold voltage and mobility of the driving TFT DT in response to a second scan signal Scan2.

As described above, since the first switching TFT T1 is an N-type TFT, and the second switching TFT T2 and the driving TFT DT are P-type TFTs, the sub-pixel shown in FIG. 1 is a CMOS type TFT. it is a fire

The storage capacitor Cst is electrically connected between a gate electrode and a source electrode of the driving TFT DT, and applies a data voltage corresponding to an image signal voltage or a voltage corresponding thereto for one frame time. can keep you

An operation of each pixel of the conventional OLED display configured as described above will be described as follows.

As shown in FIG. 2 , at the beginning of the frame, the first scan pulse Scan1 maintains a low state and outputs the second scan pulse Scan2 in a low state to form the driving TFT DT and the capacitor Cst ) is initialized.

When the second scan pulse Scan2 is maintained in a low state and the first scan pulse Scan1 is output in a high state, the data voltage DATA of the data line is charged (stored) in the capacitor Cst. . That is, the data voltage is written (data writing).

When the first scan pulse Scan1 maintains a high state and the second scan pulse Scan2 is output in a high state, the mobility of the driving TFT DT is sensed and compensated.

In addition, when the second scan pulse Scan2 is maintained in a high state and all of the first scan pulses Scan1 are output in a low state, the driving TFT DT generates data DATA stored in the capacitor Cst. The amount of light emitted by the OLED is controlled by controlling the amount of current that is turned on according to the voltage and supplied to the light emitting diode (OLED).

Also, although not shown in FIG. 2 , before power-on or after power-off, the first scan pulse Scan1 is output in a high state, and the second scan pulse Scan2 is output in a low state so that the driving TFT ( The threshold voltage Vth of the driving TFT DT is compensated by sensing the threshold voltage Vth of the DT) and compensating for data supplied to each pixel from the outside.

As described above, in order to compensate for the threshold voltage and mobility of the driving TFT of each pixel, the first scan pulse Scan1 and the second scan pulse Scan2 having the pulses shown in FIG. 2 should be separately output. Therefore, each GIP of the conventional gate driver should have two scan pulse output terminals SCAN1 and SCAN2 as shown in FIG. 3 , and since the first switching TFT T1 is an N-type TFT, the first An inverter IN for inverting the scan pulse may be additionally required.

As described above, since each GIP of the conventional gate driver must include two scan pulse output terminals SCAN1 and SCAN2 and an inverter IN, the bezel size increases in the conventional OLED display device. there was

The present invention has been devised to solve such a problem, and an object of the present invention is to provide a gate driver capable of realizing a narrow bezel and an OLED display having the same.

In order to achieve the above object, the gate driver according to the present invention includes a plurality of GIPs for sequentially supplying scan signals to each of a plurality of gate lines, and each GIP includes first and second scans to sub-pixels. a second scan pulse output unit for outputting the second scan pulse, and each GIP outputs the first scan pulse to the sub-pixel by inverting a signal output from the second scan pulse output unit and an inverter, wherein the inverter inverts the second scan pulse using a clock signal according to an operation mode.

Here, during normal driving, the clock signal is applied to the inverter at a high voltage level, and the inverter inverts the second scan pulse and outputs the second scan pulse as the first scan pulse without modulation of the pulse width.

In the threshold voltage sensing mode of the driving TFT, the clock signal is applied to the inverter at a high voltage level, and the inverter inverts the second scan pulse and outputs the first scan pulse without modulation of the pulse width. do it with

In the mobility sensing mode of the driving TFT, the clock signal is applied to the inverter in a high voltage level state in an initialization period, and is applied to the inverter in a low voltage state in the mobility sensing period, and the inverter operates the A second scan pulse is inverted and output as the first scan pulse, and a signal having the same level as that of the second scan pulse is output as the first scan pulse during the mobility sensing period.

In addition, an OLED display device according to the present invention for achieving the above object is a flat panel display device including a display panel, a gate driver, a data driver, and a timing controller, wherein the gate driver is provided to each of the plurality of gate lines. a plurality of GIPs sequentially supplying scan signals, each GIP outputting first and second scan pulses to sub-pixels, each GIP comprising a second scan pulse output unit outputting the second scan pulse; and an inverter configured to invert a signal output from the second scan pulse output unit to output the first scan pulse to the sub-pixel, wherein the inverter receives the second scan pulse using a clock signal according to an operation mode. It is characterized by inversion.

The gate driver and the OLED display having the same according to the present invention having the above characteristics have the following effects.

Since the threshold voltage and mobility of the driving TFT can be sensed by arranging the inverter IN instead of arranging the first scan pulse output terminal in the GIP, the size of the GIP can be reduced. Accordingly, a narrow bezel of the flat panel display may be implemented.

In addition, since the first scan pulse output terminal is removed, a margin of the second scan pulse output terminal and the like can be secured, thereby improving GIP performance.

1 is a circuit diagram of a 3T1C sub-pixel of a typical OLED display device;
FIG. 2 is a driving timing diagram of a pixel configured as in FIG. 1; FIG.
3 is a conventional GIP configuration block diagram
4 is a block diagram schematically showing an OLED display device according to the present invention.
5 is a block diagram of a GIP configured in a gate driver in an OLED display according to the present invention;
6 is a circuit diagram of a 3T1C sub-pixel of an OLED display device according to a first embodiment of the present invention;
7 is a circuit diagram illustrating sensing of a threshold voltage (Vth) and mobility of a driving TFT in the sub-pixel circuit configured as in FIG. 6 of the OLED display device according to the present invention;
8 is a waveform diagram for normally driving 3T1C sub-pixels of an OLED display device according to the first embodiment of the present invention;
9 is a waveform diagram for sensing a threshold voltage of a driving TFT in a 3T1C sub-pixel of an OLED display device according to the first embodiment of the present invention;
10 is a waveform diagram for sensing the mobility of a driving TFT in a 3T1C sub-pixel of an OLED display device according to the first embodiment of the present invention;

The gate driver and the OLED display having the same according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

4 is a block diagram schematically showing an OLED display device according to the present invention, and FIG. 5 is a configuration block diagram of a GIP configured in a gate driver in the OLED display device according to the present invention.

As shown in FIG. 4 , the OLED display device according to the present invention includes a timing controller 10 , a data driver 20 , a gate driver 30 , a gamma voltage generator 40 , and a display panel 50 . do.

The timing controller 10 generates a data control signal and a gate control signal for controlling driving timings of the data driver 20 and the gate driver 30, respectively, using a plurality of synchronization signals input from the outside. and output to the data driver 20 and the gate driver 30 .

The timing controller 10 aligns image data RGB input from the outside to suit the size and resolution of the display panel 50 and supplies it to the data driver 20 .

The timing controller 10 senses information including the threshold voltage Vth and mobility characteristics of the driving TFT DT of each sub-pixel through the data driver 20, and adds the sensed information (sensed data) to the sensed information (sensed data). Accordingly, it is possible to compensate the characteristic deviation of the driving TFT of each sub-pixel by compensating the data.

The gamma voltage generator 40 generates a gamma voltage set including a plurality of gamma voltages having different levels and supplies it to the data driver 20 .

The data driver 20 converts digital data from the timing controller 10 into analog data signals in response to a data control signal from the timing controller 10 , and supplies them to a plurality of data lines of the display panel 50 . do.

In this case, the data driver 20 subdivides the gamma voltage set from the gamma voltage generator 40 into gray voltages respectively corresponding to gray values of the data, and then converts digital data into an analog data signal using the subdivided gray voltages. convert to The data driver 20 is driven in a sensing mode for external compensation and a display mode for display driving under the control of the timing controller 10 .

The data driver 20 drives each subpixel through a data line using a data signal in the display mode. The data driver 20 drives each sub-pixel by using the pre-charge voltage in the sensing mode, and then senses a sensing voltage or a sensing current from each driven sub-pixel through a sensing channel (data line or reference line). It is converted into data, and the sensed data is transmitted to the timing controller 10 .

The gate driver 30 sequentially drives a plurality of gate lines of the display panel 50 in response to a gate control signal from the timing controller 10 .

The gate driver 30 may include at least one gate driver IC, but is formed in a GIP (Gate In Panel) type that is formed in a non-display area of a substrate along with a process of forming the pixel array of the display panel 50 . .

That is, the gate driver 30 includes a plurality of GIPs that are connected to each other in order to sequentially drive the pixels of the display panel 50 .

In the OLED display device according to the embodiment of the present invention, each GIP included in the gate driver is configured as shown in FIG. 5 .

That is, one scan pulse output unit SCAN2 for outputting a second scan pulse Scan2 to the sub-pixel and a signal output from the one scan pulse output unit SCAN2 are inverted to perform a first scan in the sub-pixel and an inverter IN for outputting a pulse Scan1.

Here, the constant voltage (VDD, high voltage) and the ground voltage (VSS, low voltage) are not applied to the inverter IN, but the clock signal CLK is applied instead of the constant voltage (VDD, high voltage). have.

By adjusting the clock signal CLK, the first and second scan pulses Scan1 and Scan2 may have different phases, and the threshold voltage Vth of the driving TFT may be sensed or the driving TFT may be moved. degree can be sensed. A method of adjusting the clock signal will be described in detail using a driving waveform diagram of a sub-pixel, which will be described below.

The display panel 50 includes a matrix-type pixel array. Each pixel of the pixel array implements a desired color by a combination of red (R), green (G), and blue (B) sub-pixels, and may additionally include a white (W) sub-pixel for improving luminance.

Each of the sub-pixels includes an OLED element and a pixel circuit for driving the OLED element. The pixel circuit may be variously configured, such as a 3T1C structure including a driving TFT, a storage capacitor and two switching TFTs, or a 4T1C structure including a driving TFT, a storage capacitor and three switching TFTs. In addition, the driving TFT and the switching TFT may be formed in a CMOS type, a P type type, or an N type type.

6 is a circuit diagram of a 3T1C sub-pixel of the OLED display according to the first embodiment of the present invention, and FIG. 7 is a threshold voltage (Vth) of the driving TFT in the sub-pixel circuit configured as in FIG. 6 of the OLED display according to the present invention. ) and a circuit diagram for explaining mobility sensing.

For example, the sub-pixel of the OLED display device according to the present invention is configured as described with reference to FIG. 6 .

That is, the sub-pixel of the OLED display according to the present invention includes an organic light emitting diode (OLED Diode) and a pixel circuit driving the organic light emitting diode.

The pixel circuit includes first and second switching TFTs T1 and T2, a storage capacitor Cst, and a driving TFT DT.

first and second scan lines Scan1 and Scan2 for controlling the first and second switching TFTs T1 and T2, respectively, and a data line DATA for supplying a data signal to the first switching TFT T1; , a reference line Vref for supplying a reference voltage Vref to the second switching TFT T2, an ELVDD line for supplying a high potential power ELVDD to the driving TFT DT, and a cathode of the OLED. An ELVSS line for supplying a low potential power supply (ELVSS) is provided.

The first switching TFT T1 is an N-type TFT, and a data voltage is charged to the storage capacitor Cst in response to a first scan pulse Scan1 . The driving TFT DT is a P-type TFT, and the amount of light emitted from the OLED is controlled by controlling the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst. The second switching TFT T2 is a P-type TFT and senses a threshold voltage and mobility of the driving TFT DT in response to a second scan signal Scan2.

In addition, in the sub-pixel configured as shown in FIG. 6 , in order to sense the threshold voltage Vth and mobility of the driving TFT, the first and second switches SW1 and SW2 and the sensed signal as shown in FIG. 7 . is provided with an analog/digital converter (A/D) for converting to a digital signal.

The operation of the OLED display device according to the present invention configured as described above will be described as follows.

8 is a waveform diagram for normally driving 3T1C sub-pixels of the OLED display according to the first embodiment of the present invention, and FIG. 9 is a 3T1C sub-pixel of the OLED display according to the first embodiment of the present invention. It is a waveform diagram for sensing the threshold voltage of the driving TFT in the pixel, and FIG. 10 is a waveform diagram for sensing the mobility of the driving TFT in the 3T1C sub-pixel of the OLED display according to the first embodiment of the present invention.

First, a method of normal driving a 3T1C sub-pixel of an OLED display according to a first embodiment of the present invention will be described with reference to FIGS. 5, 6 and 8 .

In order to emit OLED light in the 3T1C sub-pixel as shown in FIG. 6 , a data voltage is first stored in the storage capacitor Cst, and then the driving TFT DT operates according to the data voltage stored in the storage capacitor Cst. The amount of light emitted by the OLED is controlled by controlling the amount of current supplied to the OLED. Accordingly, the normal driving is divided into a data voltage storage step (writing) and a light emission step (Emission).

In the 3T1C sub-pixel configuration as shown in FIG. 6, in the writing of the data voltage, both the first and second switching TFTs T1 and T2 must be turned on, and in the emission Both the first and second switching TFTs T1 and T2 should be turned on.

As described above, since the first switching TFT T1 is an N-type TFT and the second switching TFT T2 is a P-type TFT, in the writing of the data voltage, the first and second In order to turn on both the switching TFTs T1 and T2, the first scan pulse Scan1 should have a high voltage level and the second scan signal Scan2 should have a low voltage level.

In the GIP according to the present invention, as shown in FIG. 5 , there is no output unit for outputting the first scan pulse Scan1 , the second scan pulse Scan2 is inverted through the inverter IN, and the inverted signal is output as the first scan pulse Scan1.

Accordingly, the second scan pulse output terminal SCAN2 of the GIP outputs a low voltage level in the writing of the data voltage and outputs a high voltage level in the emission.

In addition, when the clock signal CLK outputs a high voltage level in the writing of the data voltage, the first scan pulse Scan1 is output with a high voltage level.

In this way, when the first scan pulse Scan1 has a high voltage level and the second scan signal Scan2 has a low voltage level, the data voltage is transferred through the data line DATA to the storage capacitor Cst. is charged in

And, when the second scan pulse output terminal SCAN2 of the GIP outputs a high voltage level in the emission step, the first scan pulse Scan1 is output at a low voltage level regardless of the clock signal CLK, The driving TFT DT controls the amount of current supplied to the OLED by the driving TFT DT according to the data voltage applied to the storage capacitor Cst to adjust the amount of light emitted by the OLED.

That is, in the normal driving mode, when a high voltage level clock signal CLK is applied to the inverter IN, the inverter IN inverts the second scan pulse Scan2 to generate the inverted scan pulse It is output as a first scan pulse Scan1. In other words, in the normal driving mode, the phase clock signal CLK is applied at a high voltage level, and the inverter IN inverts the second scan pulse Scan2 without modulating the pulse width to obtain the second scan pulse Scan2. It is output as 1 scan pulse (Scan1).

Meanwhile, a method of sensing the threshold voltage Vth of the driving TFT DT in the 3T1C sub-pixel of the OLED display according to the first embodiment of the present invention will be described with reference to FIGS. 5, 7 and 9 as follows. same.

In order to accurately sense the threshold voltage (Vth) of the driving TFT, the driving TFT and the storage capacitor must be initialized first. Accordingly, the method of sensing the threshold voltage Vth of the driving TFT DT includes an initialization step (initial) and a sensing step (Vh sensing).

In order to initialize the driving TFT and the storage capacitor, in FIG. 7 , the first switch Sw1 is turned on and the second switching TFT T2 is turned on to set a reference voltage Vref to the driving TFT DT. and applied to the storage capacitor Cst.

In this way, in order to apply the reference voltage Vref to the driving TFT DT and the storage capacitor Cst, the switch SW1 is turned on, and the second scan signal Scan2 is output at a low voltage level. and the clock signal CLK is output at a high voltage level. Accordingly, the first scan pulse Scan1 is also output at a high voltage level. By this process, the driving TFT DT and the storage capacitor Cst are initialized.

After initializing in this way, the first and second switching TFTs T1 and T2 maintain the initialized state, turn off the first switch SW1, and turn on the second switch SW2 to The threshold voltage of the driving TFT DT is sensed by reading the voltage of the reference line vref. Then, the sensed threshold voltage is converted into a digital signal by an analog/digital converter (A/D) and output.

That is, in the threshold voltage Vth sensing mode of the driving TFT, the clock signal CLK is applied to the inverter IN in a high voltage level state, and the inverter IN operates without modulation of the pulse width, The second scan pulse Scan2 is inverted and output as the first scan pulse Scan1.

In addition, a method of sensing the mobility of the driving TFT (DT) in the 3T1C sub-pixel of the OLED display according to the first embodiment of the present invention will be described with reference to FIGS. 5, 7 and 10 as follows.

In order to accurately sense the mobility of the driving TFT, it is necessary to initialize the driving TFT and the storage capacitor first. Accordingly, as shown in FIG. 10 , the method of sensing the mobility of the driving TFT DT consists of an initialization step (initial) and a sensing step (mob. sensing).

In order to initialize the driving TFT and the storage capacitor, in FIG. 7 , the first switch SW1 is turned on and the second switching TFT T2 is turned on to set a reference voltage Vref to the driving TFT DT. and applied to the storage capacitor Cst. At this time, since the first switching TFT T1 must also be turned on, the clock signal CLK outputs a high voltage level to make the first scan pulse Scan1 become a high voltage level.

In this way, in order to apply the reference voltage Vref to the driving TFT DT and the storage capacitor Cst, the switch SW1 is turned on, and the second scan signal Scan2 is output at a low voltage level. and the clock signal CLK is output at a high voltage level. Accordingly, the first scan pulse Scan1 is also output at a high voltage level. By this process, the driving TFT DT and the storage capacitor Cst are initialized.

After initialization in this way, the first switching TFT T1 must be turned off in order to sense the mobility of the driving TFT DT. Accordingly, when the clock signal CLK is changed to a low voltage level, even if the second scan pulse Scan2 has a low voltage level, the first scan pulse Scan1 also has a low voltage level. Then, the first switch SW1 is turned off and the second switch SW2 is turned on to read the voltage of the reference line vref to sense the mobility of the driving TFT DT. The sensed mobility voltage is converted into a digital signal by an analog/digital converter (A/D) and output.

That is, in the mode for sensing the mobility of the driving TFT DT, the clock signal CLK is applied to the inverter IN at a high voltage level during the initial period, and during the mobility sensing period (( mob. sensing) is applied to the inverter IN in a low voltage state, so that the inverter IN inverts the second scan pulse Scan2 during the initial period to invert the first scan pulse ( Scan1), and during the mobility sensing period (mob. sensing), the second scan pulse Scan2 is not inverted and a signal having the same level as the second scan pulse Scan2 is transmitted as the first scan pulse (Scan1) to output.

8 to 10 , when the waveform of the clock signal CLK is adjusted, the inverter IN turns the first scan pulse Scan1 low when the second scan pulse Scan2 has a high voltage level. It can be output by converting it to a voltage level.

That is, when the high voltage level section of the first scan pulse Scan1 enters the low voltage level section of the second scan pulse Scan2, the first scan pulse Scan1 and the The second scan pulse Scan2 may be output as waveforms having different widths. Accordingly, the threshold voltage Vth and mobility of the driving TFT DT may be sensed without arranging the first scan pulse output terminal SCAN1 .

In general, the area occupied by the first scan pulse output terminal SCAN1 in the GIP is larger than the area of the inverter. Therefore, in the present invention, since the inverter IN is disposed instead of the first scan pulse output terminal SCAN1, the size of the GIP can be reduced. Since the size of the GIP is reduced as described above, a narrow bezel can be implemented.

In addition, since the first scan pulse output terminal SCAN1 is removed, a margin of the second scan pulse output terminal SCAN2 and the like can be secured, thereby improving GIP performance.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

10: timing controller 20: data driver
30: gate driver 40: gamma voltage generator
50: display panel

Claims (8)

a plurality of GIPs to sequentially supply a scan signal to each of the plurality of gate lines;
Each GIP outputs first and second scan pulses to sub-pixels,
Each of the GIPs includes a second scan pulse output unit for outputting the second scan pulse, and an inverter for outputting the first scan pulse to the sub-pixels by inverting the signal output from the second scan pulse output unit, ,
The inverter inverts the second scan pulse using a clock signal adjusted according to one of an operation mode of a normal driving mode, a threshold voltage sensing mode of the driving TFT, and a mobility sensing mode of the driving TFT. The method of claim 1,
In the normal driving mode, the clock signal is applied to the inverter at a high voltage level, and the inverter inverts a second scan pulse to output a first scan pulse without modulation of a pulse width. The method of claim 1,
In the threshold voltage sensing mode of the driving TFT, the clock signal is applied to the inverter in a high voltage level state, and the inverter inverts the second scan pulse and outputs the first scan pulse without modulating the pulse width. drive part. The method of claim 1,
In the mobility sensing mode of the driving TFT, the clock signal is applied to the inverter in a high voltage level state in an initialization period, and is applied to the inverter in a low voltage state in the mobility sensing period, and the inverter operates in the initialization period. The gate driver inverts the second scan pulse to output it as the first scan pulse, and outputs a signal having the same level as the second scan pulse as the first scan pulse during the mobility sensing period. A display panel in which a plurality of gates and data lines are disposed to include a plurality of sub-pixels in a matrix form, and a data voltage is supplied to the plurality of data lines in response to a scan pulse supplied to each gate line to display an image. ;
a gate driver sequentially supplying scan pulses to respective gate lines;
a data driver supplying the data voltage to the plurality of data lines; and
Image data inputted from the outside is arranged to match the size and resolution of the display panel and supplied to the data driver, and synchronization signals input from the outside are applied to a plurality of gate control signals and a plurality of data control signals to the gate driver and the A timing controller for supplying each of the data driving units is provided,
The gate driver includes a plurality of GIPs for sequentially supplying a scan signal to each of the plurality of gate lines,
Each GIP outputs first and second scan pulses to sub-pixels,
Each of the GIPs includes a second scan pulse output unit for outputting the second scan pulse, and an inverter for outputting the first scan pulse to the sub-pixels by inverting the signal output from the second scan pulse output unit, ,
The inverter inverts the second scan pulse using a clock signal adjusted according to one of a normal driving mode, a threshold voltage sensing mode of the driving TFT, and a mobility sensing mode of the driving TFT. 6. The method of claim 5,
In the normal driving mode, the clock signal is applied to the inverter in a high voltage level state, and the inverter inverts a second scan pulse and outputs a first scan pulse without modulation of a pulse width. 6. The method of claim 5,
In the threshold voltage sensing mode of the driving TFT, the clock signal is applied to the inverter at a high voltage level, and the inverter inverts the second scan pulse and outputs the first scan pulse without modulation of the pulse width. display device. 6. The method of claim 5,
In the mobility sensing mode of the driving TFT, the clock signal is applied to the inverter in a high voltage level state in an initialization period, and is applied to the inverter in a low voltage state in the mobility sensing period, and the inverter operates in the initialization period. The second scan pulse is inverted and output as the first scan pulse, and a signal having the same level as the second scan pulse is output as the first scan pulse during the mobility sensing period.

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