JP2010054788A - El display device - Google Patents

El display device Download PDF

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JP2010054788A
JP2010054788A JP2008219469A JP2008219469A JP2010054788A JP 2010054788 A JP2010054788 A JP 2010054788A JP 2008219469 A JP2008219469 A JP 2008219469A JP 2008219469 A JP2008219469 A JP 2008219469A JP 2010054788 A JP2010054788 A JP 2010054788A
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voltage
signal line
period
gate
driving transistor
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JP2008219469A
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Hitoshi Tsuge
仁志 柘植
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Toshiba Mobile Display Co Ltd
東芝モバイルディスプレイ株式会社
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Publication of JP2010054788A publication Critical patent/JP2010054788A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an organic EL display device having a threshold correcting function of a driving transistor with a minimized number of circuit elements. <P>SOLUTION: In a pixel circuit 16 having the threshold correcting function, transistors 11p and 11q supplied with EL electric power or reset electric power are shared by a plurality of pixels to be put together in one, and consequently the number of transistors for each pixel is decreased without spoiling the threshold correcting function to decrease the number of transistors for each pixel on the average of all pixels in a display area. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an EL display device using a self-luminous display panel such as an EL display panel (display device) using an organic or inorganic electroluminescence (EL) element.

  In an active matrix image display device using an organic EL material or an inorganic EL material as an electro-optic conversion substance, light emission luminance changes according to a current written to a pixel. The EL display device is a self-luminous type having a light emitting element in each pixel. The EL display device has advantages such as high image visibility, high luminous efficiency, no need for a backlight, and high response speed compared to a liquid crystal display panel.

For organic EL (PLED, OLED, OEL) panels, active matrix systems have been developed. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit. For example, Patent Documents 1 and 2 have been proposed.
JP 2003-255856 A JP 2003-271095 A

  The EL display panel is configured using a transistor array made of low-temperature or high-temperature polysilicon. However, display variations occur in organic EL elements when the transistor characteristics of the polysilicon transistor array vary.

  That is, if there is a characteristic variation in the driving transistor that supplies the driving current to the EL element, the converted current signal also varies. Usually, the transistor has a characteristic variation of 50% or more. For this reason, there is a problem that the characteristic variation of the driving transistor is displayed as display unevenness, and the image display quality is lowered.

  Therefore, the present invention provides an EL display device capable of realizing image display without characteristic display unevenness.

  The present invention is an EL display device in which pixels having organic light-emitting elements are formed in a matrix, and the drains of the driving transistors of the pixels formed in the same row in each pixel formed in the matrix An EL display device, wherein an electrode is connected to a first signal line, and the first signal line is connected to a reset power source via a first switch.

  According to the present invention, it is possible to realize image display without characteristic display unevenness.

  Hereinafter, an EL display device according to an embodiment of the present invention will be described with reference to the drawings.

(1) Pixel Configuration FIG. 1 shows a pixel configuration of an EL display device. FIG. 3 is a configuration diagram in which the gate driver circuit 12 and the source driver circuit 14 are connected to the display region 31 in which the pixels 16 are arranged in a matrix.

  In FIG. 1, the pixel 16 includes two capacitors 19a and 19b, five switching transistors 11b, 11c, 11d, 11e, and 11f, and one driving transistor 11a.

  The switching transistor 11b is a threshold voltage compensation transistor for compensating the threshold voltage by diode-connecting the transistor 11a.

  The switching transistor 11f is an initialization transistor for applying a reset voltage Vrst to initialize the capacitor 19a.

  The switching transistor 11d is a transistor for controlling the light emission of the EL element 15.

  Since the switching transistors 11b and 11f need to be made small with an off-leakage, a multi-gate structure having a dual gate or higher is used.

  The capacitor 19a is a holding capacitor that holds the potential of the gate terminal of the driving transistor 11a.

  The capacitor 19 b is applied to the source signal line 18 and holds the video signal applied to the pixel 16 in the pixel 16.

  The switching transistor 11c has a gate electrode connected to the gate signal line 17a, a source electrode connected to the source signal line 18, and is turned on / off by a selection signal from the gate driver circuit 12a.

  The source electrode of the driving transistor 11a is connected to the drain electrode of the transistor 11c. The source or drain electrode of the threshold voltage compensation transistor 11b and the first terminal of the capacitor 19a are commonly connected to determine the gate voltage of the driving transistor 11a. Therefore, the driving transistor 11a generates a driving current corresponding to the voltage applied to the gate electrode.

  The threshold voltage compensation transistor 11b is connected between the gate electrode and the source electrode of the driving transistor 11a, and diode-connects the driving transistor 11a in response to a scan signal applied to the gate signal line 17c. Accordingly, the driving transistor 11a is in a diode-like state by the scan signal, and the voltage Vdata−Vth [V] is applied to the gate terminal of the driving transistor 11a, which becomes the gate voltage of the driving transistor 11a. . The voltage Vdata is a video signal output from the source driver circuit 14 to the source signal line 18. At Vth, the threshold voltage is applied to the driving transistor 11a.

  The switch initialization transistor 11f, which is an initialization transistor, is connected between the reset voltage line Vrst and the first terminal of the capacitor 19a, and fills the capacitor 19a in response to the scan signal of the gate signal line 17d. The electric charge is discharged through the reset voltage line Vrst to initialize the capacitor 19a.

  The switching transistor 11e is connected between the first power supply voltage line Vdd and the source electrode of the driving transistor 11a, and is turned on by a light emission control signal transmitted through the gate signal line 17b connected to the gate electrode. The first power supply voltage Vdd is applied to the source electrode of the driving transistor 11a.

  The switching transistor 11d is connected between the driving transistor 11a and the EL element 15, and is generated by the driving transistor 11a in response to a light emission control signal transmitted through the gate signal line 17b connected to the gate electrode. Is transmitted to the EL element 15.

  The capacitor 19a is connected between the first power supply voltage line Vdd and the gate electrode of the driving transistor 11a, and the voltage Vdata−Vth [V applied to the first power supply voltage Vdd and the gate electrode of the driving transistor 11a. The charge corresponding to the voltage difference is maintained for one frame.

(2) Gate signal line The voltages applied to the gate signal line 17 are an off voltage (VGH) and an on voltage (VGL). By applying the VGH voltage, the switching transistors 11b, 11c, 11d, 11e, and 11f The switching transistors 11b, 11c, 11d, 11e, and 11f are turned on by applying the VGL voltage. However, as shown in FIG. 3, if the VGH voltage is common to the gate driver circuit 12a and the gate driver circuit 12b, the VGL voltage is VGL1 in the gate driver circuit 12a, and VGL2 in the gate driver circuit 12b. . That is, the on-voltages are different between the gate driver circuits 12a and 12b.

  Therefore, the ON voltage applied to the gate signal line 17a and the gate signal line 17c is VGL1, and the ON voltage applied to the gate signal line 17b and the gate signal line 17d is VGL2. In addition, the relation of VGL1> VGL2 is set. Note that VGH applied to the gate signal line 17a may be different from VGH applied to the gate signal line 17d.

(3) P-channel and N-channel transistors In this embodiment, the driving transistor 11a is a P-channel transistor, but is not limited thereto, and may be an N-channel transistor.

  In this case, the on voltage is VGH and the off voltage is VGL. In addition, the source terminal of the driving transistor 11a is described as being connected to the anode voltage Vdd, but the present invention is not limited to this. For example, it may be connected to the cathode voltage Vss or the ground voltage GND. The capacitor 18 may be replaced with a capacitor having a gate insulating film capacitance of the transistor 11.

(4) Gate Driver Circuit A start pulse ST1 for selecting the gate signal line 17a, a start pulse ST2 for selecting the gate signal line 17c, and a clock signal (CLK) for sequentially shifting the start pulse are applied to the gate driver circuit 12a. . UD is a signal for switching the up / down shift register direction of the start pulse in the gate driver circuit 12a.

  A start pulse ST3 for selecting the gate signal line 17b, a start pulse ST4 for selecting the gate signal line 17d, and a clock signal (CLK) for sequentially shifting the start pulse are applied to the gate driver circuit 12b.

  Note that it is preferable to add an enable control terminal to the gate driver circuit 12 as necessary. A shift register circuit is formed in the gate driver circuit 12, and the start pulse is sequentially shifted in synchronization with the clock signal (CLK) to change the position of the gate signal line 17 to be selected.

(5) Signals Applied to Gate Signal Lines FIG. 2 shows drive voltages applied to the gate signal lines 17a, 17b, 17c, and 17d, video signal voltages of the source signal lines 18, and light emission states of the EL elements 15.

  In FIG. 2, for ease of explanation, the off voltage is VGH and the on voltage is VGL. Further, the voltage Vdata applied to the source signal line 18 is set to the ground voltage (GND) = 0V and is equal to or lower than the anode voltage Vdd.

  1H is one horizontal scanning period. FIG. 2 is schematic, and 1H may be a few H, and 1H may be a period shorter than 1H. The VGH voltage is set to a voltage not lower than 0.5 V and not higher than 3.0 V than the Vdd voltage.

  The on-voltage is applied to the pixel 16 in the gate signal line 17d during the period from 1t to at. By applying the on voltage (VGL), the transistor 11f is turned on, and the reset voltage Vrst is applied to the gate terminal of the driving transistor 11a (point a).

  By applying the reset voltage Vrst, the driving transistor 11a is reset. The reset voltage Vrst should be set to a voltage not higher than the GND voltage and not lower than −5 (V). Further, the reset voltage Vrst may be changed corresponding to the video signal voltage Vdata. For example, the reset voltage Vrst is changed corresponding to the gradation number of the video signal. Further, the reset voltage Vrst may be changed by video signal voltages of red (R), green (G), and blue (B). This is because the amplitude of the video signal differs between RGB. In this case, a fixed reset voltage Vrst may be set for each RGB without corresponding to the gradation number. Further, the reset voltage Vrst may be changed in accordance with the current consumed on the display screen.

  After the reset voltage Vrst is applied (at), an ON voltage is applied to the gate signal line 17c. The period during which the on-voltage (VGL) is applied is 1H or more, but is not limited thereto, and may be a period of 1H or less. At least the period during which the on-voltage (VGL) is applied to the gate signal line 17c is longer than the period during which the on-voltage (VGL) is applied to the gate signal line 17a. Also overlap. Note that the application time of the reset voltage Vrst is preferably 2 μsec or more.

  By applying the gate signal line 17a on-voltage (VGL), the switching transistor 11c is turned on, and the Vdata applied to the source signal line 18 is applied to the capacitor 19b. The video signal Vdata applied to the point a is held while the switching transistor 11b is on.

  2 may be applied with an ON voltage (VGL) or an OFF voltage (VGH).

  When the switching transistor 11c and the switching transistor 11 are turned on, a path between the driving transistor and the channel of the transistor 11b is generated from the source signal line 18, and the capacitor 11a is charged. By applying Vdata, the driving transistor 11a changes the potential at the gate terminal b so that a current corresponding to Vdata flows, and the changed voltage is held in the capacitor 19a. This operation cancels the offset of the driving transistor 11a. The potential of the capacitor 19b is held for one frame period.

  After the above-described offset cancel operation, the ON voltage is applied to the gate signal line 17b, the switching transistor 11e is turned ON, and the Vdd voltage is supplied to the source terminal of the driving transistor 11a. Further, the switching transistor 11d is turned on, and the driving current for the EL element 15 is supplied from the driving transistor 11a to the EL element 15. The EL element 15 emits light by the applied current.

  An ON voltage or an OFF voltage is applied to the gate signal line 17b, and a current is supplied to the EL element 15 in synchronization with the ON / OFF voltage. The EL element emits light or goes out in synchronization with the application state of the on / off voltage.

  During an operation in which the EL element 15 emits light or is turned off (period other than the voltage programming period, a period from 3t), the transistor 11b is in an open state. At this time, the anode voltage Vdd (ignoring the channel voltage drop of the transistor 11e) is applied to the source terminal of the transistor 11a when the EL element 15 emits light. When the EL element 15 is turned off, the transistor 11e and the transistor 11d are opened. When the EL element 15 is turned off, the source terminal of the driving transistor 11a is substantially held at the anode potential Vdd by the capacitor 19b. Therefore, the potential stability of the transistor 11a is good.

  The EL element 15 is turned on and off by performing duty control on the transistor 11d (turning on / off the transistor 11d and the like to generate a strip-like non-display area on the display screen 31, and the non-display area in the vertical direction of the screen 31. The image may be displayed in synchronization with the frame period).

(6) Pixel change example 1
FIG. 10 is a first modification of the pixel in FIG.

  One terminal of the capacitor 19b is connected to the gate signal line 17a. An on voltage (VGL) or an off voltage (VGH) is applied to the gate signal line 17a, but the off voltage (VGH) is applied in a period other than after the video signal voltage is written to the pixel 16 (after voltage programming). Is applied. Therefore, the capacitor 19b holds a constant charge and is stable.

(7) Pixel change example 2
FIG. 11 is a second modification of the pixel in FIG.

  One terminal of the capacitor 19b is connected to the gate signal line 17b. An on voltage (VGL) or an off voltage (VGH) is applied to the gate signal line 17b. However, an off voltage (VGH) is applied during a period when the video signal voltage is written to the pixel 16 (at the time of voltage programming). Therefore, the capacitor 19b holds a constant charge and maintains a stable state.

  In FIG. 11, one terminal of the capacitor 19b is connected to the gate signal line 17b. However, the present invention is not limited to this and may be connected to the gate signal line 17d. The on-voltage (VGL) is applied to the gate signal line 17d only when the reset voltage Vrst is applied. However, the off voltage (VGH) is applied in other periods. An off voltage (VGH) is applied. Therefore, the capacitor 19b holds a constant charge and maintains a stable state.

(8) Pixel change example 3
FIG. 4 is a modification of the pixel in FIG.

  The difference between FIG. 1 and FIG. 4 is that a capacitor 11c is additionally formed. One object of the capacitor 11c is to realize a better black display (high contrast display) by generating a punch-through voltage due to a change in the voltage applied to the gate signal line 17a (VGL → VGL). The operation of VGL → VGH is an operation for writing and holding a video signal in the pixel 16. That is, this is a control operation of the switching transistor 11c.

  The capacitor 19c has a first electrode commonly connected to the current gate signal line 17a and the gate terminal of the transistor 11c, and a second electrode commonly connected to the capacitor 19a and the gate terminal of the driving transistor 11a.

  In the case where the driving transistor 11a is an N-channel transistor, the pixel 16 is configured so that the voltage applied to the gate signal line 17a (the voltage used when writing and holding the video signal in the pixel) is changed from VGL to VGH. To do.

  That is, the auxiliary capacitor 19b serves to boost the gate voltage (point b) of the driving transistor 11a while changing from the scanning period to the light emission period.

  When the off voltage applied to the gate signal line is VGH and the on voltage is VGL, when the voltage applied to the gate signal line 17a is changed from VGL to VGH, the gate voltage of the driving transistor 11a becomes the auxiliary voltage of the capacitor 19a. The correction voltage is increased by the coupling of the capacitor 19b. Therefore, the voltage of the gate terminal of the driving transistor 11a is shifted to the Vdd voltage side, and a good black display can be realized.

(9) Pixel change example 4
Next, pixel modification example 4 will be described with reference to FIGS. 5 and 6.

(9-1) Pixel Configuration In FIG. 5, the pixel 16 includes two capacitors 19a and 19b, five switch transistors 11b, 11c, 11d, 11e, and 11f, and one drive transistor 11a.

  The switching transistor 11b is a threshold voltage compensation transistor for compensating the threshold voltage by diode-connecting the driving transistor 11a.

  The switching transistor 11f is an initialization transistor for applying a reset voltage Vrst to initialize the capacitor 19a.

  The switching transistor 11d is a transistor for controlling the light emission of the EL element 15.

  Since the switching transistors 11b and 11f need to be made small with an off-leakage, a multi-gate structure having a dual gate or higher is used.

  The switching transistor 11c has a gate electrode connected to the gate signal line 17a, a source electrode connected to the source signal line 18, and is turned on / off by a selection signal from the gate driver circuit 12a.

  The source electrode of the driving transistor 11a is connected to the drain electrode of the transistor 11c. The source or drain electrode of the threshold voltage compensation transistor 11b and the first terminal of the capacitor 19a are commonly connected to determine the gate voltage of the driving transistor 11a. Therefore, the driving transistor 11a generates a driving current corresponding to the voltage applied to the gate electrode.

  The switching transistor 11b, which is a threshold voltage compensation transistor, is connected between the gate electrode and the source electrode of the driving transistor 11a, and causes the driving transistor 11a to be diode-connected in response to a scan signal applied to the gate signal line. . Accordingly, the driving transistor 11a is in a diode-like state by the scan signal, and the voltage Vdata−Vth [V] is applied to the gate terminal of the driving transistor 11a, which is equal to the gate voltage of the driving transistor 11a. Become.

  The switching transistor 11f, which is an initialization transistor, is connected between the reset voltage line Vrst and the first terminal of the capacitor 19a, and responds to the scan signal of the (n-1) th gate signal line 17a connected to the gate electrode. The charge charged in the capacitor 19a in the preceding frame is discharged through the reset voltage line Vrst to initialize the capacitor 19a.

  The switching transistor 11e is connected between the first power supply voltage line Vdd and the source electrode of the driving transistor 11a, and is turned on by a light emission control signal transmitted through the gate signal line 17b connected to the gate electrode. A first power supply voltage Vdd is applied to the source electrode of the driving transistor 11a.

  The switching transistor 11d is connected between the driving transistor 11a and the EL element 15, and is generated by the driving transistor 11a in response to a light emission control signal transmitted through the gate signal line 17b connected to the gate electrode. The drive current is transmitted to the EL element 15.

  The capacitor 19a is connected between the first power supply voltage line Vdd and the gate electrode of the driving transistor 11a, and the first power supply voltage Vdd and the voltage Vdata−Vth [applied to the gate electrode of the driving transistor 11a]. The charge corresponding to the voltage difference of V] is maintained for one frame.

  The auxiliary capacitor 19b has a first electrode commonly connected to the current gate signal line 17a and the gate terminal of the transistor 11b, and a second electrode commonly connected to the capacitor 19a and the gate terminal of the driving transistor 11a.

(9-2) Gate signal line A gate signal line 17a1 and a gate signal line 17a2 are branched from the gate signal line 17a, and an inverter circuit 51 is arranged in the gate signal line 17a1. Therefore, VGH and VGL are inverted and a voltage is applied to the gate signal line 17a1 and the gate signal line 17a2.

(9-3) Source Signal Line The source signal line 18a and the source signal line 18b are provided, and the pixels 16 (16a, 16b) adjacent in the vertical direction are connected to different source signal lines 18. In the present embodiment, the pixel 16b is connected to the source signal line 18b, and the pixel 16a is connected to the source signal line 18a.

  6 shows a connection state between the gate signal line 17 and the source signal line 18 in the pixel configuration of FIG. 5 and 6, the gate signal line for controlling the switching transistor 11f for applying the reset voltage Vrst and the gate signal line for controlling the switching transistor 11c for applying the video signal are provided. And can be made common. Therefore, the number of gate signal lines 17 can be reduced, and the aperture ratio of the pixels 16 can be improved.

  In addition, a plurality of pixel rows can be simultaneously set to the offset cancel state, and favorable offset cancellation can be realized.

(10) Duty Drive In this embodiment, the duty drive as shown in FIG. 12B can be realized by controlling on / off of at least one of the switching transistors 11e and 11d.

  In FIG. 12, 121 is a program pixel row (a pixel row in which a video signal is written), and 123 is a non-display region (non-display (EL element 15) by turning off at least one of the transistor 11e and the transistor 11d. The pixel row or the group of pixel rows) in which no current flows or is small even if it flows. Reference numeral 122 denotes a display region (a pixel row or a group of pixel rows in which both the transistor 11e and the transistor 11d are turned on and current is supplied to the EL element 15. The non-display region 123 and the display region 122 have a frame period or horizontal synchronization. The display screen 31 is scanned in the vertical direction in synchronization with the signal.

(10-1) Problems In the display of FIG. 13A, one display area 122 moves downward from the top of the screen. When the frame rate is low, it is visually recognized that the display area 122 moves. In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.

(10-2) Solution To solve this problem, as shown in FIGS. 12B and 12C, the display area 122 may be divided into a plurality of parts. The divided display areas 122 do not need to be equal (equally divided). For example, the display area is divided into four areas, the divided display area 122a has an area 1, the divided display area 122b has an area 2, and the divided display area 122c has an area 1. The area 4 may be 122d.

  It goes without saying that the display area 122 in several frames (fields) may be controlled so as to average the target area. For example, when the area of the display area 122 occupying the display screen 31 is 1/10, the area of the display area 122 is 1/10 for the first frame (field), and the area of the display area 122 is for the second frame (field). The area is 1/20, the area of the display region 122 is 1/20 in the third frame (field), and the area of the display region 122 is 1/5 in the fourth frame (field). A driving method for obtaining 1/10 of a predetermined display area (display luminance) is exemplified.

  Further, each of R, G, and B may be driven so that the average of the L periods is equal in several frames (fields). However, the number of frames (fields) is preferably 4 frames (fields) or less. This is because flicker may occur depending on the display image.

  Note that one frame or one field in the present embodiment is the same as the image rewriting cycle of the pixels 16 or the cycle in which the display display screen 31 is scanned from top to bottom (from bottom to top).

  Alternatively, driving may be performed so that an appropriate white balance can be obtained by varying the average of the L periods in several frames (fields) for R, G, and B. This driving method is particularly effective when the RGB luminous efficiencies are different. Further, the number of divisions K (the number of divisions of the display area 122) may be different for RGB. In particular, since it is visually noticeable in G, it is effective in G to increase the number of divisions relative to RB.

  In the above embodiment, the display area 122 is described as being divided for easy understanding. However, dividing the area means dividing a period (time). Therefore, in FIG. 1, the on period of the transistor 11 d is divided, so dividing the area is the same as dividing the period (time).

(10-3) Effect As described above, flickering of the screen is reduced by dividing the display area 122 into a plurality of parts. Therefore, no flicker occurs and a good image display can be realized. The division may be made finer. However, the moving image display performance decreases as it is divided. In addition, the frame rate of image display can be reduced, and low power consumption can be realized. For example, when the non-lighting areas 123 are integrated, flicker occurs when the frame rate is 45 Hz or less. However, when the non-lighting area 123 is divided into six or more, flicker does not occur up to 20 Hz or less.

(11) Brightness Adjustment Method FIG. 13A is a brightness adjustment method when the display area 122 is continuous as shown in FIG. The display brightness of the display screen 31 in FIG. The display brightness of the display screen 31 in FIG. 13 (a2) is the next brightest, and the display brightness of the display screen 31 in FIG. 13 (a3) is the darkest. The change from FIG. 13 (a1) to FIG. 13 (a3) (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. At this time, it is not necessary to change the Vdd voltage (anode voltage or the like) in FIG. Further, it is not necessary to change the magnitude of the program current or the program voltage output from the source driver circuit 14. That is, the luminance of the display display screen 31 can be changed without changing the power supply voltage and without changing the video signal.

  In addition, the gamma characteristic of the screen does not change at all when changing from FIG. 13 (a1) to FIG. 13 (a3). Therefore, the contrast and gradation characteristics of the display image are maintained regardless of the brightness of the display screen 31. This is the effect of this embodiment.

  In the conventional screen brightness adjustment, the gradation performance is degraded when the brightness of the display screen 31 is low. That is, even when 64 gradation display can be realized during high brightness display, only half or less gradations can be displayed during low brightness display. Compared to this, the driving method of the present embodiment can realize the highest 64 gradation display without depending on the display brightness of the screen.

  FIG. 13B shows a brightness adjustment method when the display area 122 is dispersed as described with reference to FIG. The display brightness of the display screen 31 in FIG. 13 (b1) is the brightest. The display brightness of the display screen 31 in FIG. 13 (b2) is the next brightest, and the display brightness of the display screen 31 in FIG. 13 (b3) is the darkest. The change from FIG. 13 (b1) to FIG. 13 (b3) (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. If the display area 122 is dispersed as shown in FIG. 13B, flicker does not occur even at a low frame rate.

  Further, in order to prevent flicker from occurring even at a low frame rate, the display area 122 may be finely dispersed as shown in FIG. However, the display performance of moving images decreases. Therefore, the driving method shown in FIG. 13A is suitable for displaying a moving image. When a still image is displayed and low power consumption is desired, the driving method shown in FIG. 13C is suitable. The switching of the driving method from FIG. 13A to FIG. 13C can be easily realized by controlling the shift register 61.

  In FIG. 13, the non-display areas 123 are configured at equal intervals, but the present invention is not limited to this. The display area 122 is driven so that a half area of the display screen 31 continuously forms the display area 122 and the remaining area 50 repeats the display area 122 and the non-display area 123 at equal intervals as shown in FIG. Needless to say.

(12) Display Device Next, the display device of this embodiment using the EL display device that implements the driving method of this embodiment as a display display will be described.

(12-1) First Application Example FIG. 7 is a plan view of a mobile phone of an information terminal device which is an example of an EL display device. An antenna 71 and the like are attached to the housing 73. Reference numeral 72a is a switching key for changing the brightness of the display screen, 72b is a power on / off key, and 72c is a key for switching the operation frame rate of the gate driver circuit 12b. Reference numeral 75 denotes a photo sensor. The photo sensor 75 automatically adjusts the luminance of the display screen 22 by changing the duty ratio and the like according to the intensity of external light.

(12-2) Second Application Example FIG. 8 is a perspective view of a video camera. The video camera includes a photographing (imaging) lens unit 83 and a video camera body 73. The EL display panel of this embodiment is also used as the display monitor 74. The display screen 22 can freely adjust the angle at a fulcrum 81. When the display screen 22 is not used, it is stored in the storage unit 83.

(12-3) Third Application Example The EL display panel or EL display device of the present embodiment can be applied not only to a video camera but also to an electronic camera as shown in FIG. The EL display device of this embodiment is used as the monitor 22 attached to the camera body 91. In addition to the shutter 93, switches 72 a and 72 c are attached to the camera body 91.

(13) Circuit Configuration FIG. 14 shows a circuit for one column of the EL display panel in the present embodiment. Here, the source signal line 18 has two source signal lines 18a and 18b for one column via the switching means 141, and the source signal lines connected to the pixels in the even and odd rows are different. It is a feature. The configuration of each pixel 16 includes, for example, circuits such as FIG. 1, FIG. 4, FIG. 10, and FIG. The gate driver circuit 12a has a shift register configuration, and a pulse is shifted by one stage for each clock. By connecting to the gate signal line 17 as shown in FIG. 14, a signal waveform as shown in FIG. 15 can be realized.

  The period of the shift clock is set to one horizontal scanning period, and a start pulse that outputs a pulse only for one horizontal scanning period is input. Thus, it is possible to realize a circuit that generates a pulse during one horizontal scanning period at a timing shifted by one horizontal scanning period for each row. The output of each stage of the shift register is taken into the gate signal line 17 as shown in FIG. 14, and the switching means 141 is operated as shown in FIG. 15, thereby driving the pixels 16a in the first row in the first one horizontal scanning period. The gate voltage of the transistor 11a is initialized by the Vrst power supply. At the same time, the signal voltage corresponding to the pixels in the first row corresponding to the predetermined gradation is charged from the source signal line to the source signal line 18b via the switching unit 141. The source signal line 18a is not charged. The switching means 141 separates it from the source driver circuit output. In the next one horizontal scanning period, the switching means 141 is operated to charge the source signal line 18a. At this time, since the source signal line 18b is disconnected from the source driver circuit output, the signal voltage corresponding to the pixel in the first row remains charged by the floating capacitance 142b of the source signal line. Therefore, the gate signal line 17a and the gate signal line 17c are scanned to turn on the transistors 11c and 11b of the pixel 16a, and the gradation signal is written into the pixel driving transistor 11a and the characteristic variation is canceled. At the same time, corresponding to the pixels in the second row, the gradation signal voltage corresponding to the pixel 16b is charged to the source signal line 18a, and the gate electrode of the driving transistor 11a is initialized by the Vrst power supply.

  By switching between the source signal line 18a and the source signal line 18b for each horizontal scanning period, the gradation signal to be applied to the source signal line is held for two horizontal scanning periods. You can be longer.

  In the configuration of the pixel circuit shown in FIG. 1 and the like, an operation of canceling the characteristic variation is performed while writing a gradation signal to the driving transistor 11a. The operation of canceling the characteristic variation is performed when the transistors 11f, 11d, and 11e are off and the transistor 11b is on, and the gate potential of the driving transistor 11a is set so that the drain current of the driving transistor 11a becomes zero. By changing, the characteristic variation is canceled. The gate potential of the driving transistor 11a is changed by the charge due to the drain current, and since the final state is 0 or an infinitely small current (picoampere order), the storage capacitor 19a that supports the gate potential. It takes time to charge and discharge. Therefore, it can be seen that the cancel operation takes time. When one horizontal scanning period is long, the canceling operation can be completed within one horizontal scanning period. However, when the number of vertical lines is large and one horizontal scanning period is shorter than 40 μsec, the canceling operation ends. Thus, there is a problem that the characteristic compensation becomes incomplete, and as a result, unevenness corresponding to the characteristic variation occurs.

  Therefore, as a method of extending the cancel time to one horizontal scanning period or more, as shown in FIG. 16, the gate driver circuit 12a is further composed of two gate driver circuits 12a1 and 12a2, and the initialization of the driving transistor 11a is performed. This is performed in advance before one horizontal scanning period in which the corresponding video signal is input, and gradation voltage writing and characteristic cancellation are performed in the driving transistor 11a from the horizontal scanning period in which the video signal is input to the source signal line 18a or 18b. Make an action. Since the video signal is held for two horizontal scanning periods by the operation of the switching unit 141, the gradation voltage writing and the characteristic canceling operation can be performed during the two horizontal scanning periods. In order to realize this, a start pulse 172b of the shift register 12a2 is input as shown in FIG. The transistors 17a and 17c in each row are turned on for two horizontal scanning periods. The turn-on timing is performed in synchronization with the video signals of the source signal lines 18 and 18a, 18b. Since the video signal is distributed to the two source signal lines 18a and 18c in the even and odd rows, the frequency is halved and the writing time can be doubled. Note that the enable signal 173 is a signal for preventing simultaneous selection of pixels in a plurality of rows due to waveform rounding at the time of pulse propagation. The simultaneous selection does not occur or the simultaneous selection operates without any problem. In some cases, this embodiment is unnecessary, and the present embodiment can be implemented without the enable signal 173. For example, as shown in FIG. 21, an input waveform and operation when the enable signal of the gate driver circuit 12a2 that generates a signal for canceling characteristics is deleted are shown.

  According to the waveform of FIG. 17, the characteristic correction operation of the driving transistor 11a is possible during two horizontal scanning periods, but the driving transistor 11a is initialized one horizontal scanning period before the video signal is input in advance. If the first row cannot be detected, it may not be possible to perform initialization in advance.

  Therefore, as shown in FIG. 18, a signal pattern has been devised in which the initialization operation is performed simultaneously with the video signal input in the first row. Since the characteristic correction operation cannot be performed during the initialization operation, the post-initialization characteristic correction operation is performed between two horizontal scanning periods. 18, the initialization operation is performed in the first half of the first horizontal scanning period of the two horizontal scanning periods, and the signal writing to the pixel and the characteristic compensation operation are performed in the remaining half and the next horizontal scanning period. I made it. When the gate driver circuit has a shift register configuration, when the horizontal scanning period and the shift clock coincide, the operation of different switches in the first half and the second half of the horizontal scanning period is performed by cutting the pulse width with the enable signal. It was realized. When the gate signal line 17d is at the low level, the drive transistor 11a is initialized. When the gate signal lines 17a and 17c are at the low level, the characteristics of the drive transistor 11a are canceled and the gradation is written into the pixel. It becomes. Since the low level period of 17a and 17c can be set longer than one horizontal scanning period, even if the horizontal scanning period is 30 μsec, a 1.5 times period can be obtained compared to the conventional case, so a 45 μsec cancellation period can be taken and driving It has become possible to correct variations in the characteristics of the transistors used. Since the initialization operation itself is completed in about 2 to 10 microseconds, the cancel period can be extended to a time obtained by subtracting 2 to 10 microseconds from a maximum of two horizontal scanning periods.

  19 and 20 show a method in which the shift register of the gate driver circuit 12a has one system and the cancel period is expanded to one horizontal scanning period or more.

  For example, when canceling during two horizontal scanning periods, the gate signal lines 17a and 17c need to be in a conductive state for two horizontal scanning periods. Therefore, the start pulse of the gate driver circuit 12a is input for the length of two horizontal scanning periods. Thus, the cancellation and gradation writing time can be set to two horizontal scanning periods. Similarly, it is necessary to generate a pulse for the gate signal line 17d for performing initialization. Since the pixel circuit configuration is as shown in FIGS. 1 and 25, the gate signal lines 17d and 11a and 11c must not be in a conductive state at the same time (different voltages are short-circuited). It is necessary not to overlap with the pulses for canceling and gradation writing for the other pixels. Specifically, a pulse before two horizontal scanning periods may be used as an initialization pulse. As shown in FIG. 19, when using the gate signal line for canceling the gradation signal writing and the output common to the gate signal line 17d for the shift register, it is the second stage (that is, after two horizontal scanning periods). , The same pixel 16a is initialized in two horizontal scanning periods 201 and 202 as shown in FIG. 20, and the characteristics of the driving transistor 11a in two horizontal scanning periods 203 and 204 are obtained. Cancel and gradation signal writing are performed. Similarly, the pixels 16b and 16c are also executed at a timing delayed by one horizontal scanning period.

  This method can be implemented not only for canceling two horizontal scanning periods but also for cases where three horizontal scanning periods or more are required. The number of source signal lines corresponding to one column of pixels is prepared for the number of necessary horizontal scanning periods (integer), and the pulse width of the start pulse of the gate driver circuit 12a is input for the required number of horizontal scanning periods. This is realized by extracting the gate signal for characteristic cancellation and gradation signal writing from the shift register stage after the required number of horizontal scanning periods from the stage of the shift register that takes out the gate signal corresponding to the shift, and inputting it to the pixels in the same row. Is possible. The start pulse needs to be input in advance to the video signal so that the video signal is written to the pixels in the corresponding row. It is necessary to input at least as much as the length of the horizontal scanning period to cancel. Also in FIG. 20, the input is performed earlier by two horizontal scanning periods.

  In order to reduce the cost of the source driver circuit, there is a case where a selective driving method for outputting voltages corresponding to a plurality of pixels in time series from one output may be employed. Compared with the case where there is no selection driving method, the timing at which the video signal corresponding to the pixel is input differs depending on the display color. For example, in the case of 3-selective drive in which 3 pixels of red, green, and blue are output with 1 output, as shown in FIG. 22, green and blue are not the beginning of the horizontal scanning period but the signal changes midway as shown in FIG. You can see that When the gate signal lines 17a and 17c are input with the waveform 221 for the green and blue pixels, the video signal of the previous row is written to the pixel, and the video signal of the row is written by the change of the source signal line. . In the case of liquid crystal or the like, there is no problem because the final voltage at the time of writing (the voltage at the moment when the gate signal line is turned off) is held in the pixels for one frame and displayed at a predetermined luminance, but has the pixel configuration in this embodiment. In the organic EL panel, when the video signal is written to the driving transistor 11a, an operation of correcting the characteristic variation of the driving transistor 11a is performed. In order to shorten the time required for the correction, an initialization operation is performed before writing, and the voltage is applied to the gate electrode of the driving transistor 11a at a lower voltage (the voltage at which the driving transistor 11a allows a current to flow than when white is displayed) in advance. Initialization is in progress. As the initialization voltage is lower, the characteristic correction is faster. When the voltage of the previous row is applied even a little during the selective driving, the gate voltage of the driving transistor 11a changes to the voltage of the previous row, and in the state where the voltage of the previous row is applied, The gradation signal is written by the video signal and the transistor variation characteristic correction is performed, and the effect of initialization is lost. This is a common problem when performing signal line selection driving of two or more selections, even if it is not three selection driving.

  Therefore, in this embodiment, when performing selective driving, the characteristic canceling operation is performed after all the voltages of the signal lines to be written are determined in the same horizontal scanning period.

  FIG. 23, FIG. 24, and FIG. 26 show one of the embodiments. Here, the selection driving is a three-selection driving method in which three signal lines of red, green, and blue are sequentially selected. The same can be realized with two selections or four or more selections. In order to ensure the cancellation time, two signal lines are prepared for each column, and different source signal lines are used for even rows and odd rows. FIG. 23 shows a configuration in which the gate driver circuit 12a is implemented by one shift register circuit. FIG. 26 shows signal input and operation of the signal line selection circuit 232 when the gate driver circuit 12a of FIG. 23 is used. The signal lines are switched to red (R), green (G), and blue (B) within one horizontal scanning period. The selection is performed by switching between the odd-numbered source lines 18b and the even-numbered source lines 18a every horizontal scanning period.

  In this method, the initialization timing and the writing of the video signal line in the row are the same, and the writing of the video signal to the inside of the pixel is performed in the next horizontal scanning period. The video signal does not change during signal line writing and characteristic variation correction, and similar driving can be performed even during selective driving. A timing chart focusing on one pixel is shown in FIG. Here, the gate signal line 17b which has not been described so far is also described. As for 17b, the switch to be connected must be non-conductive in the initialization period, the characteristic cancellation, and the period in which the gradation signal is written to the driving transistor. It may be in any non-conducting state. The same applies to other embodiments of the present embodiment. FIG. 24 shows an example in which conduction / non-conduction is repeatedly performed.

  The source signal line 18 transmits a signal for three pixels during one horizontal scanning period in correspondence with three selection driving. The voltage change of the source signal line 18bB corresponding to the blue pixels in the odd-numbered rows by the signal line selection circuit has a waveform indicated by 241.

  The change of the gradation signal corresponding to the first row changes at the timing of 242. At this time, the gate signal line 17b is in an OFF state, and the video signal of the previous line is not written to the gate electrode of the driving transistor 11a. The gate signal line 17a is off according to the configuration of the gate driver circuit of FIG. 23, but may be on. The configuration of the gate driver circuit may be changed and turned on. This is because the voltage of the previous row is applied to the source electrode of the driving transistor 11a but is not applied to the initialized gate electrode.

  After the time 2t, the gate signal lines 17c and 17a become conductive, and the gradation voltage and the characteristic canceling operation are performed on the driving transistor 11a. At this time, as shown in FIG. 26, the source signal line 18bB is separated from each source signal line by the signal line selection circuit 232, and the voltage written from the source driver circuit is caused by the floating capacitance 233 of the source signal line. Holds for two horizontal scan periods. The held voltage value is written to the pixel, and a predetermined voltage is written. Between times 2t and 3t, the gate voltage of the driving transistor 11a gradually changes to a potential lowered by the threshold voltage (Vth) from the written source voltage (Vs) to (Vs−Vth). After being written to a predetermined voltage at time 3t, a predetermined current flows through the EL element 15 by turning on the gate signal 17b to emit light.

  FIG. 27 is a diagram when the gate driver circuit 12a is constituted by two shift registers. According to this, by setting the start pulse individually, it is possible to set the gate signal lines 17a and 17c with different pulse widths with respect to the gate signal line 17d.

  FIG. 28 shows the input waveforms of the gate driver circuits 12a1 and 12a2 and the waveform of each gate signal line. A pulse for initialization is generated for the gate driver circuit 12a1 that generates a signal for initialization. The time required for initialization depends on the power supply capability for generating Vrst, but the initialization is completed in about 10 μsec. The gate signal line 17d is turned on in a short time. Since the time-consuming characteristic cancellation period and initialization period cannot be performed at the same time, it is important to shorten initialization in order to perform initialization to characteristic cancellation and gradation signal writing within two horizontal scanning periods. This is because. In FIG. 28, the operation is performed only during a period in which the source output is selected as red, but it may be a red and green selection period or a part of the red selection period. Since the voltage corresponding to the pixel is not applied to the source signal line 18aB or 18bB until the blue selection period is reached in the blue source signal line 18aB or 18bB where the video signal of the row is written most slowly, the characteristics Cannot transition to the cancellation period. Since the characteristics cannot be canceled, the red / green selection period has no problem as the initialization period. In the characteristic cancellation and gradation signal writing, the shift register circuit of the gate driver circuit 12a2 generates a pulse that can be selected in two horizontal scanning periods, and excludes the initialization period or the period in which the video signal is not written. An enable signal for providing an enable period for each even row is provided. The characteristic cancellation and gradation signal writing period of the first row is a period indicated by 281. The beginning of the period 281 is after completion of the blue pixel writing, but after the blue pixel is selected by the signal line selection circuit and the source signal line 18aB or 18bB is changed to a predetermined voltage, the gate signal line 17a and 17c may be set to a low level. The end of the period 281 may be set before a voltage corresponding to a pixel in a different row is next applied to the same source signal line. When the signal line selection speed is fast, the characteristic cancellation period can be set from the end of writing to the end of the next horizontal scanning period, and display with a high threshold voltage correction capability of the driving transistor 11a can be realized.

  Note that the gate signal line 17a may be at a low level in all two horizontal scanning periods. This is because the gate voltage of the driving transistor 11a is not affected even when the transistor 11c is turned on. In this case, a shift register output is input to the gate signal line 17c via an enable signal, and a shift register output is input to the gate signal line 17a without an enable signal or via a separate enable signal. It becomes composition.

  So far, the transistor used in the pixel circuit 16 has been described as a p-type transistor. However, the transistor may be an n-type transistor shown in FIG. Further, the organic EL element 15 may have a configuration in which the directions of the anode and the cathode are reversed and the Vss potential> the Vdd potential. Although the capacitor 19b is formed in FIG. 29, the present embodiment can be similarly implemented even without the capacitor 19b.

  When the capacitor 19b is formed, the voltage for one frame until the next video signal is written to the pixel is held, so that the potential at the point a is held. If the transistor 11b is turned on based on the held potential, the characteristic variation of the driving transistor 11a can be canceled with a signal corresponding to the gradation signal. This is a cancel period 302 shown in FIG. This cancel period can be arbitrarily set depending on the configuration of the gate driver circuit regardless of the length of the horizontal scanning period. The writing of the video signal and the initialization of the driving transistor 11a are performed before the cancel period 302 (period 301). Only the transistors 11f and 11c are conductive. Thus, the gate potential of the driving transistor 11a is initialized by the Vrst power supply, and at the same time, a predetermined voltage is written from the source signal line 18 to the capacitor 19b. Since the predetermined gradation voltage is held in the capacitor 19b, the number of source signal lines 18 is one, and it is only necessary to turn on the transistor 11c only for one horizontal scanning period. A method in which the grayscale voltage is held by both the stray capacitance of the source signal line 18 and the capacitor 19b may be used by preparing two source signal lines 18. In this case, the capacity 19b can be reduced.

  When the cancellation is completed, a current is applied to the EL element 15 to obtain light emission with a predetermined luminance. This period is the light emission period 304. At this time, the transistors 11d and 11e are turned on to supply current to the EL element 15. The non-light emission periods 303 before and after are inserted when black is inserted to obtain an effect such as improvement of moving image visibility. At this time, at least one of the transistors 11d and 11e is in a non-conductive state. Further, when black insertion is not performed in a constantly lit state, the period 303 may be omitted.

  In addition, the switching unit 141 and the signal line selection circuit 232 in the present embodiment are not necessarily on the array substrate, and may be configured to be incorporated in the source driver circuit IC.

  In this embodiment, the example in which there are two source signal lines connected to the pixels formed in the same column has been described. However, the present invention can be similarly applied to a plurality of three or more source signal lines. It is. In general, if N source signal lines are prepared and connected every N pixels, the source signal line can hold the gradation voltage during the N horizontal scanning period, and the characteristic canceling period is extended. Thus, the gate voltage closer to the characteristics of the driving transistor 11a can be held in the pixel circuit (maximum N horizontal scanning period), thereby improving display unevenness.

  In addition, for N source signal lines, if a pixel circuit is connected to a source signal line that differs at least between adjacent pixels, a gradation signal is held in the source signal line during two horizontal scanning periods. The characteristic cancellation period can be extended, and an EL display device with little display unevenness can be obtained.

(15) Power Supply for Initialization FIG. 31 is a circuit in which the power supply for initializing the gate voltage of the driving transistor 11a is changed from a voltage source to a current source. FIG. 32 shows the waveform of the gate signal line in the circuit configuration of FIG. In the circuit configuration in FIG. 31, the operation in one pixel is divided into a writing period 321, a light emission period 324, and a non-light emission period 323 during one frame. The non-light emitting period 323 is used when black is inserted to improve operation visibility. In the present embodiment, the non-light emitting period 323 may or may not exist. The compensation capability for characteristic variation can be improved in the same way.

  In the writing period 321, the transistors 11b, 11c, and 11f are turned on. As a result, the voltage of the source signal line 18 is applied to the source electrode of the driving transistor 11a. The gate and drain electrodes of the driving transistor 11a have the same potential by the transistor 11b, and the gate and drain voltages are such that the current supplied from the current source 312 becomes the drain current of the driving transistor 11a. Accordingly, in the writing period 321, the gate voltage of the transistor 11 a is (Vs−Vt1) when the voltage of the source signal line 18 is Vs. Here, Vt1 is a source-drain voltage when the current (Irst) of the current source 312 is passed through the driving transistor 11a, and has a different voltage value depending on the characteristics of the driving transistor 11a. When Irst flows through the driving transistor 11a, that is, the EL element 15, a voltage with corrected characteristic variation is applied to the gate electrode of the driving transistor 11a, and an EL display device without display unevenness can be realized. In the conventional configuration, the characteristic variation is completely corrected at the time of Irst = 0, that is, black display. As the current increases, current variation due to mobility variation that cannot be corrected occurs, and display unevenness occurs as the gray level increases. It was an easy situation. The display unevenness is less visible as the luminance is lower, and is more easily visible in the middle to high gradations. The correction in the middle to high gradations is easier to visually recognize than the characteristic correction with the current corresponding to the gradation 0. desirable. If the current value of the current source Irst for initialization is set to a middle to high gradation, display unevenness in gradations that are easily visible is not given priority, and mobility variations occur in gradations that are difficult to visually recognize. However, the display unevenness level in all gradation areas was improved by utilizing the fact that it is difficult to see. A feature is that the current Irst is allowed to flow during the canceling operation of the characteristic variation of the driving transistor so that the current region where the characteristic cancellation is most frequently performed can be changed.

  The circuit in FIG. 33 is characterized in that it has a voltage source 331 for initialization and a switching unit 333 for switching between the voltage source 331 and the current source 312 with respect to the configuration in FIG. This is because when the voltage of the transistor 11a is changed by the current source 312, it takes time until the current flowing through the driving transistor 11a changes to Irst in the case of a pixel displaying black one frame before, and the writing period 321. This is to solve the problem that the gate voltage of the driving transistor 11a is not easily Vs-Vt1. As the drain current of the driving transistor 11a increases, the gate voltage of the driving transistor 11a in the writing period 321 is easily changed. As the current flows more, the charge / discharge speed of the charge in the storage capacitor 19a becomes faster, and the gate voltage is likely to change. Therefore, a voltage source 331 is prepared for the purpose of improving the change speed of the gate voltage. The voltage source 331 is changed to the current source 312 at the beginning of the writing period 321, and the low voltage (in the case of the circuit configuration of FIG. By supplying the voltage to the driving transistor 11a, the drain current of the driving transistor 11a is increased at the beginning of the writing period 321 so that the canceling operation by the reset current source 312 is accelerated in the remaining period. I made it.

  FIG. 34 shows the operation of the gate signal and switching means in the circuit configuration of FIG. In the period 341 in which the voltage source is supplied in the writing period 321, the gate voltage of the driving transistor 11a becomes Vrst. The lower the voltage Vrst, the faster the change in the gate voltage when the switching means 333 switches to the current source 312. However, if the voltage Vrst is too low, the difference in the gate potential from the predetermined gradation becomes too large. There is a possibility that the voltage cannot be changed to the value. Therefore, Vrst is preferably about (voltage during white display) to (voltage during white display −5 [V]). In the subsequent period 342, the gate voltage changes to Vs−Vt1 based on the current signal 312 and the source signal line voltage Vs written. At this time, the drain current of the transistor 11a is larger than that in the configuration of FIG. 32, and the charge / discharge speed of the charge of the storage capacitor 19 is increased. Therefore, the speed changing up to Vs−Vt1 is the voltage application period 341. Even if it is included, the speed is increased and the characteristic can be corrected in a shorter time.

  FIG. 35 shows a circuit configuration in which the gate signal lines are individually controlled by the transistors 11e and 11d. In one pixel, one frame includes a reset period 361, a video signal writing and characteristic cancel period 362, a non-light emission period 363, and a light emission period 364. There are two power sources for initializing (resetting) the driving transistor 11a: a voltage source 331 and a current source 312, and a reset period in which the voltage source 331 is applied is 365, and a reset period in which the current source 312 is applied is 366. And In the reset period 361, the driving transistor 11a is initialized based on the current output from the current source 312, and the reset voltage and current are written to the pixels by using the same reset line 311 in the same column. It is necessary to carry out within the scanning period. The video signal writing and characteristic canceling period 362 need to be performed within one horizontal scanning period because the voltage corresponding to the video signal is supplied from the same source signal line 18 in the same column. When reset and characteristic cancellation do not take time, the reset period 361, video signal writing, and characteristic cancellation period 362 may be performed within one horizontal scanning period.

  The method of this embodiment is characterized in that the initialization of the gate voltage of the driving transistor 11a is performed using not only the voltage source 331 but also the current source 312. As shown in FIG. 36, in the period 365 of the reset period 361, the gate voltage of the driving transistor 11a is initialized to Vrst by the voltage source 331 as in the conventional case. At this time, the transistors 11e and 11b may be turned on or off by the gate signal lines 17e and 17c, but at least one of the transistors 11e and 11b is prevented from flowing through from the Vdd power supply to the Vrst power supply due to the characteristics of the driving transistor 11a. The transistor is preferably turned off. In this embodiment, a period 366 is further provided between the reset periods 361, the connection of the switching unit 333 is switched, and the driving transistor 11a is initialized by the current source 312. The transistors 11f, 11b, and 11e are turned on so that the current of the current source 312 becomes the drain current of the driving transistor 11a. The current value of the current source 312 is preferably set to a voltage such that the gate voltage of the driving transistor 11 a is near Vrst of the voltage source 331 in the period 366. Since there is a variation in characteristics of the driving transistor 11a, the average voltage of the pixels formed in the EL display device may be Vrst. During the period 366, the gate voltage of the driving transistor 11a changes to Vrst + ΔV1. Here, ΔV1 corresponds to the gate voltage variation when the current (Irst) of the current source 312 is passed.

  In the video signal writing and characteristic cancellation period 362, a video signal is input from the source signal line 18, the transistor 11b is in the on state, and the transistor 11f is in the off state, so that the gate voltage of the driving transistor 11a is equal to the video signal voltage. Vs changes until Vs−Vth (Vth is a threshold voltage). Vs−Vth is when the characteristic cancellation period is a sufficiently long time, and since it is necessary to end the period 362 in one horizontal scanning period, the characteristic cancellation period can be only about 40 μsec.

  Therefore, the gate voltage can change only to (Vs−Vth−ΔV2) in the conventional configuration (FIG. 41) in which the period 366 does not exist. The potential change for ΔV2 is insufficient. Therefore, the drain current ΔI2 of the driving transistor 11a flows as much as ΔV2. ΔI2 varies due to characteristic variations of the driving transistor 11a. Due to this influence, variations occur in the current flowing through the EL element 15 and display unevenness occurs.

  Here, if the period 366 exists, the potential at the end of the period 361 is shifted by ΔV1, so that the gate voltage at the end of the period 362 is (Vs−Vth−ΔV2 + ΔV1). Since the gate voltage of the transistor 11a is shifted by ΔV1 as a result of applying a constant current from the current source, in the case of the driving transistor 11a having a large ΔI2 with respect to ΔV2 (a transistor through which current flows well), ΔV1 becomes large and ΔV2 In the case of the driving transistor 11a having a small ΔI2 with respect to, ΔV1 is small (including a negative value). In a pixel in which a large amount of current flows due to display unevenness (ΔI2 relative to ΔV2 is large), ΔV1 increases and the gate voltage increases. In a pixel with a small current, ΔV1 becomes small, so the gate voltage decreases. In a pixel in which current easily flows, the gate voltage of 11a rises and the current flows, and in a pixel in which current does not easily flow, current flows due to a decrease in gate voltage. It becomes a direction which becomes small, and it becomes possible to improve display unevenness.

  In FIG. 40, when the reset period 361 is realized with only the voltage source for the driving transistor 11a having different current-voltage characteristics (a) and when the current source is used (b), the video signal writing and characteristic cancellation are performed. The difference in current value after the end of the period 362 is shown.

  In FIG. 40A, since the driving transistor 11a is initialized only by the voltage source, the gate voltage is Vrst in the driving transistors 11a of the two pixels having the characteristics 401 and 402. Is different from Irst1 and Irst2. In the characteristics 401, the points 403a and 402 are points 403b. Next, in the video signal writing and characteristic cancellation period 362, the video signal is written to the source potential of the driving transistor 11a, and the gate potential tends to change to the point where the threshold voltage is lowered from the source potential by the threshold cancel operation. Since the time required for the change takes about 100 μs, the change does not sufficiently change to the cancel voltage 406 in one horizontal scanning period, but changes to a point indicated by 405. The amount of voltage change is determined by the flowing current and stray capacitance, and is expressed by voltage change amount ΔV = i × T / C (where i: current flowing, T: length of cancel period 362, C: stray capacitance), 403a Since the point has more current than the point 403b, the transistor indicated by the curve 401 has a larger potential change amount, and the voltage changes to V2. In the curve 402, the amount of change is small because the current at the point 403b is small, and the voltage changes only up to V1. The drain currents at the points 405a and 405b are different between I2 and I1, and this difference may be visually recognized as display unevenness. On the other hand, when the reset is performed using the current source, as shown in FIG. 40B, at the end of the reset period 361, the drain current is different from Irst and the gate voltage is different between the curves 401 and 402, and Vrst1, Vrst2 It becomes. (Points 404a and 404b) Next, when canceling in the video signal writing and characteristic canceling period 362, the flowing current is the same as Irst, there is no variation in stray capacitance, and the canceling time can be set the same because it is the same panel. Therefore, ΔV is the same for the curves 401 and 402, and becomes the voltages V1 and V2 shifted by the same potential. (Points 405c and 405d) The drain currents at this time are both I1, and even if there is a difference in the characteristics of the driving transistor 11a, the written current values after the characteristic cancellation period 362 are the same, and display unevenness is eliminated. The configuration was realized.

  Even if the gate voltage of the driving transistor 11a is completely different from the canceled voltage due to the short cancellation period, the gate voltage of the driving transistor 11a is individually set with a constant current in the reset period. A configuration with small variations could be realized. There is no period 365, and the reset may be performed only with the current source in the period 366. However, since it takes time to change the gate voltage to the vicinity of the Vrst voltage by the current source 312, the voltage source 331 previously supplies the voltage to the vicinity of Vrst. It is preferable to reset the current source 312 after changing the voltage. If the reset period 361 is long and the voltage can be changed to Vrst + ΔV1 only by the current source 312, the voltage source 331, the switching unit 333, and the period 365 may be omitted.

  In the EL display device having the pixel circuit configuration of FIG. 35, a plurality of source signal lines are prepared for pixels in the same column, and video signals are written from different source signal lines in pixels adjacent in the source signal line direction. Thus, it can be implemented in combination with a configuration in which the writing time is increased. For example, FIG. 37 shows a circuit in the case where two source signal lines are prepared. If two source signal lines 18 are prepared, the gradation signal applied to the source signal line 18 changes every two horizontal scanning periods as described with reference to FIGS. The signal writing and characteristic cancellation period 362 can be expanded to a maximum of two horizontal scanning periods. For example, a driving waveform as shown in FIG. 38 can be realized. By extending the period 362, the time for changing the gate voltage of the driving transistor 11a can be increased, the absolute value of the error ΔV2 can be reduced, and cancellation can be performed more accurately.

  In the configuration of FIG. 37, one reset line 311 is provided for one column of pixels. However, if there are a plurality of (for example, two) reset lines 3 as in the case of the source signal line 18, the reset period 361 is also at most two horizontal scanning periods. The reset voltage can also be set to a voltage according to the characteristics of the driving transistor 11a.

  In the configuration of FIG. 37 and the configuration of FIG. 35, the current source 312 and the voltage source 331 are connected to the reset line 311 via the switching unit 333. However, even without the voltage source 311, within one horizontal scanning period. If the gate voltage of the driving transistor 11a can be changed by the current source 312 until the predetermined initialization potential is reached, the reset period 361 can be configured only by the current source. At this time, the operation is performed for one frame period as shown in FIG. Although the change takes time due to the reset (initialization) operation using only the current source 312, the gate voltage of the driving transistor 11a converges to Vrst + ΔV1. Even when the voltage source 331 is used together, as shown in FIG. 36 and FIG. 38, it has the same value as Vrst + ΔV1 and is the same regardless of the effect of initialization.

  Further, the current source 312 may be changed according to the video signal. For example, if the current value is increased at the time of high gradation and the current value is decreased at the time of low gradation, the characteristics can be canceled near the display gradation, and the unevenness can be further reduced.

  Since the organic EL has different light emitters for each display color, the light emission efficiency may be different for each color. For example, as shown in FIG. 42, the efficiency of blue is low with respect to red and green, and the relationship between current and luminance shown in 421 is required, and it is necessary to increase the current value with respect to the relationship between red and green 422.

  In the pixel configuration having an operation of canceling the characteristics of the driving transistor 11a as shown in FIGS. 1 and 11, the threshold variation is corrected, but the correction range is limited for the mobility variation. Therefore, correction may be possible depending on the current value, or correction may be insufficient. After the reset voltage is input by initialization, the gate voltage of the driving transistor 11a is corrected for each pixel in a limited characteristic cancellation period. If the characteristic cancellation period is short and does not change to the final state sufficiently, The correction voltage is stored for each pixel. If the gray level is in the vicinity of this voltage value, the correction is sufficient, but if it is a distant voltage (current value flowing in a distant EL), drive current variations due to mobility variations occur, and correction is not possible. It will be enough. Generally, if the reset voltage is low, the characteristics are canceled from a state where the current is large, so that correction on the high gradation side is easy, and if the reset voltage is high, correction on the low gradation side is easy. Therefore, the correctable range is a range as indicated by 441 in FIG.

  At this time, in the case of the display element having the characteristics shown in FIG. 42, it is difficult to bring the entire current range into a correctable state even if the reset voltage is adjusted.

  Therefore, display unevenness is prevented by changing the reset voltage for each display color and setting an optimum reset voltage for each color. For example, when red and green are set to a reset voltage of −1 V, it can be seen that the current variable range of the red / green element of 0 to 0.5 μA falls within the correctable range 441 as shown by the line 443. In the case of -1V in blue, since the correction range is insufficient, if the reset voltage is lowered and set to -2V, the high gradation side is applied to the correctable range 441 with respect to the current range indicated by 444. On the low gradation side, the undercorrected region 442b is below the current value indicated by 448. However, the blue visibility is low, and even if the correction is insufficient, the human eye cannot visually recognize the unevenness. There is no. In green, the visibility is good even at a low gradation, and when the reset voltage is set to −2 V, display unevenness at a low gradation can be seen. Therefore, as shown at 443, a reset voltage that falls within the correctable range 441 is set even at a low gradation. There is a need.

  Therefore, as shown in FIG. 43, the reset voltage source 371 is arranged differently for each display color, and an optimum voltage is inputted to each display device, so that a display device using display elements having different current values can be used. Even if configured, a display device with a wide correction range can be realized.

  In FIG. 43, three voltage sources 371 are prepared. However, in the characteristics shown in FIG. 42, red and green are used in common and the number of voltage sources 371 is four, or four or more color display elements are formed. More than one voltage source may be provided.

  43, the source signal line voltage output unit 431 may be formed as a source driver IC, or may be formed on the array substrate with low-temperature polysilicon. When the signal line selection drive is performed, the method can be similarly performed by forming only the signal line selection circuit on the array substrate.

  Similarly to the signal line selection circuit, only one voltage source 371 in FIG. 43 may be prepared, and a different voltage value may be output depending on display timing. For example, when the display color is the same along the gate signal line and the display color is different for each gate signal line, the display color changes for each horizontal scanning period, so the voltage value is changed for each horizontal scanning period. Thus, the three voltage sources may be substituted.

  Although the description has been made with the p-type driving transistor 11a, the present invention can be implemented with the n-type driving transistor 11a. In the case of n-type, the gate voltage decreases as the current decreases, and increases as the current increases. Therefore, the present invention can be similarly applied if the reset voltage is reversed.

The correctable range is determined from the relationship between the reset voltage and the source signal line voltage (= current flowing through the EL). If the difference between the reset voltage and the source signal line voltage is the same for each color, display can be made with the same reset voltage. It becomes. Since it is difficult to align the characteristics of the EL elements, in the present invention, the voltage of the EL power supply line 452 is individually set for each display color (VddR, VddG, VddB), and the voltage of the EL power supply line 452 is used as a reference. The difference between the white and black voltage fluctuation ranges of the gate voltage of the driving transistor 11a that determines the current flowing through the EL element 15 based on the gate voltage thus reduced is reduced. For example, in the case where the conventional configuration has a voltage range with respect to gradation as shown in FIG. 47A, the gradation range of green and red (472, 473) is reduced by 1 V and FIG. Change to such a range. When the initialization voltage is set so that the correction is optimal when the gate voltage is 1 to 2 V, the same power supply 451 is used to initialize a display element that performs display with a different current for one initialization voltage. Is possible. (Fig. 45)
In order to change the gradation range, at least two EL power supply lines 452 are prepared as shown in FIG. 45 (three types for each display in FIG. 45), and different voltage values are input.

  Since the voltage output to the source signal line is different for each display color, the gamma generator 453 has a configuration that can output a different range for each display color. When the source signal line voltage output unit 431 is configured as shown in FIG. 45, even if the same gradation data 455 is input for each display color, different voltage outputs are realized by the gamma generation unit 453 and the digital / analog conversion unit 454. The gradation voltage range (474 to 476) shown in 47 (b) can be realized.

  Note that the source signal line voltage output unit 431 in FIG. 45 has a configuration having an output unit for each source signal line 18, but can be similarly realized even with a configuration having a signal line selection circuit. Even if there is one gamma generator 453, if writing to pixels having the same gamma characteristic is performed during one horizontal scanning period, the output voltage value of the gamma generator 453 may be changed at each output timing.

  The correctable range was determined by the difference between the source signal line voltage and the reset voltage. This is because the characteristic cancellation period is not sufficiently long and the amount of voltage change from the reset potential is limited. The shorter the characteristic cancellation period, the higher the correction capability is when the source signal line voltage is closer to the reset potential.

  Therefore, in the present invention, as shown in FIG. 46, a configuration is considered in which gate signal lines 17c are prepared for the number of display colors so that on / off control of the transistor 11b for canceling characteristics can be individually controlled for each display color.

  In the case of the display element having the gate signal line range shown in FIG. 47A, if the source signal line is considered to be higher than the gate signal line by the threshold voltage, and the voltage rises uniformly, the maximum potential of each color However, the minimum potential is different by about 1.5V only for blue. Blue requires correction up to the low voltage range, but green and red do not require correction in the low voltage range. Utilizing this, the characteristic canceling period is set longer than blue with respect to red and green so that the voltage in the correctable range is increased so that correction can be made over all gradations. The blue color is short, and even if correction is not possible in the low gradation region corresponding to the vicinity of 4V of 471, correction is possible in the region of 2V or less where unevenness is conspicuous.

  It should be noted that even if characteristic correction is possible in the entire blue gradation range 471, the configuration of FIG. 46 can be used. By aligning the range in which characteristics can be corrected to the center of 472 and 473, even if the lowest maximum voltage is shifted, correction can be performed with a sufficient margin, and even if the correctable range is reduced, it is still sufficient. It is within the correction range.

  The EL power supply 452 may be common to each color or may be set separately. This is because even with the configuration of FIG. 47 (b), the characteristic canceling time can be realized by reducing only red and green by the voltage shift. Further, the source signal line selection drive can be similarly realized.

(16) A circuit capable of changing the amount of change due to penetration due to capacitive coupling of the gate voltage of the driving transistor 11a FIG. 48 shows the capacitive coupling of the gate voltage of the driving transistor 11a by the gate signal line 17c for each display color. The circuit which can change the variation | change_quantity by penetration is shown.

  As a method of changing the penetration amount for each display color, the capacitance value of the capacitor 481 is set to a different value for each display color. If the capacitance differs between 481a and 481b, 481c, the ratio of the capacitance 481 to the total capacitance of the signal connected to the gate electrode of the driving transistor 11a when the potential of the gate signal line 17c rises from the on state to the off state. As a result, the gate voltage of the driving transistor 11a after the video signal writing and the characteristic cancellation period 362 is different even when the same signal voltage is written. The voltage increases as the capacitance value of the capacitor 481 increases. Since the display is performed based on the gate voltage after the voltage fluctuation, it is necessary to lower the voltage to be written in the video signal 362 in advance for a color having a larger voltage increase amount. When this is utilized, when the image signal amplitude of each color when the penetration is common to all colors is FIG. 49A, if the capacitance of the pixel capacitance 481c corresponding to blue is reduced, FIG. 49B is obtained. As shown, the voltage range required for writing changes. The voltage in the blue gradation range indicated by 494 increases, and the average voltage level can be adjusted to the voltage range indicated by red and green 495 and 496.

  The gradation range that can be corrected by making the difference between the source signal line voltage and the reset voltage close to each other regardless of the color can be expanded. In particular, when there is no common voltage in a completely different voltage range for each color, a range from the maximum voltage to the minimum voltage for all colors is necessary. The difference in the minimum voltage is reduced, the correction range can be reduced, and there is an advantage that production can be performed even in a process having a larger variation.

  Although the gate signal line 17c for controlling the transistor 11b is an example prepared for each display color, it may be common. This is because the penetration amount can be changed for each color only by changing the capacitance value.

  When the gate signal line 17c is different for each display color, the penetration voltage can be changed for each color even if the difference between the high level and the low level of the gate signal line 17c is changed for each color. Since the penetration voltage is determined by the capacitance ratio and the potential change amount, it is effective to change the signal voltage. A method of changing the characteristic cancellation period for each color can be used together.

  The change of the video signal range can be made common even if the ratio of the channel width to the channel length of the driving transistor 11a is changed for each color. For example, as shown in FIG. 50A, when the voltage range is such that only the blue pixel 501 is shown, the ratio of the channel width is increased so that only the driving transistor 11a of the blue pixel flows (for example, 0). .7) and FIG. 50 (b), the gradation voltage range can be made uniform, and the display unevenness can be set by setting the cancel period and the reset voltage so that correction can be made within the voltage range of 1 to 4V. An EL display device without the above can be realized.

  When performing signal line selection driving, a voltage value is written to the source signal line 18, a video voltage is taken into the pixel based on the charge stored in the floating capacitance of the source signal line, and a signal is written to the pixel. Yes. The voltage written to the pixel at this time is the charge stored in the capacitor (capacitor 481, storage capacitor 19, etc.) existing on the wiring connected via the transistors 11 c and 11 b, 11 a and the floating capacitance of the source signal line. The stored charge is redistributed and written. That is, the voltage output from the source driver or source signal line voltage output unit 431 and the voltage actually written to the pixel 16 are different, and the voltage of the initialization voltage 451 is lower than the voltage applied to the source signal line 18. In this case, a lower voltage is written than when a voltage is directly applied to the pixel 16 without selective driving, and the luminance increases.

  In order to prevent the increase in luminance, a method is known in which the voltage of the driving transistor 11a is shifted in the black voltage direction by punching.

  In order to reduce the amount of change in the voltage written to the pixel, there is another method such as increasing the capacity of the source signal line 16. Further, there is a method in which an additional capacitor 19b as shown in FIG.

  In FIG. 51, an additional capacitor 19b is provided, and a video signal holding capacitor 511 having a capacitance value changed for each color is formed. When the video signal is written to the source signal line 18 and the pixel 16 by changing the capacitance for each color, the floating capacitance of the source signal line and the video signal holding capacitor 511 are changed according to the video signal. Charge is charged. At the time of writing, the transistor 11 is configured such that 11c is conductive and 11b is nonconductive.

  When the characteristic cancellation period starts, the transistor 11b is in a conductive state, and the source signal line voltage output unit 431 and the source signal line 18 are separated by the switching unit 512, the charge stored in the storage capacitor 19 and the capacitance The charges charged in the 511 and the source signal line stray capacitance are redistributed and stored. At this time, the gate voltage of the driving transistor 11 a is lowered by the charge of the storage capacitor 19 compared to the case where the storage capacitor 19 is not provided. The amount of decrease is determined by (storage capacity) / (storage capacity 19 + source signal line floating capacity + capacitance 511). Therefore, if the capacitance of the video signal holding capacitor 511 is changed for each display color, the amount of voltage drop compared with writing differs for each display color. If only the pixel corresponding to blue is made small, the voltage drop amount for only blue increases. Therefore, it is necessary to increase the voltage input to the source signal line. As shown in FIG. 42, the blue color requires a large amount of current to flow, and the source signal line voltage accordingly requires a lower voltage than red-green. Since the source signal line voltage can be increased by changing the capacitor 511, a low voltage value is not necessary, and the dynamic range of the source driver can be reduced.

  Also, if the white side or black side voltage in the voltage range can be made common to all the pixels, at least one of the white side and black side voltages of the gamma generation circuit of the gamma generation unit 453 of the source signal line voltage output unit 431 will be described. The generation part can be made common to all colors, and the circuit scale can be reduced.

  Furthermore, in the three-signal selection drive, if the signal voltage is written in the source signal line and the video signal holding capacitor 511 in the order of red to green to blue, the blue color is written in the trace with respect to the red color. The holding time may be short, and there is no problem in reducing the capacity.

  If the area per pixel is determined in the pixel circuit formed in the pixel 16, the number of transistors 11 that can be formed, the amount of wiring, and the capacity are limited. If the capacitor 511 is small, it is possible to deal with smaller and finer pixels, and by using the space that can be made by reducing the blue capacitor 511, a circuit of red-green pixels is formed, and the larger capacitor 511 is replaced with red or green. There is also an area advantage that the capacitor 511 can form a desired value even with smaller pixels.

  Changing the channel width / channel length of the driving transistor 11a for each color also allows the space of the driving transistor 11a to be changed for each color, so that an empty space can be used effectively for each color, and the same applies to the capacitor 481. is there.

  In FIG. 51, the EL power supply (Vdd) 452 is individually set for each color, but the same voltage may be used. The same applies to the gate signal line 17c that controls the transistor 11b.

  Since the effect of changing the gate voltage of the driving transistor 11a after the characteristic cancellation for the same source signal line voltage input is the same, the capacitance of the capacitor 481 may not be individual for each color, or may be changed for each color. You may implement in combination with the gate voltage rise effect in the capacity | capacitance 511. FIG. As long as the same effect as the gate voltage increase effect of the capacitor 481 can be obtained, the capacitor 481 may be omitted.

  For the capacitor 481, one electrode has the gate voltage of the driving transistor 11a, and the other electrode has a voltage rise after the end of the characteristic cancellation or signal line writing or at the same time as the end of the light emission period. If it is connected to a signal line that causes the occurrence of the problem, it may not be the gate signal line 17c. For example, it may be connected to the gate signal line 17a, or a dedicated signal line may be wired to apply a changing voltage waveform.

  In addition to the pixel configuration described in the present invention, a pixel configuration using current driving and a pixel configuration in which writing is performed using both current driving and voltage driving can be implemented in the same manner.

(17) Correction of initialization voltage (17-1) Problem FIGS. 52A and 52C show driving transistors in the video signal writing and characteristic cancel period 362 in black display and white display, respectively. The change of the gate voltage of 11a is shown. In the reset period 361, the voltage value of the initialization voltage 451 is set to -2V, the voltage applied to the source signal line 18 during black display is set to 4V, and the voltage applied to the source signal line 18 during white display is set to 1V.

  During black writing, as shown in FIG. 52A, the source electrode is at the potential indicated by 522a. The gate voltage is a curve indicated by 521a. At this time, the gate-source voltage of the driving transistor 11a is 6V, a sufficient initial drain current flows at the start of characteristic cancellation (FIG. 52B), and the voltage of the gate electrode changes to a predetermined voltage by time t1 (this Case 3V). The potential difference between 521a and 522a after the elapse of time t1 corresponds to the threshold voltage.

  On the other hand, during white writing, the source electrode potential is 522b and the gate electrode potential is 521b. At the start of the characteristic cancellation, there is only a potential difference of 3V, and the drain current of the driving transistor 11a at the start of the characteristic cancellation is smaller than that in FIG. 52B (FIG. 52D), and the gate voltage after the characteristic cancellation (this It takes time to change up to 0V).

(17-2) Solution In this embodiment, as shown in FIG. 53, the initialization voltage 451 applied in the reset period 361 is changed according to the source signal line voltage.

  53A, when the gate voltage 531 during the reset period when the source signal line is 4V is −2V, FIG. 53B shows the gate voltage 531 during the reset period when the source signal line is 1V. The change of the gate voltage when it is set to -5V is shown. According to FIG. 53, the gate-source voltage of the driving transistor 11a at the start of the characteristic cancellation is the same, and the time for changing to the voltage after the predetermined characteristic cancellation can be realized at t1. Then, the time can be shortened from t2 to t1. If the value of the initialization voltage 451 is set so that t1 is 20 μsec or less, signal line writing and characteristic cancellation can be performed within one horizontal scanning period.

  In order to make the characteristic cancellation period constant regardless of the gradation, a voltage lower than the source signal line voltage by a certain value may be applied as the initialization voltage 451 as shown in FIG. That is, (initialization voltage) = (source signal line voltage) − (constant voltage) may be set. FIG. 58 shows the relationship when the constant voltage value is 4V.

  54 and 55 show circuit configurations for supplying a voltage obtained by subtracting only a certain voltage.

(17-3) First Configuration of Pixel FIG. 54 is a configuration in which the reset line 311 and the source signal line 18 are coupled by a capacitor 543 and a voltage obtained by subtracting a constant voltage from the source signal line 18 can be applied.

  The switching units 544 and 545 are operated at the initial stage of the reset period 361 or before the reset period 361, and the capacitor 543 is charged by the power source 541 and the power source 542. The voltage difference at this time is a constant voltage to be subtracted. When a voltage as shown in FIG. 53 is applied, the power supply of the power supply 541 may be set to a value 6V lower than the power supply 542. Note that in the case where the amount of subtraction from the source signal line voltage is reduced due to the stray capacitance of the reset line 311, the potential difference between the power sources 541 and 542 may be increased in advance.

  The switching units 544 and 545 are operated at the start of the reset period 361 or before the end of the reset period 361, the voltage is supplied from the source signal line 18 to the capacitor 543, the capacitor 543 and the reset line 311 are connected, and the reset period In at least the final state of 361, a voltage obtained by subtracting a constant voltage from the source signal line voltage must be supplied to the reset line 311 and applied to the gate electrode of the driving transistor 11a via the transistor 11f.

  Note that when the switching unit 545 selects the source signal line 18, the voltage output of the source signal line voltage output unit 431 may or may not be present. If not, the video signal voltage may be stored in the stray capacitance of the source signal line 18. If the capacity is insufficient and voltage cannot be supplied to the reset line 311, there is a method in which the capacity 546 is formed to increase the amount of accumulated charge.

(17-4) Second Configuration of Pixel As shown in FIG. 55, an initialization power supply means 551 for newly forming an initialization power supply and supplying a voltage corresponding to the voltage of the source signal line 18 is provided. There is also a method of providing.

  The output voltage of the source signal line voltage output unit 431 may be detected, the voltage value may be subtracted and output, or a video signal may be detected, a desired reset voltage determined from the video signal, and output. is there.

(17-5) Third Configuration of Pixel FIG. 56 shows a configuration in which the reset voltage can be changed according to the video signal voltage by changing the pixel circuit.

  FIG. 57 shows the input waveform of the gate signal line 17.

  First, in the reset period 361, the transistor 11f is turned on, and the voltage of the reset power supply 451 is applied to the gate electrode of the driving transistor 11a.

  Next, in the second half (571) of the reset period 361, the switches 11e and 11c are turned on. At this time, the voltage of the electrode that is not in contact with the driving transistor 11a of the capacitor 19a becomes the voltage applied to the source signal line 18 from the power supply Vdd, so that the voltage change and the capacitance 19 and the gate electrode of the driving transistor 11a are applied. The gate voltage of the driving transistor 11a changes according to the capacitance ratio of the stray capacitance of the connected wiring.

  Compared to the configuration so far, the change is that the video signal is taken into the pixel 16 from the source signal line 18 in the second half (571) of the reset period. Depending on the voltage difference between the source signal line and the Vdd power supply, the gate voltage of the driving transistor 11a in the second half of the reset period 571 is different.

  As a result, the lower the source signal line 18 voltage is, the lower the voltage applied to the initialization voltage, and there is an effect of changing the initialization voltage in accordance with the video signal.

  Further, at the time of high gradation display in which the source electrode of the driving transistor 11a is applied at a low voltage, a voltage lower than that of the source electrode is applied to the gate electrode, so that a drain current flows during the characteristic cancel period 362, This makes it easier to compensate for variations in transistor characteristics.

(17-6) Modified Example Further, as shown in FIG. 59, a value obtained by subtracting a constant voltage from the source signal line voltage as indicated by a dotted line 581 is not input as an initialization voltage, but is further indicated by a solid line 591. In addition, the initialization voltage is applied at a lower voltage as the voltage is lower (high gradation), and a voltage that is not so different from the source signal line voltage is applied at the high voltage (low gradation).

  In this way, the voltage between the source and gate of the driving transistor 11a at the start of the video signal writing and characteristic cancellation period 362 becomes larger as the high gradation video signal is input, and the threshold cancellation is performed during the same characteristic cancellation time. When performing an operation in which the gate voltage is increased in order to perform the operation, the gate voltage does not rise to the black display state even at the time when the characteristic cancellation period 362 ends on the high gradation side where the gate voltage before the characteristic cancellation is low. Threshold cancellation is performed in a state where the current flows. On the other hand, on the low gradation side, the gate voltage of the driving transistor 11a in the initial stage of the characteristic cancellation period 362 is higher than that on the high gradation side, and at the end of the characteristic cancellation period 362, a current does not flow. Threshold cancellation is performed. Therefore, characteristic cancellation is performed in a state where current flows at a high gradation and no current flows in a low gradation, and threshold cancellation is performed at a gradation closer to the display gradation. It becomes possible to cancel the variation of the driving transistor 11a.

(17-7) Fourth Configuration of Pixel The pixel configuration as shown in FIG. 60 can be similarly implemented. A similar effect can be obtained by changing the voltage value of the power supply 451 in accordance with the video signal.

  The same applies to the case where an n-type transistor is used as the driving transistor 11a. The same effect as in FIG. 58 can be obtained by applying a voltage increased by a constant voltage value instead of subtracting a constant voltage value. Also in FIG. 59, weighting at low gradation and high gradation is applied to an n-type transistor. What is necessary is just to change according to current increase / decrease. For transistors other than the driving transistor 11a, n-type transistors can be similarly implemented. This is because the signal waveform of the gate signal line 17 may be reversed.

(18) Individual Control of Gate Signal Line 17 An embodiment in which the gate signal line 17 is individually controlled will be described.

(18-1) First Pixel Configuration FIG. 61 shows a first pixel configuration in which the transistor 11d and the gate signal line 17 for controlling the transistor 11e can be individually controlled.

  By making the gate signal lines 17 individually controllable, it is possible to correct current variations due to variations in mobility of the driving transistor 11a.

  FIG. 62 shows a driving method for correcting current variation due to mobility variation.

  In the reset period 361 and the video signal writing and characteristic cancellation period 362, the video signal writing and the characteristic variation operation of the driving transistor 11a are performed.

  In the video signal writing and characteristic canceling period 362, in the second half period 622, the gate signal line 17e is operated, the transistor 11e is turned on, and current is supplied to the driving transistor 11a from the power supply Vdd. Note that the transistor 11b is conductive and the transistor 11d is non-conductive.

  Then, the current flowing through the driving transistor 11a flows through the transistor 11b to the gate line of the driving transistor 11a of itself and raises the potential of the gate electrode (point b) of the driving transistor 11a.

  In the case where there is variation in mobility of the driving transistor 11a, a difference occurs in current flowing in the driving transistor 11a in the period 622. The more current flows, the greater the potential rise at point b, while the smaller the current is, the less potential rise at point b.

  Accordingly, as the potential at the point b increases, the drain current flowing through the driving transistor 11a decreases. Therefore, even if a difference occurs in the current flowing through the driving transistor 11a in the period 621, the current flows in the period 622. Even when the potential fluctuation at the point b occurs in the direction in which the variation of the transistor becomes smaller and the characteristics of the driving transistor vary, the uniformity of the current flowing through each pixel is improved.

  In the period 621, since the offset cancel operation is performed, the current variation due to the threshold voltage variation of the driving transistor 11a is mainly corrected. In the period 622, the characteristic variation of the driving transistor 11a in which the current variation cannot be corrected even in the period 621 ( For example, it is possible to realize a display device in which variation in mobility is corrected and current variation for each pixel is smaller.

  Note that the gate signal line 17a may be at either the H level or the L level in the period 622 when the source signal line 18 is not connected to the source driver output. When connected to the source driver output, the transistor 11c needs to be in a non-conductive state in order to prevent a short circuit with the Vdd power supply.

  The non-light-emitting and light-emitting states after writing can be realized by making the gate signal lines 17b and 17e non-conductive and conductive in the same operation. Note that the non-light emitting period can be realized as long as one of the gate signal lines 17b and 17e is at a high level and at least one of the transistors 11d or 11e is non-conductive.

(18-2) Second Pixel Configuration The pixel configuration in FIG. 63 is a second pixel configuration in which a transistor 11i for correcting the mobility variation is added.

  In the period 622, the transistor 11i flows current from the power supply Vdd to the driving transistor 11a. Since the transistor 11i only needs to be turned on, the transistor 11e may be off even in the period 622. Thus, the transistors 11e and 11d may operate in the same manner, and the transistors 11e and 11d may be controlled by the gate signal line 17b. A timing chart is shown in FIG. When the gate signal line 17i is turned on in the period 622, variation in mobility can be corrected as in FIG.

  In the light emission period 364, the gate signal line 17i may be in either state. If the transistor 11i is turned on, the resistance value from the power supply Vdd to the driving transistor 11a can be lowered, and the transistor 11e is less affected by the on-resistance. Since the influence of the voltage drop due to the wiring resistance and the ON resistance can be reduced, there is an effect that the voltage of the power supply Vdd can be lowered or the size of the transistor 11e can be reduced.

  Even in the non-emission period 363, if the transistors 11d and 11e are non-conductive by the gate signal line 17b, a path through which the drain current flows can not be formed in the transistor 11a. Therefore, the gate signal line 17i is in any state. Good.

(19) Circuit that compensates for characteristic variation When the display panel has a higher definition, the area per pixel becomes smaller. Therefore, a circuit that compensates for variations in the characteristics of the driving transistor 11a while reducing the number of circuit elements in one pixel is necessary.

  FIG. 65 shows a pixel circuit having a circuit for compensating for the characteristic variation of the driving transistor 11a in the present invention.

  In this configuration, the charge corresponding to the video signal and the charge corresponding to the characteristic variation of the driving transistor 11a are stored in the storage capacitor 19, and gradation display is performed.

  FIG. 66 shows the operation. The writing period 661 includes an initialization period 663, a threshold compensation period 664, and a signal writing period 665. In the initialization period, the first initialization voltage Vrst (657) is applied from the source signal line, and is applied to the gate electrode of the driving transistor 11a via the transistor 11k. At the same time, the second initialization voltage Vini (652) is applied by the transistor 11m. This operation is performed at a high speed because a voltage is directly applied from any power source via the switch.

In this period 663, the EL element 15 can be held in a non-light-emitting state by applying the second initialization voltage Vini (652) so that Vini ≦ Vthold + VSS. (Here, Vtholed is the threshold voltage of the EL element 15)
Furthermore, the difference between the first initialization voltage and the second initialization voltage needs to be larger than the threshold voltage of the driving transistor 11a. This is because in the period 664, it is necessary to sufficiently supply an initial drain current in order to correct the threshold variation of the driving transistor 11a.

  In the period 663, after the gate-source voltage of the driving transistor 11a is set to a voltage sufficiently higher than the threshold voltage, in the period 664, the transistor 11m is turned off. Since the initial value of the voltage applied to the EL element 15 is equal to or lower than the threshold voltage of the EL element 15, no current flows through the EL element 15. Therefore, the driving transistor 11a increases the voltage of the source electrode (node 655) so that the drain current does not flow, and becomes a voltage lower than the first initialization voltage Vrst (657) by the threshold voltage of the driving transistor 11a. . An offset cancel operation can be performed by setting the voltage of Vrst so that the drain current of the EL element 15 and the driving transistor 11a does not flow even if the potential of the node 655 increases. Due to the period 664, electric charges corresponding to the threshold voltage (Vth) of the driving transistor 11a are stored at both ends of the storage capacitor 19, and the voltage corresponds to the characteristic variation.

  Next, in the signal writing period 665, a voltage corresponding to the gray level displayed on the pixel is applied to the source signal line 18 and input to the gate electrode of the driving transistor 11a through the transistor 11k. The potential of the gate electrode is the same as the potential of the video signal data. (For example, Vdata) When the capacitance of the EL element 15 is Coled and the capacitance of the storage capacitor 19 is Cst, a voltage of Coled / (Cst + Coled) × (Vdata−Vrst) + Vth is stored in the storage capacitor 19, and the threshold voltage and the video signal The sum of the voltages corresponding to is the gate-source voltage of the driving transistor 11a. Thus, a video signal is written to the pixel.

  Next, the display period 662 starts, and display according to gradation is performed. At the time of display, the transistor 11k is always in a non-conductive state, and a drain current flows based on the gate-source voltage of the driving transistor 11a according to the charge of the storage capacitor 19. Since the transistor 11k is in a non-conducting state, the gate voltage of the driving transistor 11a can fluctuate, and the potential of the node 655 rises to ensure the voltage (Voled) necessary for the EL element 15, and the EL element 15 In addition, the drain current of the driving transistor 11a flows to emit light. This is a lighting period 666.

  In this pixel configuration, when the transistor 11m is changed to a conductive state with respect to the operation in the lighting period 666, the potential of the node 655 becomes the second initialization voltage Vini (652) regardless of the drain current of the driving transistor 11a. Change. When the voltages Vini and VSS are set so that Vini−VSS <Vthold, no current flows through the EL element 19 and no light is emitted. The drain current of the driving transistor 11a flows from the power supply VDD (653) into the second initialization voltage Vini (652) through the driving transistor 11a and the transistor 11m. Since the EL element 15 does not emit light, the non-lighting period 667 is set in this period. Since the charge held in the storage capacitor 19 does not change during the lighting period 666a and the non-lighting period 667, a lighting period 666b can be further provided after the non-lighting period 667.

  In this pixel configuration, the lighting period 666 and the non-lighting period 667 can be alternately inserted. Therefore, when performing black insertion, black can be divided and inserted, and the non-lighting period 667 is collectively collected. Compared with the method of inserting the flicker, the flicker is less visible.

  Further, the method of providing the non-lighting period 667 with the transistor 11m and the second initialization power supply is such that a transistor is provided in the middle of the wiring of the power supply VDD653 and VSS654, and the drain current is forcibly set to 0 by turning on and off the transistor. Compared with the method in which the element 15 is not made to emit light, the drain current flows through the driving transistor 11a even in the non-lighting period 667, so that there is an advantage that the change in the charge amount of the storage capacitor 19 is small. In other words, the amount of charge in the storage capacitor 19 is more retained, and even if the non-lighting period 667 is lengthened, the same current flows through the EL element 15 even if the lighting period 666 is provided again.

  FIG. 69 shows a pixel circuit configuration for determining whether a current is passed through the EL element 15 by the transistor 11n.

  During the non-lighting period, the transistor 11n is in a non-conducting state, and no current can flow through the driving transistor 11a and the EL element 15. This makes it possible to provide a non-lighting time. In the present invention, since the transistor 11n also has the role of the transistor 11n, it is advantageous in that a circuit inside the pixel can be formed with a smaller number of transistors.

  As another method for providing the non-lighting period, during the non-lighting period 667, the voltage of the power supply VDD (653) is set to a value equal to or lower than (power supply VSS (654) voltage) + (threshold voltage of the EL element 15). There is also a method of applying a voltage to the EL element 15 so that the current does not flow through the EL element 15. In this case, as shown in FIG. 72, it is necessary to have a function (voltage switching unit 721) for switching the voltage of the power supply VDD (653) for each scanning line. There is no need to select lighting or non-lighting for each row, and lighting rows or non-lighting rows may be selected for each of a plurality of rows. In this case, a voltage switching unit 721 may be provided for a bundle of power supply VDD 653 wires for a plurality of rows.

  Further, if the second initialization voltage Vini <VSS (654) is set, a reverse bias is applied to the EL element 15 during the non-lighting period 667, and unnecessary charges accumulated in the organic layer are reversed. There is an advantage that deterioration due to charges discharged by applying a bias and charged in the organic layer can be reduced.

  The lighting period 666 and the non-lighting period 667 in the display period 662 are changed after the signal writing period 665 in the source signal line 18, but may be switched at an arbitrary timing. This is because the operation is not related to the operation of the source signal line 18.

  The threshold compensation period 664 is used in any range of about 5 to 40 μsec. For this reason, if the writing period 661 ends within one horizontal scanning period, a panel with a large number of scanning lines may not have sufficient time to compensate the threshold value.

  Therefore, it has been considered to provide a threshold compensation period over a plurality of horizontal scanning periods. FIG. 67 shows an example in which an address period is provided over four horizontal scanning periods.

  In FIG. 67, in the first horizontal scanning period, an initialization / threshold compensation period 671 is set, and during the signal writing period 661 in FIG. In the signal writing, if the voltage from the source signal line is not written to the gate electrode of the driving transistor 11a by the gate signal line 17k, the last state of the threshold compensation period when the transistor 11m is non-conductive. Thus, the gate and source potentials of the driving transistor 11a are held. When the transistor 11m is in a conductive state, the source potential is the Vini voltage, but the source-gate voltage of the driving transistor 11a is held in the final state of the threshold compensation period. Therefore, the transistor 11m may be in either state.

  In this state, the voltage of the source signal line 18 is maintained until it becomes Vrst (first initialization power supply). When the voltage of the source signal line 18 becomes Vrst, the transistor 11k is turned on again, and the transistor 11m is turned on. The threshold compensation operation is resumed by setting the non-conduction state. When the voltage of the source signal line 18 becomes a video signal, the transistor 11k is turned off again, and the voltage between the source and gate of the driving transistor 11a is held. This operation is repeated until the level at which unevenness cannot be visually recognized by the threshold compensation, and the threshold compensation operation is repeated. This is period 672. Note that the threshold compensation operation may be performed intermittently without being performed in continuous horizontal scanning periods. For example, there is a method of performing once every two horizontal scanning periods. In addition to the threshold compensation period 672, the intermittent implementation may be performed between the initialization / threshold compensation period 671 and the threshold compensation period 672, and between the threshold compensation period 672 and the video signal writing 673. If implemented intermittently, it takes time for the threshold correction operation and there is a problem that the ratio of the display period in one frame becomes small.

  After the threshold correction is completed, the process proceeds to video signal writing 673, the gate signal line 17k is operated in response to the input of the video signal of the corresponding pixel, the video signal voltage is taken into the gate electrode of the driving transistor 11a, and the gradation is adjusted. The corresponding voltage is written in the storage capacitor 19. If there is a period in which the Vrst power is applied to the source signal line 18 in the same horizontal scanning period, the threshold compensation operation may be performed during this period using the period in which the Vrst power is applied. FIG. 67 shows an example in which the threshold compensation operation is performed. When the threshold compensation operation is also performed in the same horizontal scanning period, the writing period can be shortened by one horizontal scanning period.

  In the above invention, the driving transistor is implemented by an n-type transistor. FIG. 68 shows a configuration in the case of implementation by a p-type transistor. Since the direction of current flow and the source / drain electrodes of the transistor are inverted, the power supply voltage is inverted, but the same can be realized. The same applies to the transistors 11k and 11m. The operation of turning on and off is the same, and only the polarity of the signal input to the gate electrode is inverted. The driving transistor 11a can be applied to either p or n type, and the transistors 11k and 11m can be applied to either p or n type.

  The EL element 15 used in the present invention is configured to provide a function as an optical resonator and to effectively extract light having a wavelength necessary for a display device.

  When the EL element 15 is provided with a function as an optical resonator, the optical path length between the reflecting surfaces of the optical resonator is, for example, zero-order interference mode: first peak mode (when the optical path length is increased from zero, the normal direction Is set to an integral multiple of the optical path length at which the intensity of the light traveling first reaches the maximum value first. For example, in the case of a display device composed of blue, green, and red pixels, the blue light pixel has an optical path length within an integer multiple of 66 nm to 87 nm, and the green pixel has a light path length of more than 87 nm. It is set to an integer multiple that is large and less than 113 nm, and in the red pixel, the previous optical path length is set to an integer multiple within the range of 113 nm to 160 nm.

  In addition, the organic layer 702 can be thinned by shortening the optical path length as much as possible, that is, by setting the interference mode to a lower order, ideally setting to the 0th order interference mode. The amount of material to be reduced can be reduced. In addition, in this case, it is easy to optimize the resonance condition in each pixel of the emission color. In addition, the voltage for driving the EL element 15 can be lowered, and the power consumption can be further reduced.

  The previous optical path length is changed by changing the refractive index and thickness of the layer interposed between the reflecting surfaces of the optical resonator. However, in many cases, the refractive index of these layers cannot be changed freely. For example, the refractive index of the material used for the organic layer 702 and the electrode is normally 1.5 to 3.0. Therefore, normally, the previous optical path length is adjusted by the thickness of the layer interposed between the reflecting surfaces of the optical resonator. Note that the refractive index of the material also considers wavelength dispersion.

  The EL element 15 thus designed has a feature that the organic material layer 702 has a small film thickness, thereby increasing the capacitance of the EL element 15.

  When the capacitance Coled of the EL element 15 increases, the voltage Vdata amplitude of the video signal data can be reduced. The voltage applied to both ends of the storage capacitor 19 of the driving transistor 11a is represented by Coled / (Cst + Coled) × (Vdata−Vrst) + Vth, and an attempt is made to store more charge in the storage capacitor 19 in order to increase the current. Then, the value of Vdata may be increased, Coled may be increased, or Cst may be decreased. If the EL element 15 designed in the 0th-order interference mode is used, the Coled becomes larger than the EL element 15 designed in the higher-order interference mode, and the Coled is small, so that the auxiliary capacitance is newly added in parallel to the EL element 15. 65 is eliminated, and the circuit configuration of FIG. 65 can be applied even to higher definition pixels.

  The maximum value of the amplitude of Vdata is determined by the withstand voltage of the source driver IC that supplies the video signal from the source signal line, and 5.5 V is the maximum in the source driver IC in which the timing controller unit is incorporated in the source driver IC. Considering that it is difficult to form a power supply voltage fluctuation applied to the source driver IC or an amplifier that outputs a voltage near the power supply voltage, and in general, about 0.2 V near the power supply voltage has a poor voltage output performance. The maximum usable voltage range is about 5V. When the Vrst power supply is input via the source signal line, voltage input outside the withstand voltage range of the source driver IC cannot be used because a voltage exceeding the withstand voltage may be input to the source driver IC. 0V. Therefore, in order to make the video signal amplitude as small as possible, it is necessary to increase Coled / (Cst + Coled). FIG. 71A shows the relationship with the video signal amplitude. According to this, the value of Coled / (Cst + Coled) needs to be 0.4 or more. Although Coled should be made large and Cst should be made small, the maximum value of Coled is determined by the area (resolution) of the pixel and has the relationship shown in FIG. Cst has a limit in reducing the voltage written in the inter-frame writing period 661, and if the voltage between the frames cannot be held, the EL element 15 at the beginning and end of one frame. Flicker occurs due to a change in the current flowing through the. The retention is preferably 90% or more, and for that purpose, Cst needs to be 0.05 or more.

  In a display device using the EL element 15, in order to prevent burn-in due to initial deterioration of the EL element 15, the EL element 15 is energized in advance at the shipping stage, shipped after initial deterioration, and burn-in is performed. May prevent. At this time, in order to shorten the energization time, it is necessary to flow a larger current than usual to the EL element 15 so that the initial deterioration can be completed quickly. When the display device is formed with the configuration of FIG. 72, if the on-resistance of the switch used for the voltage switching unit 721 is large, the current is increased as the current drop increases in the normal display state even if the potential drop amount of the voltage switching unit 721 is small. The voltage drop at the voltage switching unit 721 increases, and the voltage necessary for lighting the EL element 15 cannot be obtained. In order to cope with this, the on-resistance of the switch used for the voltage switching unit 721 may be lowered. However, when the switch is formed of a transistor, it is necessary to increase the channel width of the transistor. The circuit of the voltage switching unit 721 becomes large. When the voltage switching unit 721 is formed on the array, it is often formed in a portion corresponding to the frame outside the display area, and there is a problem that the area of the frame increases. A large glass area is required with respect to the display area, and it becomes difficult to eliminate as much as possible the frame required for small devices such as mobile phones.

  Therefore, in the present invention, during the energization time for initial deterioration, the voltage (V1) necessary for causing the EL element 15 to emit light and the power source for supplying current to the power source line of the power source Vini (652) are externally supplied. The voltage is not applied to the VDD power supply 653, the switch 11k is in a non-conductive state, the switch 11m is in a conductive state, and the power supply VSS (654) and V1 are applied to the EL element 15 to cause the EL element 15 to emit light. An operation that performs initial deterioration is realized. At this time, since the write operation as shown in FIG. 66 is not performed, it is not necessary to apply the second initialization voltage to the power supply Vini (652) line, and only V1 is applied. If it is unnecessary and a drive circuit for performing initial deterioration is created and applied to the power supply Vini (652), a voltage can be directly applied from the power supply V1 without having a switching function, and a voltage generated by an analog switch or the like. A circuit without a drop can be formed, and the EL element 15 can be turned on with a large current. Since the switching unit 721 is not used at this time, it can be formed with a transistor size that does not cause a voltage drop due to a current in a normal state, and the frame can be reduced. Since the voltage applied to the power supply Vini (652) is the second initialization voltage during normal driving, the drive circuit connected during normal driving applies the second initialization voltage to the power supply Vini (652) from the outside. If so, a normal operation as shown in FIG. 66 can also be realized.

(20) Threshold Correction Function FIG. 81 is an example of a pixel configuration having a threshold correction function of the driving transistor 11a.

65 differs from FIG. 65 in the initialization means for initializing the voltage of the source electrode of the driving transistor 11a. In FIG. 65, a voltage for initialization is applied to the source electrode of the driving transistor 11a using the transistor 11m. However, in FIG. 81, the operation of the transistors 11p and 11q causes the EL power source B (734) to be initialized. ) Is input to the driving transistor 11a from the reset power supply line 731 through the transistor 11q1, and the voltage of the source electrode (node 811) of the driving transistor 11a is set to a low voltage, and at the same time, the source signal line The gate-source voltage is applied to the driving transistor 11a so that the voltage is lower than the first initialization voltage applied from 18 and current flows through the driving transistor 11a. Thereby, initialization is performed. (Corresponding to the initialization period 663)
Next, the operations of the transistors 11p and 11q are inverted, and the EL power source A (732) is input to the drain electrode of the driving transistor 11a. The voltage of the EL power source A is higher than that of the EL power source B, and is applied with a potential difference necessary for the EL element 15 to emit light. If the same voltage as VDD (653) in FIG. 65 is applied to the EL power source A (732), the operation is the same as in FIG. 65, the threshold compensation period 664 is executed, and the video signal is applied to the source signal line 18. Then, the signal writing period 665 is reached.

  In the pixel circuit 16 shown in FIG. 81, four transistors 11 are required per pixel, and there is a problem that an area necessary for forming one pixel increases.

  FIG. 73 shows a circuit in which the area per pixel is smaller and can be applied to high-definition pixels. In FIG. 73, it is considered that the drain electrode of the driving transistor 11a is connected to the red, green, and blue pixels by the common wiring 733, and the transistor 11p and the transistor 11q are shared by the three pixels. The operation is the same as in FIG.

  FIG. 74 shows timings of characteristic cancellation, gradation voltage writing in accordance with the video signal, light emission period, and non-light emission period in the pixel configuration of FIG.

  Writing is performed in a period in which a video signal to be written to the pixel 16a is input to the source signal line 18a. In order to correct the characteristics of the driving transistor 11a, there are a reset period 741 and a characteristic cancellation period 742. During this period, the first initialization voltage (Vrst) is applied to the source signal line 18a. The voltage condition of Vrst is the same as that in FIG. In the video signal writing period 743, a voltage corresponding to the pixel 16a is applied to the source signal line 16a.

  In order to cancel the characteristics, the driving transistor 11a is first reset. (Reset Period 741) At this time, the transistor 11p is turned off and the transistor 11q is turned on by the gate signal line 1 (17p), and the third reset voltage applied to the reset power supply line 731 is applied to the driving transistor 11a of each pixel. Applied. At the same time, the transistor 11k is turned on by the gate signal line 2 (17k), and the first reset voltage is applied to the gate electrode of the driving transistor 11a. If the third reset voltage is applied at a voltage lower than that of the EL power supply B (774), the potential of the node 739 becomes a sufficiently low voltage. At this time, even if it is a reverse bias voltage or a forward voltage, the EL element 15 is applied with a voltage in a state where no current below the threshold voltage flows. At this time, a voltage sufficiently higher than the threshold voltage of the driving transistor 11a is applied to the gate-source voltage of the driving transistor 11a. Next, in the characteristic cancellation period 742, the transistor 11p is turned on and 11q is turned off by the gate signal line 1 (17p), and a drain current flows through the driving transistor 11a. As a result, the potential of the node 739 rises. However, as the potential rises, the source-drain voltage of the driving transistor 11a decreases. When the voltage rises to near the threshold voltage, the drain current stops flowing, and the voltage rise of the node 739 stops. Here, by setting the potential difference between the first reset voltage and the EL power source B (734) to be smaller than the sum of the threshold voltages of the driving transistor 11a and the EL element 15, the storage capacitor 19 is stored in the characteristic cancellation period 742. A voltage corresponding to the threshold voltage of the driving transistor 11a is stored.

  Next, a gradation voltage corresponding to the pixel 16a is applied to the source signal line 18a. (Video signal writing period 743) The voltage of the gate electrode of the driving transistor 11a changes from the first reset voltage to a voltage corresponding to the gradation. On the other hand, the voltage at the node 739 is supported by the stray capacitance of the EL element 15 and is (capacitance of the storage capacitor 19) / (capacitance of the storage capacitor 19 + floating of the EL element 15) with respect to the change amount of the gate voltage of the driving transistor 11a. (Capacity). If the capacitance of the EL element 15 is sufficiently larger than the storage capacitor 19, the voltage change amount of the source signal line 18 a is applied to the storage capacitor 19 as it is, and at the end of the video signal writing period 743, the storage capacitor 19 is driven. The sum of the threshold voltage of the transistor 11a and the signal voltage corresponding to the gradation is applied, and gradation display can be realized while correcting the characteristics of the driving transistor 11a.

  When the writing is completed, a light emission period starts. In the light emission period 744, the operation of the gate signal lines 1 and 2 turns on the transistor 11p and turns off the transistors 11q and 11k. The current flowing between the EL power source A and the EL power source B is controlled by the gate-source voltage of the driving transistor 11a (that is, the electric charge stored in the storage capacitor 19), and the current corresponding to the gradation flows to the EL element 15. When black insertion is performed to improve moving image response, the gate signal line 1 (17p) is controlled, and the EL power source A (732) is changed to the reset power source 731. Applied to a non-light emitting state. (Period 745) Since the method of realizing black is not based on the voltage change of the storage capacitor 19, in the method of the present invention, it is also possible to provide a light emission period 744b after black insertion.

  Although two transistors 11p are shown here, at least one transistor may be provided as shown in FIG. In FIG. 75, the channel size of the transistor 11p can be increased to reduce the on-resistance of the transistor 11p even with a larger current. When the transistors 11p are formed as shown in FIG. 73, the number of transistors of each color pixel can be made the same, and nonuniformity due to differences in signal line coupling due to layout, etc. can be reduced rather than using different layouts for each color. There is an effect that can be done.

  The transistors 11p and 11n may be either p-type or n-type transistors. As shown in FIG. 76, the gate signal line 1 (17p) is connected to the EL power supply A (732) switch 761a and the reset power supply line (731). ) A method of preparing and controlling the connection switch 761b individually may be used. At this time, the inputs of the gate signal line 1A (17pA) and the gate signal line 1B (17pB) are as shown in FIG. Here, a high level indicates that the switch 761 is conductive, and a low level indicates that the switch 761 is not conductive. In the method in which the gate signal line 1 (17p) is divided into two and individually controlled, both the switches 761a and 761b are made non-conductive in the non-light emitting period 745, and a path for passing a current to the EL element 15 is eliminated. There is also. The gate signal 1B (17pB) may be in any state in the non-light emitting period 745.

  The switches 761a and 761b are described as a set of red, blue, and green pixels, but may be shared by a plurality of red, blue, and green. For example, FIG. 78 shows an example in which a set of 2 × (red, green, and blue) pixels is used. In general, n × (red, green, and blue) pixels may be combined into one set.

  Also, as shown in FIG. 82, one red, green, and blue pixels in different rows may be combined into one. In this case, the reset power supply line 731, EL power supply A (732), gate signal line 1A (17pA), gate signal line 1B (17pB), and switches 761a and 761b can be shared by two rows, so it is necessary for each pixel. It is possible to reduce the circuit area. FIG. 83 shows operation waveforms. The gate signal lines 1A and 1B (17p) supply the voltage of the reset power supply line 731 to the driving transistor 11a at least twice in one frame in order to create a reset period for two rows. Initialization is performed on the pixels in the nth row and then in the (n + 1) th row. (For convenience, the n-th row is scanned first.) Since writing of the video signal from the source signal line needs to be performed individually for each row of pixels, the gate signal line 2 (17k) has n rows. And n + 1 rows are controlled separately. With this scanning, the voltage corresponding to the gradation is stored in the storage capacitor while correcting the characteristics of the driving transistors in both the n-th and n + 1-th rows, and light is emitted with a predetermined luminance during the light emission period 744. The ratio of the light emission period in one frame is also the same in the nth row and the n + 1th row, so that a luminance difference between rows does not occur. It should be noted that the present invention can be similarly implemented by forming not only two rows but generally the switches 761 for m rows.

  In the pixel circuit 16, the driving transistor 11a is described as an n-type transistor. However, a p-type transistor can be similarly realized as shown in FIG. Note that the transistor 11k may be either p-type or n-type. It is only necessary to have a function capable of selecting whether or not the voltage of the source signal line is taken into the pixel circuit.

  Furthermore, when the capacitance of the EL element 15 is not large, the same operation can be performed by adding a capacitor 801 as an auxiliary capacitor as shown in FIG.

  As a method for reducing the number of output pads of the driver IC and reducing the cost of the IC, there is a signal line selection drive in which gradation voltages for a plurality of source lines are distributed to a plurality of source signal lines.

  FIG. 84 shows an example in which the signal line selection drive in the pixel configuration of the present invention is applied. The selective driving method according to the present invention has a different circuit configuration by having a function of applying the first reset voltage (Vrst) to the source signal line 18 as compared with the liquid crystal display device. FIG. 84 shows an example in the case of two selection driving (in which two source signal lines are driven for one driver output). The signal line selection circuit 841 has two sets of switching circuits 844 that output either the source driver output 842 or Vrst (657) to the source signal line 18. The two sets of switching circuits 844 perform different selection operations. That is, the source driver output 842 is connected to one of the source signal lines 18 that performs signal line selection, and the Vrst 657 is also connected to one of the source signal lines 18.

  FIG. 85 shows a timing chart of each signal. Data corresponding to the video signal for two pixels is transferred to the source driver output 842 at a double speed in one horizontal scanning period. By the signal line selection circuit 841, Vrst (657) and a voltage corresponding to the video signal are alternately input to each source signal line 18 during one horizontal scanning period.

  Since the timing of capturing the video signal into the pixel 16 differs depending on whether the video signal is the first half of the horizontal scanning period or the second half of the horizontal scanning period, it is necessary to shift the timing of the gate signal line 2 (17k). Therefore, the gate signal line 2 [n] (17k2) is applied to the pixels to which the video signal is input in the first half of the horizontal scanning period, and the gate signal line 2 [n + 0.5] is applied to the pixels to which the video signal is input in the second half. (17k1) is input. The two signals are input with a shift of 0.5 horizontal scanning period.

  The reset period starts when the gate signal line 1 (17p) and the gate signal line 2 (17k) are at a high level. At this time, the voltage of the source signal line 18 is Vrst (657).

The characteristic cancellation period 742 is performed at the timing described as “OC” in FIG. 85, when the gate signal line 1 is at the low level, the gate signal line 2 (17k) is at the high level, and the voltage of the source signal line 18 is Vrst. In addition, the pixel circuit 16 performs an offset cancel operation to correct the characteristic variation of the driving transistor 11a. Thereafter, the video signal is written in accordance with the input of the video signal, and the voltage corresponding to the gradation is stored in the pixel 16. After writing, the lighting operation is started, the EL element 15 emits light, and a predetermined luminance is obtained.

  84, when the signal line selection drive is performed as shown in FIG. 84, the switches 11p and 11q may be grouped for every two red, green, and blue pixels as shown in FIG. Modification examples such as the pixel configurations of 75, 76, and 78 to 82 can be applied.

(21) Method of Supplying Reset Power Supply Voltage to Each Pixel FIG. 87 is shown in FIG. 88 through the reset signal line 871 common to the pixels for one row, with the reset transistor 11q removed from the pixel circuit. In this way, the voltage of the reset power supply 884 is supplied to each pixel.

  In this case, it is sufficient that at least one switch 885 for determining whether or not to perform the reset is provided per row, and one transistor 11q is required for one or a plurality of pixels as shown in FIGS. Compared to the configuration, there is an advantage that the circuit area required per pixel can be reduced. Further, by diverting the wiring between the driving transistor 11a and the transistor 11q to the reset signal line 871, the amount of increase in the wiring space can be reduced.

  FIG. 90 shows a driving method in the circuit configurations of FIGS.

  In the reset period 741, the operation of the gate signal line 17 turns off the transistor 11p and turns on the transistor 11k. At this time, if the switch 885 is turned on, the voltage of the reset power supply 884 is applied to the drain electrode of the driving transistor 11a, and the power supply Vrst (657) shown in FIG. Then, the power supply Vrst (657) voltage is applied to the gate electrode of the driving transistor 11a. If the voltage of the reset power supply 884 is lower than that of the EL power supply B (734), the reset operation can be realized.

  Next, in the characteristic cancel period 742, the switch 885 is turned off, and the switch 11p is turned on by the operation of the gate signal line 17p. When the Vrst power supply is continuously applied to the driving transistor 11a, the driving transistor 11a performs an offset cancel operation.

  Finally, when a signal corresponding to the video signal to be displayed is applied to the source signal line 18, a voltage corresponding to the video signal is written to the pixel 16 via the switch 11k. (Video signal writing period 743).

  The light emission and non-light emission states after the writing is completed are determined by the conduction and non-conduction of the transistor 11p while holding the charge stored in the capacitor 19 of the pixel 16 with the switch 11k being non-conduction. In the non-light emitting period 745, the switch 885 may be in a conductive state or a non-conductive state. In the conductive state, a reverse bias voltage is applied to the EL element 15 and the life of the EL element 15 can be extended. In the non-conduction state, the voltage of the EL element 15 becomes a voltage corresponding to the light emission start voltage, and the potential of the node 811 is maintained at a higher voltage than when reverse bias is applied. As a result, in the process of transition from the non-light emitting period 745 to the light emitting period 744b, the potential change amount of the node 811 is reduced, and a voltage corresponding to a predetermined gradation is quickly applied to the EL element 15 to display the predetermined luminance in a short time. Can be implemented.

  If the load on the source signal line 18 is heavy and a voltage corresponding to a predetermined gradation cannot be written to the source signal line 18 in a short time, the video signal writing period 743 needs to be set long. However, when the video signal writing period 743 is lengthened, depending on the gradation voltage applied to the gate electrode of the driving transistor 11a, a drain current flows through the driving transistor 11a, and the drain current causes a charge to the capacitance component of the EL element 15. Accumulated. At this time, the Vrst voltage is applied as the gate voltage of the driving transistor 11a, and when electric charge is accumulated in the EL element 15, the potential of the node 811 rises and changes so that the voltage applied to both ends of the accumulation capacitor 19 becomes small. To do. If the amount of change is large, the pixel emits light with a lower luminance than the predetermined luminance, and the predetermined luminance cannot be obtained.

  Therefore, as shown in FIG. 91, in the video signal writing period 743, the signal waveform of the gate signal line 2 (17k) is changed, and in the period 911, the switch 11k is turned off, and only the source signal line 18 is supplied from the source driver. In the period 912, the switch 11k is turned on, and the voltage corresponding to the video signal written to the source signal line 18 is taken into the pixel 16 when the video signal is written and the source signal line 18 is written. A voltage corresponding to the video signal is written in the storage capacitor 19. Since only the gate electrode of the driving transistor 11 a and the storage capacitor 19 are charged from the source signal line 18, the load is small and writing can be completed in a short time (1 to 5 μs). In the method of FIG. 90, it is necessary to provide a video signal writing period 743 for about 4 to 20 μs in order to charge the source signal line 18. In FIG. 91, the time during which the drain current of the driving transistor 11a flows is 5 μsec or less at the maximum, and the potential fluctuation amount can be reduced.

  When the number of pixels connected to one source signal line 18 increases, the number of pixels to be written in one frame increases and one horizontal scanning period becomes shorter. In the drive waveform of FIG. 90 or FIG. 91, sufficient time cannot be taken in the characteristic cancellation period 742 and the video signal writing period 743, and the threshold correction operation may be insufficient or the video signal may be insufficiently written.

  In the present invention, in order to lengthen the writing time, as shown in FIG. 92, two source signal lines 18 are provided for one column of pixels, and transistors 11k are connected to different source signal lines 18 in even rows and odd rows. I did it. By alternately connecting the source signal lines, it can be used for writing in the same row for two horizontal scanning periods, and writing can be performed with a drive waveform as shown in FIG. FIG. 93 shows an example in which reset and characteristic cancellation are performed in the first horizontal scanning period, and video signal writing is performed in the next one horizontal scanning period. If each period (741 to 743) is performed between two horizontal scanning periods, the same effect can be obtained even if the period 743 is distributed from the period 731 regardless of the configuration of FIG. According to the method of FIG. 93, since reset, characteristic cancellation, and video signal writing are performed using twice the time, it is possible to realize driving in the pixel configuration of the present invention even in a panel with a shorter horizontal scanning period. It becomes.

  Note that the above-described pixel configuration can be similarly realized by configuring as shown in FIG. 89 even if the driving transistor is a p-type transistor. In addition, the transistors 11k and 11p can be similarly implemented regardless of whether they are p-type or n-type transistors.

  The EL element 15 in the configuration of the present invention has an EL corresponding to a color having a large current value flowing through the EL element 15 at the time of maximum gradation display in order to make the influence of the potential fluctuation of the node 811 in the video signal writing period 743 constant. It is preferable to increase the capacitance of the element 15.

  As an example of changing the capacitance of the EL element 15 for each color, the film thickness of the EL element 15 may be changed for each display color. The element that requires a larger current may be formed thinner.

  Although the EL power source A (732) and the EL power source B (734) are described as being formed in parallel with the gate signal line, they may be formed in parallel with the source signal line 18. The EL power source B (734) may be formed on almost the entire surface in the active area as a common cathode electrode for all the pixels of the EL element 15.

  In addition to providing two source signal lines 18, as shown in FIG. 94, a transistor 11r for applying a power source Vrst (657) to the gate electrode of the driving transistor 11a and an initialization power source line 941 are added, and an initialization power source is provided. If the power supply Vrst (657) is applied to the line 941, in the reset period and the characteristic cancellation period 742, the transistor 11r is turned on so that reset and initialization operations are performed. Since the power supply Vrst is applied to the driving transistor 11a without using the source signal line 18, the timing of the source signal line is as shown in FIG. Accordingly, the video signal writing period 743 can be lengthened, and the characteristic cancellation period 742 can be lengthened. In this example, the characteristic cancellation period 742 is executed within one horizontal scanning period, but the transistor 11r is turned on by the gate signal line 3 (17r) in a plurality of horizontal scanning periods, and a reset period 741 is provided immediately before that. Accordingly, it is possible to set a characteristic cancellation period of one horizontal scanning period or more. Note that the gate signal line 2 (17k) is an example in which the switch is in a conductive state only during the period 912. However, when the potential fluctuation of the node 811 is small, the period 911 is eliminated and the video signal is written in the horizontal scanning period. In the meantime, the gate signal line 2 (17k) may turn on the transistor 11k to write a video signal to the pixel.

(Example of change)
The transistor of the present invention can be similarly realized not only with a TFT but also with a bipolar transistor. Also, the TFT can be similarly implemented regardless of the constituent material such as polysilicon, crystalline silicon, amorphous silicon and the like.

  It is also possible to combine the embodiments of the present invention.

  In addition, the pixel of the EL display device according to the present embodiment can be applied regardless of the display color, such as a single color pixel configuration, three colors of red, green and blue, four colors of red, green, and white, three colors of cyan yellow magenta, and a pen tile pixel configuration. Is possible.

  In addition, the pixel configuration in which red, green, and blue are arranged in this embodiment is only an example.

  14 and 16 and the like show pixel configurations for one column, which are common source signal lines regardless of whether they are formed in stripes or in a delta arrangement. The same application is possible if there are a plurality of pixels.

  Since the EL display device according to the present invention can sufficiently secure the offset cancel period, it is possible to realize a good offset cancel. For this reason, even if the characteristic variation of the driving transistor 11a occurs, the characteristic variation can be canceled and a good image display can be realized.

It is a block diagram of a pixel of an EL display device. FIG. 46 is an explanatory diagram representing a driving method of an EL display device. It is an explanatory diagram of an EL display device. It is a block diagram of a pixel of an EL display device. It is a block diagram of a pixel of an EL display device. It is an explanatory diagram of an EL display device. It is explanatory drawing of the apparatus using EL display apparatus. It is explanatory drawing of the apparatus using EL display apparatus. It is explanatory drawing of the apparatus using EL display apparatus. It is a block diagram of a pixel of an EL display device. It is a block diagram of a pixel of an EL display device. FIG. 46 is an explanatory diagram representing a driving method of an EL display device. FIG. 46 is an explanatory diagram representing a driving method of an EL display device. It is the figure which showed the structure which takes in a video signal to a pixel from several source signal lines. FIG. 15 is a diagram showing an operation of the gate driver circuit 12a in the configuration of FIG. FIG. 5 is a diagram illustrating an example of a gate driver circuit and a pixel configuration when a characteristic cancel operation is performed over a plurality of horizontal scanning periods. FIG. 17 is a diagram illustrating an operation of the gate driver circuit of FIG. 16. FIG. 17 is a diagram illustrating an operation of the gate driver circuit of FIG. 16. FIG. 6 is a diagram illustrating a circuit in a case where a characteristic cancel operation is performed over a plurality of horizontal scanning periods in one shift register phase. FIG. 20 is a diagram showing the operation of the gate driver circuit when the circuit configuration of FIG. 19 is used. It is a figure showing an input waveform at the time of deleting an enable signal of gate driver circuit 12a2, and operation. It is the figure which showed the video signal change timing of each color signal line at the time of implementing 3 signal line selection drive. It is the figure which showed the circuit structure of EL display apparatus which has 3 signal line selection drive and 2 signal lines of each column. It is the figure which showed the operation | movement of the pixel 16c in FIG. It is the figure which showed the circuit of the pixel 16 in this invention. The figure which showed the operation | movement of the gate driver circuit and signal line selection circuit in the circuit of FIG. FIG. 3 is a diagram showing a circuit configuration of an EL display device that has three signal line selection driving and two signal lines in each column, and the gate driver circuit is separated for initialization, characteristic cancellation, and gradation signal writing. FIG. 28 is a diagram showing the operation of the gate driver circuit in the circuit configuration of FIG. 27. It is the figure which showed the pixel circuit using n-type TFT. FIG. 6 is a diagram illustrating the operation of a gate signal line for one frame in a pixel circuit in which a capacitor 19b is formed. FIG. 5 is a diagram illustrating a pixel circuit configuration in the case where a constant drain current is passed by a current source during an offset cancel operation of a driving transistor. FIG. 32 is a diagram showing input waveforms of a gate signal line and a source signal line, a gate voltage of a driving transistor, and an operation of an EL element in the pixel circuit configuration of FIG. 31. FIG. 5 is a diagram showing a pixel circuit configuration when a constant drain current is supplied from a current source during an offset cancel operation of a driving transistor and a gate voltage is set low using an initialization power supply before the cancel operation. FIG. 34 is a diagram showing input waveforms of a gate signal line, a source signal line, and switching means, a gate voltage of a transistor 11a, and an operation of an EL element in the circuit configuration of FIG. It is a diagram showing a pixel circuit for making the initialization voltage of the driving transistor 11a different according to the characteristic variation. FIG. 36 is a diagram showing an input pattern of a gate signal line 17, a switching unit 333, and a source signal line 18, a gate voltage of a transistor 11a, and an operation of an EL element 15 in the pixel configuration of FIG. FIG. 36 is a diagram showing a circuit configuration when gradation voltages are supplied from a plurality of source signal lines in the same column in the EL display device having the pixel circuit of FIG. FIG. 38 is a diagram showing an input signal waveform of a pixel 16a and operations of a driving transistor 11a and an EL element 15 in the circuit configuration of FIG. 38 is a diagram showing the input signal waveform of the pixel 16a, the operation of the driving transistor 11a, and the EL element 15 when the initialization power supply 331 is not used in the circuit of FIG. It is the figure which showed the mode of change when the gate voltage of the transistor 11a for a drive was initialized by (a) initialization power supply, and (b) it initialized by the current source. It is the figure which showed the change of the gate voltage of the driving transistor 11a when the characteristic cancellation period by a current source does not exist. This is a luminance characteristic with respect to current for each display color. It is the figure which showed the organic electroluminescence display which can supply different initialization power supplies for every display color. It is the figure which showed the relationship of the electric current range which flows into EL which can correct the display nonuniformity with respect to the initialization voltage. It is the figure which showed the pixel circuit structure of the display apparatus using the organic EL element which varied EL power supply for every display color. FIG. 6 is a diagram illustrating a pixel circuit configuration in which a characteristic cancellation time of a driving transistor is different for each display color. (A) In the conventional circuit configuration, (b) In the circuit configuration of FIG. 45, the amplitude of the gate voltage of the driving transistor is shown for each display color. It is the figure which showed the circuit structure of the display apparatus using the organic EL element which formed the voltage shift capacity | capacitance 481 and varied capacity | capacitance for every display color. (A) The gate voltage of the driving transistor 11a after writing by the conventional driving method and (b) the range for each color of the gate voltage after writing of the driving transistor 11a in the case of using the circuit configuration of FIG. It is a figure. The gate voltage range of each color driving transistor 11a when the ratio of the channel width to the channel length of the driving transistor 11a is changed only for the blue pixel (b) and when all the display colors are the same (a) is shown. FIG. It is a diagram showing an EL display device having a circuit in which the capacitance of a video signal holding capacitor provided in a pixel is changed for each display color. (A) The figure which showed the mode of the gate voltage change of the transistor 11a for a drive when the write voltage from the source signal line 18 was 4V, (b) The change of the drain current at the time of the change of (a) was shown. (C) A diagram showing how the gate voltage of the driving transistor 11a changes when the write voltage from the source signal line 18 is 1V. (D) Changes in the drain current when changing in (c). FIG. (A) A diagram showing a change in the gate voltage of the driving transistor 11a when the source signal line 18 voltage is 4V and the reset voltage is -2V, and (b) the source signal line 18 voltage is 1V and the reset voltage. FIG. 10 is a diagram showing a change in the gate voltage of the driving transistor 11a when -5V. FIG. 3 is a diagram showing a circuit configuration of an EL display device that can apply a reset voltage dropped by a certain voltage with respect to a voltage written from a source signal line. FIG. 6 is a diagram illustrating a circuit configuration of an EL display device that includes a reset voltage generation unit and supplies a reset potential corresponding to a voltage of a source signal line 18; In the EL display device, a reset potential that changes in accordance with the voltage value of the source signal line 18 can be supplied to the reset period 361. The figure which showed the operation | movement of the gate signal line 17 in the circuit structure of FIG. It is the figure which showed the relationship between a source signal line voltage and a reset voltage. It is the figure which showed the relationship between the source signal line and reset voltage in the form of this invention. It is the figure which showed the circuit in the case of applying with the pixel structure which performs threshold value correction | amendment FIG. 5 is a diagram illustrating a pixel circuit configuration for correcting characteristic variations of a driving transistor 11a. FIG. 62 is a diagram showing the operation of the gate signal line 17 in the circuit of FIG. 61 for one frame. FIG. 5 is a diagram illustrating a pixel circuit configuration for correcting characteristic variations of a driving transistor 11a. FIG. 64 is a diagram showing a gate signal line waveform in the pixel configuration of FIG. 63. FIG. 6 is a diagram illustrating a pixel circuit having a characteristic variation correcting function of a driving transistor 11a according to the present invention. FIG. 66 is a diagram showing signal line waveforms for operating the pixel circuit shown in FIG. 65. FIG. 66 is a diagram showing signal line waveforms when the writing period is performed over a plurality of horizontal scanning periods in the pixel circuit shown in FIG. 65. It is the figure which formed the pixel circuit with the p-type transistor. FIG. 5 is a diagram showing a pixel circuit in which a transistor 11n for determining whether or not to pass a current through an EL element 15 is inserted. It is the figure which showed the structure of EL element 15 of this invention. 65A is a diagram showing the relationship between the capacitance and the signal line amplitude in the pixel circuit of FIG. 65, FIG. 65B is a diagram showing the relationship between the capacitance of the EL element and the maximum resolution, and FIG. It is the figure which showed the circuit which has the voltage switching function of VDD power supply (653). FIG. 4 is a diagram showing a pixel circuit with a driving transistor characteristic correction function in which the number of transistors per pixel in the present invention is reduced. FIG. 74 is a diagram showing waveforms of a gate signal line 17 and a source signal line in the pixel circuit configuration of FIG. 73. FIG. 74 is a diagram showing a pixel circuit when the number of transistors 11p is reduced. It is a figure showing a pixel circuit when transistors 11p and 11q are replaced with switches. FIG. 77 is a diagram showing waveforms of gate signal lines and source signal lines in the pixel configuration of FIG. 76. It is the figure which showed the pixel circuit at the time of sharing the switch for supplying an electric current to the EL element 15 for 6 pixels. FIG. 5 is a diagram illustrating a pixel circuit when a driving transistor is formed of a p-type transistor. 3 is a diagram showing a pixel circuit when an auxiliary capacitor is formed in the EL element 15. FIG. It is the figure which showed the pixel circuit of each color at the time of comprising the transistors 11p and 11q for every color. It is the figure which showed the pixel circuit at the time of providing the switch 761 for every red-green-blue pixel for 2 rows. FIG. 83 is a diagram showing waveforms of source signal lines and gate signal lines in FIG. 82. It is the figure which showed the pixel circuit which has the switch for EL element current supply common to a red, green, and blue pixel at the time of implementing signal line selection drive. It is the figure which showed the source driver output, the waveform of a source signal line, a gate signal line, and the operation state of a pixel. FIG. 5 is a diagram showing a circuit configuration for performing signal line selection driving by sharing EL element current supply switches for two rows of red, green, and blue pixels. It is a figure showing a pixel circuit when a reset signal line is formed. It is the figure which showed the relationship between each pixel, a reset signal line, and a reset power supply. FIG. 88 is a diagram illustrating a pixel circuit that operates in the same manner as FIG. 87 using a p-type transistor driving transistor. FIG. 88 is a diagram showing drive waveforms of the pixel configuration of FIG. 87. 90 is a diagram illustrating a drive waveform in which a period during which the transistor 11k is turned off is provided in the video signal writing period with respect to the drive waveform in FIG. It is a diagram showing a display device in which two source signal lines are provided for one column of pixels. FIG. 93 is a diagram showing drive waveforms per pixel in the circuit configuration of FIG. 92. It is a diagram showing a pixel circuit that provides a power supply line for initialization and realizes a reset and characteristic cancellation period without using a source signal line. FIG. 95 is a diagram illustrating waveforms of a gate signal line and a source signal line in FIG. 94.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Transistor 12 Gate driver circuit 14 Source driver circuit 15 EL element 16 Pixel 17 Gate signal line 18 Source signal line 19 Storage capacity (addition capacitor, addition capacity)

Claims (1)

  1. An EL display device in which pixels having organic light emitting elements are formed in a matrix,
    The drain electrode of the driving transistor of the pixel formed in the same row in each pixel formed in the matrix is connected to the first signal line,
    The first signal line is connected to a reset power source via a first switch;
    An EL display device.
JP2008219469A 2008-08-28 2008-08-28 El display device Pending JP2010054788A (en)

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