KR20140071734A - Organic light emitting display device and method for driving theteof - Google Patents

Abstract

An organic light emitting display device according to the present invention, capable of sensing a characteristics change of a driving transistor for each pixel from the outside to correct the characteristics change in real time, comprises: a display panel configured to include a plurality of pixels having the driving transistor for emitting light emitting elements to a data current based on data voltage; and a panel driver configured to set a sensing section and a displaying section, generate sensing data by sensing at least one among threshold voltage and mobility of the driving transistor during a sensing period, and generate the data voltage by correcting input data according to the sensing data during the sensing period, wherein the panel driver is configured to turn off the light emitting elements of all pixels for each sensing period.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting display and a driving method thereof.

2. Description of the Related Art In recent years, importance of a flat panel display device has increased with the advent of multimedia. In response to this, flat panel display devices such as liquid crystal display devices, plasma display devices, and organic light emitting display devices have been commercialized. Among such flat panel display devices, organic light emitting display devices have attracted attention as a next generation flat panel display device because they have a high response speed, low power consumption, and self light emission, so that there is no problem in viewing angle.

A general organic light emitting display includes a display panel including a plurality of pixels and a panel driver for emitting each pixel. Here, each pixel is formed in a pixel region defined by the intersection of a plurality of data lines and a plurality of gate lines.

Each of these pixels includes a switching transistor Tsw, a driving transistor Tdr, a capacitor Cst, and a light emitting element OLED, as shown in Fig.

The switching transistor Tsw is switched in accordance with the gate signal GS supplied to the gate line GL to supply the data voltage Vdata supplied to the data line DL to the driving transistor Tdr.

The driving transistor Tdr is switched according to the data voltage Vdata supplied from the switching transistor Tsw and controls the data current Ioled flowing to the light emitting element OLED by the driving voltage VDD.

The capacitor Cst is connected between the gate terminal and the source terminal of the driving transistor Tdr to store a voltage corresponding to the data voltage Vdata supplied to the gate terminal of the driving transistor Tdr, Tdr).

The light emitting device OLED is electrically connected between the source terminal of the driving transistor Tdr and the cathode electrode CE to which the cathode voltage VSS is applied and is turned on by the data current Ioled supplied from the driving transistor Tdr do.

Each pixel of the general organic light emitting display device controls the size of the data current Ioled flowing to the light emitting element OLED by the driving voltage VDD by switching the driving transistor Tdr according to the data voltage Vdata So that a predetermined image is displayed by causing the light emitting device OLED to emit light.

However, in general organic light emitting display devices, there is a problem that the characteristics (for example, threshold voltage Vth / mobility) of the driving transistor Tdr are different depending on the driving transistor Tdr according to the non-uniformity of the manufacturing process of the thin film transistor The conventional organic light emitting display device has a problem that even if the same data voltage Vdata is applied to the driving transistor Tdr of each pixel, a uniform image quality can not be realized due to a variation in current flowing through the light emitting device OLED .

An object of the present invention is to provide an organic light emitting display device and a method of driving the same that can sense a change in characteristics of a driving transistor of each pixel from the outside and compensate it in real time.

It is another object of the present invention to provide an organic light emitting display device and a method of driving the same that can prevent image quality defects such as a line stripe phenomenon due to a difference in brightness between horizontal lines when sensing a change in characteristics of driving transistors of each pixel from the outside. .

According to an aspect of the present invention, there is provided an organic light emitting diode display comprising: a display panel including a plurality of pixels having a driving transistor for emitting a light emitting element with a data current based on a data voltage; And a sensing section for sensing the threshold voltage and the mobility of the driving transistor during the sensing period to generate sensing data and compensating input data according to the sensing data during the sensing interval, And a panel driver for generating a data voltage, wherein the panel driver turns off the light emitting elements of all the pixels during the sensing period.

The panel driver may change the driving voltage supplied to the driving transistor of each pixel or the cathode voltage supplied to the light emitting element of each pixel for each sensing period to turn off the light emitting elements of all the pixels during the sensing period have.

According to an aspect of the present invention, there is provided a method of driving an organic light emitting diode display including a display panel including a plurality of pixels having a driving transistor for emitting a light emitting element based on a data voltage based on a data voltage, The method comprising: setting a sensing period and a display period; Sensing at least one of a threshold voltage and a mobility of the driving transistor during the sensing period to generate sensing data; And generating the data voltage by compensating the input data according to the sensing data during the display period, wherein the light emitting elements of all the pixels are off in the sensing period.

In the sensing period, the light emitting elements of all the pixels may be turned off by a change in the driving voltage supplied to the driving transistor of each pixel or the cathode voltage supplied to the cathode electrode.

According to the present invention, the characteristic change of the driving transistor sensed from each pixel is reflected on the input data, so that the characteristic variation of the driving transistor included in each pixel can be compensated periodically or in real time to improve the luminance uniformity.

In addition, according to the present invention, the driving voltage or the cathode voltage supplied to the display panel is changed when sensing the change in the characteristics of the driving transistor so that the light emitting elements of all the pixels of the display panel are not emitted, There is an effect that a change in the characteristics of the driving transistor can be sensed while preventing a picture quality defect phenomenon such as a line stripe by

1 is a circuit diagram for explaining a pixel structure of a general organic light emitting display device.
2 is a view for explaining an organic light emitting diode display according to a first embodiment of the present invention.
3 is a view for explaining a configuration of an organic light emitting display according to an exemplary embodiment of the present invention.
4 is a circuit diagram for explaining the pixel structure shown in FIG.
5 is a waveform diagram for explaining a voltage control signal generated in the timing controller shown in FIG. 3 and a driving voltage according to the voltage control signal.
6 is a circuit diagram for explaining an example of the driving voltage switching unit shown in FIG.
7 is a waveform diagram showing driving waveforms in the sensing mode of the OLED display according to the first embodiment of the present invention.
8 is a waveform diagram showing driving waveforms in the display mode of the organic light emitting diode display according to the first embodiment of the present invention.
9 is a view for explaining an organic light emitting diode display according to a second embodiment of the present invention.
10 is a waveform diagram for explaining a voltage control signal generated in the timing controller shown in FIG. 9 and a driving voltage according to the voltage control signal.
11 is a circuit diagram for explaining an example of the cathode voltage switching unit shown in FIG.
12 is a waveform diagram showing driving waveforms in the sensing mode of the OLED display according to the second embodiment of the present invention.

The meaning of the terms described herein should be understood as follows.

The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms.

It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a view for explaining an organic light emitting diode display according to a first embodiment of the present invention.

Referring to FIG. 2, the organic light emitting diode display according to the first embodiment of the present invention includes a display panel 110 and a panel driver 120.

The display panel 110 includes a plurality of pixels P and a light emitting element included in each of the plurality of pixels P emits light by a data current output from a driving transistor included in each pixel P do.

The panel driver 120 drives the display panel 110 divided into a sensing period and a display period. Here, the sensing period may be set as a period overlapping the blank interval of the vertical synchronization signal, and the display period may be set as a remaining period except for the sensing period.

The panel driver 120 senses a characteristic change of the driving transistor including at least one of the threshold voltage and the mobility of the driving transistor included in each pixel P included in the corresponding horizontal line.

During the display period, the panel driver 120 displays a predetermined image on the display panel 110 by emitting a light emitting element included in each pixel P according to input data. Here, the panel driver 120 may reflect the sensing result of the driving transistor of the corresponding horizontal line sensed in the sensing period to the input data of each pixel included in the corresponding horizontal line in the display period immediately after the sensing period, Is reflected in the input data of each pixel included in each horizontal line in the display period after the characteristic change of the driving transistor of all the pixels of the display panel 110 is sensed by the interval to change the characteristic change of the driving transistor of each pixel to the horizontal line Real-time compensation or periodically compensation.

On the other hand, since the light emitting elements of the pixels P included in the corresponding horizontal line do not emit light during the sensing period, image quality defects such as line stripes may occur due to the difference in luminance between the horizontal line where the sensing operation is performed and the non- have. Accordingly, the panel driver 120 according to the present invention changes the driving voltage or the cathode voltage applied to the display panel 110 for each sensing interval overlapping the vertical blanking period of one frame, Thereby turning off the light emitting elements of all the pixels P. That is, the panel driver 120 according to the exemplary embodiment of the present invention performs a sensing operation on the pixels P included in the corresponding horizontal line for each sensing period, and performs the sensing operation on the pixels P included in the other horizontal lines P are prevented from emitting light by changing a driving voltage or a cathode voltage applied to the display panel 110, thereby preventing a picture quality defect phenomenon such as a line stripe due to a luminance difference between horizontal lines due to the sensing period.

The panel driver 120 according to the first exemplary embodiment of the present invention applies a driving voltage of a first voltage level to the display panel 110 during the sensing period and outputs a second voltage Level driving voltage is applied to the display panel 110. [ Here, the first voltage level may be a voltage level lower than the second voltage level of the driving voltage that is set to prevent the light emitting device from emitting light during the sensing period, a voltage level equal to the cathode voltage, or a voltage level of zero Can be set.

The panel driver 120 according to the second exemplary embodiment of the present invention applies the cathode voltage of the third voltage level to the display panel 110 during the sensing period and outputs a fourth voltage Level cathode voltage to the display panel 110, as shown in FIG. Here, the third voltage level may be a voltage level higher than the fourth voltage level of the cathode voltage set to prevent the light emitting device from emitting light during the sensing period, a voltage level equal to the second voltage level of the driving voltage, or zero ) ≪ / RTI >

Hereinafter, the configuration of the organic light emitting device including the panel driver according to the first and second embodiments of the present invention will be described with reference to FIGS. 3 to 12. FIG.

3 is a circuit diagram for explaining a pixel structure shown in FIG. 3, and FIG. 5 is a timing diagram of the timing control unit shown in FIG. 3 according to an embodiment of the present invention. And a driving voltage according to the voltage control signal.

3 to 5, the organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 110 and a panel driver 120 as described above.

The display panel 110 includes a plurality of pixels P. The plurality of pixels P includes a plurality of gate line groups GL1 to GLm, a plurality of data lines DL1 to DLn and a plurality of sensing lines SL1 to SLn aligned with the plurality of data lines D1 to Di, SLn in the pixel region. A plurality of driving voltage lines PLi are formed on the display panel 110 in parallel with the plurality of data lines DL1 to DLn to supply a driving voltage VDD from the panel driver 120 .

Each of the plurality of pixels P includes a pixel circuit PC and a light emitting element OLED. In this case, each of the plurality of pixels P may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel. One unit pixel for displaying one image may include an adjacent red pixel, a green pixel, and a blue pixel, or may include an adjacent red pixel, a green pixel, a blue pixel, and a white pixel.

In one embodiment, the pixel circuit PC may include a first switching transistor Tsw1, a second switching transistor Tsw2, a driving transistor Tdr, and a capacitor Cst. Here, the transistors Tsw1, Tsw2, and Tdr may be an a-Si TFT, a poly-Si TFT, an oxide TFT, an organic TFT, or the like as an N-type thin film transistor (TFT).

The first switching transistor Tsw1 includes a gate electrode connected to the first gate line GLa, a first electrode connected to the adjacent data line DLi, and a first node n1, which is a gate electrode of the driving transistor Tdr, And a second electrode connected to the second electrode. The first switching transistor Tsw1 may supply the data voltage Vdata to the data line DLi according to the first gate signal GSa of the gate-on voltage level supplied to the first gate line GLa, To the gate electrode of the node n1, that is, the driving transistor Tdr.

The second switching transistor Tsw2 includes a gate electrode connected to the second gate line GLb, a first electrode connected to the adjacent sensing line SLi, and a second node n2, which is the source electrode of the driving transistor Tdr, And a second electrode connected to the second electrode. The second switching transistor Tsw2 is connected to the reference voltage Vref supplied to the sensing line SLi according to the second gate signal GSb of the gate-on voltage level supplied to the second gate line GLb Voltage Vpre) to the second node n2, that is, the source electrode of the driving transistor Tdr.

The capacitor Cst includes first and second electrodes connected between the gate electrode and the source electrode of the driving transistor Tdr, that is, the first and second nodes n1 and n2. The capacitor Cst charges the difference voltage between the voltages supplied to the first and second nodes n1 and n2, and then switches the driving transistor Tdr according to the charged voltage.

The driving transistor Tdr includes a gate electrode commonly connected to the second electrode of the first switching transistor Tsw1 and the first electrode of the capacitor Cst, a first electrode of the second switching transistor Tsw2 and a capacitor Cst, A source electrode commonly connected to the second electrode of the light emitting device OLED, and a drain electrode connected to the driving voltage line PLi. The driving transistor Tdr is turned on by the voltage of the capacitor Cst to control the amount of current flowing from the driving power supply line PLi to the light emitting element OLED.

In the above-described embodiment, the pixel circuit PC is composed of three transistors and one capacitor. However, the number of transistors and capacitors constituting the pixel circuit PC may be variously modified.

The light emitting device OLED emits monochromatic light having a luminance corresponding to the data current Ioled by the data current Ioled supplied from the pixel circuit PC, that is, the driving transistor Tdr. To this end, the light emitting device OLED includes an anode electrode (not shown) connected to the second node n2 of the pixel circuit PC, an organic layer (not shown) formed on the anode electrode, and a cathode electrode CE) (CE). At this time, the organic layer may have a structure of a hole transporting layer / an organic light emitting layer / an electron transporting layer or a structure of a hole injecting layer / a hole transporting layer / an organic light emitting layer / an electron transporting layer / an electron injecting layer. Further, the organic layer may further include a functional layer for improving the luminous efficiency and / or lifetime of the organic light emitting layer. The cathode electrode CE may be formed individually in each of the plurality of pixels P or may be formed so as to be commonly connected to the plurality of pixels P. The cathode electrode CE may be connected to the panel driving unit 120 A cathode voltage VSS having a constant voltage level, for example, a voltage level of zero is supplied.

Each of the plurality of gate line groups GL1 to GLm is formed along the first direction of the display panel 110, for example, in the horizontal direction. At this time, each of the plurality of gate line groups GL1 to GLm consists of first and second gate lines GLa and GLb adjacent to each other. The first and second gate signals GSa and GSb are separately supplied from the panel driver 120 to the first and second gate lines GLa and GLb of the gate line groups GL1 to GLm .

Each of the plurality of data lines DL1 to DLn is formed to be parallel to the second direction of the display panel 110, for example, the longitudinal direction so as to intersect each of the plurality of gate line groups GL1 to GLm. A data voltage Vdata is separately supplied from the panel driver 120 to each of the data lines DL1 to DLn.

The data voltage Vdata supplied to each pixel P through the plurality of data lines DL1 to DLn may be compensated for by changing the characteristic of the driving transistor Tdr included in the pixel P Data voltage. At this time, the characteristics of the driving transistor Tdr include the threshold voltage of the driving transistor and the mobility of the driving transistor.

Each of the plurality of sensing lines SL1 to SLn is formed in parallel with each of the plurality of data lines DL1 to DLn. A reference voltage Vref or a precharging voltage Vpre is selectively supplied from the panel driver 120 to each of the sensing lines SL1 to SLn. That is, the reference voltage Vref is supplied to each of the sensing lines SL1 to SLn during the data charging period of the display period of each pixel P, and the precharging voltage Vpre is supplied to each of the pixels P And is supplied to the sensing lines SL1 to SLn during the voltage sensing period of the sensing period of the pixel P. [

The driving power supply line PLi is selectively supplied with the driving voltage VDD of the first voltage level or the second voltage level from the panel driving unit 120. That is, during the voltage charging period of the sensing period of each pixel P of each pixel P, the driving power supply line VDD of the first voltage level is supplied to the driving power supply line PLi, The driving power supply voltage VDD at the second voltage level is supplied during the period.

The panel driver 120 according to the first embodiment of the present invention includes a timing controller 210, a gate driver 220, a data driver 230, and a voltage supplier 240.

5, the timing control unit 210 generates the vertical synchronization signal Vsync based on the vertical synchronization signal Vsync and the data enable signal DE among the timing synchronization signals TSS supplied from the outside, A sensing interval SP overlapping the blank interval BP of the data enable signal DE and a display interval DP overlapping the valid data interval of the data enable signal DE.

The timing controller 210 drives each of the gate driver 220, the data driver 122 and the voltage supplier 240 in the sensing mode during the sensing period SP and controls the gate driver 220 The data driver 230, and the voltage supplier 240 in the display mode. At this time, the display mode may drive each pixel P as a data charging period and a light emitting period. The sensing mode may drive each pixel P in an initialization period, a voltage charging period, and a voltage sensing period.

The timing controller 210 generates a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS corresponding to the sensing mode and the display mode, respectively.

In the display mode, the timing controller 210 is connected to each gate line group GL1 to GLm based on a timing synchronization signal TSS input from outside, that is, from a system body (not shown) or a graphics card (not shown) The data control signal DCS, the gate control signal GCS and the voltage control signal VCS for driving each pixel P in the data charging period and the light emitting period, And controls the data driver 230 and the voltage supplier 240 in the display mode.

The timing synchronization signal TSS may be a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a reference clock signal DCLK, or the like. The gate control signal GCS may include a gate start signal and a plurality of clock signals. The data control signal DCS may be a data start signal, a data shift signal, a data output signal, or the like.

In the display mode, the timing controller 210 corrects the input data Idata input based on the sensing data Sdata of each pixel P provided from the data driver 230 according to the sensing mode, And supplies the generated pixel data DATA to the data driver 230. [ The pixel data DATA to be supplied to each pixel P is input to the input data Idata by a gray value of the sensing data Sdata corresponding to a characteristic change of the driving transistor Tdr of each pixel P Respectively.

Here, the input data Idata may be composed of red, green, and blue input data to be supplied to one unit pixel. When the unit pixel is composed of a red pixel, a green pixel, and a blue pixel, one pixel data (DATA) may be red, green, or blue data. On the other hand, when the unit pixel is composed of a red pixel, a green pixel, a blue pixel and a white pixel, one pixel data (DATA) may be data of red, green, blue, or white.

In the sensing mode, the timing controller 210 controls the pixels P connected to one gate line group GLi corresponding to the horizontal line corresponding to the sensing period, based on the timing synchronization signal TSS, The gate driving unit 220, the data driving unit 230, and the data driving unit 230 are generated using the data control signal DCS, the gate control signal GCS, and the voltage control signal VCS, respectively, And controls each of the voltage supply units 240 in the sensing mode.

The voltage control signal VCS has a high logic state (High) during an initialization period and a voltage charging period of a sensing period in a sensing mode, and may have a low logic state (low) during a display mode. Here, the voltage control signal VCS of the high logic state (High) is a blank interval (" VCS ") of the last data enable signal DE and the vertical synchronization signal Vsync that supply the data voltage to the last horizontal line of the display panel 110 BP of the vertical synchronizing signal Vsync and the first horizontal line of the display panel 110 and supplies the data voltage to the first horizontal line of the display panel 110. [ (BPP), which is defined as a first data enable signal (DE) between the first data enable signal (DEP) and the first data enable signal (DEP). At this time, the rising time and the falling time of the voltage control signal VCS having the high logic state (High) may be the last data enable signal DE according to the resolution and size of the display panel 110, And the first data enable signal DE can be variously changed.

The gate driver 220 is connected to the plurality of gate line groups GL1 to GLm and operates in the display mode and the sensing mode according to a gate control signal according to the mode of the timing controller 210. [

In the display mode, the gate driving unit 220 generates first and second gate signals GSa (GSa) and GSa (GSa) of the gate-on voltage level every one horizontal period according to the gate control signal GCS of the display mode supplied from the timing controller 210 , And GSb are sequentially generated and supplied to the gate line groups GL1 to GLm. At this time, each of the first and second gate signals GSa and GSb has a gate-on voltage level during a data charging period of each pixel P, and has a gate-off voltage level during a light-emitting period of each pixel P.

In the sensing mode, the gate driver 220 generates the first and second gate signals GSa and GSb corresponding to the initialization period, the voltage charging period, and the voltage sensing period of the pixels P included in the horizontal line to be sensed, And supplies it to the corresponding gate line group GLi.

The gate driver 220 may be formed in the form of an integrated circuit (IC) or may be formed directly on the substrate of the display panel 110 together with the transistor forming process of each pixel P, (GL1 to GLm).

The data driver 230 is connected to a plurality of data lines DL1 to DLn and a plurality of sensing lines SL1 to SLn and operates in a display mode and a sensing mode according to the mode control of the timing controller 210. [

During the display mode and the display period DP, the data driver 230 supplies the reference voltage Vref to the sensing lines SL1 to SLn for each data charging period of each pixel P, Described pixel data DATA supplied from the data driver 210 to the data voltage Vdata and supplies the data voltage to the corresponding data lines DL1 to DLn.

During the sensing period, the data driver 230 supplies the precharging voltage Vpre to the sensing lines SL1 to SLn during the initialization period of the sensing period SP, (DATA) into a sensing data voltage (Vdata) and supplies it to the corresponding data lines (DL1 to DLn). During the voltage charging period of the sensing period SP, the data driver 230 generates a current flowing through the driving transistor Tdr of each pixel P by the precharging voltage Vpre and the sensing data voltage Vdata, And floating the sensing lines SL1 to SLn so that the voltages corresponding to the sensing lines SL1 to SLn are charged to the sensing lines SL1 to SLn. During the sensing period SP, the data driver 230 senses the voltages charged in the sensing lines SL1 to SLn and controls the driving transistor Tdr of each pixel P Converts the voltage corresponding to the characteristics (at least one of the threshold voltage and the mobility) into sensing data (Sdata) and provides the sensing data (Sdata) to the timing controller 210.

The voltage supply unit 240 supplies the cathode voltage VSS to the cathode electrode CE of each pixel P of the display panel 110 and supplies the cathode voltage VSS to the voltage control signal VCS supplied from the timing control unit 210. [ The driving voltage VDD of the above-described first voltage level V1 of the display panel 110 or the second voltage level V2 of the display panel 110 is supplied to the driving voltage line PLi of the display panel 110 do. In supplying the driving voltage VDD, the voltage supplier 240 supplies the sensing period SP, more specifically, the initialization period of the sensing period SP and the voltage charging period SP, according to the voltage control signal VCS. The driving voltage VDD of the first voltage level V1 is supplied to the driving voltage line PLi of the display panel 110 during the remaining period excluding the sensing period SP, The driving voltage VDD of the second voltage level V2 is supplied to the driving voltage line PLi of the display panel 110 during the voltage sensing period of the display panel SP and during the display period DP. For example, the voltage supply unit 240 includes a cathode voltage generator 242, a driving voltage generator 244, and a driving voltage switching unit 246.

The cathode voltage generating unit 242 generates a cathode voltage VSS set to a constant voltage level using the input power source and supplies the generated cathode voltage VSS to the driving voltage switching unit 246. At the same time, . At this time, the cathode voltage VSS may have a voltage level lower than the driving voltage VDD of the second voltage level V2, or may have a ground voltage or a voltage level of zero. Here, when the cathode voltage VSS has a ground voltage or a voltage level of zero, the cathode voltage generator 244 may be replaced with a ground power source without generating a separate cathode voltage.

The driving voltage generator 244 generates a driving voltage VDD set to a constant voltage level using the input power source and supplies the driving voltage VDD to the driving voltage switching unit 246. At this time, the driving voltage VDD generated by the driving voltage generating unit 244 has a second voltage level V2 as shown in FIG.

The driving voltage switching unit 246 switches the driving voltage VDD of the first voltage level V1 corresponding to the cathode voltage VSS or the driving voltage VDD of the first voltage level V2 according to the voltage control signal VCS supplied from the timing controller 210. [ And supplies the driving voltage VDD of the second voltage level V2 supplied from the voltage generating unit 244 to the driving voltage line PLi of the display panel 110. [ 10, the driving voltage switching unit 246 may display the driving voltage VDD of the first voltage level V1 in accordance with the voltage control signal VCS of the high logic state (high) To the driving voltage line PLi of the panel 110 and supplies the driving voltage VDD of the second voltage level V2 to the display panel 110 in accordance with the voltage control signal VCS of the low logic state low And supplies it to the driving voltage line PLi. To this end, the driving voltage switching unit 246 includes first and second switching devices SW1 and SW2 as shown in FIG.

The first switching device SW1 is connected to a gate terminal to which a voltage control signal VCS is supplied, a first terminal to which a driving voltage VDD of a first voltage level V1 is supplied, And a second terminal connected to the output channel (Ch). Here, the first switching device SW1 may be an N-type transistor. The first switching device SW1 is turned on according to a voltage control signal VCS of a high logic state to generate a sensing period SP and more specifically an initialization period of the sensing period SP, During the charging period, the driving voltage VDD of the first voltage level V1 is supplied to the driving voltage line PLi to thereby display the sensing period SP, more specifically, during the initialization period of the sensing period SP and during the voltage charging period The light emitting devices OLED of all the pixels P of the panel 110 are turned off, that is, non-emitting state.

The second switching device SW2 includes a gate terminal to which a voltage control signal VCS is supplied, a first terminal to which a driving voltage VDD of a second voltage level V2 is supplied, And a second terminal. Here, the second switching device SW2 may be a P-type transistor. The second switching device SW2 is turned on according to the voltage control signal VCS of the low logic state to generate a remaining period excluding the sensing period SP described above, The driving voltage VDD of the second voltage level V2 is supplied to the driving voltage line PLi during the voltage sensing period of the display period SP and the remaining sensing period SP, The pixels P of the display panel 110 are caused to emit light during the voltage sensing period and the display period DP of the sensing interval SP.

7 is a waveform diagram showing driving waveforms in the sensing mode of the OLED display according to the first embodiment of the present invention.

The operation of the sensing period of the pixel P shown in FIG. 4 will be described with reference to FIGS. 3 to 7. FIG.

The timing controller 210 controls the driving timings of the gate driver 220, the data driver 230 and the voltage supplier 240 to initialize the sensing period SP for the pixel P The period t1, the voltage charging period t2, and the voltage sensing period t3. During the sensing period SP, a cathode voltage VSS having a constant voltage level is continuously supplied to the cathode electrode CE of the display panel 110 from the voltage supply unit 240.

In the initialization period t1, the first and second gate signals GSa and GSb of the gate-on voltage level are supplied to the first and second gate lines GLa and GLb by the gate driver 220, The sensing data voltage Vdata is supplied from the data driver 230 to the data line DLi and the precharging voltage Vpre is supplied to the sensing line SLi . At the same time, the driving voltage VDD of the first voltage level V1 is supplied to the driving voltage line PLi of the display panel 110 by the voltage supplier 240. Thereby, each of the first and second switching transistors Tsw1 and Tsw2 of the pixel P is turned on by the first and second gate signals GSa and GSb of the gate-on voltage level, The data voltage Vdata is supplied to the node n1 and the voltage of the second node n2 is initialized to the precharging voltage Vpre so that the data voltage Vdata and the pre- (Vdata-Vpre) of the voltage Vref is charged.

Next, in the voltage charging period t2, the first and second gate signals GSa and GSb supplied to the first and second gate lines GLa and GLb by the gate driver 220, And the driving voltage VDD supplied to the driving voltage line PLi of the display panel 110 by the voltage supplying unit 240 is maintained at the first voltage level V1. At the same time, the sensing data line (Vdata) is continuously supplied to the data line (DLi) by the data driver (230) and the sensing line (SLi) is floated. Accordingly, in the voltage charging period t2, the driving transistor Tdr is turned on by the sensing data voltage Vdata, and the voltage corresponding to the current flowing in the driving transistor Tdr, which is turned on, State sensing line SLi. The sensing line SLi connected to the pixel P is charged with a voltage corresponding to the threshold voltage of the driving transistor Tdr.

Then, in the voltage sensing period t3, the first gate signal GSa of the gate-off voltage level is supplied to the first gate line GLa by the gate driver 220, The second gate signal GSb supplied to the gate electrode of the transistor Q3 is maintained at the gate-on voltage level. At the same time, the driving voltage VDD of the second voltage level V2 is supplied to the driving voltage line PLi of the display panel 110 by the voltage supplier 240, The sensing line SLi floating in the voltage charging period t2 is connected to the data driver 230 again. Accordingly, during the voltage sensing period t3, the data driver 230 senses the voltage charged in the sensing line SLi connected to the pixel P, and outputs the sensed voltage, that is, the driving transistor Tdr, And supplies the sensing data Sdata to the timing control unit 210. The timing control unit 210 supplies the timing control unit 210 with the sensing data Sdata.

On the other hand, the timing controller 210 senses the threshold voltage of the driving transistor Tdr of each pixel P through the sensing period SP as described above, and then moves the driving transistor Tdr of each pixel P It is possible to re-execute the sensing mode for sensing the degree. In this case, the timing controller 210 performs the same sensing mode as described above, except that the first switching transistor Tsw1 of the pixel P is turned on only during the initialization period t1, The gate driver 220 and the data driver 230 are controlled such that the gate driver 220 and the data driver Vdata are supplied only during the initialization period t1. Accordingly, when the sensing mode is resumed, the gate-source voltage of the driving transistor Tdr is increased due to the turn-off of the first switching transistor Tsw1 during the voltage charging period t2, The gate-source voltage of the driving transistor Tdr is held by the voltage so that the voltage corresponding to the current flowing through the driving transistor Tdr, that is, the voltage corresponding to the mobility of the driving transistor Tdr is applied to the floating sensing line SLi, . When the sensing mode is resumed, the data driver 230 senses the voltage charged in the sensing line SLi, that is, the voltage corresponding to the mobility of the driving transistor Tdr, and outputs the sensed voltage to the sensing data Sdata And provides it to the timing control unit 210. [

8 is a waveform diagram showing driving waveforms in the display mode of the organic light emitting diode display according to the first embodiment of the present invention.

The operation of the display period DP with respect to the pixel P shown in FIG. 4 will be described with reference to FIGS. 3 to 5 and FIG.

The timing controller 210 corrects the input data Idata based on the sensing data Sdata of each pixel P provided from the data driver 230 according to the sensing period SP described above, And generates data (DATA). The timing controller 210 controls the driving timings of the gate driver 220, the data driver 230 and the voltage supplier 240 to charge the display period DP for the pixel P And is driven in the period t1 and the light emission period t2. A cathode voltage VSS having a constant voltage level from the voltage supply unit 240 is continuously supplied to the cathode electrode CE of the display panel 110 during the display period DP.

The first and second gate signals GSa and GSb of the gate-on voltage level are supplied to the first and second gate lines GLa and GLb by the gate driver 220 in the data charging period t1, The data voltage Vdata converted from the pixel data DATA by the data driver 230 is supplied to the data line DLi and the reference voltage Vref is supplied to the sensing line SLi. At the same time, the driving voltage VDD of the second voltage level V2 is supplied to the driving voltage line PLi of the display panel 110 by the voltage supplier 240. Thereby, each of the first and second switching transistors Tsw1 and Tsw2 of the pixel P is turned on by the first and second gate signals GSa and GSb of the gate-on voltage level, The data voltage Vdata is supplied to the node n1 and the voltage of the second node n2 is initialized to the reference voltage Vref so that the data voltage Vdata and the reference voltage Vref (Vdata-Vref) is charged.

The first and second gate signals GSa and GSb of the gate-off voltage level are supplied to the first and second gate lines GLa and GLb by the gate driver 220 in the light emission period t2. And the data voltage Vdata is continuously supplied or stopped to the data line DLi by the data driver 230 and the driving voltage line PLi of the display panel 110 is supplied to the voltage supply unit 240 The supplied driving voltage VDD is maintained at the second voltage level V2. Accordingly, in the light emission period t2, each of the first and second switching transistors Tsw1 and Tsw2 of the pixel P is turned on by the first and second gate signals GSa and GSb at the gate-off voltage level The driving transistor Tdr is turned on by the voltage stored in the capacitor Cst and the light emitting device OLED of the pixel P emits light.

In the light emission period t2 of the pixel P, the turn-on driving transistor Tdr is turned on in accordance with the difference voltage Vdata between the data voltage Vdata and the reference voltage Vref, And the data current Ioled flowing from the driving voltage line PLi to the cathode electrode CE by supplying the data current Ioled determined by the data current Ioled to the light emitting element OLED, . That is, in the light emission period t2, when the first and second switching transistors Tsw1 and Tsw2 are turned off, a current flows through the driving transistor Tdr, and the light emitting device OLED emits light in proportion to the current The voltage of the second node n2 rises by the capacitor Cst and the voltage of the first node n1 rises by the voltage rise of the second node n2 by the capacitor Cst, The gate-source voltage Vgs of the driving transistor Tdr is continuously maintained so that the light emitting device OLED continues to emit light until the next data charging period t1.

In Equation (2), "k" is a value determined by the structure and physical characteristics of the driving transistor Tdr as a proportional constant. The mobility of the driving transistor Tdr and the channel width Quot; W / L "which is the ratio of the channel length W to the channel length L, and the like.

The data current Ioled flowing through the light emitting device OLED during the light emitting period t2 is obtained from the pixel data DATA compensated for the change in threshold voltage / mobility of the driving transistor Tdr Is determined by the difference between the data voltage Vdata and the reference voltage Vref without being influenced by the change of the threshold voltage Vth / mobility of the driving transistor Tdr by the converted data voltage Vdata Able to know.

The organic light emitting display according to the first embodiment of the present invention includes a plurality of sensing lines SL1 to SLi for sensing the threshold voltage / The characteristic variation deviation of the driving transistor Tdr of each pixel P can be compensated periodically or in real time by generating the data Sdata and reflecting it on the input data Idata of each pixel P. [

The organic light emitting display according to the first embodiment of the present invention changes the driving voltage VDD supplied to the display panel 110 in the sensing mode, (OLED) is turned off, that is, the non-emission state, thereby preventing an image quality defect such as a line stripe caused by a luminance difference between horizontal lines due to the sensing period SP.

FIG. 9 is a view for explaining an organic light emitting display according to a second embodiment of the present invention. FIG. 10 is a waveform diagram for explaining a voltage control signal generated by the timing control unit shown in FIG. 9, Which is configured to include the panel driver according to the second embodiment of the present invention. Hereinafter, only different configurations will be described.

9 and 10, the panel driver 120 according to the second embodiment of the present invention changes the cathode voltage VSS supplied to the display panel 110 during the sensing period SP described above. The panel driver 120 according to the second embodiment of the present invention includes a timing controller 210, a gate driver 220, a data driver 230, and a voltage supplier 340, Except that the configuration of the supply unit 340 is changed, so that the description of the same configuration will be omitted.

The power supply unit 340 supplies the display panel 110 with a driving voltage VDD that is constantly maintained at the second voltage level V2 and supplies the voltage control signal VCS supplied from the timing control unit 210 The cathode voltage VSS of the third voltage level V3 or the fourth voltage level V4 is supplied to the cathode electrode CE of the display panel 110. [ In supplying the cathode voltage VSS, the voltage supplier 340 applies the third voltage level (SP) during the sensing period SP, more specifically, the sensing period SP, according to the voltage control signal VCS And supplies the cathode voltage VSS of the fourth voltage level V4 to the cathode electrode CE during the display period DP described above by supplying the cathode voltage VSS of the first voltage level V3 to the cathode electrode CE, do. The voltage supply unit 340 includes a cathode voltage generating unit 342, a driving voltage generating unit 344, and a cathode voltage switching unit 346.

The driving voltage generator 344 generates a driving voltage VDD set to a constant voltage level using the input power source and supplies the driving voltage VDD to the driving voltage line of the display panel 110, . At this time, the driving voltage VDD generated by the driving voltage generator 344 is maintained at a constant voltage level regardless of the sensing period SP and the display period DP. As shown in FIG. 5, 2 < / RTI > voltage level.

The cathode voltage generator 342 generates a cathode voltage VSS set to a constant voltage level using the input power source and supplies the cathode voltage VSS to the cathode voltage switching unit 346. At this time, the cathode voltage VSS may have a voltage level lower than the driving voltage VDD, a ground voltage, or a voltage level of zero. Here, when the cathode voltage VSS has a ground voltage or a voltage level of zero, the cathode voltage generator 342 may be replaced with a ground power source without generating a separate cathode voltage.

The cathode voltage switching unit 346 switches the third voltage level V3 from the driving voltage generator 344 to the third voltage level V3 according to the voltage control signal VCS supplied from the timing controller 210. [ And the cathode voltage VSS of the fourth voltage level V4 supplied from the cathode voltage generator 342 to the cathode electrode CE. To this end, the cathode voltage switching unit 346 includes first and second switching devices SW1 and SW2, as shown in FIG.

The first switching device SW1 is connected to the gate terminal to which the voltage control signal VCS is supplied, the first terminal to which the cathode voltage VSS of the third voltage level V3 is supplied, and the cathode electrode CE And a second terminal connected to the output channel (Ch). Here, the first switching device SW1 may be an N-type transistor. The first switching device SW1 is turned on according to the voltage control signal VCS of the high logic state to generate the cathode voltage VSS of the third voltage level V3 during the sensing period SP So that the light emitting devices OLED of all the pixels P of the display panel 110 are turned off, that is, non-emitting state, during the sensing period SP by supplying them to the cathode electrode CE.

The second switching device SW2 includes a gate terminal to which a voltage control signal VCS is supplied, a first terminal to which a cathode voltage VSS of a fourth voltage level V4 is supplied, And a second terminal. Here, the second switching device SW2 may be a P-type transistor. The second switching device SW2 is turned on according to the voltage control signal VCS of the low logic state to generate the fourth voltage level Vdd during the display period DP excluding the sensing period SP V4 to the cathode electrode CE to cause each pixel P of the display panel 110 to emit light during the display period DP excluding the sensing period SP described above.

12 is a waveform diagram showing driving waveforms in the sensing mode of the OLED display according to the second embodiment of the present invention.

The operation of the sensing period of the pixel P shown in FIG. 4 will be described with reference to FIGS. 9 to 12 as follows.

The timing controller 210 controls the driving timing of each of the gate driver 220, the data driver 230 and the voltage supplier 340 to initialize the sensing period SP for the pixel P The period t1, the voltage charging period t2, and the voltage sensing period t3. A driving voltage VDD having a constant voltage level is continuously supplied from the voltage supplier 340 to the driving voltage line PLi of the display panel 110 during the sensing period SP.

In the initialization period t1, the first and second gate signals GSa and GSb of the gate-on voltage level are supplied to the first and second gate lines GLa and GLb by the gate driver 220, The sensing data voltage Vdata is supplied from the data driver 230 to the data line DLi and the precharging voltage Vpre is supplied to the sensing line SLi . At the same time, the cathode voltage (VSS) of the third voltage level (V3) is supplied to the cathode electrode (CE) formed on the display panel (110) by the voltage supplier (340). Thereby, each of the first and second switching transistors Tsw1 and Tsw2 of the pixel P is turned on by the first and second gate signals GSa and GSb of the gate-on voltage level, The data voltage Vdata is supplied to the node n1 and the voltage of the second node n2 is initialized to the precharging voltage Vpre so that the data voltage Vdata and the pre- (Vdata-Vpre) of the voltage Vref is charged.

Next, in the voltage charging period t2, the first and second gate signals GSa and GSb supplied to the first and second gate lines GLa and GLb by the gate driver 220, On voltage level and the cathode voltage VSS supplied to the cathode electrode CE of the display panel 110 by the voltage supply unit 340 is maintained at the third voltage level V3. At the same time, the sensing data line (Vdata) is continuously supplied to the data line (DLi) by the data driver (230) and the sensing line (SLi) is floated. Accordingly, in the voltage charging period t2, the driving transistor Tdr is turned on by the sensing data voltage Vdata, and the voltage corresponding to the current flowing in the driving transistor Tdr, which is turned on, State sensing line SLi. The sensing line SLi connected to the pixel P is charged with a voltage corresponding to the threshold voltage of the driving transistor Tdr.

Then, in the voltage sensing period t3, the first gate signal GSa of the gate-off voltage level is supplied to the first gate line GLa by the gate driver 220, The second gate signal GSb supplied to the gate electrode of the transistor Q3 is maintained at the gate-on voltage level. At the same time, the cathode voltage VSS supplied to the cathode electrode CE of the display panel 110 by the voltage supplier 340 is maintained at the third voltage level V3, and the driving of the data driver 230 The sensing line SLi floating in the voltage charging period t2 is connected to the data driver 230 again. Accordingly, during the voltage sensing period t3, the data driver 230 senses the voltage charged in the sensing line SLi connected to the pixel P, and outputs the sensed voltage, that is, the driving transistor Tdr, And supplies the sensing data Sdata to the timing control unit 210. The timing control unit 210 supplies the timing control unit 210 with the sensing data Sdata.

On the other hand, the timing controller 210 senses the threshold voltage of the driving transistor Tdr of each pixel P through the sensing period SP as described above, and then moves the driving transistor Tdr of each pixel P It is possible to re-execute the sensing mode for sensing the degree. In this case, the timing controller 210 performs the same sensing mode as described above, except that the first switching transistor Tsw1 of the pixel P is turned on only during the initialization period t1, The gate driver 220 and the data driver 230 are controlled such that the gate driver 220 and the data driver Vdata are supplied only during the initialization period t1. Accordingly, when the sensing mode is resumed, the gate-source voltage of the driving transistor Tdr is increased due to the turn-off of the first switching transistor Tsw1 during the voltage charging period t2, The gate-source voltage of the driving transistor Tdr is held by the voltage so that the voltage corresponding to the current flowing through the driving transistor Tdr, that is, the voltage corresponding to the mobility of the driving transistor Tdr is applied to the floating sensing line SLi, . When the sensing mode is resumed, the data driver 230 senses the voltage charged in the sensing line SLi, that is, the voltage corresponding to the mobility of the driving transistor Tdr, and outputs the sensed voltage to the sensing data Sdata And provides it to the timing control unit 210. [

Accordingly, the organic light emitting display according to the second embodiment of the present invention includes sensing data SL1 to SLi, sensing data corresponding to the threshold voltage / mobility of the driving transistor Tdr of each pixel P, The variation of the characteristic of the driving transistor Tdr of each pixel P can be compensated periodically or in real time by reflecting the input data Idata of each pixel P by generating the data signal Sdata.

The organic light emitting display according to the second embodiment of the present invention changes the cathode voltage VSS supplied to the display panel 110 in the sensing mode, OLED) is turned off, that is, in a non-emission state, thereby preventing an image quality defect such as a line stripe caused by a luminance difference between horizontal lines due to the sensing period SP.

Meanwhile, in the display period of the OLED display according to the second embodiment of the present invention, the cathode voltage VSS is supplied to the display panel 110 at a fourth voltage level V4 as shown in FIG. 8 is the same as the display period of the organic light emitting display according to the first embodiment of the present invention described above with reference to FIG. 8, so that a description thereof will be omitted. Here, the cathode voltage VSS of the fourth voltage level V4 has the same voltage level as the cathode voltage supplied to the cathode electrode of the pixel during the display period of FIG.

The organic light emitting display according to the present invention as described above is configured such that the display panel 110 uses the plurality of sensing lines SL1 to SLi connected to each pixel P to generate a blank of the vertical synchronization signal Vsync The sensing data Sdata is sensed by sensing the change in the characteristics of the driving transistor Tdr of the pixel P every sensing interval SP overlapping the sensing period BP, The characteristic variation deviation of the driving transistor Tdr of the pixel P can be compensated periodically or in real time by reflecting the input data Idata of the pixel P by driving the pixel P. [

The organic light emitting display according to embodiments of the present invention may change the voltage level of the driving voltage VDD or the cathode voltage VSS supplied to the display panel 110 within the sensing period SP, (P) included in the horizontal line corresponding to the sensing period (SP) while sensing the characteristic change of the driving transistor (Tdr) due to the luminance difference between the horizontal lines can do.

3 and 9, the gate driver 220 is connected to one side of each of the first to m-th gate line groups GL1 to GLm. However, the present invention is not limited to this, And may be connected to both sides of the plurality of gate line groups GL1 to GLm for minimization. Similarly, the data driver 230 may be connected to both sides of each of the plurality of data lines DL1 to DLn to minimize the voltage drop of the data voltage Vdata. Each of the driving voltage VDD and the cathode voltage VSS may be supplied to the display panel 110 through the data driver 230.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

110: display panel 120:
210: timing controller 220: gate driver
230: Data driver 240, 340: Voltage supply
242, 342: cathode voltage generator 244, 344: driving voltage generator
246: driving voltage switching unit 346: cathode voltage switching unit

Claims (10)

A display panel including a plurality of pixels each having a driving transistor for causing a light emitting element to emit light with a data current based on a data voltage; And
Sensing data is generated by sensing at least one of a threshold voltage and a mobility of the driving transistor during the sensing period and compensating the input data according to the sensing data during the sensing period, And a panel driver for generating a voltage,
Wherein the panel driver turns off the light emitting elements of all the pixels during the sensing period. The method according to claim 1,
Wherein the panel driver changes a driving voltage supplied to the driving transistor of each pixel during the sensing period to turn off the light emitting elements of all the pixels during the sensing period. 3. The method of claim 2,
Wherein the panel driver supplies a driving voltage of a first voltage level to the driving transistors of the pixels in the sensing period and drives a driving voltage of a second voltage level higher than the first voltage level in the display period, And supplies the current to the transistor. The method according to claim 1,
Wherein the panel driver changes the cathode voltage supplied to the light emitting elements of all the pixels during the sensing period to turn off the light emitting elements of all the pixels during the sensing period. 5. The method of claim 4,
Wherein the panel driver supplies a cathode voltage of a third voltage level to the light emitting elements of all the pixels in the sensing period and supplies a cathode voltage of a fourth voltage level lower than the third voltage level to the light emitting elements of all pixels And the organic light emitting diode is supplied to the device. 1. A method of driving an organic light emitting display device including a display panel including a plurality of pixels each having a driving transistor for emitting a light emitting element with a data current based on a data voltage,
Setting a sensing period and a display period;
Sensing at least one of a threshold voltage and a mobility of the driving transistor during the sensing period to generate sensing data; And
And generating the data voltage by compensating the input data according to the sensing data during the display period,
And the light emitting elements of all the pixels in the sensing period are in an off state. The method according to claim 6,
Wherein the light emitting elements of all the pixels in the sensing period are turned off by a change in driving voltage supplied to the driving transistors of the pixels. 8. The method of claim 7,
Wherein the driving voltage has a first voltage level in the sensing period,
Wherein the driving voltage has a second voltage level higher than the first voltage level in the display period. The method according to claim 6,
Wherein the light emitting element of each pixel includes a cathode electrode,
Wherein the light emitting elements of all the pixels in the sensing period are turned off by a change in the cathode voltage supplied to the cathode electrode. 10. The method of claim 9,
In the sensing period, the cathode voltage has a third voltage level,
Wherein the cathode voltage has a fourth voltage level lower than the third voltage level in the display period.

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