KR101678214B1 - Shift register and display device using the same - Google Patents

Abstract

The present invention relates to a shift register and a display device using the shift register.
The n-th stage of the shift register includes a first pull-up transistor for outputting an n-th clock signal of a gate high level as a first output signal in accordance with the potential of the Q-node, A first pull-down transistor for outputting a first low-level voltage at a first gate low level as a first output signal in accordance with a potential of a QB node, a second pull-up transistor for outputting a clock signal as a second output signal, , A second pull-down transistor for outputting a second low potential voltage of a second gate low level lower than the first gate low level as a second output signal in accordance with the second gate low level, According to an output signal, a first transistor for applying a first output signal of the previous stage to the Q node and a second transistor for applying a second output signal of the second stage And a second transistor for applying a first low potential voltage to the Q node according to an output signal.

Description

[0001] SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME [0002]

The present invention relates to a shift register and a display device using the shift register.

Various flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes (Cathode Ray Tube). In general, the scan driver of the flat panel display device sequentially supplies scan pulses to scan lines using a shift register.

The shift register of the scan driver includes thin film transistors (hereinafter referred to as "TFTs ") and includes a plurality of stages connected in a dependent manner. The stages sequentially generate scan pulses and supply them to the scan lines. 1 shows a configuration of an n-th stage for generating an n-th scan pulse Vout (n) to be supplied to an n-th scan line.

1, the n-th stage includes a Q-node for controlling a pull-up transistor Tpu, a Q-bar node for controlling a pull-down transistor, Node). The pull-up transistor Tpu is turned on in the first output period in which the potential of the Q node is maintained at the charge level, and the shift clock signal CLKn is set to the nth scan pulse Vout (n) at the gate high level Output. The pull-up transistor Tpu is turned off during the second output period in which the potential of the Q node is maintained at the discharge level. The potential of the QB node is maintained at the discharge level during the first output period and is maintained at the charge level during the second output period. Due to the potential of the QB node, the pull-down transistor Tpd is turned on during the second output period to output the low potential voltage VSS as the nth scan pulse Vout (n) at the gate low level (Vgl). The pull-down transistor Tpd is turned off during the first output period.

The first, fifth, and sixth transistors T1, T5, and T6 connected to the Q node charge and discharge the voltage of the Q node through the switching action. The second to fourth transistors T2 to T4 connected to the QB node charge and discharge the voltage of the QB node through the switching action.

Recently, a gate in panel (GIP) technique for forming such transistors (Tpu, Tpd, T1 to T6) on a display panel is known. According to this GIP technique, the transistors Tpu, Tpd, T1 to T6 can be implemented in a depletion mode TFT. The depletion-mode TFT has a faster response characteristic than a normal enhancement-mode TFT.

As shown in FIG. 2, the depletion mode TFT has a disadvantage that the current blocking function is not properly performed at Vgs = 0V because the threshold voltage is shifted to (-). The following is a brief description of the problem. In order to normally output the scan pulse Vout (n) of the gate high level (Vgh) in Fig. 1, the pull-up transistor Tpu is turned on in the state where the potential of the Q node is maintained at the charge level within the first output period The pull-down transistor Tpd must be kept turned off during the first output period in addition to the turn-on. However, during the first output period, the potential of the Q node is not maintained at the charge level by the current leakage of the fifth and sixth transistors T5 and T6 turned off, and is lowered to the discharge level. In addition, current leakage also occurs in the pulldown transistor Tpd turned off during the first output period. As a result, the scan pulse Vout (n) of the gate high level (Vgh) is not normally output as shown by the solid line in FIG. In FIG. 2, 'Vgs' indicates the gate-source voltage of the TFT and 'Ids' indicates the drain-source current of the TFT, respectively. In FIG. 3, 'VQ' indicates the potential of the Q node, and 'VQB' indicates the potential of the QB node.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a shift register and a display device using the shift register.

In order to achieve the above object, according to an embodiment of the present invention, an n-th stage of a shift register including a plurality of stages connected in cascade is configured to shift an n-th clock signal of a gate high level A first pull-up transistor for outputting an output signal; A second pull-up transistor for outputting the n-th clock signal of the gate high level as a second output signal in accordance with the potential of the Q node; A first pull-down transistor for outputting the first low potential voltage of the first gate low level as the first output signal in accordance with the potential of the QB node; A second pull-down transistor for outputting, as the second output signal, a second low potential voltage of a second gate low level lower than the first gate low level in accordance with the potential of the QB node; A first transistor for applying a first output signal of the previous stage to the Q node according to a second output signal of any one of front stage stages arranged in front of the nth stage; And a second transistor for applying the first low potential voltage to the Q node in accordance with a second output signal of any one of the following single stages arranged behind the n-th stage.

The shift register according to the present invention and the display device using the shift register can greatly improve the output characteristics of the scan pulse.

1 is a view showing a configuration of a conventional n-th stage;
2 is a diagram showing a threshold voltage shift of a TFT.
3 is a view showing that a scan pulse is not normally output due to leakage current of a TFT.
4 is a view showing a display device according to an embodiment of the present invention.
Fig. 5 schematically shows the structure of a shift register; Fig.
6 is a schematic view showing a circuit configuration of an n-th stage according to the first embodiment;
FIG. 7 shows waveforms of the control signals supplied in FIG. 6; FIG.
8 is a first example showing in detail the circuit configuration of the n-th stage of Fig.
Fig. 9 is a second example showing in detail the circuit configuration of the n-th stage of Fig. 6;
10 is a third example showing the circuit configuration of the n-th stage of Fig. 6 in detail.
11 is a fourth example showing the circuit configuration of the n-th stage of Fig. 6 in detail.
12 is a fifth example showing the circuit configuration of the n-th stage of FIG. 6 in detail.
13 is a sixth example showing the circuit configuration of the n-th stage in Fig. 6 in detail.
Fig. 14 is a view schematically showing a circuit configuration of an n-th stage according to the second embodiment; Fig.
Fig. 15 shows waveforms of the control signals supplied in Fig. 14; Fig.
16 is an example showing in detail the circuit configuration of the n-th stage of Fig.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 4 to 16. FIG.

4 shows a display device according to an embodiment of the present invention. 5 schematically shows the structure of a shift register.

Referring to FIG. 4, the display device includes a display panel 10, a timing controller 11, a data driver 12, and a scan driver.

The display panel 10 includes data lines DL and scan lines GL intersecting with each other, and pixels arranged in a matrix form. The display panel 10 includes a display area 10A in which a pixel array is formed and a non-display area 10B outside the display area 10A. The display panel 10 may be implemented as a display panel of any one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoretic display (EPD).

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock DCLK from a video source through an LVDS or TMDS interface receiving circuit And receives a signal. The timing controller 11 generates timing control signals for controlling the operation timing of the data driver 12 and the scan driver on the basis of the input timing signal.

The data driver includes a plurality of source drive ICs. The source drive ICs receive digital video data (RGB) from the timing controller 11. The source drive ICs convert the digital video data RGB to a gamma compensation voltage in response to a source timing control signal DDC from the timing controller 11 to generate a data voltage and synchronize the data voltage with the scan pulse To the data lines (DL) of the display panel (10). The source drive ICs may be connected to the data lines DL of the display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The scan driver includes a level shift 13 and a shift register 14 connected between the timing controller 11 and the scan lines GL of the display panel 10.

The level shifter 13 shifts the shift clock signals CLK input from the timing controller 11 at a transistor-transistor-logic (TTL) level of 0 V to 3.3 V to a gate high level Vgh and a specific gate low level Vgl , And then supplies the resultant to the shift register 14. Here, the specific gate low level (Vgl) indicates the second gate low level.

The shift register 14 includes a plurality of stages STn-1 to STn + 2 cascade-connected as shown in FIG. The stages STn-1 to STn + 2 shift the gate start pulse Vstart according to the shift clock signals CLK to sequentially output scan pulses.

In the GIP scheme, the level shifter 13 is mounted on the control PCB together with the timing controller 11, and the shift register 14 can be formed on the non-display area 10B of the display panel 10. [

Hereinafter, the structure of the shift register 14 according to various embodiments of the present invention will be described in detail. However, for convenience of explanation, the shift clock signals CLK are implemented in four phases, and a specific stage (n-th stage) is set according to the second output signal of the front stage (n-2 stage) And the second output signal of the stage ((n + 2) th stage) is reset. However, the technical idea of the present invention is that the shift clock signals CLK are implemented in at least two phases and that the specific stage (n-th stage) is set according to the second output signal of either the front stage And reset according to the second output signal of any one of the subsequent stages.

6 schematically shows a circuit configuration of the n-th stage according to the first embodiment. Fig. 7 shows the waveforms of the control signals supplied in Fig.

6, the n-th stage STn according to the first embodiment switches the current path between the input terminal of the n-th clock signal CLKn and the first output node No1 according to the potential of the Q node Down transistor Tpu1 and a first pull-down transistor Tpd1 for switching the current path between the first output node No1 and the input terminal of the first low potential voltage VSS1 according to the potential of the QB node , And outputs the first output signal Vout (n) swung between the gate high level (Vgh) and the first gate low level (Vgl1) to the first output node (No1). The n-th stage STn includes a second pull-up transistor Tpu2 for switching the current path between the input terminal of the n-th clock signal CLKn and the second output node No2 according to the potential of the Q node, And a second pull-down transistor Tpd2 for switching a current path between the second output node No2 and the input terminal of the second low potential voltage VSS2 according to the potential of the node so that the gate high level Vgh and the second And outputs a second output signal Vout_C (n) swinging between the gate low level (Vgl2) to the second output node (No2).

The first output signal Vout (n) is supplied to the nth scan line GL (n) and the (n + 2) th stage STn + 2 via the first output node No1. The first output signal Vout (n) functions as a scan pulse. The second output signal Vout_C (n) is supplied to the (n-2) th stage STn-2 and the (n + 2) th stage STn + 2 via the second output node No2. The second output signal Vout_C (n) functions as a set / reset signal.

The n-th clock signal CLKn is swung between a gate high level Vgh and a second gate low level Vgl2 as shown in FIG. 7, and sequentially generates first to fourth clock signals CLK1 to CLK4, . ≪ / RTI > The first to fourth clock signals CLK1 to CLK4 can be generated overlappingly between neighbors as shown and can also be generated non-overlappingly. 7, the high-potential voltage VDD is set to the gate high level Vgh, the first low-potential voltage VSS1 is set to the first gate low level Vgl1, which is lower than the gate high level Vgh, 2 low potential voltage VSS2 may be input to the second gate low level (Vgl2) lower than the first gate low level (Vgl1).

The potential of the QB node is maintained at the discharge level (second gate low level (Vgl2)) during the first output period in which the potential of the Q node is maintained at the charge level (gate high level (Vgh)), During the second output period held at the discharge level (second gate low level (Vgl2)), the potential of the QB node is maintained at the charge level (gate high level (Vgh)). The first and second pull-up transistors Tpu1 and Tpu2 are turned on in the first output period to output the first and second output signals Vout (n) and Vout_C (n) of the gate high level (Vgh) do. Then, the first and second pull-up transistors Tpu1 and Tpu2 are all turned off during the second output period. The first and second pull-down transistors Tpd1 and Tpd2 are all turned off during the first output period and turned on during the second output period to turn off the first and second gate low levels Vgl1 and Vgl2 1 and the second output signals Vout (n) and Vout_C (n).

The n-th stage STn includes a first transistor T1 for maintaining the potential of the Q node at the charge level during the first output period and a second transistor T1 for maintaining the potential of the Q node at the discharge level during the second output period. And a transistor T2. The first transistor T1 is switched in response to the second output signal Vout_C (n-2) from the n-2th stage STn-2, And applies the first output signal Vout (n-2) of the high level (Vgh) to the Q node. The second transistor T2 is turned on in response to the second output signal Vout_C (n + 2) from the (n + 2) th stage STn + 2 to generate the first low potential (VSS1) to the Q node.

In this n-th stage STn, during the first output period in which the potential of the Q node is maintained at the charge level, the gate-source voltage Vgs of the second transistor T2 and the gate voltage of the gate of the first pull-down transistor Tpd1 The source-to-source voltage Vgs is lower than 0 V (Vgl2-Vgl1 < 0 V), so that current leakage by the second transistor T2 and the first pull-down transistor Tpd1 does not occur. During the first output period in which the potential of the Q node is maintained at the charge level, the gate-source voltage Vgs of the first transistor T1 is lower than 0 V (Vgl2-Vgl1 <0 V) The leakage of current by the first transistor T1 does not occur. As a result, the first output signal Vout (n) can be output to the scan line GLn at a good level as shown by the dotted line in Fig.

Fig. 8 is a first example showing in detail the circuit configuration of the n-th stage shown in Fig.

8, the n-th stage STn includes, in addition to the pull-up transistors Tpu1 and Tpu2, the pull-down transistors Tpd1 and Tpd2, the first transistor T1 and the second transistor T2, And third to fifth transistors T3 to T5.

The third transistor T3 switches the current path between the QB node and the input terminal of the second low potential voltage VSS2 according to the potential of the Q node. The fourth transistor T4 applies the high potential voltage VDD to the QB node. The third transistor T3 is turned on during the first output period in which the potential of the Q node is maintained at the charge level (gate high level (Vgh)), thereby turning the potential of the QB node to the discharge level (the second gate low level (Vgl2) (The gate high level Vgh) by turning off the QB node during the second output period in which the potential of the Q node is maintained at the discharge level (the second gate low level Vgl2) .

The fifth transistor T5 is switched in response to the (n-1) -th clock signal CLK (n-1) so that the second output signal Vout_C (n-1) from the n-1th stage STn- To the Q node. The fifth transistor T5 maintains the Q node at the second gate low level Vgl2 ahead of the gate high level voltage of the nth clock signal CLKn supplied to the pull-up transistors Tpu1 and Tpu2, (Tpu1, Tpu2) is effectively turned on.

FIG. 9 is a second example showing in detail the circuit configuration of the n-th stage shown in FIG.

9, the n-th stage STn includes the pull-up transistors Tpu1 and Tpu2, the pull-down transistors Tpd1 and Tpd2, the first internal fifth transistors T1 to T5 , A sixth transistor (T61) and a sixth transistor (T62).

The sixth transistor T61 is connected between the output terminal of the (n-2) th stage STn-2 from which the first output signal Vout (n-2) is output and the first transistor T1, 2 in response to the second output signal Vout_C (n-2) from the second stage STn-2. The sixth transistor T62 is connected between the first node N1 and the second output node No2 that connects the sixth transistor T61 and the first transistor T1 and outputs an nth clock signal CLKn. &Lt; / RTI &gt; On the other hand, although not shown in the figure, the gate electrode of the sixth transistor T62 may be connected to the second output node No2. In this case, the sixth-transistor T62 can switch the current path between the first node N1 and the second output node No2 in response to the potential of the second output node No2.

The sixth transistor T61 and the sixth transistor T62 prevent the voltage at the node Q from discharging through the first transistor T1 during the first output period to thereby stabilize the operation stability of the stage STn Increase.

Fig. 10 is a third example showing in detail the circuit configuration of the n-th stage shown in Fig.

10, the n-th stage STn includes the pull-up transistors Tpu1 and Tpd2, the pull-down transistors Tpd1 and Tpd2, the first internal fifth transistors T1 to T5, , And a seventh transistor (T7).

The seventh transistor T7 switches the current path between the Q node and the input terminal of the second low potential voltage VSS2 by being switched in response to the gate start pulse Vstart. The seventh transistor T7 is turned on during a period in which the gate start pulse Vstart is maintained at the gate high level Vgh as shown in FIG. 7, so that the potential of the Q node is set to the second gate low level (Vgl2). As a result, the operation stability of the stage STn is further improved.

11 is a fourth example showing in detail the circuit configuration of the n-th stage shown in Fig.

11, the n-th stage STn includes the pull-up transistors Tpu1 and Tpu2, the pull-down transistors Tpd1 and Tpd2 and the first and fifth transistors T1 to T5 The sixth transistor T61, the sixth transistor T62 and the seventh transistor T7 in addition to the first transistor T11.

The connection structure of the sixth transistor T61 and the sixth transistor T62 and the operation and effects thereof are substantially the same as the description of Fig. 9, and the connection structure of the seventh transistor T7 and its operation effect Is substantially the same as the description of Fig.

FIG. 12 is a fifth example showing in detail the circuit configuration of the n-th stage shown in FIG.

12, the n-th stage STn includes the pull-up transistors Tpu1 and Tpd2, the pull-down transistors Tpd1 and Tpd2, the first, second and fifth transistors T1 and T2, , T2, T5. However, the n-th stage STn need not have the third and fourth transistors T3 and T4 unlike the configuration shown in Fig. In other words, the n-th stage STn uses pull-down transistors Tpd1 and Tpd2 (n + 2) using a clock signal that does not overlap with the n-th clock signal CLKn, The third and fourth transistors T3 and T4 can be omitted. By directly controlling the switching operation of the pull-down transistors Tpd1 and Tpd2 using the non-overlapping clock signal, it is possible to easily prevent a circuit malfunction that may occur due to instability of the QB node voltage.

FIG. 13 is a sixth example showing in detail the circuit configuration of the n-th stage shown in FIG.

Referring to FIG. 13, the n-th stage STn further includes a sixth transistor T61, a sixth transistor T62 and a seventh transistor T7 in addition to the components shown in FIG.

The connection structure of the sixth transistor T61 and the sixth transistor T62 and the operation and effects thereof are substantially the same as the description of Fig. 9, and the connection structure of the seventh transistor T7 and its operation effect Is substantially the same as the description of Fig.

14 schematically shows the circuit configuration of the n-th stage according to the second embodiment. Fig. 15 shows the waveforms of the control signals supplied in Fig.

14 and 15, the n-th stage STn according to the second embodiment includes QB nodes as a pair of QB_O node and QB_E node, and a first output node No1 and a first low potential voltage A second pull-down transistor Tpd1 connected between the second output node No2 and the input terminal of the second low potential voltage VSS2, and a second pull-down transistor Tpd2 connected between the input terminal of the second low- . Then, each pair is alternately operated at a period of a predetermined period (e.g., k (k is a positive integer) frame). That is, in the n-th stage STn, when any one of the pair of QB node pairs, the first pull-down transistor pair, and the second pull-down transistor pair is normally driven, the other one of the pair is driven in the idle state, And idle drive. To this end, the high-potential voltage input to the n-th stage STn includes an odd high-potential voltage VDD_O and a even-high-potential voltage VDD_E whose potentials are inverted in a period of a predetermined period T as shown in FIG. It can have an alternating current form. The odd high potential voltage VDD_E is input to the second gate low level Vgl2 while the odd high potential voltage VDD_O is input to the gate high level Vgh, And the even high voltage (VDD_E) is input to the gate high level (Vgh) during the period of inputting to the low level (Vgl2). 16, the first pull-down transistor Tpd1 pair includes a first odd pull-down transistor Tpd1_O and a first unipulled transistor Tpd1_E and the second pull-down transistor Tpd2 pair includes a second odd pull- Tpd2_O) and a second even-numbered pull-down transistor (Tpd2_E). With this alternating operation, the degradation of the corresponding switches including the pull-down transistor pairs is greatly reduced.

In addition to the configuration and operation effect for the alternate operation, the n-th stage STn has substantially the same configuration and operational effects as the first embodiment of Fig. In this n-th stage STn, during the first output period in which the potential of the Q node is maintained at the charge level, the gate-source voltage Vgs of the second transistor T2 and the gate voltage Vgs of the first odd- (Vgl2-Vgl1 < 0V), the current leakage due to the second transistor T2 and the first pull-down transistor Tpd1 does not occur since the gate-source voltage Vgs of the first transistor T2 is lower than 0V. During the first output period in which the potential of the Q node is maintained at the charge level, the gate-source voltage Vgs of the first transistor T1 is lower than 0 V (Vgl2-Vgl1 <0 V) The leakage of current by the first transistor T1 does not occur. As a result, the first output signal Vout (n) can be output to the scan line GLn at a good level as shown by the dotted line in Fig.

FIG. 16 is an example showing in detail the circuit configuration of the n-th stage shown in FIG.

Referring to Fig. 16, the n-th stage STn adds a configuration for the alternating operation to the fourth example of the first embodiment (see Fig. 11). The pull-up transistors Tpu1 and Tpu2, the first and second transistors T1 and T2, the fifth transistor T5, the sixth and the sixth transistors T61 and T62, The transistor T7 is substantially the same as the configuration of Fig.

The n-th stage STn constitutes a pair of the third and fourth transistors for alternating operation.

For each odd number of predetermined periods, the third odd transistor T3_O switches the current path between the QB_O node and the input terminal of the second low potential voltage VSS2 according to the potential of the Q node. The fourth odd transistor T4_O applies the odd high potential (VDD_O) to the QB_O node. The third odd transistor T3_O is turned on during the first output period in which the potential of the Q node is maintained at the charge level (gate high level (Vgh)), thereby switching the potential of the QB_O node to the discharge level (the second gate low level (The gate high level Vgh) by turning off the QB_O node potential during the second output period in which the potential of the Q node is maintained at the discharge level (the second gate low level Vgl2) . The potential of the QB_O node controls the switching operation of the first and second odd pull-down transistors Tpd1_O and Tpd2_O. In the odd-numbered predetermined periods, the third and fourth even-numbered transistors T3_E and T4_E and the first and second even-numbered pull-down transistors Tpd1_E and Tpd2_E are idle-driven.

The third even-numbered transistors T3_E switch the current path between the QB_E node and the input terminal of the second low-potential voltage VSS2 according to the potential of the Q-node. The fourth even transistor T4_E applies the even higher potential voltage VDD_E to the QB_E node. The third even-numbered transistor T3_E is turned on during the first output period in which the potential of the Q-node is maintained at the charge level (gate high level (Vgh)), so that the potential of the QB_E node is set to the discharge level (The gate high level Vgh) by turning off the QB_E node during the second output period in which the potential of the Q node is maintained at the discharge level (the second gate low level Vgl2) . The potential of the QB_E node controls the switching operation of the first and second unipolar transistors Tpd1_E and Tpd2_E. In the odd second predetermined periods, the third and fourth odd transistors T3_O and T4_O and the first and second odd pull-down transistors Tpd1_O and Tpd2_O are idle-driven.

On the other hand, the alternating operation configuration of the second embodiment can also be applied to the first to third examples (see Figs. 8 to 10) of the first embodiment.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Data driver 13: Level shifter
14: Scan driver

Claims (14)

A shift register comprising a plurality of cascaded stages,
In the n-th stage,
A first pull-up transistor for outputting, as a first output signal, an nth clock signal of a gate high level in accordance with the potential of the Q node;
A second pull-up transistor for outputting the n-th clock signal of the gate high level as a second output signal in accordance with the potential of the Q node;
A first pull-down transistor for outputting the first low potential voltage of the first gate low level as the first output signal in accordance with the potential of the QB node;
A second pull-down transistor for outputting, as the second output signal, a second low potential voltage of a second gate low level lower than the first gate low level in accordance with the potential of the QB node;
A first transistor for applying a first output signal of the previous stage to the Q node according to a second output signal of any one of front stage stages arranged in front of the nth stage; And
And a second transistor for applying the first low potential voltage to the Q node according to a second output signal of any one of subsequent stages arranged behind the nth stage,
Wherein the first pull-up transistor and the first pull-down transistor are serially connected through a first output node between an input terminal of the n-th clock signal and an input terminal of the first low potential voltage,
Wherein the second pull-up transistor and the second pull-down transistor are serially connected through a second output node between an input terminal of the n-th clock signal and an input terminal of the second low potential voltage. The method according to claim 1,
A first output signal applied to the first output node swings between the gate high level and the first gate low level,
And a second output signal applied to the second output node swings between the gate high level and the second gate low level. 3. The method of claim 2,
Wherein one of said front stage stages is an (n-2) stage, and one of said next stage stages is an (n + 2) stage. The method of claim 3,
A third transistor for switching a current path between the QB node and the input terminal of the second low potential voltage according to the potential of the Q node;
A fourth transistor for applying a high potential voltage to the QB node; And
and a fifth transistor for applying a second output signal of the (n-1) th stage to the Q node according to an (n-1) th clock signal. 5. The method of claim 4,
A sixth transistor for switching a current path between the first output node of the (n-2) th stage and the first transistor according to a second output signal of the (n-2) th stage; And
And a sixth node for switching the current path between the first node connecting the sixth transistor and the first transistor and the second output node according to the nth clock signal or the potential of the second output node, A shift register further comprising a transistor. 5. The method of claim 4,
And a seventh transistor for switching a current path between the Q node and the input terminal of the second low potential voltage according to a gate start pulse. 5. The method of claim 4,
A sixth transistor for switching a current path between the first output node of the (n-2) th stage and the first transistor according to a second output signal of the (n-2) th stage;
A sixth transistor for switching a current path between a first node connecting the sixth transistor and the first transistor and the second output node according to the nth clock signal; And
And a seventh transistor for switching a current path between the Q node and the input terminal of the second low potential voltage according to a gate start pulse. The method of claim 3,
and a fifth transistor for applying a second output signal of the (n-1) -th stage to the Q-node according to an (n-1) -th clock signal;
And the first and second pull-down transistors are controlled by an (n + 2) -th clock signal. 9. The method of claim 8,
A sixth transistor for switching a current path between the first output node of the (n-2) th stage and the first transistor according to a second output signal of the (n-2) th stage;
And a sixth node for switching the current path between the first node connecting the sixth transistor and the first transistor and the second output node according to the nth clock signal or the potential of the second output node, transistor; And
And a seventh transistor for switching a current path between the Q node and the input terminal of the second low potential voltage according to a gate start pulse. 8. The method according to any one of claims 4 to 7,
The QB node includes a QB_O node and a QB_E node;
The first pull-down transistor includes a first odd pull-down transistor controlled according to a potential of the QB_O node and a first non-pull down transistor controlled according to a potential of the QB_E node;
The second pull-down transistor includes a second odd pull-down transistor controlled in accordance with a potential of the QB_O node and a second non-inverted pull-down transistor controlled according to a potential of the QB_E node;
The third transistor includes a third odd transistor connected to the QB_O node and a third even transistor connected to the QB_E node;
The fourth transistor includes a fourth odd transistor connected to the QB_O node and a fourth even transistor connected to the QB_E node;
And the third odd transistor and the fourth odd transistor, the third even transistor, and the fourth even transistor are alternately operated in a period of a predetermined period. A display panel including a plurality of pixels intersecting the data lines and the scan lines and arranged in a matrix form;
A data driver for supplying a data voltage to the data lines; And
And a scan driver for sequentially supplying scan pulses to the scan lines, the scan driver including a plurality of stages connected in cascade,
Wherein the n &lt; th &gt; stage of the scan driver comprises:
A first pull-up transistor for outputting, as a first output signal, an nth clock signal of a gate high level in accordance with the potential of the Q node;
A second pull-up transistor for outputting the n-th clock signal of the gate high level as a second output signal in accordance with the potential of the Q node;
A first pull-down transistor for outputting the first low potential voltage of the first gate low level as the first output signal in accordance with the potential of the QB node;
A second pull-down transistor for outputting, as the second output signal, a second low potential voltage of a second gate low level lower than the first gate low level in accordance with the potential of the QB node;
A first transistor for applying a first output signal of the previous stage to the Q node according to a second output signal of any one of front stage stages arranged in front of the nth stage; And
And a second transistor for applying the first low potential voltage to the Q node according to a second output signal of any one of subsequent stages arranged behind the nth stage,
Wherein the first pull-up transistor and the first pull-down transistor are serially connected through a first output node between an input terminal of the n-th clock signal and an input terminal of the first low potential voltage,
And the second pull-up transistor and the second pull-down transistor are connected in series through a second output node between an input terminal of the n-th clock signal and an input terminal of the second low potential voltage. 12. The method of claim 11,
A first output signal applied to the first output node is swung between the gate high level and the first gate low level;
And a second output signal applied to the second output node swings between the gate high level and the second gate low level. A shift register comprising a plurality of cascaded stages,
In the n-th stage,
A first pull-up transistor for outputting, as a first output signal, an nth clock signal of a gate high level in accordance with the potential of the Q node;
A second pull-up transistor for outputting the n-th clock signal of the gate high level as a second output signal in accordance with the potential of the Q node;
A first pull-down transistor for outputting the first low potential voltage of the first gate low level as the first output signal in accordance with the potential of the QB node;
A second pull-down transistor for outputting, as the second output signal, a second low potential voltage of a second gate low level lower than the first gate low level in accordance with the potential of the QB node;
A first transistor for applying a first output signal of the previous stage to the Q node according to a second output signal of any one of front stage stages arranged in front of the nth stage; And
And a second transistor for applying the first low potential voltage to the Q node according to a second output signal of any one of the subsequent stages arranged behind the n-th stage. 14. The method of claim 13,
A first output signal applied to the first output node is swung between the gate high level and the first gate low level;
A second output signal applied to the second output node is swung between the gate high level and the second gate low level;
Wherein the first pull-up transistor and the first pull-down transistor are serially connected through the first output node between an input of the nth clock signal and an input of the first low potential voltage;
And the second pull-up transistor and the second pull-down transistor are serially connected through the second output node between the input terminal of the n-th clock signal and the input terminal of the second low potential voltage.

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