KR102579251B1 - Gate driver and display device including the same, and driving method of the same - Google Patents

Abstract

A gate driver according to an embodiment of the present invention includes a plurality of stages that swing between a gate-on voltage and a gate-off voltage and output a plurality of scan signals whose phases are sequentially delayed; a plurality of clock wires supplying clock signals with different phases to the stages; and a start wire that supplies a start signal to a first stage that operates first among the stages, and during a power-on period before the start signal is input as the gate-on voltage, the clock signals reset the stages. is input as the gate-on voltage.

Description

Gate driver, display device including the same, and driving method thereof {GATE DRIVER AND DISPLAY DEVICE INCLUDING THE SAME, AND DRIVING METHOD OF THE SAME}

The present invention relates to a gate driver and a display device including the same.

Electroluminescent displays are roughly divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. Among these, the active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness and It has the advantage of a large viewing angle.

An organic light emitting display device arranges pixels, each including OLED, in a matrix form and adjusts the luminance of the pixels according to the gradation of image data. Each pixel includes a driving TFT (Thin Film Transistor) that controls the driving current flowing through the OLED according to the gate-source voltage, and switch TFTs that program the gate-sort voltage of the driving TFT according to the scan signal. The display gradation (brightness) is adjusted by the amount of light emitted by the OLED that is proportional to the current.

The organic light emitting display device includes a gate driver that generates a scan signal. The gate driver sequentially supplies scan signals to the gate lines. The scan signal is supplied to the switch TFT of each pixel through gate lines to control the switching operation of the switch TFT.

The gate driver can be implemented as a gate shift register consisting of multiple stages. Each stage outputs a scan signal as a gate-off voltage or gate-on voltage depending on the potentials of node Q and node QB. The scan signal of the gate-off voltage is a voltage that can turn off the switch TFTs, and the scan signal of the gate-on voltage is a voltage that can turn on the switch TFTs. In each stage, a scan signal of the gate-on voltage is output while node Q is activated, and a scan signal of the gate-off voltage is output while node QB is activated.

The potentials of node Q and node QB are controlled by a start signal (or carry signal) and clock signals. Clock signals swing between a gate-on voltage and a gate-off voltage and may be applied to the stages through a plurality of clock wires. Clock signals applied through different clock wires may have different phases. While node Q is activated in each stage, the clock signal of the gate-on voltage is output as a scan signal of the gate-on voltage.

In order to ensure the operational stability of this gate driver, the potential of node Q and the potential of node QB in each stage must be controlled to be opposite to each other. In other words, node QB must be deactivated with the gate-off voltage while node Q is activated with the gate-on voltage, and conversely, node QB must be activated with the gate-on voltage while node Q is deactivated with the gate-off voltage.

If the potential of node Q and the potential of node QB become unknown, the scan signal cannot be output normally. A problem in which node Q and node QB are in an unknown state may occur during initial operation of the gate driver. Initial driving occurs during the power-on period immediately after the driving power of the display device is applied. In order to resolve the above-mentioned unknown state, a method of simultaneously initializing the stages with separate reset signals during initial operation is used. Through this reset operation, node Q and node QB are initialized to opposite gate-on voltages or gate-off voltages rather than the unlocked state, and abnormal driving due to distortion of the scan signal can be prevented.

However, in order to perform the above-described reset operation, separate signal wires and switch elements that supply reset signals to the stages are needed, making the connection configuration of the stages complicated. The gate driver can be formed directly in the bezel area of the display panel, but in this case, if the connection configuration of the stages is complicated, it is difficult to reduce the bezel area.

Therefore, the present invention was developed to solve the conventional problems, and provides a gate driver that ensures stability of operation by resetting all stages without a separate reset signal during initial operation, a display device including the same, and a method of driving the same. provides.

A gate driver according to an embodiment of the present invention includes a plurality of stages that swing between a gate-on voltage and a gate-off voltage and output a plurality of scan signals whose phases are sequentially delayed; a plurality of clock wires supplying clock signals with different phases to the stages; and a start wire that supplies a start signal to a first stage that operates first among the stages, and during a power-on period before the start signal is input as the gate-on voltage, the clock signals reset the stages. is input as the gate-on voltage.

During the power-on period, the start signal is input as the gate-off voltage.

Each of the stages includes a transistor T5 that outputs a scan signal of the gate-on voltage to node Na while node Q is bootstrapped; Transistor T3 for applying the gate-on voltage to the node QB by one of the clock signals; a transistor T6 that outputs a scan signal of the gate-off voltage to the node Na while the node QB is activated with the gate-on voltage; Transistor T2 for applying the gate-off voltage to node QA while node QB is activated with the gate-on voltage; a transistor T7 that applies the gate-off voltage to the node QB according to the potential of the node QA; Transistor T1 for applying the gate-on voltage to the node QA according to the start signal or carry signal; and a transistor T4 that applies the gate-off voltage to the node QB according to the start signal or carry signal.

Each of the stages further includes a transistor TA that is connected between the node QA and the node Q and is turned off only while the node Q is bootstrapped.

During the power-on period, the node QB is reset to the gate-on voltage by turning on the transistor T3, and the node QA and the node Q are reset to the gate-off voltage by turning on the transistor T2 and the transistor TA. is reset to

During the power-on period, the transistor T5 is turned off by the gate-off voltage of the node Q, the transistor T6 is turned on by the gate-on voltage of the node QB, and the start signal of the gate-off voltage Accordingly, the transistor T1 and the transistor T4 are turned off, and the transistor T7 is turned off by the gate-off voltage of the node QA.

Additionally, a method of driving a gate driver according to an embodiment of the present invention includes supplying clock signals of different phases to a plurality of stages through a plurality of clock wires; supplying a start signal through a start wire to a first stage that operates first among the stages; and outputting, from the stages, a plurality of scan signals whose phases are sequentially delayed and swing between a gate-on voltage and a gate-off voltage in response to the start signal and the clock signals, wherein the start signal is transmitted to the gate. During the power-on period before being input as the on-voltage, the clock signals are input as the gate-on voltage to reset the stages.

In the present invention, clock signals are applied to the stages as a gate-on voltage for a reset operation during initial driving. Through this, the present invention can secure operational stability by resetting all stages without a separate reset signal during initial operation. The present invention can simplify the stage connection configuration and reduce the bezel size by omitting a separate reset signal and removing the transistor that operates according to the reset signal within each stage.

1 is a diagram showing a display device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a pixel array formed on the display panel of FIG. 1.
FIG. 3 is a diagram schematically showing one pixel circuit included in the pixel array of FIG. 2.
FIG. 4 is a diagram showing a data signal and a gate signal applied to the pixel circuit of FIG. 3.
FIG. 5 is a diagram showing a scan driver and an emission driver included in the gate driver of FIG. 1.
FIG. 6 is a diagram showing the configuration of a gate shift register included in the scan driver of FIG. 5.
FIG. 7 is a diagram showing the configuration of one stage included in the gate shift register of FIG. 6.
FIG. 8 is a diagram showing an example of an incorrect start signal and clock signal applied to the gate shift register of FIG. 6.
FIG. 9 is a diagram for explaining malfunction of the gate shift register according to the start signal and clock signals of FIG. 8.
FIG. 10 is a diagram showing an optimal example of the start signal and clock signal applied to the gate shift register of FIG. 6.
FIG. 11 is a diagram illustrating normal operation of the gate shift register after being reset according to the start signal and clock signals of FIG. 10.
FIG. 12 is a diagram showing the operation waveform of the first stage of FIG. 7.
FIGS. 13A to 13E are diagrams showing stage operation states corresponding to sections ① to section ⑤ of FIG. 12, respectively.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to substantially like elements throughout the specification.

In the present invention, the pixel circuit and gate driver formed on the substrate of the display panel may be implemented as a TFT with a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but are not limited to this. TFT is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the TFT, carriers begin to flow from the source. The drain is the electrode through which carriers go out of the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. Therefore, in the description of the embodiment of the present invention, one of the source and the drain is described as the first electrode, and the other one of the source and the drain is described as the second electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. In the following embodiments, the description will focus on an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present invention is not limited to organic light emitting display devices, but can be applied to inorganic light emitting display devices including inorganic light emitting materials.

Figure 1 shows a display device according to an embodiment of the present invention. FIG. 2 shows a pixel array formed on the display panel of FIG. 1. FIG. 3 schematically shows one pixel circuit included in the pixel array of FIG. 2. FIG. 4 shows a gate signal applied to the pixel circuit of FIG. 3. Figure 5 shows the scan driver and emission driver included in the gate driver of Figure 1.

1 to 5, the display device of the present invention includes a display panel 100, a timing controller 110, a data driver 120, a gate driver 130, and a level shifter 150.

Referring to FIGS. 1 and 2, a plurality of data lines 14 and a plurality of gate lines 15a and 15b intersect in the display panel 100, and pixels PXL are formed in a matrix form in each intersection area. It can be arranged to form a pixel array. In the display panel 100, a pixel array is formed in the active area (AA) where an image is displayed, and a bezel area (BZ) where an image is not displayed is disposed outside the pixel array.

The pixel array of the display panel 100 is provided with a plurality of horizontal pixel lines (L1 to L4) as shown in FIG. 2, and each horizontal pixel line (L1 to L4) is horizontally adjacent and has gate lines (15a, 15b). A plurality of commonly connected pixels (PXL) are disposed. Here, each of the horizontal pixel lines L1 to L4 is not a physical signal line, but rather a set of pixels for one line implemented by horizontally neighboring pixels PXL. The pixel array includes a first power line 17 that supplies a high-potential power supply voltage (EVDD) to the pixels (PXL), and a second power line 16 that supplies an initialization voltage (Vint) to the pixels (PXL). You can. Additionally, the pixels PXL may be connected to the low-potential power supply voltage EVSS. Each of the gate lines may include a first gate line 15a to which the scan signal SCAN is supplied, and a second gate line 15b to which the emission signal EM is supplied, as shown in FIG. 2 .

Each of the pixels PXL may be one of a red pixel, a green pixel, a blue pixel, and a white pixel. Red pixels, green pixels, blue pixels, and white pixels constitute one unit pixel and can implement various colors. The color implemented in a unit pixel may be determined according to the emission ratio of the red pixel, green pixel, blue pixel, and white pixel. Meanwhile, white pixels may be omitted from this unit pixel. A data line 14, a first gate line 15a, a second gate line 15b, a first power line 17, a second power line 16, etc. may be connected to each of the pixels PXL.

As shown in FIG. 3, each of the pixels PXL may include an OLED and a switch circuit (SWC) that generates a driving current to drive the OLED. The switch circuit (SWC) includes a plurality of switch TFTs for programming the gate-source voltage of the driving TFT according to at least one scan signal (SCAN), and a driving circuit that generates a driving current according to the programmed gate-source voltage. It may include a TFT and at least one capacitor. The switch circuit (SWC) may further include an emission TFT (ET) that is turned on/off according to the emission signal (EM) to determine the emission timing of the OLED. The switch circuit (SWC) can be configured in various ways depending on the product model and specifications. The TFTs included in each pixel (PXL) can be implemented as a PMOS-type LTPS TFT, and through this, the desired response characteristics can be secured. However, the technical idea of the present invention is not limited thereto. For example, among the TFTs, at least one TFT may be implemented as an NMOS-type oxide TFT with good off-current characteristics, and the remaining TFTs may be implemented as PMOS-type LTPS TFTs with good response characteristics.

For example, each of the pixels PXL may be driven according to a data signal and a gate signal as shown in FIG. 4 . In this case, each of the pixels PXL may perform an initialization operation, a programming operation, a holding operation, and an emission operation according to the scan signal SCAN and the emission signal EM. For operational safety during the initialization period (A), the switch circuit (SWC) may initialize specific nodes within the pixel circuit to the initialization voltage (Vint). During the programming period (B), the switch circuit (SWC) may program the gate-source voltage of the driving TFT based on the data voltage (Vdata). During the programming period (B), the threshold voltage of the driving TFT can be sampled and compensated. During the holding period (C), the voltage between the gate and source of the driving TFT may be stabilized. And, during the emission period (D), a driving current corresponding to the gate-source voltage flows between the source and drain of the driving TFT, and this driving current causes the OLED to emit light. Meanwhile, the emission TFT can be controlled to turn on only during the emission period (C) according to the emission signal (EM).

In FIG. 4, Gate On Voltage is the voltage of a gate signal (scan signal, emission signal) at which TFTs of pixels can be turned on. Gate Off Voltage is the voltage of the gate signal at which the TFT can be turned off. For example, in PMOS, the gate-on voltage (VGL) is a gate low voltage, and the gate-off voltage (VGH) is a gate high voltage that is higher than the gate low voltage.

Referring to FIG. 1, the data driver 120 receives image data (DATA) and a source timing control signal (DDC) from the timing controller 110. The data driver 120 converts the image data (DATA) into a gamma compensation voltage in response to the source timing control signal (DDC) from the timing controller 110 to generate a data voltage (Vdata), and the data voltage (Vdata) is supplied to the data lines 14 of the display panel 100 in synchronization with the scan signal SCAN. The data driver 120 may be connected to the data lines of the display panel 100 through a Chip On Glass (COG) process or a Tape Automated Bonding (TAB) process.

Referring to FIG. 1, the level shifter 150 uses the Transistor-Transistor-Logic (TTL) level voltage of the gate timing control signal (GDC) input from the timing controller 110 to drive the TFT formed on the display panel 100. Boosting is performed using the available gate high voltage (VGH) and gate low voltage (VGL) and supplied to the gate driver 130.

Referring to FIG. 1, the gate driver 130 operates according to the gate timing control signal (GDC) input from the level shifter 150 to generate a gate signal. Then, the gate signal is sequentially supplied to the gate lines. The gate driver 130 may be formed directly on the lower substrate of the display panel 100 using a gate driver in panel (GIP) method. The gate driver 130 is formed in a non-display area (i.e., bezel area BZ) outside the screen of the display panel 100. In the GIP method, the level shifter 150 may be mounted on a printed circuit board (Printed Circuit Board) 140 together with the timing controller 110.

The gate driver 130 is provided in a double bank manner on both opposing sides of the display panel 100 as shown in FIG. 5, so that signal distortion due to load variation of each gate line can be minimized. The gate driver 130 includes a scan driver 131 that generates a scan signal (SCAN) and an emission driver 132 that generates an emission signal (EM).

The scan driver 131 may supply the scan signal SCAN to the first gate lines 15a(1) to 15a(n) in a line sequential manner. The emission driver 132 may supply the emission signal EM to the second gate lines 15b(1) to 15b(n) in a line sequential manner. The scan driver 131 may be implemented as a gate shift register consisting of multiple stages.

Referring to FIG. 1, the timing controller 110 may be connected to an external host system (not shown) through various known interface methods. The timing controller 110 receives image data (DATA) from the host system, corrects the image data (DATA) to compensate for the luminance deviation due to differences in electrical characteristics of the pixels (PXL), and then sends the image data (DATA) to the data drivers 120. Can be transmitted.

The timing controller 110 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock (MCLK) from the host system, and receives these timing signals. Based on this, a gate timing control signal (GDC) and a source timing control signal (DDC) can be generated. The gate timing control signal (GDC) may include an external start signal, clock signals, etc.

FIG. 6 shows the configuration of a gate shift register included in the scan driver 131 of FIG. 5.

Referring to FIG. 6, the scan driver 131 according to an embodiment of the present invention may be implemented with a gate shift register consisting of a plurality of stages (ST1 to ST4,...). The stages ST1 to ST4,... may be GIP elements formed directly on the display panel.

The stages (ST1~ST4,...) are sequentially activated according to the external start signal (VST) and output scan signals (SCAN(1)~SCAN(4),...). The top stage (ST1) is activated according to the external start signal (VST), and the next top stage (ST2) to the bottom stage are activated according to the scan signal of the previous stage. The scan signal of the front stage is an internal start signal and becomes the carry signal (CRY). Here, the “front stage” refers to a stage that is located above the reference stage and generates a scan signal that is ahead in phase compared to the scan signal output from the reference stage.

The stages (ST1 to ST4,...) receive an external start signal (VST) and a plurality of clock signals (CLK1) from the level shifter 150 in order to output scan signals (SCAN(1) to SCAN(4),...). ~CLK4) can be input. Both the external start signal (VST) and the clock signals (CLK1 to CLK4) swing between a gate-off voltage (eg, gate high voltage (VGH)) and a gate-on voltage (eg, gate low voltage (VGL)).

In particular, during the power-on period, the voltages of the clock signals (CLK1 to CLK4) and the voltage of the external start signal (VST) are input opposite to each other so that all stages (ST1 to ST4,...) are initialized without a separate reset signal. . The power-on period refers to the initial driving period before the external start signal (VST) is input as the gate-on voltage (VGL). During the power-on period, the external start signal (VST) is input as the gate-off voltage (VGH), and the clock signals (CLK1 to CLK4) are all input as the gate-on voltage (VGL).

The stages (ST1 to ST4,...) may be connected to the signal wires (CL1 to CL4) and the power wires (WL1, WL2) through a plurality of connection terminals (A1, A2, B1, B2, C1). The signal wire CL5 may be connected to the top stage (ST1), where the operation is performed first among the stages (ST1 to ST4,...).

Clock signals CLK1, CLK2, CLK3, and CLK4 are applied to the signal wires CL1, CL2, CL3, and CL4, respectively. An external start signal (VST) is applied to the signal wire CL5. A gate-off voltage (VGH) and a gate-on voltage (VGL) are applied to the power wires WL1 and WL2, respectively.

Each of the stages (ST1 to ST4,...) has a clock terminal B1 to which a first clock signal is input so as to be synchronized with the scan signals (SCAN(1) to SCAN(4)), and a second clock signal whose phase is behind the first clock signal. It includes a clock terminal B2 to which is input. Here, the first clock signal and the second clock signal may be determined from clock signals CLK1 to CLK4. In this case, the first to fourth clock signals are different from each other in four adjacent stages (ST1 to ST4). The first and second clock signals are clock signals CLK1 and CLK3 in the first stage (ST1), clock signals CLK2 and CLK4 in the second stage (ST2), and clock signals CLK3 in the third stage (ST3). ,CLK1, and may be clock signals CLK4 and CLK2 in the fourth stage (ST4).

Each of the stages (ST1 to ST4,...) includes a VGH power terminal A1 to which a gate-off voltage (VGH) is input, a VGL power terminal A2 to which a gate-on voltage (VGL) is input, and an external start signal (VST) or It includes a start terminal (C1) into which an internal start signal (or carry signal) is input.

FIG. 7 shows the first stage configuration included in the gate shift register of FIG. 6. The configuration of the second upper stage to the lowermost stage in FIG. 6 is substantially the same as that of the first stage, except that there is a difference in the input clock signal.

Referring to FIG. 7, the first stage ST1 may include an output unit, a QA control unit, a QB control unit, and a degradation reduction unit.

The output unit may include a transistor T5 controlled according to node Q, a transistor T6 controlled according to node QB, and a capacitor CB connected to node Q and node Na.

Transistor T5 is a pull-up device that outputs a scan signal (SCAN(1)) of the gate-on voltage (VGL) to node Na while node Q is bootstrapped according to the clock signal CLK1. The gate electrode of transistor T5 is connected to node Q, the first electrode is connected to clock terminal B1, and the second electrode is connected to node Na.

Capacitor CB is connected between node Q and node Na. When the clock signal CLK1 is inverted from the gate-off voltage (VGH) to the gate-on voltage (VGL) while the potential of node Q is the gate-on voltage (VGL), the potential of node Q becomes gate-on due to the coupling effect of the capacitor CB. The voltage (VGL) drops to a lower boosting level. Due to this bootstrapping, the potential of the node Na quickly drops to the gate-on voltage (VGL). Using the bootstrapping effect, the scan signal (SCAN(1)) of the gate-on voltage (VGL) can be output quickly and without distortion.

Transistor T6 is a pull-down element that outputs a scan signal (SCAN(1)) of the gate-off voltage (VGH) to node Na when node QB is activated with the gate-on voltage (VGL). The gate electrode of transistor T6 is connected to node QB, the first electrode is connected to node Na, and the second electrode is connected to VGH power supply terminal A1.

The QA control unit may include transistors T1 and T2 that control the potential of node QA.

Transistor T1 is switched according to an external start signal (VST) whose phase is ahead of the clock signal CLK1 and applies a gate-on voltage (VGL) to node QA. The gate electrode of transistor T1 is connected to the start terminal C1, the first electrode is connected to the VGL power supply terminal A2, and the second electrode is connected to the node QA.

Transistor T2 is switched according to the potential of node QB and applies a gate-off voltage (VGH) to node QA. The gate electrode of transistor T2 is connected to node QB, the first electrode is connected to node QA, and the second electrode is connected to VGH power supply terminal A1.

The QB control unit may include transistors T3, T4, and T7 that control the potential of node QB and a capacitor CQB.

Transistor T3 switches according to the clock signal CLK3, which is out of phase with the clock signal CLK1, activating node QB with the gate-on voltage (VGL). The gate electrode of transistor T3 is connected to the clock terminal B2, the first electrode is connected to the VGL power supply terminal A2, and the second electrode is connected to the node QB.

Transistor T4 switches according to the external start signal (VST) to disable node QB to the gate-off voltage (VGH). The gate electrode of transistor T4 is connected to the start terminal C1, the first electrode is connected to the VGH power supply terminal A1, and the second electrode is connected to the node QB.

Transistor T7 disables node QB with its gate-off voltage (VGH) while node QA is activated. The gate electrode of transistor T7 is connected to node QA, the first electrode is connected to VGH power supply terminal A1, and the second electrode is connected to node QB.

Capacitor CQB is connected between node QB and VGH power supply terminal A1 to stabilize the potential of node QB while node QB is floating.

The degradation reduction unit may be implemented with a transistor TA connected between node Q and node QA. The gate electrode of transistor TA is connected to the VGL power supply terminal A2. Transistor TA is normally turned on by the gate-on voltage (VGL) input from the VGL power supply terminal A2. However, during the period when node Q is bootstrapped, the gate-source voltage applied to transistor TA becomes lower than the threshold voltage, so transistor TA is turned off.

Transistor TA remains turned on and turns off only while the potential of node Q is boosted, blocking the current between node Q and node QA. Even if the potential of node Q is boosted, the effect is not applied to the transistors T1, T2, and T7 with one electrode connected to node QA. Accordingly, the voltage between the drain and source of the transistors T1, T2, and T7 is prevented from increasing due to the boosting potential of the node Q. In other words, when node Q is bootstrapped, if the voltage between the drain and source of transistors T1, T2, and T7 increases above the threshold, device destruction, or so-called break down phenomenon, may occur due to overload. Problems can be prevented in advance.

FIG. 8 is a diagram showing an example of an incorrect start signal and clock signal applied to the gate shift register of FIG. 6. And, FIG. 9 is a diagram for explaining malfunction of the gate shift register according to the start signal and clock signals of FIG. 8.

Referring to FIG. 8, no separate reset signal is applied during the power-on period (PON), and the start signal (VST) and clock signals CLK1 to 4 are all input as the gate-off voltage (VGH). Since the clock signals CLK1 to CLK4 are all input as the gate-off voltage (VGH), node Q and node QB of the stages cannot be reset in the power-on period (PON). That is, in the power-on period (PON), node Q and node QB of the stages are not reset to the gate-on voltage (VGL) or gate-off voltage (VGH) and are maintained in a floating state.

In the display period (DIS) following the power-on period (PON), the start signal (VST) is input as the gate-on voltage (VGL) and the operation of the top stage begins. Then, the top to bottom stages begin operation by receiving the output of the previous stage as a carry signal (internal start signal).

With further reference to FIG. 9, the operations of the stages in the display period (DIS) are as follows. Because node Q and node QB of the stages were not reset in the power-on period (PON), some scan signals are distorted in the display period (DIS) as shown in FIG. 9. For example, in section ①, all scan signals of stages 1 to 8 must be output at a gate-off voltage (i.e., high level (H)), but in the case of stages 4 and 8, the scan signals are output at an abnormal voltage (M). It is being distorted. The abnormal voltage (M) is a third voltage that is not defined by the gate-off voltage (i.e., high level (H)) and the gate-on voltage (i.e., low level (L)). This is due to the fact that nodes Q and node QB of the corresponding stages 4 and 8 and the preceding stages 3 and 7 are floating (indicated by “X” in FIG. 9). Distortion of the scan signal also appears in sections ② to ⑤. If the scan signal is distorted like this, image data cannot be written normally to the display panel.

FIG. 10 is a diagram showing an optimal example of the start signal and clock signal applied to the gate shift register of FIG. 6. And, FIG. 11 is a diagram to explain the normal operation of the gate shift register after being reset according to the start signal and clock signals of FIG. 10.

Referring to FIG. 10, no separate reset signal is applied in the power-on period (PON), the start signal (VST) is input as the gate-off voltage (VGH), and clock signals CLK1 to 4 are all input at the gate-on voltage (VGH). It is being input as VGL). Since the clock signals CLK1 to CLK4 are all input as the gate-on voltage (VGL), node Q and node QB of the stages can be reset simultaneously during the power-on period (PON) without a separate reset signal. That is, in the power-on period (PON), the nodes QB of the stages are simultaneously reset to the gate-on voltage (VGL) by the clock signal of the gate-on voltage (VGL) (i.e., the clock signal applied to B2 in FIG. 7), and the nodes Q can be reset simultaneously with the gate-off voltage (VGH).

In the display period (DIS) following the power-on period (PON), the start signal (VST) is input as the gate-on voltage (VGL) and the operation of the top stage begins. Then, the top to bottom stages begin operation by receiving the output of the previous stage as a carry signal (internal start signal).

With further reference to FIG. 11, the operations of the stages in the display period (DIS) are as follows. Since node Q and node QB of the stages are reset simultaneously in the power-on period (PON), distortion of scan signals in the display period (DIS) can be prevented as shown in FIG. 11. That is, in section ②, all scan signals of stages 1 to 8 are output at a gate-off voltage (i.e., high level (H)), and in section ③ to section ⑨, the scan signals of stages 1 to 8 are sequentially gated. It is output at on voltage (i.e. low level (L)).

FIG. 12 is a diagram showing the operation waveform of the first stage of FIG. 7. And, FIGS. 13A to 13E are diagrams showing stage operation states corresponding to sections ① to section ⑤ of FIG. 12, respectively. Here, section① corresponds to the power-on period, and section② to section⑤ corresponds to the display period.

Referring to FIGS. 12 and 13A, for the reset operation in section ①, the external start signal (VST) is input as the gate-off voltage (VGH) and the clock signals CLK1 to CLK4 are input as the gate-on voltage (VGL). A separate reset signal is not input.

In section ①, transistors T1 and T4 are turned off according to the external start signal (VST) of the gate-off voltage (VGH). In section ①, transistor T3 is turned on according to the clock signal CLK3 of the gate-on voltage (VGL), and node QB is reset to the gate-on voltage (VGL). Then, transistor T2 is turned on according to the gate-on voltage (VGL) of node QB, and node QA and node Q are reset to the gate-off voltage (VGH). Transistor TA is turned on by the gate-on voltage (VGL), so node QA and node Q are at the same potential.

In section ①, transistor T5 is turned off according to the gate-off voltage (VGH) of node Q, and transistor T6 is turned on according to the gate-on voltage (VGL) of node QB. Accordingly, the scan signal (SCAN(1)) output from node Na becomes the gate-off voltage (VGH).

Referring to Figures 12 and 13b, in section ②, the external start signal (VST) and clock signal CLK4 are input as the gate-on voltage (VGL), and the clock signals CLK1, CLK2, and CLK3 are input as the gate-off voltage (VGH). do.

In section ②, transistors T1 and T4 are turned on according to the external start signal (VST) of the gate-on voltage (VGL), and the gate-on voltage (VGL) is applied to node QA, and the gate-off voltage (VGH) is applied to node QB. This is approved. At this time, transistor T3 is turned off according to the clock signal CLK3 of the gate-off voltage (VGH).

In section ②, transistor T2 is turned off according to the gate-off voltage (VGH) of node QB. Then, transistor T7 is turned on according to the gate-on voltage (VGL) of node QA and applies the gate-off voltage (VGH) to node QB. In section ②, transistor TA remains on, and the potential of node Q becomes the gate-on voltage (VGL).

In section ②, transistor T6 is turned off according to the gate-off voltage (VGH) of node QB, and transistor T5 is turned on according to the gate-on voltage (VGL) of node Q. Accordingly, the scan signal (SCAN(1)) output from node Na becomes the gate-off voltage (VGH) of the clock signal CLK1.

Referring to FIGS. 12 and 13C, in section ③, the clock signal CLK1 is input as the gate-on voltage (VGL), and the external start signal (VST) and clock signals CLK4, CLK2, and CLK3 are input as the gate-off voltage (VGH). do.

In section ③, the transistors T1 and T4 are turned off according to the external start signal (VST) of the gate-off voltage (VGH), and the node QA is floated. At this time, transistor T3 remains in the off state according to the clock signal CLK3 of the gate-off voltage (VGH). In section ③, transistor T7 is turned on according to the gate-on voltage (VGL) of node QA and applies the gate-off voltage (VGH) to node QB.

In section ③, when the clock signal CLK1 of the gate-on voltage (VGL) is input, the potential of node Q is bootstrapped and lowered from the gate-on voltage (VGL) to a lower boosting voltage (VGL'). At this time, transistor TA is turned off to electrically block node QA and node Q, thereby eliminating boosting stress applied to transistors T1, T2, and T7.

In section ③, transistor T6 remains off according to the gate-off voltage (VGH) of node QB, and transistor T5 remains on according to the boosting voltage (VGL') of node Q. Therefore, the scan signal (SCAN(1)) output from node Na becomes the gate-on voltage (VGL) of the clock signal CLK1.

Referring to Figures 12 and 13D, in section ④, the clock signal CLK2 is input as the gate-on voltage (VGL), and the external start signal (VST) and clock signals CLK4, CLK1, and CLK3 are input as the gate-off voltage (VGH). do.

In section ④, the transistors T1 and T4 remain in the off state according to the external start signal (VST) of the gate-off voltage (VGH), and the node QA continues to float. At this time, transistor T3 is also maintained in an off state according to the clock signal CLK3 of the gate-off voltage (VGH). In section ④, transistor T7 remains on according to the gate-on voltage (VGL) of node QA and applies the gate-off voltage (VGH) to node QB.

In section ④, when the clock signal CLK1 of the gate-off voltage (VGH) is input, the potential of node Q increases from the boosting voltage (VGL') to the gate-on voltage (VGL). At this time, transistor TA is turned on.

In section ④, transistor T6 remains off according to the gate-off voltage (VGH) of node QB, and transistor T5 remains on according to the gate-on voltage (VGL) of node Q. Accordingly, the scan signal (SCAN(1)) output from node Na becomes the gate-off voltage (VGH) of the clock signal CLK1.

Referring to Figures 12 and 13e, in section ⑤, the clock signal CLK3 is input as the gate-on voltage (VGL), and the external start signal (VST) and clock signals CLK4, CLK1, and CLK2 are input as the gate-off voltage (VGH). do.

In section ⑤, transistor T3 is turned on according to the clock signal CLK3 of the gate-off voltage (VGH), and the gate-on voltage (VGL) is applied to node QB. Then, transistor T2 is turned on by the gate-on voltage (VGL) of node QB, and the gate-off voltage (VGH) is applied to node QA. At this time, transistor T7 is turned off according to the gate-off voltage (VGH) of node QA, and transistors T1 and T4 remain off according to the external start signal (VST) of the gate-off voltage (VGH). Then, the transistor TA is turned on by the gate-on voltage (VGL), and the node Q becomes the gate-off voltage (VGH).

In section ⑤, transistor T5 is turned off according to the gate-off voltage (VGH) of node Q, and transistor T6 is turned on according to the gate-on voltage (VGL) of node QB. Accordingly, the scan signal (SCAN(1)) output from node Na becomes the gate-off voltage (VGH).

As described above, the present invention applies clock signals to the stages as a gate-on voltage for a reset operation during initial driving. Through this, the present invention can secure operational stability by resetting all stages without a separate reset signal during initial operation. The present invention can simplify the stage connection configuration and reduce the bezel size by omitting a separate reset signal and removing the transistor that operates according to the reset signal within each stage.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

100: display panel 110: timing controller
120: data driver 130: gate driver
131: scan driver

Claims (11)

A plurality of stages swinging between a gate-on voltage and a gate-off voltage and outputting a plurality of scan signals whose phases are sequentially delayed;
a plurality of clock wires supplying clock signals with different phases to the stages; and
It includes a start wire that supplies a start signal to the first stage that operates first among the stages,
During the power-on period before the start signal is input to the gate-on voltage, the clock signals are input to the gate-on voltage to reset the stages,
Each of the above stages is,
Transistor T5 that outputs a scan signal of the gate-on voltage to node Na while node Q is bootstrapped;
Transistor T3 for applying the gate-on voltage to node QB by any one of the clock signals;
a transistor T6 that outputs a scan signal of the gate-off voltage to the node Na while the node QB is activated with the gate-on voltage;
Transistor T2 for applying the gate-off voltage to node QA while the node QB is activated with the gate-on voltage;
a transistor T7 that applies the gate-off voltage to the node QB according to the potential of the node QA;
Transistor T1 for applying the gate-on voltage to the node QA according to the start signal or carry signal; and
A gate driver including a transistor T4 that applies the gate-off voltage to the node QB according to the start signal or carry signal. According to claim 1,
A gate driver wherein the start signal is input as the gate-off voltage during the power-on period. delete According to claim 1,
Each of the above stages is,
A gate driver further comprising a transistor TA connected between the node QA and the node Q and turned off only while the node Q is bootstrapped. According to claim 4,
During the power-on period,
By turning on the transistor T3, the node QB is reset to the gate-on voltage,
A gate driver in which the node QA and the node Q are reset to the gate-off voltage by turning on the transistor T2 and the transistor TA. According to claim 5,
During the power-on period,
The transistor T5 is turned off by the gate-off voltage of the node Q,
The transistor T6 is turned on by the gate-on voltage of the node QB,
The transistor T1 and transistor T4 are turned off according to the start signal of the gate-off voltage,
A gate driver in which the transistor T7 is turned off by the gate-off voltage of the node QA. delete delete A display device comprising the gate driver according to any one of claims 1 to 2 and claims 4 to 6. In a display device having a plurality of stages that receive a plurality of clock signals of different phases and output a plurality of scan signals whose phases are sequentially delayed and swing between a gate-on voltage and a gate-off voltage,
Each of the above stages is,
Transistor T1 for applying the gate-on voltage to node QA according to a start signal or carry signal;
Transistor T5 outputting a scan signal of the gate-on voltage to node Na while node Q is bootstrapped by a first clock signal whose phase is later than the start signal or carry signal;
Transistor T3 for applying the gate-on voltage to node QB in response to a second clock signal whose phase is later than the first clock signal;
a transistor T6 that outputs a scan signal of the gate-off voltage to the node Na while the node QB is activated with the gate-on voltage; and
While the node Q is bootstrapped, it is turned off to cut off the electrical connection between the node QA and the node Q, and while the node Q is not bootstrapped, it is turned on to electrically connect the node QA and the node Q. A display device containing a transistor TA. According to claim 10,
A display device in which the gate electrode of the transistor TA is connected to a power terminal of the gate-on voltage.