KR20200030422A - Gate driver for external compensation and organic light emitting display device including the same - Google Patents

Abstract

According to one embodiment of the present specification, a gate driver for external compensation capable of improving the driving reliability has a plurality of stages. Among the stages, an n^th stage continuously outputs an n^th emission signal for sensing and an n^th emission signal for display, an (n-1)^th stage outputs an (n-1)^th emission signal for display having a phase in advance of a phase of the n^th emission signal for sensing, and an (n+1)^th stage outputs an (n+1)^th emission signal for display having a phase posterior to the phase of the n^th emission signal for sensing.

Description

Gate driver for external compensation and organic light emitting display device including the same {GATE DRIVER FOR EXTERNAL COMPENSATION AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME}

The present specification relates to an external compensation gate driver and an organic light emitting display device including the same.

The organic light emitting display device arranges pixels including OLEDs on a display panel in a matrix form and adjusts the luminance of pixels according to the gradation of image data. Each of the pixels includes a driving thin film transistor (TFT) that controls the driving current flowing through the OLED according to the voltage between the gate and source, and switch TFTs that program the voltage between the gate and sort of the driving TFT according to the scan signal. The display gradation (luminance) is controlled by the amount of light emitted by the OLED proportional to the current. Further, each of the pixels may further include an emission TFT that is turned on / off according to the emission signal to determine the emission timing of the OLED.

Meanwhile, the organic light emitting display device uses an external compensation technology to enhance image quality. The external compensation technology compensates for driving characteristic deviation between pixels by sensing the pixel voltage or current according to the driving characteristic (or electrical characteristic) of the pixel, and modulating the data of the input image based on the sensed result. In order to implement such an external compensation technology, a gate driver suitable for it is required. The external compensation gate driver may include a scan driver generating a scan signal and an emission driver generating an emission signal.

The external compensation gate driver can be made of p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) -based transistors with low power consumption. The p-type MOSFET-based transistor has a large leakage current (Off current) and is weak against device stress. There are disadvantages. If the leakage current is large, the voltage of the Q node or QB node in the gate driver may become unstable and an incorrect gate output may be generated. In addition, if the device stress is large, the threshold voltage and mobility characteristics of the device may fluctuate and an incorrect gate output may occur.

Therefore, this specification improves the unstable holding characteristics caused by leakage current in the gate driver made of p-type MOSFET-based transistors and improves the circuit structure vulnerable to device stress to improve the driving reliability and the external compensation gate driver. An electroluminescent display device is provided.

The external compensation gate driver according to the exemplary embodiment of the present specification includes a plurality of stages. Among them, the n-th stage continuously outputs an n-th emission signal and an n-th emission signal, and the n-1th stage is n-1 in phase with the n-th emission signal. The output emission signal is output, and the n + 1 stage outputs an n + 1 display emission signal that is out of phase with the n-th sensing emission signal. The n-th stage applies a gate-on voltage to the node NO according to the voltage of the node Q, and applies a gate-off voltage to the node NO according to the voltage of the node QB, following the emission signal for the n-th sensing driving. Output unit elements for continuously outputting the n-th display driving emission signal; Based on the voltages of the first global signal, the second global signal, and the third global signal having different phases and waveforms, the emission signal for the n + 1 display, and the node QB at the rear end of the n + 1 stage. Sensing-related elements that control the voltage of the node Q and the voltage of the node QB; And a first stabilization unit refreshing the voltage of the node Q by bootstrapping according to a first clock signal.

According to the present specification, in the gate driver made of p-type MOSFET-based transistors, it is possible to improve unstable holding characteristics due to leakage current and improve driving reliability by improving a circuit structure vulnerable to device stress.

1 is a view showing an organic light emitting diode display according to an exemplary embodiment of the present specification.
FIG. 2 is a view showing a pixel array formed on the display panel of FIG. 1.
3 is a diagram schematically illustrating a pixel circuit included in the pixel array of FIG. 2.
FIG. 4 is a diagram for describing the data driver of FIG. 1.
5 is a view for explaining the gate driver of FIG. 1.
6 is a diagram illustrating a gate signal applied to the pixel array of FIG. 2.
7 is a diagram illustrating an example of a gate shift register constituting the emission driver of FIG. 5.
8 is a diagram illustrating one configuration of an n-th stage included in the gate shift register of FIG. 7.
9A to 9G are diagrams for describing an operation of the n-th stage illustrated in FIG. 8.
10 is a diagram illustrating another example of a gate shift register constituting the emission driver of FIG. 5.
FIG. 11 is a diagram illustrating one configuration of an n-th stage included in the gate shift register of FIG. 10.
12 is a driving waveform diagram for explaining the operation of FIG. 11.
13A to 13G are diagrams for describing an operation of the n-th stage illustrated in FIG. 11.

Advantages and features of the present specification, and a method of achieving them will be apparent with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the present embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person having the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. When 'include', 'have', 'consist of', etc. mentioned in this specification are used, other parts may be added unless '~ only' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In analyzing the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship of two parts is described as '~ on', '~ on top', '~ on the bottom', '~ next to', etc., 'right' Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

The first, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be the second component within the technical spirit of the present invention.

Throughout the specification, the same reference numerals refer to substantially the same components.

In the present specification, the gate driver formed on the substrate of the display panel may be implemented as a TFT of a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. TFT is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers begin to flow from the source. The drain is an electrode through which the carrier exits from the TFT. That is, the carrier flow in the MOSFET flows from the source to the drain. In the case of the p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be changed according to the applied voltage. Therefore, in the description of the embodiment of the present specification, any one of the source and the drain is described as the first electrode, and the other of the source and the drain is described as the second electrode.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following embodiments, the field display device will be mainly described with respect to an organic light emitting display device including an organic light emitting material. However, the technical idea of the present invention is not limited to the organic light emitting display device, and can be applied to an inorganic light emitting display device including an inorganic light emitting material.

1 is a view showing an organic light emitting diode display according to an exemplary embodiment of the present specification. FIG. 2 is a view showing a pixel array formed on the display panel of FIG. 1. 3 is a diagram schematically illustrating a pixel circuit included in the pixel array of FIG. 2. FIG. 4 is a diagram for describing the data driver of FIG. 1. And, FIG. 5 is a view for explaining the gate driver of FIG. 1.

1 to 5, the display device of the present specification may include a display panel 100, a timing controller 110, a data driver 120, a gate driver 130, and a level shifter 150. have.

In the display panel 100, a plurality of data lines 14 and a plurality of gate lines 15a, 15b, and 15c intersect, and pixels PXL are arranged in a matrix form for each of the intersection areas, thereby forming a pixel array Pixel. array). The pixels PXL may be arranged in various ways in addition to the matrix form to form a pixel array.

The pixel array is located in the active area AA of the display panel 100. The pixel array is provided with a plurality of horizontal pixel lines L1 to L4, and horizontally neighboring on each horizontal pixel line L1 to L4 and a plurality of pixels commonly connected to the gate lines 15a, 15b, and 15c. (PXL) is placed. Here, each of the horizontal pixel lines L1 to L4 is not a physical signal line, but refers to a pixel aggregate of one line that is implemented by horizontally neighboring pixels PXL. The pixel array includes a first power line 16 that supplies the reference voltage Vref to the pixels PXL and a second power line 17 that supplies the high potential power voltage EVDD to the pixels PXL. Can be included. Also, the pixels PXL may be further connected to the input terminal of the low potential power voltage EVSS.

The configuration of the gate lines 15a, 15b, and 15c may vary depending on the pixel circuit. For example, each of the gate lines, as shown in FIG. 2, a first gate line 15a to which a first scan signal SCAN1 is supplied, a second gate line 15b to which a second scan signal SCAN2 is supplied, and an emie The third gate line 15c to which the Sean signal EM is supplied may be included.

Each of the pixels PXL may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel. The red pixel, the green pixel, the blue pixel, and the white pixel may constitute one unit pixel for various color realization. The color implemented in the unit pixel may be determined according to the emission ratio of the red pixel, the green pixel, the blue pixel, and the white pixel. In some cases, a white pixel may be omitted from each unit pixel. Each of the pixels PXL includes a data line 14, a first gate line 15a, a second gate line 15b, a third gate line 15c, a first power line 16, and a second power line ( 17) etc. can be connected.

The pixel circuit can be configured in various ways. For example, each of the pixels PXL is an OLED as shown in FIG. 3, a switch circuit for programming the gate-source voltage Vgs of the driving TFT DT, and the OLED according to the gate-source voltage Vgs. It may include a driving TFT (DT) for controlling the driving current flowing in, and an emission TFT (ET) that is turned on / off according to the emission signal EM to determine the emission timing of the OLED. Here, the switch circuit may include a plurality of switch TFTs ST1 and ST2 and at least one or more storage capacitors CST, and various modifications are possible according to product models and specifications. The pixel circuit will be described with reference to FIG. 3 as follows.

Each pixel PXL includes an OLED, a driving TFT (DT), an emission TFT (ET), a storage capacitor (CST), a first switch TFT (ST1), and a second switch TFT (ST2). The TFT ET, the first switch TFT ST1, and the second switch TFT ST2 may be connected to different gate lines 15a, 15b, and 15c.

The OLED is a light emitting device, and includes an anode electrode connected to the source node Ns, a cathode electrode connected to the input terminal of the low potential power voltage (EVSS), and an organic compound layer positioned between the anode electrode and the cathode electrode.

The driving TFT DT is a driving element and controls driving current flowing through the OLED according to a voltage difference between the gate node Ng and the source node Ns. The driving TFT DT includes a gate electrode connected to the gate node Ng, a first electrode connected to one electrode of the emission TFT ET, and a second electrode connected to the source node Ns. The storage capacitor CST is connected between the gate node Ng and the source node Ns to store the gate-source voltage Vgs of the driving TFT DT.

The emission TFT (ET) is turned on / off according to the emission signal EM to determine the light emission timing of the OLED. The emission TFT ET includes a gate electrode connected to the third gate line 15c, a first electrode connected to the second power line 17 to which the high potential power voltage (EVDD) is applied, and a driving TFT (DT). And a second electrode connected to the first electrode.

The first switch TFT ST1 turns on the current flow between the first power line 16 and the gate node Ng according to the first scan signal SCAN1, so that the first power line 16 is charged. The voltage Vref is applied to the gate node Ng. The first switch TFT ST1 includes a gate electrode connected to the first gate line 15a, a first electrode connected to the first power line 16, and a second electrode connected to the gate node Ng. .

The second switch TFT ST2 turns on the current flow between the data line 14 and the source node Ns according to the second scan signal SCAN2, so that the data voltage Vdata charged in the data line 14 is turned on. Is applied to the source node Ns, or the voltage Vsen of the source node Ns according to the pixel current is transferred to the data line 14. The second switch TFT ST2 includes a gate electrode connected to the second gate line 15b, a first electrode connected to the data line 14, and a second electrode connected to the source node Ns.

Referring to FIG. 3, TFTs included in each of the pixels PXL may be implemented as a PMOS type LTPS TFT or an NMOS type LTPS TFT, thereby securing desired response characteristics. However, the technical spirit of the present specification is not limited thereto. For example, at least one TFT (for example, DT, ST1) among TFTs is implemented as an NMOS type oxide TFT having good off current characteristics, and the remaining TFTs (ET, ST2) are PMOS type LTPS having good response characteristics. It can also be implemented with TFT.

1 to 5, the data driver 120 communicates with the timing controller 110 through a preset interface circuit. The data driver 120 receives the image data DATA and the source timing control signal DDC from the timing controller 110 to generate a data voltage Vdata, and the data voltage Vdata to the data lines 14 ). Then, the data driver 120 receives the sensing voltage Vsen related to the driving characteristics of the pixels PXL through the data lines 14 to generate sensing data, and transmits the sensing data to the timing controller 110. send.

To this end, the data driver 120 is a switching unit (SWU) connected to each data line 14, a digital analog converter (Digital Analog Converter), which is selectively connected to the data line 14 according to the operation of the switching unit (SWU) DAC) and a sensing unit SU. The switching unit SWU may connect a digital-to-analog converter (DAC) to the data line 14 for driving a display, and may connect a sensing unit SU to the data line 14 for sensing driving.

The digital-to-analog converter (DAC) generates a data voltage (Vdata) when driving the display, and synchronizes the data voltage (Vdata) to the second scan signal (SCAN2) of the gate-on voltage to display the data line (14) of the display panel (100). ).

When the sensing unit SU senses the driving, the driving characteristics of the pixels PXL, for example, the threshold voltage and mobility of the driving TFT DT, and / or the operating point voltage of the OLED are the second scan signals of the gate-on voltage. It can be sensed through the data line 14 in synchronization with (SCAN2). The sensing unit SU may be implemented in a known voltage sensing type or a current sensing type. The voltage sensing type may sense the voltage Vsen charged in the source node Ns of the pixel PXL according to a predetermined sensing condition. The current sensing type may obtain a sensing voltage Vsen by directly sensing the current flowing through the source node Ns of the pixel PXL according to a predetermined sensing condition.

The data driver 120 may be connected to data lines of the display panel 100 through a chip on glass (COG) process or a tape automated bonding (TAB) process.

1 to 5, the level shifter 150 sets the transistor-transistor-logic (TTL) level voltage of the gate timing control signal GDC input from the timing controller 110 to the TFTs of the pixels PXL. The gate-off voltage and the gate-on voltage that can be driven are boosted to supply the gate driver 130. The gate timing control signal GDC may include an external start signal, a clock signal, a global signal, and the like.

1 to 5, the gate driver 130 operates according to the gate timing control signal GDC input from the level shifter 150 to generate a gate signal. Then, the gate signal is supplied to each of the gate lines 15a, 15b, and 15c in a line sequential manner. The gate driver 130 may be directly formed on a non-display area of the display panel 100 in a GIP (Gate driver In Panel) method. The non-display area refers to a bezel area BZ located outside the active area AA. In the GIP method, the level shifter 150 may be mounted on the printed circuit board 140 together with the timing controller 110.

The gate driver 130 is provided in a double bank method on both side bezel areas BZ of the display panels 100 facing each other, thereby minimizing signal distortion due to load variation for each location. The gate driver 130 generates a first scan driver 131 that generates a first scan signal SCAN1 and a second scan driver 132 that generates a second scan signal SCAN2 and an emission signal EM. It may include an emission driver 133.

The first scan driver 131 may supply the first scan signal SCAN1 in a line sequential manner to the first gate lines 15a (1) to 15a (n) connected to the pixels PXL. The second scan driver 132 may supply the second scan signal SCAN2 in a line sequential manner to the second gate lines 15b (1) to 15b (n) connected to the pixels PXL. The emission driver 133 may supply the emission signal EM to the third gate lines 15c (1) to 15c (n) connected to the pixels PXL in a line sequential manner.

Each of the first scan driver 131, the second scan driver 132, and the emission driver 133 may be implemented as a gate shift register composed of a plurality of stages. In particular, each stage of the emission driver 133 may be formed of p-type MOSFET-based transistors to reduce power consumption. At this time, each stage of the emission driver 133 is implemented as shown in FIG. 10 to improve unstable holding characteristics due to leakage current and improve a circuit structure vulnerable to device stress, thereby increasing driving reliability.

1 to 5, the timing controller 110 may be connected to an external host system through various well-known interface circuits and may be connected to the data driver 120. The timing controller 110 may receive image data DATA from the host system and receive sensing data from the data driver 120. The timing controller 110 may correct the image data DATA to compensate for the luminance deviation due to the difference in driving characteristics of the pixels PXL and then transmit the image data DATA to the data driver 120.

The timing controller 110 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a data enable signal (Data Enable, DE) from the host system, and controls the gate timing based on the timing signal. The signal GDC and the source timing control signal DDC can be generated. The timing controller 110 may supply the gate timing control signal GDC to the level shifter 150 and the source timing control signal DDC to the data driver 120.

6 is a diagram illustrating a gate signal applied to the pixel array of FIG. 2.

Referring to FIGS. 1 to 6, the gate on voltage is a voltage of a gate signal through which a TFT can be turned on. The gate off voltage is a voltage at which the TFT can be turned off. For example, in the PMOS, the gate on voltage is the gate low voltage (VGL, VEL), and the gate off voltage is the gate high voltage (VGH, VHE) higher than the gate low voltage (VGL, VEL). Conversely, in the NMOS, the gate on voltage is the gate high voltage (VGH), and the gate off voltage is the gate low voltage (VGL) lower than the gate high voltage (VGH).

1 to 6, three gate signals may be applied to each horizontal pixel line. Accordingly, the pixels PXL of the first horizontal pixel line L1 include the first to third gate lines 15a (1), 15b (1), and 15c (1) SCAN1 (1), SCAN2 ( 1), EM (1) is applied, and pixels PXL of the second horizontal pixel line L2 are the first to third gate lines 15a (2), 15b (2), and 15c (2). SCAN1 (2), SCAN2 (2), and EM (2) are applied, and pixels PXL of the i-th horizontal pixel line Li include first to third gate lines 15a (i), 15b ( i), 15c (i)) are applied to SCAN1 (i), SCAN2 (i), and EM (i), and pixels PXL of the i + 1 horizontal pixel line Li + 1 are first to first 3 Gate lines (15a (i + 1), 15b (i + 1), 15c (i + 1)) will receive SCAN1 (i + 1), SCAN2 (i + 1), and EM (i + 1). You can.

The first scan signals SCAN1 (1) to SCAN1 (i + 2) are output from the first scan driver 131. The first scan signals SCAN1 (1) to SCAN1 (i + 2) alternate the gate-on voltage and the gate-off voltage. The first scan signals SCAN1 (1) to SCAN1 (i + 2) are first switch TFTs of the pixels PXL through the first gate lines 15a (1) to 15a (i + 2). It is applied to the gate electrodes of (ST1). As shown in FIG. 3, when the first switch TFTs ST1 are implemented by NMOS, the gate-on voltage is the gate high voltage VGH, and the gate-off voltage is the gate low voltage VGL. The phases of the first scan signals SCAN1 (1) to SCAN1 (i + 2) are sequentially shifted (or delayed) in units of horizontal pixel lines.

The second scan signals SCAN2 (1) to SCAN2 (i + 2) are output from the second scan driver 132. The second scan signals SCAN2 (1) to SCAN2 (i + 2) alternate the gate-on voltage and the gate-off voltage. The second scan signals SCAN2 (1) to SCAN2 (i + 2) are second switch TFTs of the pixels PXL through the second gate lines 15b (1) to 15b (i + 2). It is applied to the gate electrodes of (ST2). As shown in FIG. 3, when the second switch TFTs ST2 are implemented with PMOS, the gate-on voltage is the gate low voltage VGL, and the gate-off voltage is the gate high voltage VGH. The phases of the second scan signals SCAN2 (1) to SCAN2 (i + 2) are sequentially shifted (or delayed) in units of horizontal pixel lines.

The emission signals EM (1) to EM (i + 2) are output from the emission driver 133. The emission signals EM (1) to EM (i + 2) alternate the gate-on voltage and the gate-off voltage. The emission signals EM (1) to EM (i + 2) are the emission TFTs ET of the pixels PXL through the third gate lines 15c (1) to 15c (i + 2). ) Is applied to the gate electrodes. As shown in FIG. 3, when the emission TFTs ET are implemented as a PMOS, the gate-on voltage is the gate low voltage VEL, and the gate-off voltage is the gate high voltage VEH. The emission signals EM (1) to EM (i + 2) are sequentially shifted (or delayed) in phase in units of horizontal pixel lines.

1 to 6, in one frame, display driving is sequentially performed for all horizontal pixel lines, and sensing driving is performed for a specific 1 horizontal pixel line. The position of the horizontal pixel line on which the sensing driving is performed is predetermined in every frame. The position of the horizontal pixel line on which the sensing driving is performed may be determined sequentially in lines or may be randomly and randomly determined. In a horizontal pixel line in which sensing driving is performed, display driving may be performed immediately after sensing driving is finished in the same frame.

For example, as illustrated in FIG. 6, when the position of the horizontal pixel line in which a sensing driving is performed in a specific frame is determined as the i-th horizontal pixel line Li, the remaining horizontal pixel lines excluding the i-th horizontal pixel line Li ( L1 to Li-1 and Li + 1 to Li + 2) perform display driving, and the i-th horizontal pixel line Li continuously performs sensing driving and display driving.

Display driving for all horizontal pixel lines (ie, L1 to Li + 2) within one frame includes a programming period (Tp), a programming period (Tp) followed by an emission period (Te), and an emission period (Te). ) Followed by a masking period (Tm). The OLEDs of the pixels PXL emit light only in the emission period Te, and do not emit light in the programming period Tp and the masking period Tm. The masking period Tm is introduced to eliminate the deviation of the light emission period between the horizontal pixel line that is sensed and the horizontal pixel line that is not sensed.

In the programming period Tp, the gate-source voltage Vgs of the driving TFT DT is set according to the first and second scan signals SCAN1 and SCAN2 of the gate-on voltages VGH and VGL. In the emission period Te, the emission TFT ET is turned on according to the emission signal EM of the gate-on voltage VEL, and the driving TFT DT is the set gate-source voltage Vgs. ) To apply the current corresponding to the OLED to emit the OLED. In the masking period Tm, since the emission TFT ET is turned off according to the emission signal EM of the gate-off voltage VEH, no current flows through the driving TFT DT, and the OLED is non-emission.

Meanwhile, the sensing driving for a specific horizontal pixel line (ie, Li) within one frame may include an initialization period Ti and a sensing period Ts following the initialization period Ti. The OLED of the pixels PXL may be non-emitted in the initialization period Ti and the sensing period Ts.

In the initialization period Ti, the gate node Ng of the driving TFT DT is initialized to the reference voltage Vref according to the first scan signal SCAN1 of the gate-on voltage VGH, and the driving TFT DT It is set in the turn-on condition. In the sensing period Ts, the emission TFT ET is turned on according to the emission signal EM of the gate-on voltage VEL, and the driving TFT DT sources a current corresponding to the set initialization condition. Charge the node Ns. At this time, the voltage (or current) of the source node Ns is transferred to the data line 14 according to the second scan signal SCAN2 of the gate-on voltage VGL. The voltage (or current) of the source node Ns transferred to the data line 14 in the sensing period Ts may include driving characteristics of the driving TFT DT (or OLED).

On the other hand, referring to FIG. 6, the waveforms of the gate signals applied to the sensed driving horizontal pixel line Li and the waveforms of the gate signals applied to the non sensed driving horizontal pixel line are different, but the emission period Te The length of is characterized by being designed substantially the same. To this end, a masking period Tm may be further provided after the emission period Te, and the length of the gate-off period (VEH period) of the emission signal EM to which the programming period Tp belongs is sensed. The horizontal pixel lines Li are different from each other in the front horizontal pixel lines and the rear horizontal pixel lines. In other words, the length of the gate-off period (VEH period) of the emission signal EM to which the programming period Tp belongs belongs to the front horizontal pixel lines L1 to Li-1 and the sensed driving horizontal pixel line Li. Is relatively short, and is relatively long in the rear horizontal pixel lines Li + 1 and Li + 2.

7 is a diagram illustrating an example of a gate shift register constituting the emission driver 133 of FIG. 5.

Referring to FIG. 7, the emission driver 133 according to an embodiment of the present specification may be implemented as a gate shift register including a plurality of stages ST1 to ST4,?. The stages ST1 to ST4, ... may be GIP elements formed by a GIP method.

The stages ST1 to ST4, ... sequentially output emission signals EM (1) to EM (4),? According to the display driving timing and the sensing driving timing as shown in FIG. 6. To this end, the stages ST1 to ST4, ... are the external start signal EVST, the first clock signal ECLK1, the second clock signal ECLK2, the first global signal GBL1 from the level shifter 150, The second global signal GBL2 and the third global signal GBL3 are received. The external start signal EVST, the clock signals ECLK1, ECLK2, and the global signals GBL1, GBL2, and GBL3 may all swing between the gate off voltage VEH and the gate on voltage VEL.

The stages ST1 to ST4, ... are sequentially activated to transmit the emission signals EM (1) to EM (4) ,? of the gate-on voltage VEL to the third gate lines 15c (1). ~ 15c (4) ,?). The uppermost stage ST1 is activated according to the external start signal EVST, and the uppermost stage ST2 to the lowermost stage is activated according to the emission signal of the previous stage. The emission signal of the front stage is an internal start signal, and is a carry signal (CRY). Here, the " shear stage " means a stage that is located above the stage to be a reference and generates an emission signal whose phase is higher than that of the emission signal output from the reference stage.

On the other hand, the stages ST1 to ST4, ... receive the emission signal of the rear stage and the QB node voltage, etc., thereby securing the stability of the operation. Here, the "back stage" refers to a stage that is located below the reference stage and generates an emission signal that is out of phase compared to the emission signal output from the reference stage.

The external start signal EVST is input to the uppermost stage ST1, the first clock signal ECLK1 is input to the odd stages ST1, ST3,? Through the first clock wiring, and the second clock signal ECLK2. ) Is input to the even stages ST2, ST4,? Through the second clock wiring. In order to ensure the stability of the operation, the first clock signal ECLK1 and the second clock signal ECLK2 may have a narrower gate-on period than a gate-off period. Also, the first clock signal ECLK1 and the second clock signal ECLK2 may have different phases. Specifically, the gate-on period of the first clock signal ECLK1 overlaps the gate-off period of the second clock signal ECLK2, and, conversely, the gate-on period of the second clock signal ECLK2 is the first clock signal ECLK1. It may overlap with the gate-off period.

The global signals GBL1, GBL2, and GBL3 are for generating an emission signal suitable for sensing driving, and are commonly input to all stages. That is, the first global signal GBL1 is commonly input to all stages through the first global wiring, and the second global signal GBL2 is commonly input to all stages through the second global wiring, and the third The global signal GBL3 is commonly input to all stages through the third global wiring.

Since each of the stages ST1 to ST4,… operates based on one clock signal and three global signals, the circuit configuration is simple. In other words, since each of the stages ST1 to ST4,… can reversely control the voltage of the node Q and the voltage of the node QB based on one clock signal and three global signals, the emission driver is simplified and the emission is simplified. The mounting area of the Sean driver may be reduced.

Each of the stages ST1 to ST4, ... starts to reversely control the operation of the node Q and the node QB according to the external start signal EVST or the carry signal CRY applied to the start terminal every frame. Each of the stages ST1 to ST4, ... deactivates node QB while node Q is activated, and conversely activates node QB while node Q is deactivated. Here, when the node is activated, it means that a gate-on voltage (VEL) or a corresponding voltage is applied to the node. And, that the node is deactivated means that a gate-off voltage (VEH) or a corresponding voltage is applied to the node.

Each of the stages ST1 to ST4, ... is supplied with a gate-off voltage VEH and a gate-on voltage VEL from an external power supply. The gate-off voltage VEH may be set to any value between 20V and 30V, and the gate-on voltage VEL may be set to any value between (-) 10V to 0V, but is not limited thereto. Does not.

8 is a diagram illustrating a configuration of an n-th stage STn included in the gate shift register of FIG. 7.

Referring to FIG. 8, the n-th stage STn may be any one of odd-numbered stages after the second to which the first clock signal ECLK1 is input. In the case of the first odd stage, the rest of the configuration is substantially the same as in FIG. 8 except that the external start signal EVST is applied instead of the front end carry signal EM (n-1). Meanwhile, the other stages have substantially the same configuration as in FIG. 8 except that the second clock signal ECLK2 is applied instead of the first clock signal ECLK1.

Referring to FIG. 8, the n-th stage STn includes an emission signal of the gate-off voltage VEH while the node Q is deactivated with the gate-off voltage VEH and the node QB is activated with the gate-on voltage VEL. EM (n)) is output. In addition, the n-th stage STn has the emission signal EM (n) of the gate-on voltage VEL while the node Q is activated with the gate-on voltage VEL and the node QB is deactivated with the gate-off voltage VEH. ).

To this end, the n-th stage STn may include input unit elements, sensing-related elements, and output unit elements.

Referring to FIG. 8, the input element may be composed of a plurality of transistors T3, T4, T5, T6, TA and Ty, and a capacitor CON.

The transistor T3 is turned on according to the first clock signal ECLK1 to apply the front end carry signal EM (n-1) to one electrode of the transistor Tx. The gate electrode of the transistor T3 is connected to the input terminal of the first clock signal ECLK1, and the first electrode and the second electrode of the transistor T3 are respectively the input terminal of the front end carry signal EM (n-1) and one electrode of the transistor Tx. Is connected to.

Transistor T4 is turned on according to the front end carry signal EM (n-1) to apply the gate off voltage VEH to node Q1. The gate electrode of the transistor T4 is connected to the input terminal of the front end carry signal EM (n-1), and the first electrode and the second electrode of the transistor T4 are connected to the node Q1 and the input terminal of the gate-off voltage VEH, respectively.

Transistor T5 is turned on according to the voltage of node Q1 to apply the first clock signal ECLK1 to node QB. The gate electrode of the transistor T5 is connected to the node Q1, and the first electrode and the second electrode of the transistor T5 are connected to the input terminal of the first clock signal ECLK1 and the node QB, respectively.

Transistor T6 is turned on according to the voltage of node Q2 to apply the gate off voltage (VEH) to node QB. The gate electrode of the transistor T6 is connected to the node Q2, and the first electrode and the second electrode of the transistor T6 are connected to the node QB and the input terminal of the gate-off voltage (VEH), respectively.

The gate electrode of the transistor TA is connected to the input terminal of the gate-on voltage VEL, and the first electrode and the second electrode of the transistor TA are connected to the node Q and the node Q2, respectively. The channel current between the first and second electrodes of the transistor TA becomes zero when the node Q is boot-strapping. In other words, the transistor TA is turned off when the node Q bootstraps, thereby blocking the electrical connection between the node Q and the node Q2. On the other hand, while the node Q is not bootstrapping, the transistor TA remains turned on.

Transistor TA remains turned on and is turned off only when node Q bootstraps, blocking current flow between node Q and node Q2. Therefore, when node Q is bootstrapping, the potential of node Q2 is different from the potential of node Q. Since the potential of node Q2 does not change even when the potential of node Q changes at the moment of bootstrapping, transistors Tx, Ty, and T6 connected to node Q2 are not overloaded at the moment of bootstrapping. If there is no transistor TA, the drain-to-source voltage (Vds) of each of the transistors Tx, Ty, and the gate-to-source voltage (Vgs) of the transistor T6 may increase above a threshold due to bootstrapping. If the overload phenomenon continues, a device destruction phenomenon, a so-called break down phenomenon may occur. Transistor TA prevents breakdown of transistors connected to node Q2 at the moment of node Q bootstrapping.

Transistor Ty is turned on according to the voltage of node QB to apply a gate-off voltage (VEH) to node Q2. The gate electrode of the transistor Ty is connected to the node QB, and the first and second electrodes of the transistor Ty are connected to the node Q2 and the input terminal of the gate-off voltage (VEH).

The capacitor CON is a coupling capacitor connected between the input terminal of the first clock signal ECLK1 and the node Q1.

Referring to FIG. 8, sensing-related elements may include a plurality of transistors T7, T8, T9, Tx, and Tz.

Transistor T7 is turned on according to the voltage of node QB1 to apply a third global signal GLB3 to node QB. The gate electrode of the transistor T7 is connected to the node QB1, and the first electrode and the second electrode of the transistor T7 are connected to the input terminal of the third global signal GLB3 and the node QB, respectively.

The transistor T8 is turned on according to the rear-end carry signal EM (n + 1) to apply the gate-off voltage VEH to the node QB1. The gate electrode of the transistor T8 is connected to the input terminal of the rear end carry signal EM (n + 1), and the first electrode and the second electrode of the transistor T8 are connected to the node QB1 and the input terminal of the gate-off voltage VEH, respectively.

Transistor T9 is turned on according to the back-end node QB (QB (n + 1)) to connect node QB1 and node NO. The gate electrode of transistor T9 is connected to the input terminal of the rear node QB (QB (n + 1)), and the first electrode and the second electrode of transistor T9 are connected to node QB1 and node NO, respectively.

Transistor Tx is turned on according to the first global signal GLB1 to connect one electrode of transistor T3 to node Q2. The gate electrode of the transistor Tx is connected to the input terminal of the first global signal GLB1, and the first electrode and the second electrode of the transistor Tx are connected to one electrode and the node Q2 of the transistor T3, respectively.

The transistor Tz is turned on according to the second global signal GLB2 to apply the gate-off voltage VEH to the node Q1. The gate electrode of the transistor Tz is connected to the input terminal of the second global signal GLB2, and the first electrode and the second electrode of the transistor Tz are connected to the node Q1 and the input terminal of the gate-off voltage (VEH), respectively.

Referring to FIG. 8, the output unit elements may include a plurality of transistors T1 and T2 and a plurality of capacitors CB and CQB.

When the transistor T1 is turned on, the n-th emission signal EM (n) is output as the gate-on voltage VEL. The transistor T1 is turned on according to the voltage of the node Q to apply the gate-on voltage VEL to the node NO. The gate electrode of the transistor T1 is connected to the node Q, and the first electrode and the second electrode of the transistor T1 are connected to the input terminal of the gate-on voltage VEL and the node NO, respectively.

Capacitor CB is a bootstrapping capacitor connected between node Q and node NO. When the gate-on voltage VEL is applied to the node NO by the coupling effect of the capacitor CB, the voltage of the node Q bootstraps lower than the gate-on voltage VEL, and the gate-source voltage VEL of the transistor T1 -Node Q voltage) becomes larger. Therefore, if the capacitor CB bootstraps the voltage of the node Q, the gate-on voltage VEL is rapidly applied to the node NO, and the output delay of the n-th emission signal EM (n) can be minimized.

When the transistor T2 is turned on, the n-th emission signal EM (n) is output as the gate-off voltage VEH. Transistor T2 is turned on according to the voltage of node QB to apply the gate-off voltage (VEH) to node NO. The gate electrode of the transistor T2 is connected to the node QB, and the first electrode and the second electrode of the transistor T2 are connected to the input terminal of the gate-off voltage (VEH) and the node NO, respectively.

The capacitor CQB is connected between the node QB and the input terminal of the gate-off voltage (VEH) to stabilize the voltage of the node QB.

9A to 9G are diagrams for describing an operation of the n-th stage STn illustrated in FIG. 8. Here, the emission signal EM (n) output from the n-th stage STn is an emission signal including both sensing driving and display driving, while emission signals EM output from other stages It is assumed that (n-2), EM (n-1), EM (n + 1)) are emission signals that include only display driving.

Referring to FIG. 9A, the first clock signal ECLK1, the first global signal GLB1 and the rear carry signal EM (n + 1) are input as the gate-on voltage VEL in the X1 period, and the front carry signal (EM (n-1)) and the second and third global signals GLB2 and GLB3 are input as the gate-off voltage VEH.

In the X1 period, the transistors T3, Tx, and TA are turned on and the node Q is charged with the gate off voltage VEH. Transistor T1 is turned off according to node Q of gate off voltage VEH. Meanwhile, the transistor T4 is turned off according to the front end carry signal EM (n-1) of the gate off voltage VEH.

In the X1 period, when the first clock signal ECLK1 is inverted to the gate-on voltage VEL, the voltage of the node Q is also inverted to the gate-on voltage VEL by the coupling effect of the capacitor CON. The transistor T5 is turned on according to the node Q1 of the gate-on voltage VEL, and the node QB is charged with the gate-on voltage VEL. As a result, the transistor T2 is turned on according to the node QB of the gate-on voltage VEL, and the gate-off voltage VEH is output through the node NO as the nth emission signal EM (n).

 In the X1 period, the transistor Ty is turned on according to the node QB of the gate-on voltage VEL, and the gate-off voltage VEH is applied to the node Q2. Then, the transistor T6 is turned off according to the node Q2 of the gate off voltage VEH.

In the X1 period, the transistor Tz is turned off according to the second global signal GLB2 of the gate off voltage VEH, and the transistor T9 according to the rear node QB (QB (n + 1)) of the gate off voltage VEH. Turn off. On the other hand, the transistor T8 is turned on according to the rear end carry signal EM (n + 1) of the gate-on voltage VEL to apply the gate-off voltage VEH to the node QB1. Transistor T7 is turned off according to node QB1 of gate off voltage VEH.

Referring to FIG. 9B, in the X2 period, the first clock signal ECLK1 and the front carry signal EM (n-1) are input as a gate-on voltage VEL, and the rear carry signal EM (n + 1) And the first to third global signals GLB1, GLB2, and GLB3 are input as the gate-off voltage VEH.

In the X2 period, the transistor Tx is turned off according to the first global signal GLB1 of the gate-off voltage VEH, and the transistor T4 according to the front-end carry signal EM (n-1) of the gate-on voltage VEL. Turn on. Then, the node Q1 is charged with the gate off voltage (VEH), and the transistor T5 is turned off.

In the X2 period, node Q is maintained at the gate-off voltage (VEH). The transistor T1 remains turned off according to the node Q of the gate off voltage VEH.

In the X2 period, transistor T6 remains turned off, and node QB is floating. By the capacitor CQB, the node QB maintains the gate-on voltage, the transistor T2 is turned on, and the gate-off voltage VEH is output through the node NO as the nth emission signal EM (n).

In the X2 period, transistors Tz and T7 remain turned off, while transistor T8 is turned off, transistor T9 is turned on.

Referring to FIG. 9C, the first global signal GLB1 is input as the gate-on voltage VEL in the X3 period. Then, the first clock signal ECLK1 and the front carry signal EM (n-1) are input as the gate-on voltage VEL, and the rear carry signal EM (n + 1) and the second and third globals The signals GLB2 and GLB3 are input as the gate-off voltage VEH.

In the X3 period, the transistors T3, Tx, and TA are turned on and the node Q is charged with the gate-on voltage VEL. The transistor T1 is turned on according to the node Q of the gate-on voltage VEL, and the gate-on voltage VEL is output through the node NO as the nth emission signal EM (n).

In the X3 period, the transistor T6 is turned on according to the node Q2 of the gate-on voltage VEL, and the node QB is charged with the gate-off voltage VEH. Transistor T2 is turned off according to the QB of gate off voltage VEH.

In the X3 period, transistor T8 is turned off, transistor T9 is turned on, and node QB1 is charged with a gate-on voltage (VEL). The transistor T7 is turned on according to the node QB1 of the gate-on voltage VEL, and the third global signal GLB3 of the gate-off voltage VEH is applied to the node QB.

In the X3 period, the transistor Ty is turned off according to the node QB of the gate off voltage (VEH). The transistor T4 maintains the turn-on state according to the front end carry signal EM (n-1) of the gate-on voltage VEL, and the transistors T5 and Tz maintain the turn-off state.

Referring to FIG. 9D, the third global signal GLB3 is input as the gate-on voltage VEL in the X4 period. In addition, the first clock signal ECLK1 and the front carry signal EM (n-1) are input as the gate-on voltage VEL, and the rear carry signal EM (n + 1) and the first and second globals The signals GLB1 and GLB2 are input as the gate-off voltage VEH.

In the X4 period, the transistor Tx is turned off according to the first global signal GLB1 of the gate-off voltage VEH, and the node Q is floated to maintain the gate-on voltage VEL (operation ①). Then, the transistor T1 is turned on, and the gate-on voltage VEL is applied to the node NO (operation ②).

In the X4 period, the gate-on voltage VEL of the node NO is applied to the node QB1 through the transistor T9 (operation ③). Then, the transistor T7 is turned on, and the third global signal GLB3 of the gate-on voltage VEL is charged to the node QB (operation ④).

In the X4 period, the transistor Ty is turned on according to the node QB of the gate-on voltage VEL, and the node Q2 and the node Q are charged with the gate-off voltage VEH. Accordingly, transistor T1 is turned off (operation ⑤). Then, the transistor T6 is turned off according to the node Q2 of the gate off voltage VEH (operation ⑥).

In the X4 period, the transistor T2 is turned on according to the node QB of the gate-on voltage VEL, and the gate-off voltage VEH is output through the node NO as the nth emission signal EM (n).

In the X4 period, transistors T3 and T4 remain turned on, and transistors T5 and Tz remain turned off.

Referring to FIG. 9E, the first global signal GLB1 is input as the gate-on voltage VEL in the X5 period. Then, the first clock signal ECLK1 and the front carry signal EM (n-1) are input as the gate-on voltage VEL, and the rear carry signal EM (n + 1) and the second and third globals The signals GLB2 and GLB3 are input as the gate-off voltage VEH.

The operation of section X5 is substantially the same as the operation of section X3.

That is, in the X5 period, the transistors T3, Tx, and TA are turned on and the node Q is charged with the gate-on voltage VEL. The transistor T1 is turned on according to the node Q of the gate-on voltage VEL, and the gate-on voltage VEL is output through the node NO as the nth emission signal EM (n).

In the X5 period, the transistor T6 is turned on according to the node Q2 of the gate-on voltage VEL, and the node QB is charged with the gate-off voltage VEH. Transistor T2 is turned off according to the QB of gate off voltage VEH.

Referring to FIG. 9F, the second global signal GLB2 is inverted to the gate-on voltage VEL in the X6 period. In addition, the first global signal GLB1, the first clock signal ECLK1, and the rear carry signal EM (n + 1) are input as the gate-on voltage VEL, and the previous carry signal EM (n-1). And the third global signal GLB3 are input as a gate-off voltage VEH.

In the X6 period, the transistors T3, Tx, and TA are turned on and the node Q is charged with the gate off voltage VEH. Transistor T1 is turned off according to node Q of gate off voltage VEH. Meanwhile, the transistor T4 is turned off according to the front end carry signal EM (n-1) of the gate off voltage VEH.

In the X6 period, the transistor Tz is turned on by the second global signal GLB2 of the gate-on voltage VEL, and Q1 is charged with the gate-off voltage VEH to turn off the transistor T5. In addition, transistor T6 is turned off according to node Q2 of gate off voltage VEH, and transistor T7 is turned off according to node QB1 of gate off voltage VEH.

In the X6 period, the node QB is floated by the turn-off of the transistors T5, T6, and T7, and the node QB is maintained by the capacitor CQB to turn off the transistor T2 by maintaining the gate-off voltage VEH.

In the X6 period, since the transistors T1 and T2 are turned off, the nth emission signal EM (n) maintains the gate-on voltage VEL in the X5 period.

Referring to FIG. 9G, the second global signal GLB2 is inverted to the gate-off voltage VEH in the X7 period. In addition, the first global signal GLB1, the first clock signal ECLK1, and the rear carry signal EM (n + 1) are input as the gate-on voltage VEL, and the previous carry signal EM (n-1). And the third global signal GLB3 are input as a gate-off voltage VEH.

In the X7 period, the transistors T3, Tx, and TA are turned on and the node Q is charged with the gate off voltage VEH. Transistor T1 is turned off according to node Q of gate off voltage VEH. Meanwhile, the transistor T4 is turned off according to the front end carry signal EM (n-1) of the gate off voltage VEH.

In the X7 period, the transistor Tz is turned off by the second global signal GLB2 of the gate-off voltage VEH, and Q1 is charged to the gate-on voltage VEL by the coupling effect of the capacitor CON, so that the transistor T5 is turned It comes. In addition, transistor T6 is turned off according to node Q2 of gate off voltage VEH, and transistor T7 is turned off according to node QB1 of gate off voltage VEH.

In the X7 period, the node QB is charged with the gate-on voltage VEL by the turn-on of the transistor T5, and the transistor T2 is turned on by the node QB of the gate-on voltage VEL. As a result, the gate-off voltage VEH is output through the node NO as the n-th emission signal EM (n).

As can be seen from the above-described operation process, the transistor Ty remains turned off while the n-th emission signal EM (n) is output as the gate-on voltage VEL. At this time, since the voltage difference (VEH-VEL) between the first and second electrodes of the transistor Ty is large, the load on the transistor Ty is large. In one frame, the period during which the nth emission signal EM (n) is output as the gate-on voltage VEL is relatively long, including the sensing period Ts and the emission period Te. Therefore, when the overload of the transistor Ty is accumulated, the leakage current may be a problem in the transistor Ty, and the switching characteristics of the transistor Ty may be wrong. As described above, when a problem occurs in the operation of the transistor Ty, the voltage of the node Q cannot be stably secured and the n-th emission signal EM (n) cannot be output as the gate-on voltage VEL for a desired time. In the following examples, supplementary measures are proposed.

10 is a diagram illustrating another example of a gate shift register constituting the emission driver of FIG. 5.

Referring to FIG. 10, the emission driver 133 according to another embodiment of the present specification may be implemented as a gate shift register including a plurality of stages ST1 to ST4,?. The stages ST1 to ST4, ... may be GIP elements formed by a GIP method.

The stages ST1 to ST4, ... sequentially output emission signals EM (1) to EM (4),? According to the display driving timing and the sensing driving timing as shown in FIG. 6. To this end, the stages ST1 to ST4, ... are the external start signal EVST, the first clock signal ECLK1, the second clock signal ECLK2, the first global signal GBL1 from the level shifter 150, The second global signal GBL2 and the third global signal GBL3 are received. The external start signal EVST, the clock signals ECLK1, ECLK2, and the global signals GBL1, GBL2, and GBL3 may all swing between the gate off voltage VEH and the gate on voltage VEL.

The stages ST1 to ST4, ... are sequentially activated to transmit the emission signals EM (1) to EM (4) ,? of the gate-on voltage VEL to the third gate lines 15c (1). ~ 15c (4) ,?). The uppermost stage ST1 is activated according to the external start signal EVST, and the uppermost stage ST2 to the lowermost stage is activated according to the emission signal of the previous stage. The emission signal of the front stage is an internal start signal, and is a carry signal (CRY). Here, the " shear stage " means a stage that is located above the stage to be a reference and generates an emission signal whose phase is higher than that of the emission signal output from the reference stage.

On the other hand, the stages ST1 to ST4, ... receive the emission signal of the rear stage and the QB node voltage, etc., thereby securing the stability of the operation. Here, the "back stage" refers to a stage that is located below the reference stage and generates an emission signal that is out of phase compared to the emission signal output from the reference stage.

The external start signal EVST is input to the uppermost stage ST1, the first clock signal ECLK1 is input to the stages ST1 to ST4, ... through the first clock wiring, and the second clock signal ECLK2. Is input to the stages ST1 to ST4, ... through the second clock wiring. Each of the stages ST1 to ST4, ... has two clock input terminals. The first clock input terminal of each of the odd stages ST1, ST3,? Is connected to the first clock wire, and the second clock input terminal is connected to the second clock wire. As a result, the first clock signal ECLK1 is input to the first clock input terminal of each of the odd stages ST1, ST3,?, And the second clock signal ECLK2 is input to the second clock input terminal. Conversely, the first clock input terminal of each of the even stages ST2, ST4,? Is connected to the second clock wire, and the second clock input terminal is connected to the first clock wire. As a result, the second clock signal ECLK2 is input to the first clock input terminal of each of the even stages ST2, ST4,?, And the first clock signal ECLK1 is input to the second clock input terminal. In order to ensure the stability of the operation, the first clock signal ECLK1 and the second clock signal ECLK2 may have a narrower gate-on period than a gate-off period. Also, the first clock signal ECLK1 and the second clock signal ECLK2 may have different phases. Specifically, the gate-on period of the first clock signal ECLK1 overlaps the gate-off period of the second clock signal ECLK2, and, conversely, the gate-on period of the second clock signal ECLK2 is the first clock signal ECLK1. It may overlap with the gate-off period.

The global signals GBL1, GBL2, and GBL3 are for generating an emission signal suitable for sensing driving, and are commonly input to all stages ST1 to ST4,…. That is, the first global signal GBL1 is commonly input to all the stages ST1 to ST4, ... through the first global wiring, and the second global signal GBL2 is all stages through the second global wiring. Field stages ST1 to ST4,… are commonly input, and the third global signal GBL3 is commonly input to all stages ST1 to ST4,… through a third global wiring.

Since each of the stages ST1 to ST4,… operates based on two clock signals and three global signals, the circuit configuration is simple. In other words, since each of the stages ST1 to ST4,… can reversely control the voltage of the node Q and the voltage of the node QB based on two clock signals and three global signals, the emission driver is simplified. The installation area of the emission driver can be reduced.

Each of the stages ST1 to ST4, ... starts to reversely control the operation of the node Q and the node QB according to the external start signal EVST or the carry signal CRY applied to the start terminal every frame. Each of the stages ST1 to ST4, ... deactivates node QB while node Q is activated, and conversely activates node QB while node Q is deactivated. Here, when the node is activated, it means that a gate-on voltage (VEL) or a corresponding voltage is applied to the node. And, that the node is deactivated means that a gate-off voltage (VEH) or a corresponding voltage is applied to the node.

Each of the stages ST1 to ST4, ... is supplied with a gate-off voltage VEH and a gate-on voltage VEL from an external power supply. The gate-off voltage VEH may be set to any value between 20V and 30V, and the gate-on voltage VEL may be set to any value between (-) 10V to 0V, but is not limited thereto. Does not.

Each of the stages ST1 to ST4, ... includes a plurality of stabilizing parts to prevent overload of elements connected to the node Q and stabilize the voltage of the node Q. This will be described in detail in FIG. 11.

FIG. 11 is a diagram illustrating one configuration of an n-th stage included in the gate shift register of FIG. 10. And, FIG. 12 is a drive waveform diagram for explaining the operation of FIG. 11.

Referring to FIG. 11, the n-th stage STn is one of the second and subsequent stages, and may be an odd or even stage. When the n-th stage STn is an odd stage after the second, the remaining configuration except for receiving the external start signal EVST instead of the front-end carry signal EM (n-1) is shown in FIG. 11. And substantially the same, except that the second stage is applied to the second clock signal ECLK2 instead of the first clock signal ECLK1 and the first clock signal ECLK1 instead of the second clock signal ECLK2. The rest of the configuration is substantially the same as in FIG. 11. Meanwhile, when the n-th stage STn is an excellent stage, the odd-numbered stages are applied with a second clock signal ECLK2 instead of the first clock signal ECLK1 and a first clock signal (instead of the second clock signal ECLK2). The rest of the configuration is substantially the same as in Fig. 11 except that ECLK1) is applied.

Referring to FIG. 11, the n-th stage STn includes an emission signal of the gate-off voltage VEH while the node Q is deactivated with the gate-off voltage VEH and the node QB is activated with the gate-on voltage VEL. EM (n)) is output. In addition, the n-th stage STn has the emission signal EM (n) of the gate-on voltage VEL while the node Q is activated with the gate-on voltage VEL and the node QB is deactivated with the gate-off voltage VEH. ).

In other words, the n-th stage STn continuously outputs an n-th emission emission signal and an n-th emission emission signal as shown in FIG. 12. At this time, the n-1 stage outputs an n-1 display emission signal that is in phase with the n-th sensing emission signal, and the n + 1 stage has a phase higher than the n-th emission emission signal. The emission signal for the nth + 1 display is output.

Here, in the n-1 display emission signal, the nth display emission signal, and the n + 1 display emission signal, the sections maintaining the gate-on voltage VEL are the same. Do. This is to eliminate luminance deviation between a specific horizontal pixel line in which sensing driving is performed and other horizontal pixel lines in which sensing driving is not performed. In order to make the sustain period of the gate-on voltage VEL the same, the external start signal EVST is input as the gate-on voltage VEL as long as the sustain period of the gate-on voltage VEL, and the gate-off voltage in other periods (VEH).

Meanwhile, a period in which the n + 1 display emission signal maintains a gate-off voltage (VEH) is longer than a period in which the emission signal for n-th display maintains a gate-off voltage (VEH). . This is because the emission signal for the nth sensing and the emission signal for the nth display are located between the emission signal for the n-1 display and the emission signal for the n + 1 display.

When the first clock signal ECLK1 is input to the first clock input terminal of the n-th stage STn and the second clock signal ECLK2 is input to the second clock input terminal, the n-1 stage and the n In each of the +1 stages, the second clock signal ECLK2 is input to the first clock input terminal and the first clock signal ECLK1 is input to the second clock input terminal. At this time, the gate-on period of the first clock signal ECLK1 overlaps the gate-off period of the second clock signal ECLK2, and the gate-on period of the second clock signal ECLK2 is the gate of the first clock signal ECLK1. It may overlap with the off period. Through this, the stability of the operation can be secured.

Specifically, the n-th stage STn may include input unit elements, sensing-related elements, and output unit elements. In addition, the n-th stage STn includes first to third stabilization units to stabilize the voltage of the Q node.

Referring to FIG. 11, the input unit elements transmit the front end carry signal EM (n-1) (ie, the emission signal for the n-1 display) and the first clock signal ECLK1 and the second clock signal ECLK2. Based on this, the voltage of node Q and the voltage of node QB are controlled. To this end, the input element may be composed of a plurality of transistors (T1, T4, T5, T8, T9, T10) and a capacitor CON.

The transistor T1 is turned on according to the second clock signal ECLK2 to apply the front end carry signal EM (n-1) to one electrode of the transistor Tx. The gate electrode of the transistor T1 is connected to the input terminal of the second clock signal ECLK2, and the first electrode and the second electrode of the transistor T1 are respectively input terminals of the front end carry signal EM (n-1) and one electrode of the transistor Tx. Is connected to.

The transistor T4 is turned on according to the second clock signal ECLK2 to apply the gate-on voltage VEL to the node Q1. The gate electrode of the transistor T4 is connected to the input terminal of the second clock signal ECLK2, and the first electrode and the second electrode of the transistor T4 are connected to the input terminal of the gate-on voltage VEL and the node Q1, respectively.

Transistor T5 is turned on according to the voltage of node Q to apply the second clock signal ECLK2 to node Q1. The gate electrode of the transistor T5 is connected to the node Q, and the first electrode and the second electrode of the transistor T5 are connected to the input terminal of the second clock signal ECLK2 and the node Q1, respectively.

Transistor T8 is turned on according to the voltage of node Q1 to apply the first clock signal ECLK1 to node QB1. The gate electrode of the transistor T8 is connected to the node Q1, and the first electrode and the second electrode of the transistor T8 are connected to the input terminal of the first clock signal ECLK1 and the node QB1, respectively.

Transistor T9 is turned on according to the first clock signal ECLK1 to connect node QB1 and node QB. The gate electrode of the transistor T9 is connected to the input terminal of the first clock signal ECLK1, and the first electrode and the second electrode of the transistor T9 are connected to the node QB1 and the node QB, respectively.

Transistor T10 is turned on according to the voltage of node Q to apply a gate-off voltage (VEH) to node QB. The gate electrode of the transistor T10 is connected to the node Q, and the first electrode and the second electrode of the transistor T10 are connected to the input terminal of the gate-off voltage (VEH) and the node QB.

Capacitor CON is a coupling capacitor connected between node Q1 and node QB1.

Referring to FIG. 11, sensing-related elements include a first global signal GLB1, a second global signal GLB2, and a third global signal GLB3 having different phases and waveforms, and a trailing carry signal EM (n + 1)) (that is, the emission signal for the n + 1 display) and the voltage of the node QB and the voltage of the node QB are controlled based on the voltage of the node QB at the rear stage of the n + 1 stage. To this end, sensing-related elements may be composed of a plurality of transistors (T11, T12, T13, Tx, Tz) and a capacitor C1.

Transistor T11 is turned on according to the voltage of node QB2 to apply the third global signal GLB3 to node QB. The gate electrode of the transistor T11 is connected to the node QB2, and the first electrode and the second electrode of the transistor T11 are connected to the input terminal of the third global signal GLB3 and the node QB, respectively.

The transistor T12 is turned on according to the rear-end carry signal EM (n + 1) to apply the gate-off voltage VEH to the node QB2. The gate electrode of the transistor T12 is connected to the input terminal of the rear end carry signal EM (n + 1), and the first electrode and the second electrode of the transistor T12 are connected to the input terminal of the gate-off voltage VEH and the node QB2, respectively.

Transistor T13 is turned on according to the back-end node QB (QB (n + 1)) to connect node QB2 and node NO. The gate electrode of the transistor T13 is connected to the input terminal of the rear node QB (QB (n + 1)), and the first electrode and the second electrode of the transistor T13 are connected to the node QB2 and the node NO, respectively.

Transistor Tx is turned on according to the first global signal GLB1 to connect one electrode of transistor T1 to node Q. The gate electrode of the transistor Tx is connected to the input terminal of the first global signal GLB1, and the first electrode and the second electrode of the transistor Tx are connected to one electrode and the node Q of the transistor T1, respectively.

The transistor Tz is turned on according to the second global signal GLB2 to apply the gate-off voltage VEH to the node QB1. The gate electrode of the transistor Tz is connected to the input terminal of the second global signal GLB2, and the first electrode and the second electrode of the transistor Tz are connected to the input terminal of the gate-off voltage VEH and the node QB1, respectively.

Capacitor C1 is connected between node QB2 and node QB to stabilize the voltage at node QB2.

Referring to FIG. 11, the output unit elements apply a gate-on voltage VEL to the node NO according to the voltage of the node Q, and a gate-off voltage VEH to the node NO according to the voltage of the node QB. Following the n-driven emission signal, the n-th display driving emission signal is continuously output. To this end, the output element may be composed of a plurality of transistors (T6, T7) and a capacitor CQB.

When the transistor T6 is turned on, the n-th emission signal EM (n) is output as the gate-on voltage VEL. The transistor T6 is turned on according to the voltage of the node Q to apply the gate-on voltage VEL to the node NO. The gate electrode of the transistor T6 is connected to the node Q, and the first electrode and the second electrode of the transistor T6 are connected to the input terminal of the gate-on voltage VEL and the node NO, respectively.

When the transistor T7 is turned on, the n-th emission signal EM (n) is output as the gate-off voltage VEH. Transistor T7 is turned on according to the voltage of node QB to apply the gate-off voltage (VEH) to node NO. The gate electrode of the transistor T7 is connected to the node QB, and the first electrode and the second electrode of the transistor T7 are connected to the input terminal of the gate-off voltage (VEH) and the node NO, respectively.

The capacitor CQB is connected between the node QB and the input terminal of the gate-off voltage (VEH) to stabilize the voltage of the node QB.

Referring to FIG. 11, the first stabilization unit refreshes the voltage of the node Q by bootstrapping according to the first clock signal ECLK1. The first stabilization unit includes a capacitor CQ connected between the input terminal of the first clock signal ECLK1 and the node Q. When transistors connected to node Q are turned off, node Q is floating. At this time, the voltage of the node Q may change due to deterioration of the transistors connected to the node Q. Capacitor CQ is a coupling voltage synchronized with the first clock signal ECLK1 to minimize voltage fluctuation of node Q.

Referring to FIG. 11, the second stabilization unit includes a transistor Ty 'and a transistor Ty connected in series between the node Q and the input terminal of the first global signal GLB1. The gate electrode of the transistor Ty 'is connected to the input terminal of the third global signal GLB3, and the first electrode and the second electrode of the transistor Ty' are connected to the node Q and one electrode of the transistor Ty. The gate electrode of the transistor Ty is connected to the node QB, and the first electrode and the second electrode of the transistor Ty are connected to one electrode of the transistor Ty 'and an input terminal of the first global signal GLB1.

While the emission signal for the n-th display is output as the gate-on voltage VEL, the transistor Ty and the transistor Ty 'are turned off, and the potential difference between the node Q and the input terminal of the first global signal GLB1 is zero. Accordingly, while the emission signal for the n-th display is output as the gate-on voltage (VEL), the load on the transistor Ty and the transistor Ty 'is almost eliminated, and problems such as leakage current due to overload and distortion of switching characteristics are inevitable. Since it is prevented, the voltage at the Q node can be stabilized.

Referring to FIG. 11, the third stabilization unit includes a transistor T2 and a transistor T3 connected in series between the node Q and the input terminal of the gate off voltage (VEH). Transistors T2 and T3 are connected in series, thereby more effectively blocking leakage current. The gate electrode of the transistor T2 is connected to the input terminal of the first clock signal ECLK1, and the first electrode and the second electrode of the transistor T2 are connected to the node Q and one electrode of the transistor T3. The gate electrode of the transistor T3 is connected to the node Q1 whose voltage is determined according to the gate-on voltage VEL and the second clock signal ECLK2, and the first electrode and the second electrode of the transistor T3 are one electrode of the transistor T2. And a gate-off voltage (VEH).

Meanwhile, the first to third global signals GLB1, GLB2, and GLB3 will be described in detail with reference to FIG. 12.

The n-th sensing emission signal is inverted from the gate-off voltage VEH to the gate-on voltage VEL in synchronization with the first falling edge FE1 of the first global signal GLB1.

The nth sensing emission signal is inverted from the gate-on voltage VEL to the gate-off voltage VEH in synchronization with the falling edge FE of the third global signal GLB3.

The emission signal for the nth display is inverted from the gate-off voltage VEH to the gate-on voltage VEL in synchronization with the second falling edge FE2 of the first global signal GLB1.

In addition, the emission signal for the nth display is inverted from the gate-on voltage VEL to the gate-off voltage VEH in synchronization with the rising edge RE of the second global signal GLB2.

13A to 13G are diagrams for describing the operation of the n-th stage STn shown in FIG. 11. Here, the emission signal EM (n) output from the n-th stage STn is an emission signal including both sensing driving and display driving, while emission signals EM output from other stages (n-2), EM (n-1), EM (n + 1)) are emission signals including only display driving.

Referring to FIG. 13A, the first clock signal ECLK1, the first global signal GLB1, and the rear carry signal EM (n + 1) in the Y1 period are input as the gate-on voltage VEL, and the second clock The signal ECLK2, the front-end carry signal EM (n-1), and the second and third global signals GLB2 and GLB3 are input as the gate-off voltage VEH.

In the Y1 period, the transistors T2 and T3 are turned on and the node Q is charged with the gate off voltage VEH. The transistors T5, T6, and T10 are turned off according to the node Q of the gate off voltage VEH.

In the Y1 period, the transistors T8 and T9 are turned on and the node QB is charged with the gate-on voltage VEL. The transistor T7 is turned on according to the node QB of the gate-on voltage VEL, and the gate-off voltage VEH is output through the node NO as the nth emission signal EM (n).

In the Y1 period, the transistors T1 and T4 are turned off according to the second clock signal ECLK2 of the gate off voltage VEH. Then, the transistor Tz is turned off according to the second global signal GLB2 of the gate off voltage VEH.

In the Y1 period, the transistor Ty is turned on according to the node QB of the gate-on voltage VEL, and the transistor Ty 'is turned off according to the third global signal GLB3 of the gate-off voltage VEH.

In the Y1 period, the transistor T13 is turned off according to the back node QB (QB (n + 1)) of the gate off voltage VEH. On the other hand, the transistor T12 is turned on according to the carry signal EM (n + 1) of the rear end of the gate-on voltage VEL to apply the gate-off voltage VEH to the node QB2. Transistor T11 is turned off according to node QB2 of gate off voltage VEH.

Referring to FIG. 13B, in the Y2 period, the second clock signal ECLK2 and the front carry signal EM (n-1) are input as the gate-on voltage VEL, and the first clock signal ECLK1 and the rear carry signal (EM (n + 1)) and the first to third global signals GLB1, GLB2, and GLB3 are input as the gate-off voltage VEH.

In the Y2 period, since the transistors Tx, T2 and Ty 'connected to the node Q are turned off, the node Q is floating and maintains the gate off voltage VEH in the Y1 period. The transistors T5, T6, and T10 remain turned off according to the node Q of the gate off voltage VEH.

In the Y2 period, the first clock signal ECLK1 of the gate-off voltage VEH is applied to one electrode of the capacitor CQ. The voltage at node Q is stabilized to the gate-off voltage (VEH) by the coupling effect of capacitor CQ.

In the Y2 period, since the transistor T9 connected to the node QB is turned off, the node QB is floating and maintains the gate-on voltage VEL in the Y1 period. The transistor T2 maintains a turn-on state according to the node QB of the gate-on voltage VEL, and the gate-off voltage VEH is output through the node NO as the nth emission signal EM (n).

In the Y2 period, the transistors Tz, Ty ', and T11 remain turned off, and the transistor Ty remains turned on. And, while the transistor T12 is turned off, the transistor T13 is turned on.

Referring to FIG. 13C, the first global signal GLB1 is input as the gate-on voltage VEL in the Y3 period. In addition, the second clock signal ECLK2 and the front carry signal EM (n-1) are input as the gate-on voltage VEL, and the first clock signal ECLK1 and the rear carry signal EM (n + 1). ) And the second and third global signals GLB2 and GLB3 are input as the gate-off voltage VEH.

In the Y3 period, the transistors T1 and Tx are turned on and the node Q is charged with the gate-on voltage VEL. The transistor T6 is turned on according to the node Q of the gate-on voltage VEL, and the gate-on voltage VEL is output through the node NO as the nth emission signal EM (n).

In the Y3 period, the transistor T10 is turned on according to the node Q of the gate-on voltage VEL, and the node QB is charged with the gate-off voltage VEH. Transistor T7 is turned off according to QB of gate off voltage VEH.

In the Y3 period, the node QB2 is charged to the gate-on voltage VEL through the transistor T13. The transistor T11 is turned on according to the node QB2 of the gate-on voltage VEL, and the third global signal GLB3 of the gate-off voltage VEH is applied to the node QB.

In the Y3 period, the transistor Ty 'remains turned off, and the transistor Ty is turned off according to the node QB of the gate off voltage VEH. Then, the transistor T5 is turned on according to the node Q of the gate-on voltage VEL, and the transistors T2 and Tz remain turned off.

Referring to FIG. 13D, the first clock signal ECLK1 and the third global signal GLB3 are input as the gate-on voltage VEL in the Y4 period. Then, the front carry signal EM (n-1) is input as the gate-on voltage VEL, the second clock signal ECLK2 and the rear carry signal EM (n + 1), and the first and second globals. The signals GLB1 and GLB2 are input as the gate-off voltage VEH.

In the Y4 section, the node QB2 maintains the gate-on voltage VEL of the Y3 section, and the third global signal GLB3 of the gate-on voltage VEL is charged to the node QB through the transistor T11 (operations ①, ②). Then, the transistor T7 is turned on according to the node QB of the gate-on voltage VEL, and the gate-off voltage VEH is output through the node NO as the n-th emission signal EM (n).

In the Y4 period, the transistor Ty 'is turned on according to the third global signal GLB3 of the gate-on voltage VEL, and the transistor Ty is turned on according to the node QB of the gate-on voltage VEL, thereby gated to the node Q The first global signal GLB1 of the off voltage VEH is applied. The node Q is charged with the first global signal GLB1 of the gate-off voltage VEH through the transistors Ty 'and Ty, and the transistor T6 is turned off (operation ③).

In the Y4 period, the transistors T1, T4, T5, and Tx are turned off, and the node Q1 is floated to maintain the gate-on voltage VEL in the Y3 period. The transistor T3 remains turned on by the node Q1 of the gate-on voltage VEL, and the transistor T2 is turned on by the first clock signal ECLK1 of the gate-on voltage VEL. The node Q is charged with the gate-off voltage VEH through the transistors T2 and T3, and the transistor T6 is turned off (operation ③).

In the Y4 period, the node QB1 is charged with the first clock signal ECLK1 of the gate-on voltage VEL through the transistor T8. The transistor T9 is turned on according to the first clock signal ECLK1 of the gate-on voltage VEL to charge the node QB with the gate-on voltage VEL.

In the Y4 period, the transistors T5 and T10 are turned off by the node Q of the gate off voltage VEH.

Referring to FIG. 13E, the first global signal GLB1 and the second clock signal ECLK2 are input as the gate-on voltage VEL in the Y5 period. Then, the front carry signal EM (n-1) is input as the gate-on voltage VEL, the first clock signal ECLK1 and the rear carry signal EM (n + 1), and the second and third globals. The signals GLB2 and GLB3 are input as the gate-off voltage VEH.

The operation of the Y5 section is substantially the same as the operation of the Y3 section.

That is, in the Y5 period, the transistors T1 and Tx are turned on and the node Q is charged with the gate-on voltage VEL. The transistor T6 is turned on according to the node Q of the gate-on voltage VEL, and the gate-on voltage VEL is output through the node NO as the nth emission signal EM (n). Then, the node QB is charged with the gate-off voltage VEH by the turn-on of the transistor T10, and the transistor T7 is turned off.

In the Y5 period, the transistor Ty 'is turned off according to the third global signal GLB3 of the gate off voltage VEH, and the transistor Ty is turned off according to the node QB of the gate off voltage VEH.

Referring to FIG. 13F, the second global signal GLB2 and the first clock signal ECLK1 are inverted to the gate-on voltage VEL in the Y6 period. In addition, the first global signal GLB1 and the rear carry signal EM (n + 1) are input as the gate-on voltage VEL, and the second clock signal ECLK2 and the front carry signal EM (n-1). And the third global signal GLB3 are input as a gate-off voltage VEH.

In the Y6 period, since the transistors T1, Ty, Ty ', and T3 are turned off, the node Q is floating and maintains the gate-on voltage VEL in the Y5 period. The transistors T5, T6, and T10 remain turned on according to the node Q of the gate-on voltage VEL. Then, the gate-on voltage VEL is output to the node NO through the transistor T6 as the n-th emission signal EM (n).

In the Y6 period, the first clock signal ECLK1 of the gate-on voltage VEH is applied to one electrode of the capacitor CQ. The voltage at the node Q is stabilized to the gate-on voltage (VEL) by the coupling effect of the capacitor CQ.

In the Y6 period, the transistor Tz is turned on by the second global signal GLB2 of the gate-on voltage VEL, and the transistor T9 is turned on by the first clock signal ECLK1 of the gate-on voltage VEL. Therefore, the node QB is charged with the gate-off voltage, and the transistor T7 is turned off.

In the Y6 section, the transistors Ty 'and Ty remain turned off. At this time, since both the node Q and the first global signal GLB1 are gate-on voltages VEL, the voltage difference between the transistors Ty 'and Ty, that is, the voltage difference between the node Q and the input terminal of the first global signal GLB1 is zero. to be. Therefore, the load applied to the turned off transistors Ty 'and Ty is minimized.

Referring to FIG. 13G, the second global signal GLB2 is inverted to the gate-off voltage VEH in the Y7 period. In addition, the first global signal GLB1, the first clock signal ECLK1, and the rear carry signal EM (n + 1) are input as the gate-on voltage VEL, and the second clock signal ECLK2 and the previous carry signal (EM (n-1)) and the third global signal GLB3 are input as the gate-off voltage VEH.

The operation of the Y7 section is substantially the same as the operation of the Y1 section.

In the Y7 period, the transistor T7 is turned on according to the node QB of the gate-on voltage VEL, and the gate-off voltage VEH is output through the node NO as the nth emission signal EM (n).

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100: display panel 110: timing controller
120: data driver 130: gate driver

Claims (17)

In the external compensation gate driver having a plurality of stages,
Among the plurality of stages, the n-th stage continuously outputs an n-th emission emission signal and an n-th emission emission signal, and an n-1 stage has a higher phase than the n-th emission emission signal. The n-1 signal is output for the n-1 display, and the n + 1 stage outputs the n + 1 display emission signal that is out of phase with the n-th sensing emission signal.
The n-th stage,
A gate-on voltage is applied to the node NO according to the voltage of the node Q, and a gate-off voltage is applied to the node NO according to the voltage of the node QB, followed by the n-th sensing driving emission signal, followed by the n-th display driving Output unit elements for continuously outputting an emission signal;
Based on the voltages of the first global signal, the second global signal, and the third global signal having different phases and waveforms, the emission signal for the n + 1 display, and the node QB at the rear end of the n + 1 stage. Sensing-related elements that control the voltage of the node Q and the voltage of the node QB; And
A gate driver including a first stabilization unit to refresh the voltage of the node Q by bootstrapping according to a first clock signal. According to claim 1,
The first stabilization unit,
A gate driver including a capacitor CQ connected between the input terminal of the first clock signal and the node Q. According to claim 1,
The n-th stage,
A gate driver further comprising a second stabilizing part stabilizing the voltage of the node Q through transistor Ty 'and transistor Ty connected in series between the node Q and the input terminal of the first global signal. The method of claim 3,
The gate electrode of the transistor Ty 'is connected to the input terminal of the third global signal, and the first electrode and the second electrode of the transistor Ty' are connected to the node Q and one electrode of the transistor Ty,
The gate driver of the transistor Ty is connected to the node QB, and the first electrode and the second electrode of the transistor Ty are connected to one electrode of the transistor Ty 'and an input terminal of the first global signal. The method of claim 4,
While the emission signal for the n-th display is output to the gate-on voltage, the transistor Ty and the transistor Ty 'are turned off, and the potential difference between the node Q and the input terminal of the first global signal is zero. According to claim 1,
The n-th stage,
A gate driver further comprising a third stabilization unit stabilizing the voltage of the node Q through transistors T2 and T3 connected in series between the node Q and the input terminal of the gate-off voltage. The method of claim 6,
The gate electrode of the transistor T2 is connected to the input terminal of the first clock signal, and the first electrode and the second electrode of the transistor T2 are connected to the node Q and one electrode of the transistor T3,
The gate electrode of the transistor T3 is connected to the node Q1, and the first and second electrodes of the transistor T3 are connected to one electrode of the transistor T2 and an input terminal of the gate-off voltage. According to claim 1,
The output element,
A transistor T6 having a gate electrode connected to the node Q, a first electrode connected to the input terminal of the gate-on voltage, and a second electrode connected to the node NO; And
A gate driver comprising a transistor T7 with a gate electrode connected to the node QB, a first electrode connected to the input terminal of the gate off voltage, and a second electrode connected to the node NO. According to claim 1,
The n-th stage,
An input unit for controlling the voltage of the node Q and the voltage of the node QB based on the first clock signal, a second clock signal having a different phase from the first clock signal, and the emission signal for the n-1 display Gate driver further comprising a. The method of claim 9,
The input element,
The transistor T1 having a gate electrode connected to the input terminal of the second clock signal, and a first electrode connected to the input terminal of the n-1 display emission signal;
A transistor T4 having a gate electrode connected to the input terminal of the second clock signal, a first electrode connected to the input terminal of the gate-on voltage, and a second electrode connected to the node Q1;
A transistor T5 having a gate electrode connected to the node Q, a first electrode connected to the input terminal of the second clock signal, and a second electrode connected to the node Q1;
A transistor T8 having a gate electrode connected to the node Q1, a first electrode connected to the input terminal of the first clock signal, and a second electrode connected to the node QB1;
A transistor T9 having a gate electrode connected to the input terminal of the first clock signal, a first electrode connected to the node QB1, and a second electrode connected to the node QB;
A transistor T10 having a gate electrode connected to the node Q, a first electrode connected to the input terminal of the gate-off voltage, and a second electrode connected to the node QB; And
A gate driver including a capacitor CON connected between the node Q1 and the node QB1. The method of claim 10,
The sensing-related elements,
A transistor Tx having a gate electrode connected to the input terminal of the first global signal, a first electrode connected to the second electrode of transistor T1, and a second electrode connected to the node Q;
A transistor Tz having a gate electrode connected to the input terminal of the second global signal, a first electrode connected to the input terminal of the gate-off voltage, and a second electrode connected to the node QB1;
A transistor T11 in which a gate electrode is connected to the node QB2, a first electrode is connected to the input terminal of the third global signal, and a second electrode is connected to the node QB;
A transistor T12 having a gate electrode connected to the input terminal of the n + 1 display emission signal, a first electrode connected to the input terminal of the gate-off voltage, and a second electrode connected to the node QB2; And
A gate driver comprising a transistor T13, wherein a gate electrode is connected to the input terminal of the node QB voltage at the rear end of the n + 1 stage, a first electrode is connected to the node NO, and a second electrode is connected to the node QB2. According to claim 1,
The nth sensing emission signal is inverted from the gate-off voltage to the gate-on voltage in synchronization with the first falling edge of the first global signal,
The nth sensing emission signal is inverted from the gate-on voltage to the gate-off voltage in synchronization with the falling edge of the third global signal,
The emission signal for the nth display is inverted from the gate-off voltage to the gate-on voltage in synchronization with the second falling edge of the first global signal,
A gate driver in which the emission signal for the n-th display is inverted from the gate-on voltage to the gate-off voltage in synchronization with the rising edge of the second global signal. According to claim 1,
A gate driver having a section in which the gate-on voltage is maintained between the n-1 display emission signal, the n-th display emission signal, and the n + 1 display emission signal. According to claim 1,
The period in which the n + 1 display emission signal maintains a gate-off voltage is longer than a period in which the emission signal for n-th display maintains a gate-off voltage. The method of claim 9,
The gate driver of the first clock signal overlaps the gate-off period of the second clock signal, and the gate-on period of the second clock signal overlaps the gate off period of the first clock signal. The external compensation gate driver of any one of claims 1 to 15;
A gate line to which the n-th sensing emission signal and the n-th emission emission signal are continuously supplied from the external compensation gate driver;
Pixels connected to the gate line;
Sensing units operating in response to the nth emission signal; And
An organic light emitting display device comprising digital-analog converters operating in response to the nth emission signal. The method of claim 16,
The sensing units sense driving characteristics of the pixels within a period in which the n-th emission signal is maintained at the gate-on voltage,
The light emitting devices of the pixels emit light during the period in which the emission signal for the nth display is maintained at the gate-on voltage.

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