KR102652818B1 - Gate driver for external compensation and organic light emitting display device including the same - Google Patents

Abstract

A gate driver for external compensation according to an embodiment of the present specification has a plurality of stages. Among the plurality of stages, the nth stage continuously outputs the nth sensing emission signal and the nth display emission signal, and the n-1th stage is ahead of the nth sensing emission signal in phase. The n-1th display emission signal is output, and the n+1th stage outputs the n+1th display emission signal whose phase is behind the nth sensing emission signal.

Description

Gate driver for external compensation and organic light emitting display device including the same {GATE DRIVER FOR EXTERNAL COMPENSATION AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME}

This specification relates to a gate driver for external compensation and an organic light emitting display device including the same.

An organic light emitting display device arranges pixels, each including OLED, in a matrix form on a display panel and adjusts the luminance of the pixels according to the gradation of image data. Each pixel includes a driving TFT (Thin Film Transistor) that controls the driving current flowing through the OLED according to the gate-source voltage, and switch TFTs that program the gate-sort voltage of the driving TFT according to the scan signal. The display gradation (brightness) is adjusted by the amount of light emitted by the OLED that is proportional to the current. Additionally, each of the pixels may further include an emission TFT that is turned on/off according to the emission signal to determine the emission timing of the OLED.

Meanwhile, organic light emitting display devices use external compensation technology to improve image quality. External compensation technology compensates for differences in driving characteristics between pixels by sensing pixel voltage or current according to the driving characteristics (or electrical characteristics) of the pixel and modulating the data of the input image based on the sensed results. In order to implement this external compensation technology, a suitable gate driver is required. The gate driver for external compensation may include a scan driver that generates a scan signal and an emission driver that generates an emission signal.

The gate driver for external compensation can be made of p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor)-based transistors with low power consumption. The p-type MOSFET-based transistor has a large leakage current (Off current) and is weak to device stress. There is a downside. If the leakage current is large, the voltage at the Q node or QB node within the gate driver may become unstable and incorrect gate output may occur. Additionally, if device stress is large, the threshold voltage and mobility characteristics of the device may change and cause incorrect gate output.

Therefore, this specification provides an external compensation gate driver that improves driving reliability by improving the unstable holding characteristics caused by leakage current in a gate driver composed of p-type MOSFET-based transistors and improving the circuit structure vulnerable to device stress, and the same. Provides an electroluminescent display device including:

A gate driver for external compensation according to an embodiment of the present specification has a plurality of stages. Among the plurality of stages, the nth stage continuously outputs the nth sensing emission signal and the nth display emission signal, and the n-1th stage is ahead of the nth sensing emission signal in phase. The n-1th display emission signal is output, and the n+1th stage outputs the n+1th display emission signal whose phase is behind the nth sensing emission signal. Here, the nth stage applies a gate-on voltage to the node NO according to the voltage of the node Q, and applies a gate-off voltage to the node NO according to the voltage of the node QB, to the nth sensing driving emission signal. Next, output unit elements that continuously output the nth display driving emission signal; Input elements that control the voltage of the node Q and the voltage of the node QB based on the n-1 display emission signal and the first clock signal; and a first global signal, a second global signal, and a third global signal having different phases and waveforms, the emission signal for the n+1th display, and the voltage of the rear node QB of the n+1th stage. It includes sensing elements that control the voltage of the node Q and the voltage of the node QB.

According to this specification, driving reliability can be increased by improving unstable holding characteristics caused by leakage current and improving circuit structure vulnerable to device stress in a gate driver composed of p-type MOSFET-based transistors.

1 is a diagram showing an organic light emitting display device according to an embodiment of the present specification.
FIG. 2 is a diagram showing a pixel array formed on the display panel of FIG. 1.
FIG. 3 is a diagram schematically showing one pixel circuit included in the pixel array of FIG. 2.
FIG. 4 is a diagram for explaining the data driver of FIG. 1.
FIG. 5 is a diagram for explaining the gate driver of FIG. 1.
FIG. 6 is a diagram showing a gate signal applied to the pixel array of FIG. 2.
FIG. 7 is a diagram showing a gate shift register constituting the emission driver of FIG. 5.
FIG. 8 is a diagram showing a configuration of the nth stage included in the gate shift register of FIG. 7.
FIGS. 9A to 9G are diagrams for explaining the operation of the nth stage shown in FIG. 8.
FIG. 10 is a diagram showing another configuration of the nth stage included in the gate shift register of FIG. 7.
FIG. 11 is a driving waveform diagram for explaining the operation of FIG. 10.
FIGS. 12A to 12G are diagrams for explaining the operation of the nth stage shown in FIG. 10.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to substantially like elements throughout the specification.

In this specification, the gate driver formed on the substrate of the display panel may be implemented as a TFT with a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. TFT is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the TFT, carriers begin to flow from the source. The drain is the electrode through which carriers go out of the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. Accordingly, in the description of the embodiments of the present specification, one of the source and the drain is described as the first electrode, and the other one of the source and the drain is described as the second electrode.

Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings. In the following embodiments, the electric field display device will be described focusing on an organic light emitting display device including an organic light emitting material. However, the technical idea of the present invention is not limited to organic light emitting display devices, but can be applied to inorganic light emitting display devices including inorganic light emitting materials.

1 is a diagram showing an organic light emitting display device according to an embodiment of the present specification. FIG. 2 is a diagram showing a pixel array formed on the display panel of FIG. 1. FIG. 3 is a diagram schematically showing one pixel circuit included in the pixel array of FIG. 2. FIG. 4 is a diagram for explaining the data driver of FIG. 1. And, FIG. 5 is a diagram for explaining the gate driver of FIG. 1.

1 to 5, the display device of the present specification may include a display panel 100, a timing controller 110, a data driver 120, a gate driver 130, and a level shifter 150. there is.

In the display panel 100, a plurality of data lines 14 and a plurality of gate lines 15a, 15b, and 15c intersect, and pixels PXL are arranged in a matrix form in each intersection area to form a pixel array (Pixel array). array) can be configured. Pixels PXL may be arranged in various ways other than a matrix form to form a pixel array.

The pixel array is located in the active area (AA) of the display panel 100. The pixel array is provided with a plurality of horizontal pixel lines (L1 to L4), and on each horizontal pixel line (L1 to L4), a plurality of pixels are horizontally adjacent and commonly connected to the gate lines (15a, 15b, and 15c). (PXL) is deployed. Here, each of the horizontal pixel lines (L1 to L4) is not a physical signal line, but rather a one-line pixel aggregate implemented by horizontally neighboring pixels (PXL). The pixel array includes a first power line 16 that supplies a reference voltage (Vref) to the pixels (PXL) and a second power line (17) that supplies a high-potential power supply voltage (EVDD) to the pixels (PXL). may be included. Additionally, the pixels PXL may be further connected to the input terminal of the low-potential power supply voltage EVSS.

The configuration of the gate lines 15a, 15b, and 15c may vary depending on the pixel circuit. For example, as shown in FIG. 2, each of the gate lines includes a first gate line 15a to which the first scan signal SCAN1 is supplied, a second gate line 15b to which the second scan signal SCAN2 is supplied, and an EMI It may include a third gate line 15c to which a signal EM is supplied.

Each of the pixels PXL may be one of a red pixel, a green pixel, a blue pixel, and a white pixel. Red pixels, green pixels, blue pixels, and white pixels can form one unit pixel to implement various colors. The color implemented in a unit pixel may be determined according to the emission ratio of the red pixel, green pixel, blue pixel, and white pixel. In some cases, white pixels may be omitted from each unit pixel. Each of the pixels PXL includes a data line 14, a first gate line 15a, a second gate line 15b, a third gate line 15c, a first power line 16, and a second power line ( 17) etc. can be connected.

Pixel circuits can be configured in various ways. For example, each of the pixels PXL is an OLED as shown in FIG. 3, a switch circuit for programming the gate-source voltage (Vgs) of the driving TFT (DT), and the OLED according to the gate-source voltage (Vgs). It may include a driving TFT (DT) that controls the driving current flowing through the device, and an emission TFT (ET) that turns on/off according to the emission signal (EM) and determines the emission timing of the OLED. Here, the switch circuit may include a plurality of switch TFTs (ST1, ST2) and at least one storage capacitor (CST), and various modifications are possible depending on the product model and specifications. The pixel circuit will be explained in detail with reference to FIG. 3 as follows.

Each pixel (PXL) includes an OLED, a driving TFT (DT), an emission TFT (ET), a storage capacitor (CST), a first switch TFT (ST1), and a second switch TFT (ST2), and the emission The TFT (ET), the first switch TFT (ST1), and the second switch TFT (ST2) may be connected to different gate lines 15a, 15b, and 15c.

OLED is a light-emitting device and includes an anode electrode connected to a source node (Ns), a cathode electrode connected to an input terminal of a low-potential power supply voltage (EVSS), and an organic compound layer located between the anode electrode and the cathode electrode.

The driving TFT (DT) is a driving element that controls the driving current flowing through the OLED according to the voltage difference between the gate node (Ng) and the source node (Ns). The driving TFT (DT) includes a gate electrode connected to the gate node (Ng), a first electrode connected to one electrode of the emission TFT (ET), and a second electrode connected to the source node (Ns). The storage capacitor (CST) is connected between the gate node (Ng) and the source node (Ns) to store the gate-source voltage (Vgs) of the driving TFT (DT).

The emission TFT (ET) is turned on/off according to the emission signal (EM) to determine the emission timing of the OLED. The emission TFT (ET) includes a gate electrode connected to the third gate line 15c, a first electrode connected to the second power line 17 to which a high-potential power supply voltage (EVDD) is applied, and a driving TFT (DT). and a second electrode connected to the first electrode.

The first switch TFT (ST1) turns on the current flow between the first power line 16 and the gate node (Ng) according to the first scan signal (SCAN1), and the reference voltage charged in the first power line 16 A voltage (Vref) is applied to the gate node (Ng). The first switch TFT (ST1) has a gate electrode connected to the first gate line 15a, a first electrode connected to the first power line 16, and a second electrode connected to the gate node Ng. .

The second switch TFT (ST2) turns on the current flow between the data line 14 and the source node (Ns) according to the second scan signal (SCAN2), thereby increasing the data voltage (Vdata) charged in the data line 14. is applied to the source node (Ns), or the voltage (Vsen) of the source node (Ns) according to the pixel current is transmitted to the data line 14. The second switch TFT (ST2) includes a gate electrode connected to the second gate line 15b, a first electrode connected to the data line 14, and a second electrode connected to the source node Ns.

Referring to FIG. 3, the TFTs included in each of the pixels PXL may be implemented as a PMOS-type LTPS TFT or an NMOS-type LTPS TFT, through which desired response characteristics can be secured. However, the technical idea of the present specification is not limited thereto. For example, among the TFTs, at least one TFT (e.g., DT, ST1) is implemented as an NMOS-type oxide TFT with good off-current characteristics, and the remaining TFTs (ET, ST2) are implemented as PMOS-type LTPS with good response characteristics. It can also be implemented as a TFT.

1 to 5, the data driver 120 communicates with the timing controller 110 through a preset interface circuit. The data driver 120 receives image data (DATA) and the source timing control signal (DDC) from the timing controller 110, generates a data voltage (Vdata), and sends the data voltage (Vdata) to the data lines (14). ) is supplied to. Then, the data driver 120 receives the sensing voltage Vsen related to the driving characteristics of the pixels PXL through the data lines 14 to generate sensing data, and transmits the sensing data to the timing controller 110. send.

To this end, the data driver 120 includes a switching unit (SWU) connected to each data line 14, and a digital analog converter (Digital Analog Converter) that is selectively connected to the data line 14 according to the operation of the switching unit (SWU). DAC) and a sensing unit (SU). The switching unit (SWU) may connect a digital analog converter (DAC) to the data line 14 for display driving, and may connect the sensing unit (SU) to the data line 14 for sensing driving.

The digital analog converter (DAC) generates a data voltage (Vdata) when driving the display, and synchronizes the data voltage (Vdata) with the second scan signal (SCAN2) of the gate-on voltage to connect the data line 14 of the display panel 100. ) is supplied to.

During sensing operation, the sensing unit (SU) uses the driving characteristics of the pixels (PXL), such as the threshold voltage and mobility of the driving TFT (DT) and/or the operating point voltage of the OLED, as a second scan signal of the gate-on voltage. Sensing can be done through the data line 14 in synchronization with (SCAN2). The sensing unit (SU) may be implemented as a known voltage sensing type or current sensing type. The voltage sensing type can sense the voltage (Vsen) charged in the source node (Ns) of the pixel (PXL) according to specified sensing conditions. The current sensing type can obtain the sensing voltage (Vsen) by directly sensing the current flowing through the source node (Ns) of the pixel (PXL) according to specified sensing conditions.

The data driver 120 may be connected to the data lines of the display panel 100 through a Chip On Glass (COG) process or a Tape Automated Bonding (TAB) process.

1 to 5, the level shifter 150 shifts the Transistor-Transistor-Logic (TTL) level voltage of the gate timing control signal (GDC) input from the timing controller 110 to the TFTs of the pixels (PXL). Boosting is performed using the gate-off voltage and gate-on voltage that can be driven, and then supplied to the gate driver 130. The gate timing control signal (GDC) may include an external start signal, clock signal, global signal, etc.

1 to 5, the gate driver 130 operates according to the gate timing control signal (GDC) input from the level shifter 150 to generate a gate signal. Then, the gate signal is supplied to each gate line (15a, 15b, and 15c) in a line sequential manner. The gate driver 130 may be formed directly on the non-display area of the display panel 100 using a gate driver in panel (GIP) method. The non-display area refers to the bezel area (BZ) located outside the active area (AA). In the GIP method, the level shifter 150 may be mounted on a printed circuit board (Printed Circuit Board) 140 together with the timing controller 110.

The gate driver 130 is provided in a double bank manner in the bezel areas (BZ) on both sides of the display panel 100 facing each other, so that signal distortion due to load deviation for each position can be minimized. The gate driver 130 generates a first scan driver 131 that generates a first scan signal (SCAN1) and a second scan driver 132 that generates a second scan signal (SCAN2) and an emission signal (EM). It may include an emission driver 133 that does.

The first scan driver 131 may supply the first scan signal SCAN1 to the first gate lines 15a(1) to 15a(n) connected to the pixels PXL in a line sequential manner. The second scan driver 132 may supply the second scan signal SCAN2 to the second gate lines 15b(1) to 15b(n) connected to the pixels PXL in a line sequential manner. The emission driver 133 may supply the emission signal EM to the third gate lines 15c(1) to 15c(n) connected to the pixels PXL in a line sequential manner.

Each of the first scan driver 131, the second scan driver 132, and the emission driver 133 may be implemented as a gate shift register consisting of multiple stages. In particular, each stage of the emission driver 133 may be comprised of p-type MOSFET-based transistors to reduce power consumption. At this time, each stage of the emission driver 133 is implemented as shown in FIG. 10 so that unstable holding characteristics due to leakage current can be improved and the circuit structure vulnerable to device stress can be improved, thereby improving driving reliability.

Referring to FIGS. 1 to 5 , the timing controller 110 may be connected to an external host system and the data driver 120 through various known interface circuits. The timing controller 110 can receive image data (DATA) from the host system and sensing data from the data driver 120. The timing controller 110 may correct the image data DATA to compensate for the luminance deviation due to differences in driving characteristics of the pixels PXL and then transmit the image data DATA to the data driver 120.

The timing controller 110 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a data enable signal (Data Enable, DE) from the host system, and controls gate timing based on these timing signals. A signal (GDC) and a source timing control signal (DDC) can be generated. The timing controller 110 may supply a gate timing control signal (GDC) to the level shifter 150 and a source timing control signal (DDC) to the data driver 120.

FIG. 6 is a diagram showing a gate signal applied to the pixel array of FIG. 2.

Referring to Figures 1 to 6, the gate on voltage (Gate On Voltage) is the voltage of the gate signal at which the TFT can be turned on. Gate Off Voltage is the voltage at which the TFT can be turned off. For example, in PMOS, the gate-on voltage is the gate low voltage (VGL, VEL), and the gate-off voltage is the gate high voltage (VGH, VEH), which is higher than the gate low voltage (VGL, VEL). Conversely, in NMOS, the gate-on voltage is the gate high voltage (VGH), and the gate-off voltage is the gate low voltage (VGL), which is lower than the gate high voltage (VGH).

Referring to Figures 1 to 6, three gate signals may be applied to each horizontal pixel line. Accordingly, the pixels PXL of the first horizontal pixel line L1 connect the first to third gate lines 15a(1), 15b(1), and 15c(1) to SCAN1(1) and SCAN2( 1), EM(1) is applied, and the pixels PXL of the second horizontal pixel line L2 are connected to the first to third gate lines 15a(2), 15b(2), and 15c(2). SCAN1(2), SCAN2(2), and EM(2) are applied, and the pixels PXL of the ith horizontal pixel line Li are connected to the first to third gate lines 15a(i) and 15b( i), 15c(i)) are applied to SCAN1(i), SCAN2(i), and EM(i), and the pixels (PXL) of the i+1th horizontal pixel line (Li+1) are the first to 3 Gate lines (15a(i+1), 15b(i+1), 15c(i+1)) are used to receive SCAN1(i+1), SCAN2(i+1), and EM(i+1). You can.

The first scan signals (SCAN1(1) to SCAN1(i+2)) are output from the first scan driver 131. The first scan signals (SCAN1(1) to SCAN1(i+2)) alternate between gate-on voltage and gate-off voltage. The first scan signals SCAN1(1) to SCAN1(i+2) are transmitted to the first switch TFTs of the pixels PXL through the first gate lines 15a(1) to 15a(i+2). It is applied to the gate electrodes of (ST1). When the first switch TFTs (ST1) are implemented as NMOS as shown in FIG. 3, the gate-on voltage is the gate high voltage (VGH) and the gate-off voltage is the gate low voltage (VGL). The first scan signals (SCAN1(1) to SCAN1(i+2)) are sequentially phase-shifted (or delayed) in units of horizontal pixel lines.

The second scan signals (SCAN2(1) to SCAN2(i+2)) are output from the second scan driver 132. The second scan signals (SCAN2(1) to SCAN2(i+2)) alternate between gate-on voltage and gate-off voltage. The second scan signals SCAN2(1) to SCAN2(i+2) are transmitted to the second switch TFTs of the pixels PXL through the second gate lines 15b(1) to 15b(i+2). It is applied to the gate electrodes of (ST2). When the second switch TFTs (ST2) are implemented as PMOS as shown in FIG. 3, the gate-on voltage is the gate low voltage (VGL) and the gate-off voltage is the gate high voltage (VGH). The second scan signals (SCAN2(1) to SCAN2(i+2)) are sequentially phase-shifted (or delayed) in units of horizontal pixel lines.

Emission signals (EM(1) to EM(i+2)) are output from the emission driver 133. Emission signals (EM(1) to EM(i+2)) alternate between gate-on and gate-off voltages. The emission signals (EM(1) to EM(i+2)) are transmitted to the emission TFTs (ET) of the pixels (PXL) through the third gate lines (15c(1) to 15c(i+2)). ) is applied to the gate electrodes. When the emission TFTs ET are implemented as PMOS as shown in FIG. 3, the gate-on voltage is the gate low voltage (VEL), and the gate-off voltage is the gate high voltage (VEH). The emission signals (EM(1) to EM(i+2)) are sequentially phase shifted (or delayed) in units of horizontal pixel lines.

Referring to Figures 1 to 6, display driving is performed sequentially targeting all horizontal pixel lines within one frame, and sensing driving is performed targeting one specific horizontal pixel line. The position of the horizontal pixel line where sensing operation occurs is predetermined for each frame. The position of the horizontal pixel line where sensing operation is performed may be determined sequentially, or may be determined randomly and irregularly. In a horizontal pixel line where sensing driving is performed, display driving may be performed immediately after the sensing driving is completed within the same frame.

For example, as shown in FIG. 6, when the position of the horizontal pixel line on which sensing operation is performed in a specific frame is set to the i-th horizontal pixel line (Li), the remaining horizontal pixel lines (Li) except for the i-th horizontal pixel line (Li) L1~Li-1, Li+1~Li+2) perform display driving, and the i-th horizontal pixel line (Li) continuously performs sensing driving and display driving.

Display driving for all horizontal pixel lines (i.e., L1 to Li+2) within one frame involves a programming period (Tp), an emission period (Te) following the programming period (Tp), and an emission period (Te). ) may include a masking period (Tm) following the masking period (Tm). The OLED of the pixels (PXL) emits light only in the emission period (Te) and does not emit light in the programming period (Tp) and the masking period (Tm). The masking period (Tm) is introduced to eliminate the difference in the emission period between the horizontal pixel line that is driven by sensing and the horizontal pixel line that is driven by non-sensing.

In the programming period (Tp), the gate-source voltage (Vgs) of the driving TFT (DT) is set according to the first and second scan signals (SCAN1 and SCAN2) of the gate-on voltages (VGH and VGL). In the emission period (Te), the emission TFT (ET) is turned on according to the emission signal (EM) of the gate-on voltage (VEL), and the driving TFT (DT) is turned on according to the gate-source voltage (Vgs) set above. ) is applied to the OLED to emit light. In the masking period (Tm), the emission TFT (ET) is turned off according to the emission signal (EM) of the gate-off voltage (VEH), so current cannot flow to the driving TFT (DT), and the OLED does not emit light.

Meanwhile, sensing driving targeting a specific horizontal pixel line (i.e., Li) within one frame may include an initialization period (Ti) and a sensing period (Ts) following the initialization period (Ti). The OLED of the pixels PXL may not emit light during the initialization period Ti and the sensing period Ts.

In the initialization period (Ti), the gate node (Ng) of the driving TFT (DT) is initialized to the reference voltage (Vref) according to the first scan signal (SCAN1) of the gate-on voltage (VGH), and the driving TFT (DT) It is set as a turn-on condition. In the sensing period (Ts), the emission TFT (ET) is turned on according to the emission signal (EM) of the gate-on voltage (VEL), and the driving TFT (DT) sources a current corresponding to the initialization condition set above. Charge to node (Ns). At this time, the voltage (or current) of the source node (Ns) is transmitted to the data line 14 according to the second scan signal (SCAN2) of the gate-on voltage (VGL). The voltage (or current) of the source node (Ns) transmitted to the data line 14 in the sensing period (Ts) may include the driving characteristics of the driving TFT (DT) (or OLED).

Meanwhile, referring to FIG. 6, although the waveforms of the gate signals applied to the horizontal pixel lines Li that are sensed and driven are different from the waveforms of the gate signals applied to the horizontal pixel lines that are not sensed driven, the emission period Te The length of has the characteristic of being designed to be substantially the same. For this purpose, a masking period (Tm) may be further provided after the emission period (Te), and the length of the gate-off section (VEH section) of the emission signal (EM) to which the programming period (Tp) belongs may be sensed and driven. The front and rear horizontal pixel lines are different based on the horizontal pixel line (Li). In other words, the length of the gate-off section (VEH section) of the emission signal (EM) to which the programming period (Tp) belongs is the front-end horizontal pixel lines (L1 to Li-1) and the sensing-driven horizontal pixel line (Li) It is relatively short in and relatively long in the rear horizontal pixel lines (Li+1, Li+2).

FIG. 7 is a diagram showing a gate shift register constituting the emission driver 133 of FIG. 5.

Referring to FIG. 7, the emission driver 133 according to an embodiment of the present specification may be implemented with a gate shift register consisting of a plurality of stages (ST1 to ST4, ??). The stages (ST1 to ST4,…) may be GIP elements formed in the GIP method.

The stages (ST1 to ST4,...) sequentially output emission signals (EM(1) to EM(4),??) according to the display driving timing and sensing driving timing as shown in FIG. 6. To this end, the stages (ST1 to ST4,...) receive an external start signal (EVST), a first clock signal (ECLK1), a second clock signal (ECLK2), a first global signal (GBL1) from the level shifter 150, A second global signal (GBL2) and a third global signal (GBL3) are input. The external start signal (EVST), clock signals (ECLK1, ECLK2), and global signals (GBL1, GBL2, GBL3) can all swing between the gate-off voltage (VEH) and the gate-on voltage (VEL).

The stages (ST1 to ST4,...) are sequentially activated to transmit the emission signal (EM(1) to EM(4),??) of the gate-on voltage (VEL) to the third gate lines (15c (1)). )~15c(4),??) are output sequentially. The top stage (ST1) is activated according to the external start signal (EVST), and the next top stage (ST2) to the bottom stage are activated according to the emission signal of the previous stage. The emission signal of the front stage is an internal start signal and becomes the carry signal (CRY). Here, the “front stage” refers to a stage that is located above the reference stage and generates an emission signal that is ahead in phase compared to the emission signal output from the reference stage.

Meanwhile, the stages (ST1 to ST4,...) receive the emission signal and QB node voltage of the subsequent stage to ensure stability of operation. Here, the “rear stage” refers to a stage that is located below the reference stage and generates an emission signal that lags in phase compared to the emission signal output from the reference stage.

The external start signal (EVST) is input to the top stage (ST1), the first clock signal (ECLK1) is input to the odd stages (ST1, ST3, ??) through the first clock wire, and the second clock signal ( ECLK2) is input to the superior stages (ST2, ST4, ??) through the second clock wiring. To ensure operational stability, the gate-on period of each of the first clock signal (ECLK1) and the second clock signal (ECLK2) may be narrower than the gate-off period. Also, the first clock signal (ECLK1) and the second clock signal (ECLK2) may have different phases. Specifically, the gate-on period of the first clock signal (ECLK1) overlaps with the gate-off period of the second clock signal (ECLK2), and conversely, the gate-on period of the second clock signal (ECLK2) overlaps with the gate-off period of the second clock signal (ECLK2). It may overlap with the gate-off section of .

Global signals (GBL1, GBL2, GBL3) are used to generate emission signals suitable for sensing driving, and are commonly input to all stages. That is, the first global signal (GBL1) is commonly input to all stages through the first global wiring, the second global signal (GBL2) is commonly input to all stages through the second global wiring, and the third global signal (GBL2) is commonly input to all stages through the second global wiring. The global signal (GBL3) is commonly input to all stages through the third global wiring.

Since each of the stages (ST1 to ST4,…) operates based on one clock signal and three global signals, the circuit configuration is simple. In other words, each of the stages (ST1 to ST4,...) can control the voltage of node Q and the voltage of node QB inversely based on one clock signal and three global signals, so the emission driver is simplified and the emission The mounting area of the driver may be reduced.

Each of the stages (ST1 to ST4,...) begins to control the operations of node Q and node QB in reverse according to the external start signal (EVST) or carry signal (CRY) applied to the start terminal every frame. Each of the stages (ST1 to ST4,...) deactivates node QB while node Q is activated, and conversely, activates node QB while node Q is deactivated. Here, activating a node means that the gate-on voltage (VEL) or a voltage equivalent thereto is applied to the node. And, deactivating a node means that the gate-off voltage (VEH) or a voltage equivalent thereto is applied to the node.

Each stage (ST1 to ST4,...) receives the gate-off voltage (VEH) and gate-on voltage (VEL) from an external power supply. For example, the gate-off voltage (VEH) can be set to any value between 20V and 30V, and the gate-on voltage (VEL) can be set to any value between (-)10V and 0V, but are not limited to this. No.

FIG. 8 is a diagram showing a configuration of the nth stage (STn) included in the gate shift register of FIG. 7.

Referring to FIG. 8, the nth stage (STn) may be one of the second and subsequent odd stages to which the first clock signal (ECLK1) is input. In the case of the first odd stage, the remaining configuration is substantially the same as that of FIG. 8 except that the external start signal (EVST) is applied instead of the previous carry signal (EM(n-1)). Meanwhile, the configuration of the superior stages is substantially the same as that of FIG. 8 except that the second clock signal (ECLK2) is applied instead of the first clock signal (ECLK1).

Referring to FIG. 8, the nth stage (STn) generates an emission signal ( EM(n)) is output. And, the nth stage (STn) generates an emission signal (EM(n)) of the gate-on voltage (VEL) while node Q is activated by the gate-on voltage (VEL) and node QB is deactivated by the gate-off voltage (VEH). ) is output.

To this end, the nth stage (STn) may include input elements, sensing-related elements, and output elements.

Referring to FIG. 8, the input elements may be composed of a plurality of transistors (T3, T4, T5, T6, TA, Ty) and a capacitor CON.

Transistor T3 is turned on according to the first clock signal (ECLK1) and applies the front-end carry signal (EM(n-1)) to one electrode of the transistor Tx. The gate electrode of transistor T3 is connected to the input terminal of the first clock signal (ECLK1), and the first and second electrodes of transistor T3 are respectively the input terminal of the previous carry signal (EM(n-1)) and one electrode of transistor Tx. is connected to

Transistor T4 is turned on according to the front-end carry signal (EM(n-1)) and applies the gate-off voltage (VEH) to node Q1. The gate electrode of the transistor T4 is connected to the input terminal of the previous carry signal EM(n-1), and the first and second electrodes of the transistor T4 are connected to the input terminal of the node Q1 and the gate-off voltage VEH, respectively.

Transistor T5 is turned on according to the voltage of node Q1 and applies the first clock signal (ECLK1) to node QB. The gate electrode of transistor T5 is connected to node Q1, and the first and second electrodes of transistor T5 are connected to the input terminal of the first clock signal (ECLK1) and node QB, respectively.

Transistor T6 is turned on according to the voltage of node Q2 and applies the gate-off voltage (VEH) to node QB. The gate electrode of transistor T6 is connected to node Q2, and the first and second electrodes of transistor T6 are connected to node QB and the input terminal of the gate-off voltage (VEH), respectively.

The gate electrode of transistor TA is connected to the input terminal of the gate-on voltage (VEL), and the first and second electrodes of transistor TA are connected to node Q and node Q2, respectively. The channel current between the first and second electrodes of transistor TA becomes zero when node Q is bootstrapped. In other words, transistor TA is turned off when node Q is bootstrapped, thus blocking the electrical connection between node Q and node Q2. Meanwhile, while node Q is not bootstrapped, transistor TA remains turned on.

Transistor TA remains turned on and turns off only when node Q is bootstrapped, blocking current flow between node Q and node Q2. Therefore, when node Q is bootstrapped, the potential of node Q2 becomes different from the potential of node Q. Even if the potential of node Q changes at the moment of bootstrapping, the potential of node Q2 does not change, so the transistors Tx, Ty, and T6 connected to node Q2 are not overloaded at the moment of bootstrapping. If there is no transistor TA, the voltage between the drain and source of each of the transistors Tx and Ty (Vds) and the voltage between the gate and source of transistor T6 (Vgs) may increase above the threshold due to bootstrapping. If the overload phenomenon continues, device destruction, or so-called break down phenomenon, may occur. Transistor TA prevents the transistors connected to node Q2 from breaking down at the moment of bootstrapping of node Q.

Transistor Ty is turned on according to the voltage of node QB and applies the gate-off voltage (VEH) to node Q2. The gate electrode of the transistor Ty is connected to the node QB, and the first and second electrodes of the transistor Ty are connected to the node Q2 and the input terminal of the gate-off voltage (VEH).

Capacitor CON is a coupling capacitor connected between the input terminal of the first clock signal (ECLK1) and node Q1.

Referring to FIG. 8, elements involved in sensing may be composed of a plurality of transistors (T7, T8, T9, Tx, and Tz).

Transistor T7 is turned on according to the voltage of node QB1 and applies the third global signal (GLB3) to node QB. The gate electrode of transistor T7 is connected to node QB1, and the first and second electrodes of transistor T7 are connected to the input terminal of the third global signal GLB3 and node QB, respectively.

Transistor T8 is turned on according to the rear carry signal (EM(n+1)) and applies the gate-off voltage (VEH) to node QB1. The gate electrode of transistor T8 is connected to the input terminal of the rear carry signal (EM(n+1)), and the first and second electrodes of transistor T8 are connected to the input terminal of node QB1 and gate-off voltage (VEH), respectively.

Transistor T9 is turned on according to the rear node QB (QB(n+1)) and connects node QB1 and node NO. The gate electrode of transistor T9 is connected to the input terminal of the rear node QB (QB(n+1)), and the first and second electrodes of transistor T9 are connected to node QB1 and node NO, respectively.

Transistor Tx is turned on according to the first global signal (GLB1) and connects one electrode of transistor T3 to node Q2. The gate electrode of the transistor Tx is connected to the input terminal of the first global signal (GLB1), and the first and second electrodes of the transistor Tx are connected to one electrode of the transistor T3 and node Q2, respectively.

The transistor Tz is turned on according to the second global signal (GLB2) and applies the gate-off voltage (VEH) to the node Q1. The gate electrode of the transistor Tz is connected to the input terminal of the second global signal (GLB2), and the first and second electrodes of the transistor Tz are connected to the node Q1 and the input terminal of the gate-off voltage (VEH), respectively.

Referring to FIG. 8, the output unit elements may be composed of a plurality of transistors (T1, T2) and a plurality of capacitors (CB, CQB).

When transistor T1 is turned on, the nth emission signal (EM(n)) is output as the gate-on voltage (VEL). Transistor T1 is turned on according to the voltage of node Q and applies the gate-on voltage (VEL) to node NO. The gate electrode of transistor T1 is connected to node Q, and the first and second electrodes of transistor T1 are connected to the input terminal of the gate-on voltage (VEL) and node NO, respectively.

Capacitor CB is a bootstrapping capacitor connected between node Q and node NO. When the gate-on voltage (VEL) is applied to node NO due to the coupling effect of capacitor CB, the voltage of node Q is bootstrapped lower than the gate-on voltage (VEL), and the gate-source voltage (VEL) of transistor T1 -Node Q voltage) increases. Accordingly, when capacitor CB is bootstrapped to the voltage of node Q, the gate-on voltage (VEL) is quickly applied to node NO, and the output delay of the n-th emission signal (EM(n)) can be minimized.

When transistor T2 is turned on, the nth emission signal (EM(n)) is output as the gate-off voltage (VEH). Transistor T2 is turned on according to the voltage of node QB and applies the gate-off voltage (VEH) to node NO. The gate electrode of transistor T2 is connected to node QB, and the first and second electrodes of transistor T2 are connected to the input terminal of the gate-off voltage VEH and node NO, respectively.

Capacitor CQB is connected between node QB and the input terminal of the gate-off voltage (VEH) to stabilize the voltage of node QB.

FIGS. 9A to 9G are diagrams for explaining the operation of the nth stage (STn) shown in FIG. 8. Here, the emission signal (EM(n)) output from the nth stage (STn) is an emission signal including both sensing driving and display driving, while the emission signals (EM) output from other stages are (n-2), EM(n-1), EM(n+1)) are assumed to be emission signals that include only display driving.

Referring to Figure 9a, in the X1 section, the first clock signal (ECLK1), the first global signal (GLB1), and the rear-end carry signal (EM(n+1)) are input as the gate-on voltage (VEL), and the front-end carry signal (EM(n-1)) and the second and third global signals (GLB2 and GLB3) are input as the gate-off voltage (VEH).

In the X1 section, the transistors (T3, Tx, TA) are turned on and node Q is charged to the gate-off voltage (VEH). Transistor T1 is turned off according to the node Q of the gate-off voltage (VEH). Meanwhile, transistor T4 is turned off according to the carry signal (EM(n-1)) preceding the gate-off voltage (VEH).

In the X1 section, when the first clock signal (ECLK1) is inverted to the gate-on voltage (VEL), the voltage of node Q is also inverted to the gate-on voltage (VEL) due to the coupling effect of the capacitor CON. Transistor T5 is turned on according to the gate-on voltage (VEL) of node Q1, and node QB is charged with the gate-on voltage (VEL). As a result, transistor T2 is turned on according to the node QB of the gate-on voltage (VEL), and the gate-off voltage (VEH) is output through the node NO as the n-th emission signal (EM(n)).

In the X1 section, the transistor Ty is turned on according to the node QB of the gate-on voltage (VEL), and the gate-off voltage (VEH) is applied to the node Q2. And, transistor T6 is turned off according to the node Q2 of the gate-off voltage (VEH).

In the It turns off. On the other hand, transistor T8 is turned on according to the carry signal (EM(n+1)) following the gate-on voltage (VEL), and applies the gate-off voltage (VEH) to node QB1. Transistor T7 is turned off according to the node QB1 of the gate-off voltage (VEH).

Referring to FIG. 9b, in the X2 section, the first clock signal (ECLK1) and the front-end carry signal (EM(n-1)) are input as the gate-on voltage (VEL), and the rear-end carry signal (EM(n+1)) and the first to third global signals GLB1, GLB2, and GLB3 are input as the gate-off voltage VEH.

In the Turn on. Then, node Q1 is charged to the gate-off voltage (VEH) and transistor T5 is turned off.

In the X2 section, node Q is maintained at the gate-off voltage (VEH). Transistor T1 remains turned off according to the node Q of the gate-off voltage (VEH).

In the X2 period, transistor T6 remains turned off and node QB is floating. The node QB maintains the gate-on voltage by the capacitor CQB, the transistor T2 turns on, and the gate-off voltage VEH is output through the node NO as the n-th emission signal EM(n).

In the X2 section, transistors Tz and T7 remain turned off, transistor T8 is turned off, while transistor T9 is turned on.

Referring to FIG. 9C, the first global signal GLB1 is input as the gate-on voltage VEL in section X3. And, the first clock signal (ECLK1) and the front-end carry signal (EM(n-1)) are input as the gate-on voltage (VEL), and the rear-end carry signal (EM(n+1)) and the second and third global Signals (GLB2, GLB3) are input as the gate-off voltage (VEH).

In the X3 section, the transistors (T3, Tx, TA) are turned on and node Q is charged to the gate-on voltage (VEL). Transistor T1 is turned on according to the node Q of the gate-on voltage (VEL), and the gate-on voltage (VEL) is output as the n-th emission signal (EM(n)) through the node NO.

In the X3 section, transistor T6 is turned on according to the gate-on voltage (VEL) of node Q2, and node QB is charged with the gate-off voltage (VEH). Transistor T2 is turned off according to QB of the gate-off voltage (VEH).

In the X3 section, transistor T8 is turned off, transistor T9 is turned on, and node QB1 is charged to the gate-on voltage (VEL). Transistor T7 is turned on according to the gate-on voltage (VEL) of node QB1, and the third global signal (GLB3) of the gate-off voltage (VEH) is applied to node QB.

In the X3 section, transistor Ty is turned off according to the node QB of the gate-off voltage (VEH). Transistor T4 maintains a turn-on state according to the carry signal (EM(n-1)) preceding the gate-on voltage (VEL), and transistors T5 and Tz maintain a turn-off state.

Referring to FIG. 9D, the third global signal GLB3 is input as the gate-on voltage VEL in the X4 section. And, the first clock signal (ECLK1) and the front-end carry signal (EM(n-1)) are input as the gate-on voltage (VEL), and the rear-end carry signal (EM(n+1)) and the first and second global The signals (GLB1 and GLB2) are input as the gate-off voltage (VEH).

In the X4 section, the transistor Tx is turned off according to the first global signal (GLB1) of the gate-off voltage (VEH), and the node Q is floating to maintain the gate-on voltage (VEL) (① operation). Then, transistor T1 is turned on and the gate-on voltage (VEL) is applied to node NO (② operation).

In the X4 section, the gate-on voltage (VEL) of node NO is applied to node QB1 through transistor T9 (③ operation). Then, transistor T7 is turned on, and the third global signal (GLB3) of the gate-on voltage (VEL) is charged to node QB (④ operation).

In the X4 section, transistor Ty is turned on according to node QB of the gate-on voltage (VEL), and node Q2 and node Q are charged with the gate-off voltage (VEH). Accordingly, transistor T1 is turned off (⑤ operation). And, transistor T6 is turned off according to the node Q2 of the gate-off voltage (VEH) (⑥ operation).

In the X4 section, transistor T2 is turned on according to the node QB of the gate-on voltage (VEL), and the gate-off voltage (VEH) is output as the n-th emission signal (EM(n)) through the node NO.

In the X4 section, transistors T3 and T4 remain turned on, and transistors T5 and Tz remain turned off.

Referring to FIG. 9E, the first global signal GLB1 is input as the gate-on voltage VEL in the X5 section. And, the first clock signal (ECLK1) and the front-end carry signal (EM(n-1)) are input as the gate-on voltage (VEL), and the rear-end carry signal (EM(n+1)) and the second and third global Signals (GLB2, GLB3) are input as the gate-off voltage (VEH).

The operation of the X5 section is substantially the same as the operation of the X3 section.

That is, in the X5 section, the transistors (T3, Tx, TA) are turned on and the node Q is charged to the gate-on voltage (VEL). Transistor T1 is turned on according to the node Q of the gate-on voltage (VEL), and the gate-on voltage (VEL) is output as the n-th emission signal (EM(n)) through the node NO.

In the X5 section, transistor T6 is turned on according to the gate-on voltage (VEL) of node Q2, and node QB is charged with the gate-off voltage (VEH). Transistor T2 is turned off according to QB of the gate-off voltage (VEH).

Referring to FIG. 9F, the second global signal GLB2 is inverted to the gate-on voltage VEL in the X6 section. In addition, the first global signal (GLB1), the first clock signal (ECLK1), and the rear-end carry signal (EM(n+1)) are input as the gate-on voltage (VEL), and the front-end carry signal (EM(n-1)) and the third global signal (GLB3) are input as the gate-off voltage (VEH).

In the X6 section, the transistors (T3, Tx, TA) are turned on and node Q is charged to the gate-off voltage (VEH). Transistor T1 is turned off according to the node Q of the gate-off voltage (VEH). Meanwhile, transistor T4 is turned off according to the carry signal (EM(n-1)) preceding the gate-off voltage (VEH).

In the X6 section, transistor Tz is turned on by the second global signal (GLB2) of the gate-on voltage (VEL), and Q1 is charged to the gate-off voltage (VEH) to turn off transistor T5. Additionally, transistor T6 is turned off according to the node Q2 of the gate-off voltage VEH, and transistor T7 is turned off according to the node QB1 of the gate-off voltage VEH.

In the

In the X6 section, transistors T1 and T2 are turned off, so the n-th emission signal EM(n) maintains the gate-on voltage (VEL) in the X5 section.

Referring to FIG. 9g, the second global signal GLB2 is inverted to the gate-off voltage VEH in section X7. In addition, the first global signal (GLB1), the first clock signal (ECLK1), and the rear-end carry signal (EM(n+1)) are input as the gate-on voltage (VEL), and the front-end carry signal (EM(n-1)) and the third global signal (GLB3) are input as the gate-off voltage (VEH).

In the X7 section, the transistors (T3, Tx, TA) are turned on and node Q is charged to the gate-off voltage (VEH). Transistor T1 is turned off according to the node Q of the gate-off voltage (VEH). Meanwhile, transistor T4 is turned off according to the carry signal (EM(n-1)) preceding the gate-off voltage (VEH).

In the It comes. Additionally, transistor T6 is turned off according to the node Q2 of the gate-off voltage VEH, and transistor T7 is turned off according to the node QB1 of the gate-off voltage VEH.

In the X7 section, the node QB is charged to the gate-on voltage (VEL) by turning on the transistor T5, and the transistor T2 is turned on by the node QB of the gate-on voltage (VEL). As a result, the gate-off voltage VEH is output through node NO as the n-th emission signal EM(n).

As can be seen from the above-described operation process, while the n-th emission signal EM(n) is output as the gate-on voltage VEL, the transistor Ty remains turned off. At this time, since the voltage difference (VEH-VEL) between the first and second electrodes of the transistor Ty is large, a large load is applied to the transistor Ty. In one frame, the period during which the n-th emission signal (EM(n)) is output as the gate-on voltage (VEL) is relatively long, including the sensing period (Ts) and the emission period (Te). Therefore, if overload on transistor Ty accumulates, leakage current may become a problem in transistor Ty, and the switching characteristics of transistor Ty may be distorted. As such, if a problem occurs in the operation of the transistor Ty, the voltage at the node Q cannot be stably secured, so the n-th emission signal (EM(n)) cannot be output as the gate-on voltage (VEL) for the desired time. In the following examples, a complementary measure is presented.

FIG. 10 is a diagram showing another configuration of the nth stage included in the gate shift register of FIG. 7. And, FIG. 11 is a driving waveform diagram for explaining the operation of FIG. 10.

Referring to FIG. 10, the nth stage (STn) may be one of the second and subsequent odd stages to which the first clock signal (ECLK1) is input. In the case of the first odd stage, the remaining configuration is substantially the same as that of FIG. 10 except that the external start signal (EVST) is applied instead of the previous carry signal (EM(n-1)). Meanwhile, the configuration of the superior stages is substantially the same as that of FIG. 10 except that the second clock signal (ECLK2) is applied instead of the first clock signal (ECLK1).

Referring to FIG. 10, the nth stage (STn) generates an emission signal ( EM(n)) is output. And, the nth stage (STn) generates an emission signal (EM(n)) of the gate-on voltage (VEL) while node Q is activated by the gate-on voltage (VEL) and node QB is deactivated by the gate-off voltage (VEH). ) is output.

In other words, the nth stage STn continuously outputs the nth sensing emission signal and the nth display emission signal as shown in FIG. 11. At this time, the n-1th stage outputs the n-1th display emission signal whose phase is ahead of the nth sensing emission signal, and the n+1th stage outputs the nth sensing emission signal ahead of the phase. Outputs an emission signal for the n+1 display.

Here, the emission signal for the n-1th display, the emission signal for the nth display, and the emission signal for the n+1th display have the same section in which the gate-on voltage (VEL) is maintained. do. This is to eliminate the luminance difference between a specific horizontal pixel line on which sensing operation is performed and other horizontal pixel lines on which sensing operation is not performed. In order to make the maintenance period of the gate-on voltage (VEL) the same, the external start signal (EVST) is input as the gate-on voltage (VEL) for the maintenance period of the gate-on voltage (VEL), and the gate-off voltage is applied in other sections. (VEH) is entered.

Meanwhile, the section in which the emission signal for the n+1th display maintains the gate-off voltage (VEH) is longer than the section in which the emission signal for the n-1th display maintains the gate-off voltage (VEH). . This is because the nth sensing emission signal and the nth display emission signal are located between the n-1th display emission signal and the n+1th display emission signal.

When the first clock signal (ECLK1) is input to the nth stage (STn), the n-1th stage and the n+1 stage receive a second clock signal (ECLK2) whose phase is different from the first clock signal (ECLK1). is entered. At this time, the gate-on period of the first clock signal (ECLK1) overlaps the gate-off period of the second clock signal (ECLK2), and the gate-on period of the second clock signal (ECLK2) is the gate-off period of the first clock signal (ECLK1). It may overlap with the off section. Through this, stability of operation can be ensured.

Specifically, the nth stage (STn) may include input elements, sensing-related elements, and output elements.

Referring to FIG. 10, the input elements are connected to the voltage of node Q and the node Q based on the front-end carry signal (EM(n-1)) (i.e., the emission signal for the n-1 display) and the first clock signal (ECLK1). Controls the voltage of QB. For this purpose, the input elements may be composed of a plurality of transistors (T3, T4, T5, T6, TA) and a capacitor CON.

Transistor T3 is turned on according to the first clock signal (ECLK1) and applies the front-end carry signal (EM(n-1)) to one electrode of the transistor Tx. The gate electrode of transistor T3 is connected to the input terminal of the first clock signal (ECLK1), and the first and second electrodes of transistor T3 are respectively the input terminal of the previous carry signal (EM(n-1)) and one electrode of transistor Tx. is connected to

Transistor T4 is turned on according to the front-end carry signal (EM(n-1)) and applies the gate-off voltage (VEH) to node Q1. The gate electrode of the transistor T4 is connected to the input terminal of the previous carry signal EM(n-1), and the first and second electrodes of the transistor T4 are connected to the input terminal of the node Q1 and the gate-off voltage VEH, respectively.

Transistor T5 is turned on according to the voltage of node Q1 and applies the first clock signal (ECLK1) to node QB. The gate electrode of transistor T5 is connected to node Q1, and the first and second electrodes of transistor T5 are connected to the input terminal of the first clock signal (ECLK1) and node QB, respectively.

Transistor T6 is turned on according to the voltage of node Q2 and applies the gate-off voltage (VEH) to node QB. The gate electrode of transistor T6 is connected to node Q2, and the first and second electrodes of transistor T6 are connected to node QB and the input terminal of the gate-off voltage (VEH), respectively.

The gate electrode of transistor TA is connected to the input terminal of the gate-on voltage (VEL), and the first and second electrodes of transistor TA are connected to node Q and node Q2, respectively. The channel current between the first and second electrodes of transistor TA becomes zero when node Q is bootstrapped. In other words, transistor TA is turned off when node Q is bootstrapped, thus blocking the electrical connection between node Q and node Q2. Meanwhile, while node Q is not bootstrapped, transistor TA remains turned on.

Transistor TA remains turned on and turns off only when node Q is bootstrapped, blocking current flow between node Q and node Q2. Therefore, when node Q is bootstrapped, the potential of node Q2 becomes different from the potential of node Q. Even if the potential of node Q changes at the moment of bootstrapping, the potential of node Q2 does not change, so the transistors Tx, Ty, and T6 connected to node Q2 are not overloaded at the moment of bootstrapping. If there is no transistor TA, the voltage between the drain and source of each of the transistors Tx and Ty (Vds) and the voltage between the gate and source of transistor T6 (Vgs) may increase above the threshold due to bootstrapping. If the overload phenomenon continues, device destruction, or so-called break down phenomenon, may occur. Transistor TA prevents the transistors connected to node Q2 from breaking down at the moment of bootstrapping of node Q.

Transistor Ty is turned on according to the voltage of node QB and applies the gate-off voltage (VEH) to node Q2. The gate electrode of the transistor Ty is connected to the node QB, and the first and second electrodes of the transistor Ty are connected to the node Q2 and the input terminal of the gate-off voltage (VEH).

Capacitor CON is a coupling capacitor connected between the input terminal of the first clock signal (ECLK1) and node Q1.

Referring to FIG. 10, the sensing elements include a first global signal (GLB1), a second global signal (GLB2), and a third global signal (GLB3) having different phases and waveforms, and a rear-end carry signal (EM(n+) 1)) (i.e., the emission signal for the n+1th display) and the voltage of the subsequent node QB of the n+1th stage to control the voltage of node Q and the voltage of node QB. For this purpose, the sensing elements may be composed of a plurality of transistors (T7, T8, T9, Tx, Tz, Ty, Ty') and a capacitor C1.

Transistor T7 is turned on according to the voltage of node QB1 and applies the third global signal (GLB3) to node QB. The gate electrode of transistor T7 is connected to node QB1, and the first and second electrodes of transistor T7 are connected to the input terminal of the third global signal GLB3 and node QB, respectively.

Transistor T8 is turned on according to the rear carry signal (EM(n+1)) and applies the gate-off voltage (VEH) to node QB1. The gate electrode of transistor T8 is connected to the input terminal of the rear carry signal (EM(n+1)), and the first and second electrodes of transistor T8 are connected to the input terminal of node QB1 and gate-off voltage (VEH), respectively.

Transistor T9 is turned on according to the rear node QB (QB(n+1)) and connects node QB1 and node NO. The gate electrode of transistor T9 is connected to the input terminal of the rear node QB (QB(n+1)), and the first and second electrodes of transistor T9 are connected to node QB1 and node NO, respectively.

Transistor Tx is turned on according to the first global signal (GLB1) and connects one electrode of transistor T3 to node Q2. The gate electrode of the transistor Tx is connected to the input terminal of the first global signal (GLB1), and the first and second electrodes of the transistor Tx are connected to one electrode of the transistor T3 and node Q2, respectively.

The transistor Tz is turned on according to the second global signal (GLB2) and applies the gate-off voltage (VEH) to the node Q1. The gate electrode of the transistor Tz is connected to the input terminal of the second global signal (GLB2), and the first and second electrodes of the transistor Tz are connected to the node Q1 and the input terminal of the gate-off voltage (VEH), respectively.

Transistor Ty' and transistor Ty are connected in series between node Q2 and the input terminal of the first global signal (GLB1). The gate electrode of transistor Ty' is connected to the input terminal of the third global signal (GLB3), and the first and second electrodes of transistor Ty' are connected to node Q2 and one electrode of transistor Ty. Additionally, the gate electrode of the transistor Ty is connected to the node QB, and the first and second electrodes of the transistor Ty are connected to one electrode of the transistor Ty' and the input terminal of the first global signal (GLB1).

While the nth display emission signal is output as the gate-on voltage (VEL), transistor Ty and transistor Ty' are turned off, and the potential difference between node Q2 and the input terminal of the first global signal (GLB1) is zero. Therefore, while the emission signal for the nth display is output at the gate-on voltage (VEL), the load on transistor Ty and transistor Ty' is almost eliminated, and problems such as leakage current and distortion of switching characteristics due to overload are prevented in advance. It can be prevented.

Capacitor C1 is connected between node QB1 and node QB to stabilize the voltage at node QB1.

Meanwhile, with reference to FIG. 11, the first to third global signals (GLB1, GLB2, and GLB3) will be explained in detail as follows.

In synchronization with the first falling edge FE1 of the first global signal GLB1, the nth sensing emission signal is inverted from the gate-off voltage VEH to the gate-on voltage VEL.

In synchronization with the falling edge (FE) of the third global signal (GLB3), the nth sensing emission signal is inverted from the gate-on voltage (VEL) to the gate-off voltage (VEH).

In synchronization with the second falling edge FE2 of the first global signal GLB1, the nth display emission signal is inverted from the gate-off voltage VEH to the gate-on voltage VEL.

And, in synchronization with the rising edge (RE) of the second global signal (GLB2), the n-th display emission signal is inverted from the gate-on voltage (VEL) to the gate-off voltage (VEH).

Referring to FIG. 10, the output unit elements apply a gate-on voltage (VEL) to node NO according to the voltage of node Q, and apply a gate-off voltage (VEH) to node NO according to the voltage of node QB, Following the n-sensing driving emission signal, the n-th display driving emission signal is continuously output. For this purpose, the output elements may be composed of a plurality of transistors (T1, T2) and a plurality of capacitors (CB, CQB).

When transistor T1 is turned on, the nth emission signal (EM(n)) is output as the gate-on voltage (VEL). Transistor T1 is turned on according to the voltage of node Q and applies the gate-on voltage (VEL) to node NO. The gate electrode of transistor T1 is connected to node Q, and the first and second electrodes of transistor T1 are connected to the input terminal of the gate-on voltage (VEL) and node NO, respectively.

Capacitor CB is a bootstrapping capacitor connected between node Q and node NO. When the gate-on voltage (VEL) is applied to node NO due to the coupling effect of capacitor CB, the voltage of node Q is bootstrapped lower than the gate-on voltage (VEL), and the gate-source voltage (VEL) of transistor T1 -node Q voltage) increases. Accordingly, when capacitor CB is bootstrapped to the voltage of node Q, the gate-on voltage (VEL) is quickly applied to node NO, and the output delay of the n-th emission signal (EM(n)) can be minimized.

When transistor T2 is turned on, the nth emission signal (EM(n)) is output as the gate-off voltage (VEH). Transistor T2 is turned on according to the voltage of node QB and applies the gate-off voltage (VEH) to node NO. The gate electrode of transistor T2 is connected to node QB, and the first and second electrodes of transistor T2 are connected to the input terminal of the gate-off voltage VEH and node NO, respectively.

Capacitor CQB is connected between node QB and the input terminal of the gate-off voltage (VEH) to stabilize the voltage of node QB.

FIGS. 12A to 12G are diagrams for explaining the operation of the nth stage (STn) shown in FIG. 10. Here, the emission signal (EM(n)) output from the nth stage (STn) is an emission signal including both sensing driving and display driving, while the emission signals (EM) output from other stages are (n-2), EM(n-1), EM(n+1)) are emission signals that include only display driving.

Referring to FIG. 12A, in the Y1 section, the first clock signal (ECLK1), the first global signal (GLB1), and the rear-end carry signal (EM(n+1)) are input as the gate-on voltage (VEL), and the front-end carry signal (EM(n-1)) and the second and third global signals (GLB2 and GLB3) are input as the gate-off voltage (VEH).

In the Y1 section, the transistors (T3, Tx, TA) are turned on and node Q is charged to the gate-off voltage (VEH). Transistor T1 is turned off according to the node Q of the gate-off voltage (VEH). Meanwhile, transistor T4 is turned off according to the carry signal (EM(n-1)) preceding the gate-off voltage (VEH).

In the Y1 section, when the first clock signal (ECLK1) is inverted to the gate-on voltage (VEL), the voltage of node Q is also inverted to the gate-on voltage (VEL) due to the coupling effect of the capacitor CON. Transistor T5 is turned on according to the gate-on voltage (VEL) of node Q1, and node QB is charged with the gate-on voltage (VEL). As a result, transistor T2 is turned on according to the node QB of the gate-on voltage (VEL), and the gate-off voltage (VEH) is output through the node NO as the n-th emission signal (EM(n)).

In the Y1 section, transistor Ty is turned on according to the node QB of the gate-on voltage (VEL), and transistor Ty' is turned off according to the third global signal (GLB3) of the gate-off voltage (VEH). And, transistor T6 is turned off according to the node Q2 of the gate-off voltage (VEH).

In the Y1 section, transistor Tz is turned off according to the second global signal (GLB2) of the gate-off voltage (VEH), and transistor T9 is turned on according to the rear node QB (QB(n+1)) of the gate-off voltage (VEH). It turns off. On the other hand, transistor T8 is turned on according to the carry signal (EM(n+1)) following the gate-on voltage (VEL), and applies the gate-off voltage (VEH) to node QB1. Transistor T7 is turned off according to the node QB1 of the gate-off voltage (VEH).

Referring to FIG. 12b, in the Y2 section, the first clock signal (ECLK1) and the front-end carry signal (EM(n-1)) are input as the gate-on voltage (VEL), and the rear-end carry signal (EM(n+1)) and the first to third global signals GLB1, GLB2, and GLB3 are input as the gate-off voltage VEH.

In the Y2 section, transistor Tx is turned off according to the first global signal (GLB1) of the gate-off voltage (VEH), and transistor T4 is turned on according to the previous carry signal (EM(n-1)) of the gate-on voltage (VEL). Turn on. Then, node Q1 is charged to the gate-off voltage (VEH) and transistor T5 is turned off.

In the Y2 section, node Q is maintained at the gate-off voltage (VEH). Transistor T1 remains turned off according to the node Q of the gate-off voltage (VEH).

In the Y2 period, transistor T6 remains turned off and node QB is floating. The node QB maintains the gate-on voltage by the capacitor CQB, the transistor T2 turns on, and the gate-off voltage VEH is output through the node NO as the n-th emission signal EM(n).

In the Y2 section, transistors Tz, T7, and Ty' remain turned off, and transistor Ty remains turned on. And, while transistor T8 is turned off, transistor T9 is turned on.

Referring to FIG. 12C, the first global signal (GLB1) is input as the gate-on voltage (VEL) in the Y3 section. And, the first clock signal (ECLK1) and the front-end carry signal (EM(n-1)) are input as the gate-on voltage (VEL), and the rear-end carry signal (EM(n+1)) and the second and third global Signals (GLB2, GLB3) are input as the gate-off voltage (VEH).

In the Y3 section, the transistors (T3, Tx, TA) are turned on and node Q is charged to the gate-on voltage (VEL). Transistor T1 is turned on according to the node Q of the gate-on voltage (VEL), and the gate-on voltage (VEL) is output as the n-th emission signal (EM(n)) through the node NO.

In the Y3 section, transistor T6 is turned on according to the gate-on voltage (VEL) of node Q2, and node QB is charged with the gate-off voltage (VEH). Transistor T2 is turned off according to QB of the gate-off voltage (VEH).

In the Y3 section, transistor T8 is turned off, transistor T9 is turned on, and node QB1 is charged to the gate-on voltage (VEL). Transistor T7 is turned on according to the gate-on voltage (VEL) of node QB1, and the third global signal (GLB3) of the gate-off voltage (VEH) is applied to node QB.

In the Y3 section, transistor Ty' remains turned off, and transistor Ty is turned off according to the node QB of the gate-off voltage (VEH). Additionally, transistor T4 remains turned on according to the carry signal (EM(n-1)) preceding the gate-on voltage (VEL), and transistors T5 and Tz remain turned off.

Referring to FIG. 12D, the third global signal GLB3 is input as the gate-on voltage VEL in the Y4 section. And, the first clock signal (ECLK1) and the front-end carry signal (EM(n-1)) are input as the gate-on voltage (VEL), and the rear-end carry signal (EM(n+1)) and the first and second global The signals (GLB1 and GLB2) are input as the gate-off voltage (VEH).

In the Y4 section, the transistor Tx is turned off according to the first global signal (GLB1) of the gate-off voltage (VEH), and the node Q is floating to maintain the gate-on voltage (VEL) (① operation). Then, transistor T1 is turned on and the gate-on voltage (VEL) is applied to node NO (② operation).

In the Y4 section, the gate-on voltage (VEL) of node NO is applied to node QB1 through transistor T9 (③ operation). Then, transistor T7 is turned on, and the third global signal (GLB3) of the gate-on voltage (VEL) is charged to node QB (④ operation).

In the Y4 section, transistor Ty is turned on according to the node QB of the gate-on voltage (VEL), and transistor Ty' is turned on according to the third global signal (GLB3) of the gate-on voltage (VEL), so that node Q2 and node Q is charged to the gate-off voltage (VEH). Accordingly, transistor T1 is turned off (⑤ operation). And, transistor T6 is turned off according to the node Q2 of the gate-off voltage (VEH) (⑥ operation).

In the Y4 section, transistor T2 is turned on according to the node QB of the gate-on voltage (VEL), and the gate-off voltage (VEH) is output as the nth emission signal (EM(n)) through the node NO.

In the Y4 section, transistors T3 and T4 remain turned on, and transistors T5 and Tz remain turned off.

Referring to FIG. 12e, the first global signal (GLB1) is input as the gate-on voltage (VEL) in the Y5 section. And, the first clock signal (ECLK1) and the front-end carry signal (EM(n-1)) are input as the gate-on voltage (VEL), and the rear-end carry signal (EM(n+1)) and the second and third global Signals (GLB2, GLB3) are input as the gate-off voltage (VEH).

The operation of the Y5 section is substantially the same as the operation of the Y3 section.

That is, in the Y5 section, the transistors (T3, Tx, TA) are turned on and the node Q is charged to the gate-on voltage (VEL). Transistor T1 is turned on according to the node Q of the gate-on voltage (VEL), and the gate-on voltage (VEL) is output as the n-th emission signal (EM(n)) through the node NO.

In the Y5 section, transistor T6 is turned on according to the gate-on voltage (VEL) of node Q2, and node QB is charged with the gate-off voltage (VEH). Transistor T2 is turned off according to QB of the gate-off voltage (VEH).

In the Y5 section, transistor Ty' is turned off according to the third global signal GLB3 of the gate-off voltage VEH, and transistor Ty is turned off according to the node QB of the gate-off voltage VEH. At this time, the voltage between both ends of the turned-off transistors Ty' and Ty, that is, the voltage difference between node Q2 and the input terminal of the first global signal (GLB1) is zero. Accordingly, the load applied to the turned-off transistors Ty' and Ty is minimized.

Referring to FIG. 12f, the second global signal GLB2 is inverted to the gate-on voltage VEL in the Y6 section. In addition, the first global signal (GLB1), the first clock signal (ECLK1), and the rear-end carry signal (EM(n+1)) are input as the gate-on voltage (VEL), and the front-end carry signal (EM(n-1)) and the third global signal (GLB3) are input as the gate-off voltage (VEH).

In the Y6 section, the transistors (T3, Tx, TA) are turned on and node Q is charged to the gate-off voltage (VEH). Transistor T1 is turned off according to the node Q of the gate-off voltage (VEH). Meanwhile, transistor T4 is turned off according to the carry signal (EM(n-1)) preceding the gate-off voltage (VEH).

In the Y6 section, transistor Tz is turned on by the second global signal (GLB2) of the gate-on voltage (VEL), and Q1 is charged to the gate-off voltage (VEH) to turn off transistor T5. Additionally, transistor T6 is turned off according to the node Q2 of the gate-off voltage VEH, and transistor T7 is turned off according to the node QB1 of the gate-off voltage VEH.

In the Y6 section, the node QB is floating by turning off the transistors T5, T6, and T7, and the node QB maintains the gate-off voltage (VEH) by the capacitor CQB to turn off the transistor T2.

In the Y6 section, transistors T1 and T2 are turned off, so the n-th emission signal EM(n) maintains the gate-on voltage (VEL) in the Y5 section.

Referring to FIG. 12g, the second global signal GLB2 is inverted to the gate-off voltage VEH in the Y7 section. In addition, the first global signal (GLB1), the first clock signal (ECLK1), and the rear-end carry signal (EM(n+1)) are input as the gate-on voltage (VEL), and the front-end carry signal (EM(n-1)) and the third global signal (GLB3) are input as the gate-off voltage (VEH).

In the Y7 section, the transistors (T3, Tx, TA) are turned on and node Q is charged to the gate-off voltage (VEH). Transistor T1 is turned off according to the node Q of the gate-off voltage (VEH). Meanwhile, transistor T4 is turned off according to the carry signal (EM(n-1)) preceding the gate-off voltage (VEH).

In the Y7 section, transistor Tz is turned off by the second global signal (GLB2) of the gate-off voltage (VEH), and node Q1 is charged to the gate-on voltage (VEL) due to the coupling effect of the capacitor CON, so that transistor T5 is turned on. Turn on. Additionally, transistor T6 is turned off according to the node Q2 of the gate-off voltage VEH, and transistor T7 is turned off according to the node QB1 of the gate-off voltage VEH.

In the Y7 section, the node QB is charged to the gate-on voltage (VEL) by turning on the transistor T5, and the transistor T2 is turned on by the node QB of the gate-on voltage (VEL). As a result, the gate-off voltage VEH is output through node NO as the n-th emission signal EM(n).

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

100: display panel 110: timing controller
120: data driver 130: gate driver

Claims (14)

In a gate driver for external compensation having a plurality of stages,
Among the plurality of stages, the nth stage continuously outputs the nth sensing emission signal and the nth display emission signal, and the n-1th stage is ahead of the nth sensing emission signal in phase. An emission signal for the n-1th display is output, and the n+1th stage outputs an emission signal for the n+1th display whose phase is behind the nth sensing emission signal,
The nth stage is,
A gate-on voltage is applied to the node NO according to the voltage of node Q, and a gate-off voltage is applied to the node NO according to the voltage of node QB, so that the nth emission signal for sensing is followed by the emission signal for the nth display. Output elements that continuously output signals;
Input elements that control the voltage of the node Q and the voltage of the node QB based on the n-1 display emission signal and the first clock signal; and
Based on the first global signal, second global signal, and third global signal with different phases and waveforms, the emission signal for the n+1th display, and the voltage of the rear node QB of the n+1th stage A gate driver including sensing elements that control the voltage of the node Q and the voltage of the node QB. According to claim 1,
The output elements are,
a transistor T1 whose gate electrode is connected to the node Q, a first electrode connected to the input terminal of the gate-on voltage, and a second electrode connected to the node NO;
a transistor T2 whose gate electrode is connected to the node QB, a first electrode connected to the input terminal of the gate-off voltage, and a second electrode connected to the node NO; and
A gate driver including a capacitor CB connected between the node Q and the node NO. According to claim 1,
The input elements are,
a transistor T3 whose gate electrode is connected to the input terminal of the first clock signal and whose first electrode is connected to the input terminal of the n-1th display emission signal;
a transistor T4, the gate electrode of which is connected to the input terminal of the n-1 display emission signal, the first electrode connected to the input terminal of the gate-off voltage, and the second electrode connected to the node Q1;
a transistor T5 whose gate electrode is connected to the node Q1, a first electrode connected to the input terminal of the first clock signal, and a second electrode connected to the node QB;
a transistor T6, the gate electrode of which is connected to the node Q2, the first electrode connected to the input terminal of the gate-off voltage, and the second electrode connected to the node QB; and
A gate driver including a capacitor CON connected between the input terminal of the first clock signal and the node Q1. According to claim 3,
The input elements are,
A gate driver further comprising a transistor TA having a gate electrode connected to the input terminal of the gate-on voltage, a first electrode connected to the node Q2, and a second electrode connected to the node Q. According to claim 3,
The sensing elements involved are,
A gate driver including a transistor Ty' and a transistor Ty connected in series between the node Q2 and the input terminal of the first global signal. According to claim 5,
The gate electrode of the transistor Ty' is connected to the input terminal of the third global signal, and the first and second electrodes of the transistor Ty' are connected to the node Q2 and one electrode of the transistor Ty,
A gate electrode of the transistor Ty is connected to the node QB, and a first electrode and a second electrode of the transistor Ty are connected to one electrode of the transistor Ty' and an input terminal of the first global signal. According to claim 5,
While the nth display emission signal is output at the gate-on voltage, the transistor Ty and transistor Ty' are turned off, and the potential difference between the node Q2 and the input terminal of the first global signal is zero. According to claim 5,
The sensing elements involved are,
a transistor Tx whose gate electrode is connected to the input terminal of the first global signal, whose first electrode is connected to the second electrode of the transistor T3, and whose second electrode is connected to the node Q2;
a transistor Tz, the gate electrode of which is connected to the input terminal of the second global signal, the first electrode connected to the input terminal of the gate-off voltage, and the second electrode connected to the node Q1;
a transistor T7 whose gate electrode is connected to node QB1, whose first electrode is connected to the input terminal of the third global signal, and whose second electrode is connected to the node QB;
a transistor T8, the gate electrode of which is connected to the input terminal of the n+1 display emission signal, the first electrode connected to the input terminal of the gate-off voltage, and the second electrode connected to the node QB1; and
The gate driver further includes a transistor T9, the gate electrode of which is connected to the input terminal of the voltage of the rear node QB of the n+1th stage, the first electrode connected to the node NO, and the second electrode connected to the node QB1. According to claim 1,
The nth sensing emission signal is inverted from the gate-off voltage to the gate-on voltage in synchronization with the first falling edge of the first global signal,
The nth sensing emission signal is inverted from the gate-on voltage to the gate-off voltage in synchronization with the falling edge of the third global signal,
The nth display emission signal is inverted from the gate-off voltage to the gate-on voltage in synchronization with the second falling edge of the first global signal,
A gate driver wherein the nth display emission signal is inverted from the gate-on voltage to the gate-off voltage in synchronization with the rising edge of the second global signal. According to claim 1,
A gate driver in which the emission signal for the n-1th display, the emission signal for the nth display, and the emission signal for the n+1th display have the same section for maintaining the gate-on voltage. According to claim 1,
A gate driver in which the section in which the emission signal for the n+1th display maintains the gate-off voltage is longer than the section in which the emission signal for the n-1th display maintains the gate-off voltage. According to claim 1,
A second clock signal having a different phase from the first clock signal is input to the n-1th stage and the n+1 stage,
A gate driver wherein the gate-on period of the first clock signal overlaps with the gate-off period of the second clock signal, and the gate-on period of the second clock signal overlaps with the gate-off period of the first clock signal. The external compensation gate driver of any one of claims 1 to 12;
a gate line through which an n-th sensing emission signal and an n-th display emission signal are continuously supplied from the external compensation gate driver;
pixels connected to the gate line;
Sensing units operating in response to the nth sensing emission signal; and
An organic light emitting display device comprising digital-to-analog converters that operate in response to the nth display emission signal. According to claim 13,
The sensing units sense driving characteristics of the pixels within a period in which the n-th sensing emission signal is maintained at the gate-on voltage,
An organic light emitting display device in which the light emitting elements of the pixels emit light during a period in which the nth display emission signal is maintained at the gate-on voltage.