KR102600691B1 - shift register for generating EM signal for OLED and OLED display device using the same - Google Patents

Abstract

The present invention uses different types of clock signals to generate a scan signal output for driving the gate line and an EM signal output for driving the light emission control driver from different output switching devices, and to prevent leakage of the turned-off switching device. This relates to an EM signal generation shift register for OLED that can obtain stable output by preventing current and an OLED display device using the same. The EM signal generation shift register for OLED is a shift register having a plurality of stages, each stage having a plurality of stages. , a set unit that charges the start signal, the EM signal or scan signal output from the previous stage, or the first high potential voltage to the Q node in accordance with the start signal, or the EM signal or scan signal output from the previous stage, and a reset signal Or, a reset unit that discharges the Q node with a first discharge voltage according to an EM signal or scan signal output from a later stage, and a Q clearer that clears the Q node with a second discharge voltage according to the logic state of the QB node. An inverter unit that inverts the Q node voltage and outputs it to the QB node, receives one EM clock pulse among a plurality of EM clock pulses, and receives the EM clock pulse according to the logic states of the Q node and the QB node. An EM signal output unit that outputs a clock pulse as an EM signal, receives one scan clock pulse among a plurality of scan clock pulses, and outputs the scan clock pulse according to the logic states of the Q node and the QB node. It is comprised of a scan signal output unit that outputs a scan signal.

Description

Shift register for generating EM signal for OLED and OLED display device using the same {shift register for generating EM signal for OLED and OLED display device using the same}

The present invention relates to a shift register for OLED, and in particular, to a shift register for generating an emission control (EM) signal for OLED that can output a normal output signal by preventing leakage current, and to an OLED display device using the same.

Flat display devices that have recently been in the spotlight as display devices include liquid crystal displays (LCD) using liquid crystals, OLED displays using organic light emitting diodes (OLED), and display devices using electrophoretic particles. A representative example is an electrophoretic display (EPD).

Among these, each of the plurality of pixels or subpixels constituting the pixel array of the OLED display device includes an OLED element composed of an organic light-emitting layer between an anode and a cathode, and a pixel circuit that independently drives the OLED element. The pixel circuit includes a switching thin film switching element (Thin Film Tansistor (TFT)) that switches the data voltage to charge the storage capacitor with a voltage corresponding to the data voltage, and an OLED element that controls the current according to the voltage charged in the storage capacitor. It may further include a driving TFT that supplies power to the OLED device, and an emission control TFT that controls the emission period of the OLED device by switching the current flowing to the OLED device through the driving TFT.

The switching TFT is in an off state for most of the entire period and is in an on state for some periods for charging new data. On the other hand, the light emission control TFT is in an on state for most of the entire period, is in an off state for a part of the period, and often repeats on and off several times in a part of the period.

Generally, an OLED display device includes a gate driver that drives a gate line connected to a switching TFT and an emission control driver that drives an emission control line connected to the emission control TFT. That is, the emission control driver is installed separately from the gate driver, and an input signal is used to drive the emission control driver. Therefore, when the gate driver and the emission control driver are built into an OLED display panel, they occupy a large area.

Additionally, the gate driver and the light emission control driver each include a shift register that sequentially generates output.

The shift register configured in the gate driver includes a plurality of stages that are dependently connected to each other, and each stage is composed of a plurality of thin film switching elements. The output of each stage is supplied as a scan pulse to each gate line and as a control signal to control other stages. Each stage consists of an output unit that generates output and a control unit that controls the output unit.

The shift register configured in the light emission control driver also includes a plurality of stages that are dependently connected to each other, and each stage is composed of a plurality of TFTs that invert the input voltage and generate an output according to the logic state of the internal control node. Normal output can be generated when the voltage remains stable.

Each of the shift registers is composed of an N-type TFT, and the gate voltage of the N-type TFT does not become lower than the low potential voltage applied to the source electrode. Accordingly, even if a low voltage is applied as the gate voltage and the TFT is logically turned off, a leakage current may occur because the gate-source voltage (Vgs) is greater than 0V (Vgs>0V). This phenomenon occurs when the threshold voltage (Vth) of the TFT shifts to negative, the leakage current becomes larger, and the gate driver and emission control driver may not operate normally and may not output a normal waveform.

For example, when using a light-sensitive oxide TFT, if the threshold voltage (Vth) of the oxide TFT shifts to negative by the application of light, the turn-off device is connected between the control node of each stage and the low-potential voltage source. Leakage current may occur in the TFT. As a result, the control node voltage decreases, thereby distorting the output waveforms of the gate driver and the light emission control driver and causing output defects.

The present invention was developed to solve the conventional problems, and outputs a scan signal for driving the gate line and an EM signal for driving the light emission control driver from different output switching devices using different types of clock signals. The purpose is to provide an EM signal generating shift register for OLED that can obtain stable output by preventing leakage current of turned-off switching elements, and an OLED display device using the same.

The EM signal generation shift register for OLED according to the present invention to achieve the above object is a shift register having a plurality of stages, each stage having a start signal, an EM signal or a scan signal output from a previous stage. A set unit that charges the Q node with the start signal, an EM signal or scan signal output from the previous stage, or a first high potential voltage, and a first device according to the reset signal or the EM signal or scan signal output from the rear stage. A reset unit that discharges the Q node with a discharging voltage, a Q clear unit that clears the Q node with a second discharging voltage according to the logic state of the QB node, and a Q clear unit that inverts the Q node voltage and outputs it to the QB node. An inverter unit, an EM signal output unit that receives one EM clock pulse among a plurality of EM clock pulses and outputs the EM clock pulse as an EM signal according to the logic states of the Q node and the QB node, It is configured to include a scan signal output unit that receives one scan clock pulse among a plurality of scan clock pulses and outputs the scan clock pulse as a scan signal according to the logic states of the Q node and the QB node. There is.

In addition, in the OLED display device according to the present invention for achieving the above object, a plurality of scan lines, a plurality of data lines, and a plurality of emission control lines are arranged to form a plurality of subpixels, and each subpixel is an OLED display device. It has a pixel circuit that independently drives the device and the OLED device, and the pixel circuit includes a switching transistor that switches the data voltage supplied through each data line to charge a storage capacitor with a voltage corresponding to the data voltage, A driving transistor that controls current and supplies it to the OLED device according to the voltage charged in the storage capacitor, and a light emission control transistor that controls the emission period of the OLED device by switching the current flowing to the OLED device through the driving transistor. An OLED display panel, a shift register that outputs a scan signal for sequentially driving the plurality of gate lines from different output switching elements using different types of clock signals and simultaneously outputs an EM signal, the shift register It is characterized by having a light emission control driver that inputs an EM signal output from and outputs an EM control signal that drives the light emission control transistor of the OLED panel.

The EM signal generating shift register for OLED according to the present invention and the OLED display device using the same have the following effects.

First, the shift register of the present invention has a simple circuit configuration, outputs a scan signal for driving the scan line from different output switching elements using different types of clock signals, and generates an EM signal for driving the light emission control line. Therefore, when the shift register and the light emission control driver are built into the OLED display panel, the area occupied by the shift register and the light emission control driver can be reduced.

Second, it is possible to prevent the leakage current of the switching device that is turned off depending on the low state of the Q node, thereby obtaining a stable output, increasing the range of the threshold voltage that allows normal operation, and turning the gate on by low-frequency driving. Even if the voltage output period increases, stable output can be maintained.

1 is a basic configuration block diagram for explaining an OLED display device according to the present invention.
2A to 2C are block diagrams of various configurations of each stage of the EM signal generation shift register for OLED according to the present invention.
Figure 3 is a waveform diagram of clock pulses for EM and clock pulses for scanning according to an embodiment of the present invention.
Figure 4 is a block diagram of each stage of the EM signal generation shift register for OLED according to an embodiment of the present invention.
Figure 5 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the first embodiment of the present invention.
Figure 6 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the second embodiment of the present invention.
Figure 7 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the third embodiment of the present invention.
Figure 8 is a circuit configuration diagram of another embodiment of the fifth switching element in the circuit configuration of each stage of the EM signal generating shift register for OLED according to the third embodiment of the present invention.
9 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the fourth embodiment of the present invention.
Figure 10 is a circuit configuration diagram of another embodiment of the first switching element (T1) of the set portion (QS) in the circuit configuration of each stage of the EM signal generation shift register for OLED according to the fourth embodiment of the present invention.
Figure 11 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the fifth embodiment of the present invention.
Figure 12 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the sixth embodiment of the present invention.
13A to 13B are circuit diagrams of another embodiment of the twelfth switching element T10 in the circuit configuration of each stage of the EM signal generating shift register for OLED according to the sixth embodiment of the present invention.
Figure 14 is a circuit configuration diagram of an embodiment other than the first switching element (T1) of the set portion (QS) in the circuit configuration of each stage of the EM signal generating shift register for OLED according to each embodiment of the present invention.
15A to 15B are circuit diagrams of other embodiments instead of the second switching element (T2) of the reset unit (QR) in the circuit configuration of each stage of the EM signal generating shift register for OLED according to each embodiment of the present invention.
16 shows a pull-down switching element (T7) of the EM signal output unit (IO) or the scan signal output unit (SO) in the circuit configuration of each stage of the EM signal generation shift register for OLED according to each embodiment of the present invention. Or T7c) Circuit diagram of another embodiment instead
17(a) to 17(d) are inverter circuit configuration diagrams of various embodiments according to the present invention.
Figures 18(a) and 18(b) are circuit diagrams of switching elements that can be added to the inverter according to the embodiment of the present invention.
FIG. 19 shows the results of simulating the driving waveforms of each stage of the EM signal generation shift register in which the reset unit (QR) is configured as shown in FIG. 15b in the EM signal generation shift register according to the fourth embodiment of the present invention described in FIG. 9. This is a waveform diagram showing .

The OLED shift register according to the present invention having the above-mentioned characteristics and the OLED display device using the same will be described in more detail with reference to the attached drawings as follows.

Figure 1 is a basic configuration block diagram for explaining the OLED display device according to the present invention, and Figures 2A to 2C are various configuration block diagrams of each stage of the shift register for OLED according to the present invention. Figure 3 is a waveform diagram of clock pulses for EM and scan pulses according to an embodiment of the present invention.

First, the OLED display device according to the present invention is comprised of an OLED display panel 1, a shift register 2, and an emission control driver 3, as shown in FIG. 1.

The OLED display panel 1 is an OLED device in which a plurality of scan lines, a plurality of data lines, and a plurality of emission control lines are arranged to form a plurality of subpixels, and each subpixel is an organic light-emitting layer between an anode and a cathode. and a pixel circuit that independently drives the OLED elements.

The pixel circuit includes a switching TFT that switches the data voltage supplied through each data line to charge a storage capacitor with a voltage corresponding to the data voltage, and controls a current according to the voltage charged in the storage capacitor to the OLED element. It is comprised of a driving TFT that supplies a light emission control TFT that controls the emission period of the OLED device by switching the current flowing to the OLED device through the driving TFT.

The shift register 2 uses different types of clock signals to output scan signals for sequentially driving the plurality of gate lines from different output switching elements and at the same time EM signals for driving the light emission control driver. outputs.

The emission control driver 3 inputs the EM signal output from the shift register and outputs an EM control signal that drives the emission control TFT of the OLED panel. The emission control driver 3 functions as an inverter to invert the EM signal output from the shift register.

Although not shown in the drawing, the shift register 2 and the light emission control driver 3 are configured with a plurality of stages.

Here, as shown in FIG. 2A, the shift register uses an EM signal output node (Qnc) that controls an EM signal output unit that outputs an EM signal (Vc1) using an EM clock pulse and a scanning clock pulse. and a scan signal output node (Qns) that controls the scan signal output unit that outputs the scan signal (Vg1).

At this time, as shown in FIG. 2B, the shift register is formed between the EM signal output node (Qnc) and the scan signal output node (Qns) and is turned on or off according to an external control signal. A switching element that switches between the EM signal output node (Qnc) and the scan signal output node (Qns) when turned on may be further included.

In addition, as shown in FIG. 2C, the shift register is formed between the EM signal output node (Qnc) and the scan signal output node (Qns) and is turned on according to the signal of the scan signal output node (Qns). Alternatively, a switching element may be further provided to switch between the EM signal output node (Qnc) and the scan signal output node (Qns) when turned off and turned on.

The EM clock pulses and the scan clock pulses are as shown in FIG. 3.

As shown in FIG. 3, the EM clock pulse and the scan clock pulse are m-phase and n-phase cyclic clock pulses (CLKi1 to CLKi6 and CLKs1 to CLKs6), respectively. Here, m and n are natural numbers, and m and n may be the same or different. The EM clock pulse and the scan clock pulse are the same in that they have two or more impulses, but the EM clock pulse and the scan clock pulse are different pulses. Although FIG. 3 shows 6-phase EM clock pulses and 6-phase scan clock pulses, the present invention is not limited thereto.

Figure 4 is a block diagram of each stage of the EM signal generation shift register for OLED according to each embodiment of the present invention.

The configuration of each stage of the EM signal generation shift register for OLED according to each embodiment of the present invention is, as shown in FIG. 4, the start signal, or the start signal according to the EM signal or scan signal output from the front stage, A set section (QS) that charges the Q node with the EM signal or scan signal output from the front stage, or the high potential voltage (VDD), and the discharge voltage ( A reset unit (QR) that discharges the Q node with Vssc), a Q clear unit (QC) that clears the Q node with a discharge voltage (Vssb) according to the logic state of the QB node, and inverts the Q node voltage. and an inverter unit (IN) that outputs to the QB node, receives one EM clock pulse among the plurality of EM clock pulses (CLKi1 to CLKi6), and transmits the EM according to the logic states of the Q node and the QB node. An EM signal output unit (IO) that outputs a clock pulse as an EM signal (Vinp), and receives one scan clock pulse among the plurality of scan clock pulses (CLKs1 to CLKs6) to connect the Q node and the QB. It is comprised of a scan signal output unit (SO) that outputs the scan clock pulse as a scan signal (Vout) according to the logic state of the node.

The specific circuit configuration of each stage of the EM signal generating shift register for OLED according to each embodiment of the present invention configured as described above will be described as follows.

Figure 5 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the first embodiment of the present invention.

The circuit configuration of each stage of the EM signal generation shift register for OLED according to the first embodiment of the present invention is as shown in FIG. 4, where the set unit (QS) is a start signal or an EM signal output from a previous stage. Or, a first switching element (T1) that is turned on or turned off according to a scan signal and charges the start signal, an EM signal or scan signal output from the front stage, or a high potential voltage (VDD) to the Q node when turned on. Equipped with

The reset unit (QR) is turned on or off according to a reset signal or an EM signal or scan signal output from a rear stage, and includes a second switching element (T2) that discharges the Q node to the discharge voltage when turned on. Equipped with

The Q clear unit (QC) is connected in series between the Q node and the supply terminal of the discharging voltage (VSSb), and is turned on or turned off depending on the logic state of the QB node, so that when turned on, the Q node The first and second clear switching elements (T3a, T3b) supply a discharge voltage (VSS), and the first and second clear switching elements (T3a, T3b) are turned on or turned off according to the logic state of the Q node and set an offset voltage (VD) when turned on. and a third clear switching element (T3c) supplied to the connection node (cn) of the second clear switching elements (T1, T2).

The first and second clear switching elements (T3a, T3b) of the Q clear unit (QC) are turned on when the QB node is in high logic to discharge the Q node to the discharge voltage (VSSb), and the QB node is turned on. When the node is in low logic, it is turned off to block the connection between the Q node and the discharge voltage (VSSb).

When the first and second clear switching elements T3a and T3b are turned off by the low logic of the QB node, the third clear switching element T3c is turned on by the high logic of the Q node. do. The turned-on third clear switching element (T3c) applies the offset voltage (VD) to the connection node (cn) of the first and second clear switching elements (T3a, T3b), that is, the second clear switching element (T3b). An offset voltage (VD) is applied to the source of the first clear switching element (T3a) connected to the drain of . Accordingly, the low logic of the QB node is applied to the gate terminal of the first clear switching device (T3a), and an offset voltage (VD) higher than the low logic is applied to the source terminal of the first clear switching device (T3a). The gate-source voltage (Vgs) has a negative value lower than the threshold voltage, resulting in complete turn-off. In addition, even if the threshold voltage of the first clear switching element (T3a) moves to negative, the gate-source voltage (Vgs) is lower than the threshold voltage due to the offset voltage (VD) applied to the source, so that the first clear switching element (T3a) (T3a) is completely turned off. Accordingly, leakage current of the Q node through the first and second clear switching elements T3a and T3b can be prevented.

In this way, when the Q node is in high logic, the first clear switching device (T3a) is completely turned off by the offset voltage (VD) supplied through the turned-on third clear switching device (T3c). As the Q node maintains stable high logic by preventing charge leakage, the high logic output (Vinp) to the OLED emission control driver can be normally maintained.

The inverter unit (IN) includes an inverter (IN) that receives the high potential voltage (VH) and the low potential voltage (VL), inverts the Q node voltage, and outputs the inverted Q node voltage to the QB node.

The EM signal output unit (IO) receives one EM clock pulse (CLKi) among the plurality of EM clock pulses (CLKi1 to CLKi6) and is turned on or turned off according to the logic state of the Q node. A first pull-up switching element (T6c) that outputs the EM clock pulse to the output terminal (Vinp) when turned on, and the discharge voltage (Vssb) when turned on or turned off depending on the logic state of the QB node. It is configured to include a first pull-down switching element (T7c) that discharges the output terminal.

The scan signal output unit (SO) receives one scan clock pulse (CLKs) among the plurality of scan clock pulses (CLKs1 to CLKs6) and is turned on or turned off according to the logic state of the Q node. A second pull-up switching element (T6) that outputs the scan clock pulse to the output terminal (Vout) when turned on, and is turned on or turned off depending on the logic state of the QB node to be converted to a discharge voltage (Vssa) when turned on. It is comprised of a second pull-down switching element (T7) that discharges the output terminal (Vout).

Here, VD, VDD, and VH may be the same or different, the start signal and reset signal are externally applied signals, and Vssa, Vssb, and Vssc preferably satisfy the condition of Vssa ≥ Vssb ≥ Vssc.

In addition, in Figure 5, the input terminal of the inverter (IN) is shown to be connected to the Q node, but it is not limited to this and may have other inputs (see the drawings below).

Figure 6 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the second embodiment of the present invention.

The circuit configuration of each stage of the EM signal generation shift register for OLED according to the second embodiment of the present invention is the circuit configuration of each stage of the EM signal generation shift register for OLED according to the first embodiment of the present invention described in FIG. As described in FIG. 2B, it is formed between the EM signal output node (Qnc) and the scan signal output node (Qns) and is turned on or off according to an external control signal (Vx), so that when turned on, the EM It is further provided with a third switching element (Tt) that switches between the signal output node (Qnc) and the scan signal output node (Qns).

Here, the Q node is an EM signal output node (Qnc) to which the gate terminal of the first pull-up switching element (T6c) of the EM signal output unit (IO) is connected and the second pull of the scan signal output unit (SO). It has a scan signal output node (Qns) to which the gate terminal of the up switching element (T6) is connected.

The external control signal (Vx) may be a signal such as VD, VDD, or VH.

The remaining configuration is the same as Figure 5. Therefore, description of the remaining configuration is omitted.

Figure 7 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the third embodiment of the present invention, and Figure 8 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the third embodiment of the present invention. In the circuit configuration of , this is a circuit configuration diagram of another embodiment of the fifth switching element.

The circuit configuration of each stage of the EM signal generation shift register for OLED according to the third embodiment of the present invention is the circuit configuration of each stage of the EM signal generation shift register for OLED according to the first embodiment of the present invention described in FIG. As described in FIG. 2C, it is formed between the EM signal output node (Qnc) and the scan signal output node (Qns) and is turned on or off according to the signal of the scan signal output node (Qns). A fourth switching element (Tt1) that switches between the EM signal output node (Qnc) and the scan signal output node (Qns), and is turned on or turned off depending on the logic state of the QB node, and when turned on, the EM It is further provided with a fifth switching element (Tt2) that discharges the signal output node (Qnc) to the discharge voltage (Vssb).

The remaining configuration is the same as Figure 5. Therefore, description of the remaining configuration is omitted.

Here, instead of the fifth switching element Tt2, it may be configured as shown in FIG. 8.

That is, it is connected in series between the Q node or the EM signal output node (Qnc) and the supply terminal of the discharge voltage (Vssb), and is turned on or off depending on the logic state of the QB node, so that when turned on, the Q The sixth and seventh switching elements (Tt2a, Tt2b) that supply the discharge voltage (Vssb) to the node are turned on or off depending on the logic state of the Q node or the EM signal output node (Qnc). It may be configured to include an eighth switching element (Tt2c) that supplies the offset voltage (VD) or high potential voltage (VH) to the connection node of the sixth and seventh switching elements (Tt2a, Tt2b) when turned on.

If configured as shown in FIG. 8 instead of the fifth switching device (Tt2), the sixth and seventh switching devices (Tt2a, Tt2b) are turned on when the QB node is in high logic to transmit the Q node or the EM signal. The output node (Qnc) is discharged to the discharging voltage (Vssb), and when the QB node is in low logic, it is turned off to block the connection between the Q node and the discharging voltage (Vssb).

When the sixth and seventh switching devices (Tt2a, Tt2b) are turned off by the low logic of the QB node, the eighth switching device (Tt2c) is turned on by the high logic of the Q node. The turned-on eighth switching device (Tt2c) connects the offset voltage (VD) to the connection node of the sixth and seventh switching devices (Tt2a and Tt2b), that is, the sixth switch connected to the drain of the seventh switching device (Tt2b). An offset voltage (VD) or high potential voltage (VH) is applied to the source of the switching element (Tt2a). Accordingly, the low logic of the QB node is applied to the gate terminal of the sixth switching device (Tt2a), and the offset voltage (VD) or high potential voltage (VD) higher than the low logic is applied to the source terminal of the sixth switching device (Tt2a). VH) is applied so that the gate-source voltage (Vgs) has a negative value lower than the threshold voltage, thereby completely turning off. In addition, even if the threshold voltage of the sixth switching device (Tt2a) moves to negative, the gate-source voltage (Vgs) is lower than the threshold voltage due to the offset voltage (VD) applied to the source, so the sixth switching device (Tt2a) ) is completely turned off. Accordingly, leakage current of the Q node through the sixth and seventh switching elements Tt2a and Tt2b can be prevented.

Figure 9 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the fourth embodiment of the present invention, and Figure 10 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the fourth embodiment of the present invention. In the circuit configuration of , this is a circuit configuration diagram of another embodiment of the first switching element (T1) of the set portion (QS).

The circuit configuration of each stage of the EM signal generation shift register for OLED according to the fourth embodiment of the present invention is the circuit configuration of each stage of the EM signal generation shift register for OLED according to the first embodiment of the present invention described in FIG. , further comprising a ninth switching element (T5) that is turned on or turned off according to an EM signal, scan signal, or start signal output from the front stage and discharges the QB node to a discharge voltage (Vssb) when turned on. will be.

In this way, if the ninth switching element T5 is further provided, conversion of the QB node from a high state to a low state can be promoted.

FIG. 9 shows that a high potential voltage (VH) is applied to the third clear switching element (T3c) of the Q clear unit (QC) instead of an offset voltage.

In the circuit configuration of each stage of the EM signal generation shift register for OLED according to the fourth embodiment, EM output from the previous stage is connected to both the gate terminal and the source terminal of the first switching element (T1) of the set section (QS). A signal (Vinp) may be applied.

In addition, in the circuit configuration of each stage of the EM signal generating shift register for OLED according to the fourth embodiment, the gate terminal of the first switching element (T1) of the set portion (QS) has an EM signal output from the previous stage ( Vinp) may be applied, and a scan signal (Vout) output from the previous stage may be applied to the source terminal of the first switching element (T1).

In addition, in Figure 9, it is explained that the set part (QS) is composed of one switching element (T1), but it is not limited to this, and as shown in Figure 10, it is composed of two switching elements (T1a, T1b). And, the offset voltage (VD) or high potential voltage (VH) is applied to the connection terminals of the two switching elements (T1a, T1b) through the third clear switching element (T3c) of the Q clear unit (QC). It can be done as much as possible.

That is, the two switching elements (T1a, T1b) are connected in series between the EM signal (Vinp) supply terminal output from the front stage and the Q node, and the gate terminals of the two switching elements (T1a, T1b) are connected in common. The EM signal (Vinp) output from the front stage is applied, the EM signal (Vinp) output from the front stage is applied to the source terminal of the switching element (T1ab), and the two switching elements (T1a and T1b) The offset voltage (VD) or the high potential voltage (VH) is applied to the connection terminal of the Q clear unit (QC) through the third clear switching element (T3c).

In this configuration, the two switching elements (T1a, T1b) are turned on when the EM signal output from the front stage is high logic and charge the Q node with the EM signal output from the front stage, When the EM signal output from the front stage is low logic, it is turned off to block the connection between the Q node and the EM signal supply terminal output from the front stage.

When the two switching elements (T1a, T1b) are turned off by the low logic of the EM signal output from the front stage, the third clear switching element (T3c) of the Q clear unit (QC) is connected to the Q node. It is turned on by the high logic of . The turned-on third clear switching element (T3c) applies the offset voltage (VD) or the high potential voltage (VH) to the connection node of the two switching elements (T1a, T1b). Accordingly, the two switching elements T1a and T1b are completely turned off. Therefore, when the EM signal output from the front stage has low logic, leakage current of the Q node through the two switching elements T1a and T1b can be prevented.

Figure 11 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the fifth embodiment of the present invention.

The circuit configuration of each stage of the EM signal generation shift register for OLED according to the fifth embodiment of the present invention is the circuit configuration of each stage of the EM signal generation shift register for OLED according to the fourth embodiment of the present invention described in FIG. In , the tenth switching element (T8) is turned on by the high potential voltage (VH) and connects between the Q node and the gate terminal of the first pull-up switching element (T6c) of the EM signal output unit (IO). It is further provided with.

Figure 12 is a circuit diagram of each stage of the EM signal generation shift register for OLED according to the sixth embodiment of the present invention, and Figures 13a and 13b are diagrams of the EM signal generation shift register for OLED according to the sixth embodiment of the present invention. In the circuit configuration of each stage, this is a circuit diagram of another embodiment of the twelfth switching element (T10).

The circuit configuration of each stage of the EM signal generation shift register for OLED according to the sixth embodiment of the present invention is the circuit configuration of each stage of the EM signal generation shift register for OLED according to the fourth embodiment of the present invention described in FIG. In , the eleventh switching element (T9) is turned on or turned off according to the logic state of the scan signal output node (Qns) and connects the scan signal output node (Qns) and the EM signal output node (Qnc) when turned on. ) and a twelfth switching element (T10) that is turned on or turned off according to the logic state of the QB node and discharges the EM signal output node (Qnc) to a discharge voltage (Vssb) when turned on. .

And, the remaining configuration is the same as Figure 9.

Here, instead of the twelfth switching element T10, it may be configured as shown in FIGS. 13A and 13B.

That is, as shown in FIG. 13A, it is connected in series between the Q node or the EM signal output node (Qnc) and the supply terminal of the discharge voltage (VSSb), and is turned on or off depending on the logic state of the QB node. Logic states of the 13th and 14th switching elements (T10a, T10b) that supply the discharge voltage (VSSb) to the Q node when turned on, and the EM signal output node (Qnc) or the scan signal output node (Qns) It may be configured to include a 15th switching element (T10c) that is turned on or off and supplies the offset voltage (VD) to the connection node of the 13th and 14th switching elements (T10a, T10b) when turned on. there is.

If configured as shown in FIG. 13A instead of the twelfth switching device (T10), the thirteenth and fourteenth switching devices (T10a, T10b) are turned on when the QB node is in high logic to transmit the Q node or the EM signal. The output node (Qnc) is discharged to the discharging voltage (VSSb), and when the QB node is in low logic, it is turned off to block the connection between the Q node and the discharging voltage (VSSb).

When the 13th and 14th switching elements T10a and T10b are turned off by the low logic of the QB node, the 15th switching element T10c is turned on by the high logic of the Q node. The turned-on fifteenth switching device (T10c) connects the offset voltage (VD) to the connection node of the thirteenth and fourteenth switching devices (T10a and T10b), that is, the 13th node connected to the drain of the fourteenth switching device (T10b). An offset voltage (VD) is applied to the source of the switching element (T10a). Accordingly, the low logic of the QB node is applied to the gate terminal of the 13th switching device (T10a), and an offset voltage (VD) higher than the low logic is applied to the source terminal of the 13th switching device (T10a), causing the gate- As the source-to-source voltage (Vgs) has a negative value lower than the threshold voltage, it is completely turned off. In addition, even if the threshold voltage of the 13th switching device (T10a) moves to negative, the gate-source voltage (Vgs) is lower than the threshold voltage due to the offset voltage (VD) applied to the source, so the 13th switching device (T10a) ) is completely turned off. Accordingly, leakage current of the Q node or the EM signal output node (Qnc) through the 13th and 14th switching elements (T10a and T10b) can be prevented.

In addition, instead of the twelfth switching element (T10), as shown in FIG. 13b, it is connected in series between the Q node or the EM signal output node (Qnc) and the supply terminal of the discharge voltage (VSSb), and the QB node It further includes 13th and 14th switching elements (T10a, T10b) that are turned on or turned off according to the logic state and supply the discharging voltage (VSSb) to the Q node when turned on. The offset voltage (VD) or the high potential voltage (VH) is applied to the connection terminals of the switching elements (T10a, T10b) through the third clear switching element (T3c) of the Q clear unit (QC).

With this configuration, as described above, leakage current of the Q node or the EM signal output node (Qnc) through the 13th and 14th switching elements (T10a and T10b) can be prevented.

Meanwhile, in each embodiment of the present invention, instead of the first switching element (T1), the second switching element (T2), and the first and second pull-down switching elements (T7, T7c), it may be configured as follows. .

Figure 14 is a circuit configuration diagram of an embodiment other than the first switching element (T1) of the set portion (QS) in the circuit configuration of each stage of the EM signal generation shift register for OLED according to each embodiment of the present invention.

That is, instead of the first switching element T1 of each of the above embodiments, the start signal or the EM signal or the scan signal output from the front stage is connected in series between the end and the Q node to provide the start signal or the front stage. 16th and 17th switching elements that are turned on or turned off according to the logic state of the EM signal or scan signal output from and charge the start signal or the EM signal or scan signal output from the front stage to the Q node when turned on. (T1a, T1b), and is turned on or turned off according to the logic state of the Q node and supplies the offset voltage (VD) to the connection nodes of the 16th and 17th switching elements (T1a, T1b) when turned on. It is composed of an 18th switching element (T1c).

In each of the above embodiments, when the set unit (QS) is composed of one first switching element (T1) and the start signal or the EM signal or scan signal output from the previous stage is in a low state, during the set period If the first switching element (T1) is not completely turned off, the voltage of the Q node may leak, and the threshold voltage of the first switching element (T1) is deflected in the negative (-) direction, The leakage current may become more severe.

However, when configured as shown in FIG. 14, the 16th and 17th switching elements T1a and T1b are turned on when the start signal, or the EM signal or scan signal output from the previous stage is high logic, and the Q node The start signal, or the EM signal or scan signal output from the previous stage is charged, and when the start signal or the EM signal or scan signal output from the previous stage is low logic, it is turned off to connect the Q node and the start stage. Block the signal, or the connection to the EM signal or scan signal supply terminal output from the front stage.

When the 16th and 17th switching elements (T1a, T1b) are turned off by the start signal or the low logic of the EM signal or scan signal output from the previous stage, the 18th switching element (T1c) is turned off. It is turned on by the high logic of the Q node. sThe -on 18th switching element (T1c) applies the offset voltage (VD) or the high potential voltage (VH) to the connection node of the 16th and 17th switching elements (T1a and T1b). Accordingly, the sixteenth switching element T1a is completely turned off. Accordingly, when the start signal or the EM signal or scan signal output from the front stage has low logic, leakage current of the Q node through the 16th and 17th switching elements T1a and T1b can be prevented.

15A to 15B are circuit diagrams of embodiments other than the second switching element (T2) of the reset unit (QR) in the circuit configuration of each stage of the EM signal generating shift register for OLED according to each embodiment of the present invention. .

That is, as shown in FIG. 15A, instead of the second switching element (T2) in each embodiment, the Q node, the EM signal output node (Qnc), or the scan signal output node (Qns) and the discharge voltage (VSSc) is connected in series between stages and is turned on or turned off depending on the logic state of the reset signal (Vrst) or the EM signal or scan signal output from the next stage, and when turned on, the Q node and the EM signal output node (Qnc) or the 19th and 20th switching elements (T2a, T2b) that discharge the scan signal output node (Qns) to the discharge voltage (VSSc), and the Q node, the EM signal output node (Qnc), or A 21st node that is turned on or turned off according to the logic state of the scan signal output node (Qns) and supplies the offset voltage (VD) to the connection nodes of the 19th and 20th switching elements (T2a and T2b) when turned on. It is composed of a switching element (T2c).

In each of the above embodiments, when the reset unit (QR) is composed of one second switching element (T2) and the reset signal (Vrst) or the EM signal or scan signal output from the next stage is in a low state. , the second switching element (T2) is not completely turned off during the set period, so the voltage of the Q node, the EM signal output node (Qnc), or the scan signal output node (Qns) may leak, If the threshold voltage of the second switching element T2 is biased in the negative (-) direction, the leakage current may become worse.

However, when configured as shown in Figure 15a, the 19th and 20th switching elements (T2a, T2b) are turned on when the reset signal (Vrst) or the EM signal or scan signal output from the next stage is high logic. to discharge the Q node, the EM signal output node (Qnc), or the scan signal output node (Qns) to the discharge voltage (VSSc), and the reset signal or the EM signal or scan signal output from the next stage is When the logic is low, it is turned off to block the connection between the Q node, the EM signal output node (Qnc), or the scan signal output node (Qns) and the discharge voltage (VSSc) terminal.

When the 19th and 20th switching elements (T2a, T2b) are turned off by the reset signal or the low logic of the EM signal or scan signal output from the next stage, the 21st switching element (T2c) is turned off. It is turned on by the high logic of the Q node, the EM signal output node (Qnc), or the scan signal output node (Qns). The turned-on 21st switching element (T2c) applies the offset voltage (VD) or the high potential voltage (VH) to the connection node of the 19th and 20th switching elements (T2a and T2b). Accordingly, the 19th switching element T2a is completely turned off. Therefore, when the reset signal (Vrst) or the EM signal or scan signal output from the next stage has low logic, the Q node and the EM signal output through the 19th and 20th switching elements (T2a and T2b) Leakage current of the node Qnc or the scan signal output node Qns can be prevented.

Meanwhile, as shown in FIG. 15B, instead of the second switching element T2 in each embodiment, the Q node, the EM signal output node (Qnc), or the scan signal output node (Qns) and the discharge voltage (VSSc) is connected in series between stages and is turned on or turned off depending on the logic state of the reset signal (Vrst) or the EM signal or scan signal output from the next stage, and when turned on, the Q node and the EM signal output node (Qnc) or the scan signal output node (Qns) is provided with 19th and 20th switching elements (T2a, T2b) for discharging the discharge voltage (VSSc), and the 19th and 20th switching elements (T2a, T2b) ), the offset voltage (VD) or the high potential voltage (VH) is applied to the connection terminal of the Q clear unit (QC) through the third clear switching element (T3c) of the Q clear unit (QC).

Even with this configuration, when the reset signal (Vrst) or the EM signal or scan signal output from the next stage has low logic, the Q node through the 19th and 20th switching elements (T2a, T2b), Leakage current of the EM signal output node (Qnc) or the scan signal output node (Qns) can be prevented.

16 shows a pull-down switching element (T7) of the EM signal output unit (IO) or the scan signal output unit (SO) in the circuit configuration of each stage of the EM signal generation shift register for OLED according to each embodiment of the present invention. Or T7c) is a circuit diagram of another embodiment instead.

That is, as shown in FIG. 16, instead of the first or second pull-down switching element (T7 or T7c) of each of the above embodiments, the output terminal (Vinp) of the EM signal output unit (IO) or the scan signal output unit It is connected in series between the output terminal (Vout) of (SO) and the discharge voltage (VSSa or VSSb) terminal and is turned on or turned off depending on the logic state of the QB node, and when turned on, the output terminal of the EM signal output unit (IO) (Vinp) or the 22nd and 23rd switching elements (T11a, T11b) that discharge the output terminal (Vout) of the scan signal output unit (SO) to the discharge voltage (VSSa or VSSb), the Q node, and the EM The signal output node (Qnc) or the scan signal output node (Qns) is turned on or off according to the logic state, and when turned on, the offset voltage (VD) is applied to the 22nd and 23rd switching elements (T11a, T11b). It is comprised of a 24th switching element (T11c) that supplies power to the connection node.

In each of the above embodiments, the EM signal output unit (IO) or the scan signal output unit (SO) consists of one pull-down switching element (T7 or T7c), and when the QB node is in a low state, the pull down Since the down switching element (T7 or T7c2) is not completely turned off, the voltage at the output terminal (Vinp) of the EM signal output unit (IO) or the output terminal (Vout) of the scan signal output unit (SO) may leak. , if the threshold voltage of the pull-down switching element (T7 or T7c) is biased in the negative (-) direction, the leakage current may become worse.

However, when configured as shown in FIG. 16, the 22nd and 23rd switching elements (T11a, T11b) are turned on when the QB node is in high logic, and the Q node, the EM signal output node (Qnc), or the scan The signal output node (Qns) is discharged to the discharge voltage (VSSa or VSSb), and when the QB node is low logic, it is turned off and the Q node, the EM signal output node (Qnc), or the scan signal output node (Qns) and the discharge voltage (VSSa or VSSb) terminal are disconnected.

When the 22nd and 23rd switching devices (T11a, T11b) are turned off by the low logic of the QB node, the 24th switching device (T11c) is connected to the Q node, the EM signal output node (Qnc), or It is turned on by the high logic of the scan signal output node (Qns). The turned-on 24th switching device (T11c) applies the offset voltage (VD) or the high potential voltage (VH) to the connection node of the 22nd and 23rd switching devices (T11a and T11b).

Accordingly, the 22nd switching element T11a is completely turned off. Therefore, when the QB node has low logic, the output terminal (Vinp) of the EM signal output unit (IO) or the output terminal of the scan signal output unit (SO) through the 22nd and 23rd switching elements (T11a, T11b) Leakage current of (Vout) can be prevented.

Additionally, the inverter (IN) described above is described as follows.

Generally, the inverter receives the voltage of the Q node, inverts it, and outputs the inverted voltage to the QB node. Accordingly, when the Q node is high, the QB node becomes low, and the low value of the inverter output has a low potential voltage (VL). Additionally, when the Q node is low, the QB node becomes high, and the high value of the inverter output has a high potential voltage (VH).

However, the input terminal of the inverter IN may not be connected to the Q node, but may be connected to a signal Qeq having an equivalent logic value. The signal (Qeq) includes a section in which the output (Vinp) of the EM signal output unit (IO) or the output (Vout) of the scan signal output unit (SO) is high among the sections in which the Q node is high. Any signal that is high during the period is sufficient. Additionally, the signal Qeq may have a low voltage or a partially high voltage during a period when the Q node is low.

The inverter (IN) may be configured in various forms.

17(a) to 17(d) are inverter circuit configuration diagrams of various embodiments according to the present invention.

As shown in Figure 17a, the configuration of the inverter includes first and second inverter switching elements (Ia, Ib) connected in series between a high potential voltage (VH) end and a low potential voltage (VL) end, and The high potential voltage (VH) is applied to the gate terminal and source terminal of the first inverter switching device (Ia), and the gate terminal of the second inverter switching device (Ib) is applied to the voltage of the Q node or another input signal (Qeq). ) is applied, and the connection loads of the first and second inverter switching elements (Ia, Ib) are connected to the QB node.

In addition, the configuration of the inverter includes first and second inverter switching elements (Ia, Ib) connected in series between the high potential voltage (VH) end and the low potential voltage (VL) end, as shown in FIG. 17b. A control signal (control) is input to the gate terminal of the first inverter switching device (Ia), the high potential voltage (VH) is applied to the source terminal of the first inverter switching device (Ia), and the second The Q node or another input signal Qeq is applied to the gate terminal of the inverter switching device Ib, and the connecting rods of the first and second inverter switching devices Ia and Ib are connected to the QB node.

In addition, the configuration of the inverter includes first and second inverter switching elements (Ia, Ib) connected in series between the high-potential voltage (VH) terminal and the low-potential voltage (VL) terminal, as shown in FIG. 17C, Third and fourth inverter switching elements (Ic, Is) are connected in series between the high potential voltage (VH) end and the low potential voltage (VL) end. The first and second inverter switching elements (Ia, Ib) and the third and fourth inverter switching elements (Ic, Is) are connected in parallel with each other.

A control signal (control) is input to the gate terminal of the first inverter switching device (Ia), the high potential voltage (VH) is applied to the source terminal of the first inverter switching device (Ia), and the second inverter switching The voltage of the Q node or another input signal (Qeq) is applied to the gate terminal of the element (Ib), and the connection load (A node) of the first and second inverter switching elements (Ia, Ib) is connected to the third inverter. It is connected to the gate terminal of the switching element (Ic). The voltage of the Q node or another input signal (Qeq) is applied to the gate terminal of the fourth inverter switching device (Id), and the connecting load (A node) of the third and fourth inverter switching devices (Ic, Id) is connected to the QB node.

In addition, the configuration of the inverter includes first and second inverter switching elements (Ia, Ib) connected in series between the high potential voltage (VH) end and the low potential voltage (VL) end, as shown in FIG. 17D, Third and fourth inverter switching elements (Ic, Is) are connected in series between the high potential voltage (VH) end and the low potential voltage (VL) end. The first and second inverter switching elements (Ia, Ib) and the third and fourth inverter switching elements (Ic, Is) are connected in parallel with each other.

The high potential voltage (VH) is applied to the gate terminal and source terminal of the first inverter switching device (Ia), and the gate terminal of the second inverter switching device (Ib) is applied to the voltage of the Q node or another input signal ( Qeq) is applied, and the connection load (A node) of the first and second inverter switching elements (Ia and Ib) is connected to the gate terminal of the third inverter switching element (Ic). The voltage of the Q node or another input signal (Qeq) is applied to the gate terminal of the fourth inverter switching device (Id), and the connecting load (A node) of the third and fourth inverter switching devices (Ic, Id) is connected to the QB node.

Meanwhile, in each embodiment of the present invention, switching elements such as those shown in FIGS. 18A and 18B can be further added to the inverter.

Figures 18(a) and 18(b) are diagrams showing the configuration of a switching element circuit that can be added to an inverter according to an embodiment of the present invention.

As shown in FIG. 18A, a switching element (Tb) can be added that is turned on or off according to the EM signal or scan signal of the front stage and discharges the QB node to a low potential voltage (VL) when turned on. .

In addition, as shown in Figure 18b, a switching element (Tb) is turned on or turned off according to the EM signal or scan signal of the next stage and charges the QB node with the high potential voltage (VH) when turned on. You can add

FIG. 19 shows the results of simulating the driving waveforms of each stage of the EM signal generation shift register in which the reset unit (QR) is configured as shown in FIG. 15b in the EM signal generation shift register according to the fourth embodiment of the present invention described in FIG. 9. This is a waveform diagram showing .

In other words, this is a simulation result when the threshold voltage (Vth) of the switching element is -2V.

Using the EM clock pulses and scan clock pulses shown in FIG. 3, the EM signal (Vinp, CLKi1) output from the previous stage is applied to the set unit (QS), and the reset unit (QR) The EM signal (Vinp, CLKi5) output from the next stage was applied.

As can be seen in Figure 19, the EM signal (Vinp(2)) and the scan signal (Vout(2)) are output while the Q node is high, and there is no leakage current in the Q node during the period when the Q node is floating. can confirm.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is commonly known in the technical field to which the present invention pertains that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of.

QS: Set section QR: Reset section
QC: Q clear section IN: Inverter section
IO: EM signal output SO: Scan signal output

Claims (16)

In a shift register with a plurality of stages, each stage is:
a set unit that charges the start signal, the EM signal or scan signal output from the previous stage, or the first high potential voltage to the Q node according to the start signal, or the EM signal or scan signal output from the previous stage;
a reset unit discharging the Q node with a first discharge voltage according to a reset signal or an EM signal or scan signal output from a rear stage;
a Q clear unit that clears the Q node with a second discharge voltage according to the logic state of the QB node;
an inverter unit that inverts the voltage of the Q node and outputs it to the QB node;
an EM signal output unit that receives one EM clock pulse among a plurality of EM clock pulses and outputs the EM clock pulse as an EM signal according to the logic states of the Q node and the QB node; and
An OLED device comprising a scan signal output unit that receives one scan clock pulse among a plurality of scan clock pulses and outputs the scan clock pulse as a scan signal according to the logic states of the Q node and the QB node. EM signal generation shift register. According to claim 1,
An EM signal generating shift register for an OLED further comprising a switching element that discharges the QB node to a second discharge voltage according to the start signal or the EM signal or scan signal output from the front stage. According to claim 1,
The Q node includes the EM signal output node and the scan signal output node,
An EM signal for OLED further comprising a switching element formed between the EM signal output node and the scan signal output node and switching between the EM signal output node and the scan signal output node according to an external control signal or high potential voltage. Occurrence shift register. According to claim 1,
The Q node includes the EM signal output node and the scan signal output node,
A first switching element formed between the EM signal output node and the scan signal output node and switching between the EM signal output node and the scan signal output node according to a signal from the scan signal output node, and logic of the QB node An EM signal generation shift register for OLED further comprising a second switching element that discharges the EM signal output node to the second discharge voltage depending on the state. According to claim 4,
Instead of the second switching element,
It is connected in series between the EM signal output node and a second discharge voltage supply terminal that supplies the second discharge voltage, and discharges the EM signal output node to the second discharge voltage according to the logic state of the QB node. An EM signal for OLED comprising third and fourth switching elements that supply an offset voltage to the connection node of the third and fourth switching elements according to the logic state of the EM signal output node. Occurrence shift register. According to claim 1,
The Q clear unit is connected in series between the Q node and a second discharge power supply terminal that supplies the second discharge voltage, and controls the Q node to the second discharge voltage according to the logic state of the QB node. First and second clear switching elements that discharge,
An EM signal generating shift register for OLED comprising a third clear switching element that supplies an offset voltage or a second high potential voltage to the connection node of the first and second clear switching elements according to the logic state of the Q node. According to claim 6,
The Q node includes the EM signal output node and the scan signal output node,
a first switching element formed between the EM signal output node and the scan signal output node and switching between the EM signal output node and the scan signal output node according to a signal from the scan signal output node;
Third and fourth switching elements connected in series between the EM signal output node and the second discharge voltage supply terminal and discharging the EM signal output node to the second discharge voltage according to the logic state of the QB node A shift register for generating an EM signal for an OLED, wherein the offset voltage or the second high potential voltage is applied to the connection node of the third and fourth switching elements through the third clear switching element of the Q clear unit. According to claim 6,
The set unit is connected in series between the EM signal supply terminal output from the front stage and the Q node, and includes two switching elements for applying the EM signal output from the front stage to the Q node according to the EM signal output from the front stage. An EM signal generating shift register for OLED, wherein the offset voltage or the second high potential voltage is applied to the connection terminals of the two switching elements through the third clear switching element of the Q clear unit. According to claim 6,
The reset unit is connected in series between the Q node and the first discharge voltage terminal to set the Q node to the first discharge voltage according to the logic state of the reset signal or the EM signal or scan signal output from the rear stage. An EM signal generating shift register for OLED, comprising two switching elements for discharging, and applying an offset voltage or a high potential voltage to the connection rods of the two switching elements through the third clear switching element of the Q clear unit. According to claim 1,
The set unit is a sixth unit that charges the start signal, the EM signal or scan signal output from the previous stage, or the first high potential voltage to the Q node according to the start signal or the EM signal or scan signal output from the previous stage. It is composed of a switching element, or
The start signal, or the EM signal or scan signal output from the front stage is connected in series between the supply terminal and the Q node, and the start signal, or the start signal according to the logic state of the EM signal or scan signal output from the front stage, or Seventh and eighth switching elements for charging the Q node with an EM signal or a scan signal or a first high potential voltage output from the front stage, and an offset voltage or a second high power voltage according to the logic state of the Q node An EM signal generating shift register for OLED comprising a 9th switching element that supplies a connection node of the 7th and 8th switching elements. According to claim 1,
The reset unit is configured to include a tenth switching element that discharges the Q node with the first discharge voltage according to the reset signal or an EM signal or scan signal output from a rear stage, or
A second terminal connected in series between the Q node and the first discharge voltage terminal to discharge the Q node to the first discharge voltage according to the logic state of the reset signal or the EM signal or scan signal output from the rear stage. An OLED display comprising 11th and 12th switching elements and a 13th switching element that supplies an offset voltage or a second high potential voltage to the connection node of the 11th and 12th switching elements according to the logic state of the Q node. EM signal generation shift register. According to claim 1,
The EM signal output unit,
a first pull-up switching element that receives one EM clock pulse (CLKi) among the plurality of EM clock pulses and outputs the EM clock pulse to an output terminal according to the logic state of the Q node;
An EM signal generating shift register for OLED comprising a first pull-down switching element that discharges the output terminal with the second discharge voltage (Vssb) according to the logic state of the QB node. According to claim 1,
The scan signal output unit,
a second pull-up switching element that receives one scan clock pulse among the plurality of scan clock pulses and outputs the scan clock pulse to an output terminal according to the logic state of the Q node;
An EM signal generating shift register for OLED comprising a second pull-down switching element that discharges the output terminal with a third discharge voltage according to the logic state of the QB node. The method of claim 12 or 13,
Instead of the first or second pull-down switching element, it is connected in series between the output terminal of the EM signal output unit or the output terminal of the scan signal output unit and the second or third discharge voltage terminal according to the logic state of the QB node. Logic of the 14th and 15th switching elements for discharging the output terminal of the EM signal output unit or the output terminal of the scan signal output unit to the second or third discharge voltage, and the Q node, EM signal output node, or scan signal output node An EM signal generating shift register for OLED comprising a 16th switching element that supplies an offset voltage or a high potential voltage to the connection nodes of the 14th and 15th switching elements depending on the state. A plurality of scan lines, a plurality of data lines, and a plurality of light emission control lines are arranged to form a plurality of subpixels, and each subpixel includes an OLED element and a pixel circuit that independently drives the OLED element, and the pixel circuit A switching transistor that switches the data voltage supplied through each data line to charge the storage capacitor with a voltage corresponding to the data voltage, and a driving device that controls the current according to the voltage charged in the storage capacitor and supplies it to the OLED element. An OLED display panel including a transistor and an emission control transistor that controls the emission period of the OLED device by switching a current flowing to the OLED device through the driving transistor;
A scan signal for sequentially driving the plurality of gate lines is output from the first output switching device using scan clock pulses, and at the same time, using EM clock pulses of a different type from the scan clock pulses, the a shift register that outputs an EM signal from a second output switching device that is different from the first output switching device; and
An OLED display device including an emission control driver that inputs the EM signal output from the shift register and outputs an EM control signal that drives the emission control transistor of the OLED display panel. According to clause 15,
The shift register has a plurality of stages, and each stage has:
a set unit that charges the start signal, the EM signal or scan signal output from the previous stage, or the first high potential voltage to the Q node according to the start signal, or the EM signal or scan signal output from the previous stage;
a reset unit discharging the Q node with a first discharge voltage according to a reset signal or an EM signal or scan signal output from a rear stage;
a Q clear unit that clears the Q node with a second discharge voltage according to the logic state of the QB node;
an inverter unit that inverts the voltage of the Q node and outputs it to the QB node;
an EM signal output unit that receives one EM clock pulse among a plurality of EM clock pulses and outputs the EM clock pulse as an EM signal to the emission control driver according to the logic states of the Q node and the QB node; and
A scan that receives one scan clock pulse among a plurality of scan clock pulses and outputs the scan clock pulse as a scan signal to the corresponding scan line of the OLED display panel according to the logic states of the Q node and the QB node. An OLED display device comprised of a signal output unit.