KR101366877B1 - Display Device - Google Patents

Abstract

An embodiment of the present invention is a display panel comprising: a display panel; And a shift register coupled to the display panel, the level shifter outputting clock signals, and a shift register configured to shift gate output pulses in response to the clock signals, wherein the nth stage of the stages corresponds to the potential of the Q node. A pull-up transistor section including a first pull-up transistor for outputting the X-th clock signal to the output terminal of the n-th stage, and a first pull-down transistor for outputting the first low potential voltage to the output terminal of the n-th stage in response to the potential of the QB node. A pull-down transistor unit comprising: a Q node charge and discharge unit for charging and discharging a Q node; a QB node charge and discharge unit for charging a QB node and discharging it to a second low potential voltage lower than the first low potential voltage; and an X clock signal In response to the above, there is provided a display device including a first transistor for switching a current path between a Q node and an output terminal of an nth stage.

Description

[0001]

An embodiment of the present invention relates to a display device.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as organic light emitting display (OLED), liquid crystal display (LCD), plasma display panel (PDP), and the like is increasing.

Some of the aforementioned display devices, for example, a liquid crystal display or an organic light emitting display device, include a display panel including a plurality of subpixels arranged in a matrix form and a driving unit for driving the display panel. The driver includes a gate driver for supplying a gate signal (or scan signal) to the display panel and a data driver for supplying a data signal to the display panel.

In the above display device, when a gate signal and a data signal are supplied to subpixels arranged in a matrix form, the selected subpixel emits light, thereby displaying an image.

The gate driver outputting the gate signal is classified into an external circuit mounted on an external substrate of the display panel in the form of an integrated circuit and an embedded type directly formed on the display panel in the form of a gate in panel formed with a thin film transistor process.

Since the gate driver is composed of a plurality of thin film transistors (hereinafter, TFTs), the performance depends on the characteristics of the TFTs. TFTs used in the gate driver include an enhancement mode in which the threshold voltage is located in the positive (+) direction and a depletion mode in which the threshold voltage is located in the negative (-) direction.

In the case of the depletion mode TFT, the threshold voltage is shifted in the negative (-) direction, so that the current blocking function (turn off function) is not properly performed at Vgs = 0V. Therefore, current leakage occurs in the turned off pull-down transistor, and as a result, the gate signal is not normally output.

Therefore, when the gate driver is formed in a built-in type, there is a need for a method of avoiding malfunction of the circuit and improving operation characteristics even when using the depletion mode TFT as well as the enhancement mode TFT.

Embodiments of the present invention for solving the above-described problems of the related art include a gate driver capable of improving output characteristics by improving turn-on / off operation characteristics of a depletion mode TFT as well as an enhancement mode TFT. It is to provide a display device.

According to an embodiment of the present invention, there is provided a display panel comprising: a display panel; And a shift register coupled to the display panel, the level shifter outputting clock signals, and a shift register configured to shift gate output pulses in response to the clock signals, wherein the nth stage of the stages corresponds to the potential of the Q node. A pull-up transistor section including a first pull-up transistor for outputting the X-th clock signal to the output terminal of the n-th stage, and a first pull-down transistor for outputting the first low potential voltage to the output terminal of the n-th stage in response to the potential of the QB node. A pull-down transistor unit comprising: a Q node charge and discharge unit for charging and discharging a Q node; a QB node charge and discharge unit for charging a QB node and discharging it to a second low potential voltage lower than the first low potential voltage; and an X clock signal. In response to the above, there is provided a display device including a first transistor for switching a current path between a Q node and an output terminal of an nth stage.

The Q node charging and discharging unit charges the Q node to the output terminal voltage of the n-1 stage in response to the X-1 clock signal, and then applies the Q node to the output terminal voltage of the n-1 stage in response to the X-1 clock signal. The QB node charging and discharging unit discharges the QB node to a second low potential voltage lower than the first low potential voltage in response to the potential of the Q node, and then discharges the QB node high potential in response to the potential and high potential voltage of the Q node. Can be charged to a voltage.

The pull-up transistor unit includes a second pull-up transistor that outputs the X clock signal to the second output terminal of the n-th stage in response to the potential of the Q node, and the pull-down transistor unit supplies the second low potential voltage in response to the potential of the QB node. and a second pull-down transistor output to the second output terminal of the n-stage, and the first transistor may maintain the potential of the Q node at the potential of the second output terminal of the n-th stage in response to the X clock signal.

The QB node charging and discharging unit includes a third transistor having a gate electrode and a first electrode connected to a high potential voltage terminal, a gate electrode connected to a Q node, and a first electrode connected to a second electrode and a QB node of a second transistor. Or a third transistor having a second electrode connected to the second low potential voltage terminal.

The QB node charging and discharging unit has a 2-1 transistor connected to a gate electrode and a first electrode at a high potential voltage terminal, a gate electrode connected to a second electrode of a 2-1 transistor, and a first electrode connected to a high potential voltage terminal. A 2-1 transistor, a 3-1 transistor having a gate electrode connected to the Q node, a first electrode connected to the second electrode of the 2-1 transistor, and a second electrode connected to the first low potential voltage terminal; The gate electrode may be connected to the Q node, the second electrode of the second-2 transistor, and the first electrode connected to the QB node, and the third second transistor connected to the second low potential voltage terminal.

The nth stage may include a fourth transistor configured to discharge the Q node to the first low potential voltage in response to the voltage of the second output terminal of the n + 1th stage.

Q-node charging and discharging unit has a gate electrode connected to the X-1 clock signal terminal or the second output terminal of the n-1 stage, and a first electrode connected to the first output terminal or high potential voltage terminal of the n-1 stage, and Q It may include a fifth transistor having a second electrode connected to the node and the first electrode of the fourth transistor.

The Q-node charge / discharge unit includes a 5-1 transistor having a gate electrode connected to the X-1 clock signal terminal and a first electrode connected to the first output terminal of the n-1 stage, and a gate electrode connected to the X-1 clock signal terminal. The second electrode connected to the second electrode of the fifth transistor and the second electrode connected to the Q node, the gate electrode connected to the X clock signal terminal, and the first electrode of the nth stage. The first electrode may be connected to the second output terminal, and may include a fifth-3 transistor having a second electrode connected to the first electrode of the 5-2 transistor.

The Q-node charge / discharge unit includes a fifth gate electrode connected to the X-1 clock signal terminal or the second output terminal of the n-1 stage, and a first electrode connected to the first output terminal or high potential voltage terminal of the n-1 stage. A -1 transistor, a gate electrode connected to the X-1 clock signal terminal or the second output terminal of the n-1 stage, a first electrode connected to the second electrode of the 5-1 transistor, and a second electrode connected to the Q node. The connected 5-2 transistor, a gate electrode connected to the X clock signal terminal, a first electrode connected to the second output terminal of the nth stage, and a second electrode connected to the first electrode of the 5-2 transistor. It may include a 5-3 transistor.

The logic low voltage of the clock signals may have a voltage between the first low potential voltage and the second low potential voltage.

The pull-up transistor includes a first pull-up transistor having a gate electrode connected to a Q node, a first electrode connected to a X clock signal terminal, a second electrode connected to a first output terminal of an nth stage, and a gate electrode connected to a Q node. And a second pull-up transistor having a first electrode connected to the X-clock signal terminal and a second electrode connected to a second output terminal of the n-th stage, wherein the pull-down transistor unit has a gate electrode connected to the QB node and a first stage of the n-th stage. A first pull-down transistor having a first electrode connected to the output terminal, a second electrode connected to the first low potential voltage terminal, a gate electrode connected to the QB node, and a first electrode connected to the second output terminal of the nth stage; And a second pull-down transistor having a second electrode connected to the low potential voltage terminal.

According to the embodiment of the present invention, even when the depletion mode TFT as well as the enhancement mode TFT is applied, the voltage Vgs between the gate sources of the TFTs is made negative and the turn-on / off operation characteristics of the TFTs are improved to improve output characteristics. There is an effect of providing a display device including a gate driver that can be improved.

1 is a schematic block diagram of a display device;
2 and 3 are diagrams illustrating stages constituting a shift register.
4 is a diagram showing a threshold voltage according to a mode of a TFT constituting a shift register.
5 is a circuit diagram of an n-th stage according to the first embodiment of the present invention;
6 is an input / output signal waveform diagram of an nth stage.
7 is a simulation waveform diagram for a Q node, a QB node, and a first output stage.
8 is a circuit diagram of a modified n-th stage.
9 is a circuit diagram of an nth stage according to a second embodiment of the present invention;
10 is a circuit diagram of an n-th stage according to the third embodiment;
Fig. 11 is a circuit diagram of an nth stage according to the fourth embodiment.
12 is a circuit diagram illustrating a QB node charge and discharge unit according to a modified example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a display device, FIGS. 2 and 3 are diagrams illustrating stages constituting a shift register, and FIG. 4 is a diagram illustrating a threshold voltage according to a mode of a TFT constituting a shift register.

As shown in FIG. 1, the display device includes a display panel 10, a timing controller 11, a data driver 12, and gate drivers 13 and 14.

The display panel 10 includes subpixels separated from and connected to the data lines DL and the gate lines GL. The display panel 10 includes a display area 10A in which subpixels are formed, and a non-display area 10B in which various signal lines or pads are formed outside the display area 10A. The display panel 10 may be implemented by any one of a liquid crystal display (LCD), an organic light emitting display (OLED), and an electrophoretic display (EPD).

The timing controller 11 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock DCLK through an LVDS or TMDS interface receiving circuit connected to an image board. Receive a timing signal. The timing controller 11 generates timing control signals for controlling the operation timing of the data driver 12 and the gate drivers 13 and 14 based on the input timing signal.

The data driver 12 includes a plurality of source drive integrated circuits (ICs). The source drive ICs receive the digital video data RGB and the source timing control signal DDC from the timing controller 11. The source drive ICs convert the digital video data RGB into a gamma compensation voltage in response to the source timing control signal DDC to generate a data voltage, and transmit the data voltage to the data lines DL of the display panel 10. Supply. The source drive ICs are connected to the data lines DL of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate drivers 13 and 14 include a level shifter 13 and a shift register 14. The gate drivers 13 and 14 are formed by a gate in panel (GIP) method or an IC method in which the level shifter 13 and the shift register 14 are divided. In the following embodiment, the GIP method in which the shift register 14 is formed in the non-display area 10B is taken as an example.

The level shifter 13 receives the clock signals CLK input from the timing controller 11 to the TTL (Transistor-Transistor-Logic) level of 0V to 3.3V, and has a gate high level Vgh and a first gate low level Vgl1. After level shifting to < RTI ID = 0.0 > In addition, the level shifter 13 shifts the clock signals CLK to the gate high level Vgh and the first and second gate low levels Vgl1 and Vgl2, and then supplies them to the shift register 14. Here, the first gate low level Vgl1 and the second gate low level Vgl2 have a relationship of Vgl1> Vgl2.

The shift register 14 is formed of a plurality of thin film transistors (hereinafter TFTs) by the GIP method. The shift register 14 is composed of stages for shifting the gate output pulse in response to the clock signals CLK. Stages included in the shift register 14 sequentially output gate signals through the output stages.

The shift register 14 of the embodiment has the output stages Vg [n-2] to Vg [n + 2] of the respective stages ST [n-2] to ST [n + 2] as shown in FIG. ) Is cascaded to the stages in the next stage. In addition, the shift register 14 of the embodiment has the first output terminals Vg [n-2] to Vg [of the respective stages ST [n-2] to ST [n + 2], as shown in FIG. n + 2]) is connected to the stages located in the next stage, and the second output terminals Vc [n-2] to Vc [of the respective stages ST [n-2] to ST [n + 2]. n + 2]) is cascaded to the stages located at the front end.

On the other hand, the TFTs constituting the shift register 14 are located in the enhancement mode E and the negative direction where the threshold voltage is located in the positive (+) direction as shown in FIG. 4. There is a depletion mode (D).

Unlike the enhancement mode TFT, in the depletion mode TFT, the threshold voltage is located in the negative (-) direction. Therefore, if the voltage condition between gate sources is not satisfied (the current is not small enough at Vgs = 0V), the turn off function will not be performed properly.

Therefore, the embodiment is based on the gate drivers 13 and 14 of the GIP method (embedded type) which can avoid malfunction of the circuit and improve the operation characteristics even when using the depletion mode TFT as well as the enhancement mode TFT. A display device is provided, which will be described below.

≪ Embodiment 1 >

5 is a circuit diagram of an nth stage according to a first embodiment of the present invention, FIG. 6 is an input / output signal waveform diagram of an nth stage, and FIG. 7 is a simulation waveform of a Q node, a QB node, and a first output terminal. 8 is a circuit diagram of the modified n-th stage.

As shown in FIG. 5, the n-th stage according to the first embodiment of the present invention includes a Q node charging and discharging unit T5 and a QB node charging and discharging unit T2-1, T2-2, T3-1, and T3-2. , Pull-up transistor units TPU1 and TPU2, pull-down transistor units TPD1 and TPD2, and first transistor T1.

Q node charge / discharge unit T5, QB node charge / discharge unit T2-1, T2-2, T3-1, T3-2, pull-up transistor units TPU1, TPU2, pull-down transistor units TPD1, TPD2, and first The transistor T1 is composed of enhancement mode or depletion mode TFTs. The enhancement mode and depletion mode TFTs have a gate, a source and a drain electrode. In the first embodiment, since the TFTs are n-type, the drain / source electrode is referred to as a first electrode / second electrode.

The Q-node charge / discharge unit T5 has a gate electrode connected to the X-1 clock signal terminal CLK [X-1] and a first electrode connected to the first output terminal Vg [n-1] of the n-1 stage. The fifth transistor T5 is connected to the Q node Q and is connected to the second electrode.

The fifth transistor T5 charges the Q node Q to the first output terminal voltage of the n-th stage in response to the X-1 clock signal, and then n-th stage in response to the X-1 clock signal. The Q node Q is discharged at the output terminal voltage of. The first electrode of the fifth transistor T5 constituting the Q-node charge / discharge unit T5 is connected to the first output terminal Vg [n-1] of the n-th stage. Therefore, the Q node Q is charged when the output voltage of the front end becomes logic high, but the output voltage of the front end becomes logic low, thereby maintaining the discharge state. That is, the Q node charging and discharging unit T5 is turned on in response to the X-1 clock signal and maintains a discharge state after charging the Q node Q according to the voltage of the first output terminal of the n-1 stage.

The QB node charging and discharging units T2-1, T2-2, T3-1, and T3-2 have the second low potential voltage lower than the first low potential voltage of the QB node QB in response to the potential of the Q node Q. After discharge, the QB node QB is charged to a high potential voltage in response to the potential and high potential voltage of the Q node Q. To this end, the QB node charging and discharging units T2-1, T2-2, T3-1, and T3-2 are the 2-1 transistors T2-1, the 2-2 transistors, and the 3-3 transistors. It consists of one transistor T3-1 and a third-2 transistor T3-2.

In the 2-1 transistor T2-1, the gate electrode and the first electrode are connected to the high potential voltage terminal VDD. In the second-2 transistor T2-2, a gate electrode is connected to the second electrode of the 2-1 transistor T2-1, and a first electrode is connected to the high potential voltage terminal VDD. In the 3-1 transistor T3-1, a gate electrode is connected to the Q node Q, and a first electrode is connected to the second electrode of the 2-1 transistor T2-1, and the first low potential voltage terminal ( The second electrode is connected to VGL1). A gate electrode is connected to the Q node Q and a first electrode is connected to the second electrode and the QB node QB of the second-2 transistor T2-2. The second electrode is connected to the second low potential voltage terminal VGL2.

Since the gate electrode is connected to the high potential voltage terminal VDD, the 2-1 transistor T2-1 maintains a turn-on state at all times. On the other hand, in the 2-2 transistor T2-2, the gate electrode is connected to the first electrode of the 2-1 transistor T2-1, so whether the 2-1 transistor T2-1 is turned on or off. Will be turned on. Therefore, the QB node QB is charged when the 2-1 and 2-2 transistors T2-1 and T2-2 are turned on.

Since the gate electrode is connected to the Q node Q, the 3-1 transistor T3-1 is turned on when the potential of the Q node Q is logic high, and is turned on when the potential of the Q node Q is logic low. Is off. Therefore, when the 3-1 transistor T3-1 is turned on, the 2-2 transistor T2-2 is turned off by the first low potential voltage. Since the gate electrode is connected to the Q node Q, the third node T3-2 is turned on when the potential of the Q node Q is logic high, and is turned on when the potential of the Q node Q is logic low. Is off. Accordingly, the QB node QB is discharged by the second low potential voltage when the third-2 transistor T3-2 is turned on.

The pull-up transistor units TPU1 and TPU2 include a first pull-up transistor TPU1 and a second pull-up transistor TPU2. In the first pull-up transistor TPU1, a gate electrode is connected to the Q node Q, a first electrode is connected to the X clock signal terminal CLK [X], and a second electrode is connected to the first output terminal Vg [n]. This is connected. In the second pull-up transistor TPU2, a gate electrode is connected to the Q node Q, a first electrode is connected to the X clock signal terminal CLK [X], and a second electrode is connected to the second output terminal Vc [n]. This is connected.

The first pull-up transistor TPU1 outputs the X-th clock signal to the first output terminal Vg [n] of the nth stage in response to the potential of the Q node Q. On the other hand, the second pull-up transistor TPU2 outputs the X clock signal to the second output terminal Vc [n] of the nth stage in response to the potential of the Q node Q.

The pull-down transistor units TPD1 and TPD2 include a first pull-down transistor TPD1 and a second pull-down transistor TPD2. In the first pull-down transistor TPD1, a gate electrode is connected to the QB node QB, a first electrode is connected to the first output terminal Vg [n], and a second electrode is connected to the first low potential voltage terminal VGL1. do. In the second pull-down transistor TPD2, a gate electrode is connected to the QB node QB, a first electrode is connected to the second output terminal Vc [n], and a second electrode is connected to the second low potential voltage terminal VGL2. do.

The first pull-down transistor TPD1 outputs the first low potential voltage to the first output terminal Vg [n] of the nth stage in response to the potential of the QB node QB. On the other hand, the second pull-down transistor TPD2 outputs the second low potential voltage to the second output terminal Vc [n] of the nth stage in response to the potential of the QB node QB.

In the first transistor T1, a gate electrode is connected to the X clock signal terminal CLK [X], a first electrode is connected to the Q node Q, and a second electrode is connected to the second output terminal Vc [n]. Connected. The first transistor T1 switches the current path between the Q node Q and the second output terminal Vc [n] of the nth stage in response to the X clock signal. When the X-th clock signal is supplied, the first transistor T1 maintains the Q node Q at a voltage of the second output terminal Vc [n] of the nth stage, that is, a discharge state (logic low state). That is, the first transistor T1 serves to prevent the pull-up transistor units TPU1 and TPU2 from turning on in the discharge state of the Q node Q.

As shown in FIG. 6, the X-th clock signal terminal CLK [X] of the n-th stage may receive one of the first to fourth clock signals CLK1 to CLK4. In the figure, the shift register receives four phase clock signals as an example. However, the shift register of the first embodiment can also be driven by clock signals of two or more phases. In the drawing, the shift register is supplied with four phase clock signals that are not overlapped. However, the shift register of the first embodiment can be driven by two or more overlapping clock signals. In addition, the logic low voltages of the first to fourth clock signals CLK1 to CLK4 may correspond to the first low potential voltage corresponding to the first gate low level Vgl1 to the second gate low level Vgl2. Has a voltage between the low potential voltage. For example, the logic low voltages of the first to fourth clock signals CLK1 to CLK4 have a voltage equal to or similar to the second low potential voltage depending on the circuit configuration.

On the other hand, when the Q node Q is charged by the Q node charge / discharge unit T5, the QB node QB is charged by the QB node charge / discharge units T2-1, T2-2, T3-1, and T3-2. It becomes a discharge state. As a result, since the Q node Q and the QB (QB) node alternately charge and discharge, the output terminal of the nth stage outputs a gate signal as follows.

First, when the Q node Q is charged, the pull-up transistor units TPU1 and TPU2 are turned on. Accordingly, the first output terminal Vg [n] of the nth stage outputs the gate signal switched from the first gate low level Vgl1 to the gate high level Vgh. On the other hand, the second output terminal Vc [n] of the nth stage outputs the gate signal switched from the second gate low level Vgl2 to the gate high level Vgh.

As described above, after the first and second output terminals Vg [n] and Vc [n] of the nth stage are output during the charging period of the Q node Q, the Q node Q is discharged and pulled up. The transistor units TPU1 and TPU2 are kept turned off.

Next, when the QB node QB is in a charged state, the pull-down transistor units TPD1 and TPD2 are turned on. Accordingly, the first output terminal Vg [n] of the nth stage outputs the gate signal switched from the gate high level Vgh to the first gate low level Vgl1. On the other hand, the second output terminal Vc [n] of the nth stage outputs the gate signal switched from the gate high level Vgh to the second gate low level Vgl2.

As described above, after the outputs of the first and second output terminals Vg [n] and Vc [n] are generated during the charging period of the QB node QB, the QB node QB is discharged and the pull-down transistor unit TPD1 , TPD2) will remain turned off.

During the period in which the potential of the Q node Q is maintained in the charged state, the third-second transistor T3-2 is turned on by the potential of the Q node Q. When the third-2 transistor T3-2 is turned on, the QB node QB is discharged by the second gate low level Vgl2. In this case, the second gate low level Vgl2 is applied to the gate electrode of the first pull-down transistor TPD1, and the first gate low level Vgl1 is applied to the source electrode. The second gate low level Vgl2 applied to the gate electrode of the first pull-down transistor TPD1 has a lower potential than the first gate low level Vgl1 applied to the source electrode. Therefore, the voltage Vgs between the gate sources of the first pull-down transistor TPD1 satisfies the conditions Vgl2-Vgl1 <0V lower than 0V. Therefore, since the voltage Vgs between the gate sources of the first pull-down transistor TPD1 becomes negative and the current Ids between the drain sources becomes I2 instead of I1 as shown in FIG. 4, no current leakage occurs. As a result, the first output terminal Vg [n] of the n-th stage can output the gate signal while maintaining a normal gate high level (or gate low level) as shown in FIG. 6.

In addition, during the period in which the potential of the Q node Q is maintained in the discharge state, the first transistor T1 is turned on by the X clock signal. When the first transistor T1 is turned on, the second gate low level Vgl2 is applied to the Q node Q. The first transistor T1 maintains the second output terminal Vc [n] of the Q node Q and the nth stage in a logic low state before the Q node Q is charged, thereby causing a ripple in the output. Prevent problems. That is, the first transistor T1 periodically logics the second output terminal Vc [n] of the Q node Q and the nth stage in response to the X clock signal in order to prevent the output ripple. Keep it low.

In addition, while the potential of the Q node Q is maintained in the discharged state, the gate electrode of the fifth transistor T5 receives the X-1 clock signal corresponding to the second gate low level Vgl2 and the drain electrode. The first output terminal voltage of the n-1 stage corresponding to the first gate low level Vgl1 is applied, and the second low potential voltage corresponding to the second gate low level Vgl2 is applied to the source electrode. The second gate low level Vgl2 applied to the source electrode of the fifth transistor T5 has a lower potential than the first gate low level Vgl1 applied to the gate electrode and the drain electrode. Therefore, since the fifth transistor T5 operates as a diode, the potential of the Q node Q is discharged to the first output terminal Vg [n-1] of the n-th stage through the fifth transistor T5. do. That is, the fifth transistor T5 forms a discharge path for discharging the potential of the Q node Q during the period in which the potential of the Q node Q is maintained in the discharge state, thereby turning on the first pull-up transistor TPU1. prevent. As a result, the first output terminal Vg [n] of the nth stage can output a gate signal while maintaining a normal gate low level as shown in FIG. 6.

According to the first embodiment, since the voltage condition between the gate sources of the transistors constituting the shift register is satisfied with Vgs = 0V, the turn-on / off operation characteristic of the TFT can be improved by the above-described configuration and operation, thereby improving output characteristics. Will be. This is because the first low potential voltage and the second low potential voltage having a relationship of Vgl1> Vgl2 are used as described above.

According to the above configuration, the shift register of FIG. 5 may configure stages to have a shape as shown in FIG. 2. As can be seen from the first embodiment through the Q node voltage Q-node, QB node voltage QB-node and the first output voltage Vg [n] shown in the waveform diagram of the simulation of FIG. Can be configured as a depletion mode TFT to perform normal output.

On the other hand, the shift register according to the first embodiment may be configured by simplifying the circuit as follows.

As shown in FIG. 8, the n-th stage according to the modified example is different from the first embodiment except for the configuration and connection relationship of the pull-up transistor unit TPU1, the pull-down transistor unit TPD1, and the first transistor T1. same. Therefore, only portions different from those of the first embodiment will be described in order to prevent duplication of description.

The pull-up transistor unit TPU1 is configured only with the first pull-up transistor TPU1, and the pull-down transistor unit TPD1 is configured only with the first pull-down transistor TPD1. Therefore, the n th stage outputs the gate signal switched from the gate high level Vgh to the first gate low level Vgl1 through the output terminal Vg [n].

Unlike the first embodiment, the first transistor T1 according to the modified example has a gate electrode connected to the X clock signal terminal CLK [X], a first electrode connected to the Q node Q, and an output terminal ( The second electrode is connected to Vg [n]). Accordingly, the first transistor T1 switches the current path between the Q node Q and the output terminal Vg [n] of the nth stage in response to the X clock signal. When the X-th clock signal is supplied, the first transistor T1 maintains the Q node Q at a voltage of the output terminal Vg [n] of the nth stage, that is, a discharge state (logic low state). That is, the first transistor T1 prevents the first pull-up transistor TPU1 from turning on in the discharge state of the Q node Q.

&Lt; Embodiment 2 >

9 is a circuit diagram of the n-th stage according to the second embodiment of the present invention.

As shown in FIG. 9, the n-th stage according to the second embodiment of the present invention includes a Q node charging and discharging unit T5 and a QB node charging and discharging unit T2-1, T2-2, T3-1, and T3-2. , Pull-up transistor units TPU1 and TPU2, pull-down transistor units TPD1 and TPD2, a first transistor T1, and a fourth transistor T4.

Q node charge / discharge unit T5, QB node charge / discharge unit T2-1, T2-2, T3-1, T3-2, pull-up transistor units TPU1, TPU2, pull-down transistor units TPD1, TPD2, first The transistor T1 and the fourth transistor T4 are composed of enhancement mode or depletion mode TFTs. The enhancement mode and depletion mode TFTs have a gate, a source and a drain electrode. The second embodiment also assumes that the TFTs are n-type, so that the drain / source electrode is referred to as the first electrode / second electrode.

The nth stage according to the second embodiment of the present invention is the same as the first embodiment except for the configuration and connection relationship between the Q-node charge and discharge unit T5 and the fourth transistor T4. Therefore, only portions different from those of the first embodiment will be described in order to prevent duplication of description.

The Q-node charge / discharge unit T5 has a gate electrode connected to the X-1 clock signal terminal CLK [X-1] or the second output terminal Vc [n-1] of the n-1 stage, and the n− The first electrode is connected to the first output terminal Vg [n-1] or the high potential voltage terminal VDD of one stage, and the second electrode is connected to the first electrodes of the Q node Q and the fourth transistor T4. It is composed of a fifth transistor (T5) connected.

In the fourth transistor T4, a gate electrode is connected to the second output terminal Vc [n + 1] of the n + 1th stage, and the first electrode of the fourth transistor T5 is connected to the second electrode and Q node Q of the fifth transistor T5. The second electrode is connected to the first low potential voltage terminal VGL1. The fourth transistor T4 discharges the Q node Q to the first low potential voltage in response to the voltage of the second output terminal of the n + 1th stage.

When the gate electrode of the fifth transistor T5 is connected to the X-1 clock signal terminal CLK [X-1], the first electrode of the fifth transistor T5 is the first output terminal of the n-1 stage ( Vg [n-1]). In contrast, when the gate electrode of the fifth transistor T5 is connected to the second output terminal Vc [n-1] of the n-1 stage, the first electrode of the fifth transistor T5 is the n-1 stage. Is connected to the first output terminal (Vg [n-1]) or the high potential voltage terminal (VDD).

The fifth transistor T5 corresponds to the X-1 clock signal or the voltage of the second output terminal Vc [n-1] of the n-1th stage, and corresponds to the first output terminal Vg [n-1 of the n-1th stage. ]) Charges Q node (Q) with voltage or high potential voltage. Subsequently, Q corresponds to the voltage of the first output terminal Vg [n-1] of the n-1 stage in response to the X-1 clock signal or the voltage of the second output terminal Vc [n-1] of the n-1 stage. The node Q is discharged. That is, the fifth transistor T5 resets / sets the Q node Q to the first output terminal Vg [n-1] voltage or the high potential voltage of the n−1th stage.

On the other hand, when the first electrode of the fifth transistor T5 is connected to the high potential voltage terminal VDD, the Q node Q is charged by the high potential voltage. However, since the fourth transistor T4 is turned on by the voltage of the second output terminal of the n + 1th stage, the Q node Q maintains the discharge state after the output. That is, the fourth transistor T4 resets the Q node Q to the voltage of the second output terminal of the n + 1th stage.

Second Embodiment Also, like the first embodiment, after the first and second output terminals Vg [n] and Vc [n] are output during the charging period of the Q node Q, the Q node Q is subsequently performed. Is discharged, and the pull-up transistors TPU1 and TPU2 are kept turned off.

After the first and second output terminals Vg [n] and Vc [n] are output during the charging period of the QB node QB, the QB node QB is discharged and the pull-down transistor unit TPD1, TPD2) will remain turned off.

According to the above configuration, the shift register of FIG. 9 may configure stages to have a form as shown in FIG. 3. Since the second embodiment is also based on the first embodiment, it is possible to perform normal output even when the shift register is configured as the depletion mode TFT.

In addition, according to the above configuration, two output terminals Vg [n] and Vc [n] are used, and an output voltage of the first output terminal Vg [n] is used as a gate signal for driving the subpixel. On the other hand, the output voltage of the second output terminal Vc [n] is used as a driving signal for driving the shift register.

Third Embodiment

10 is a circuit diagram of the n-th stage according to the third embodiment.

As shown in FIG. 10, the n-th stage according to the third embodiment of the present invention includes Q node charging and discharging units T5-1, T5-2, and T5-3, and QB node charging and discharging units T2-1 and T2-. 2, T3-1 and T3-2, pull-up transistor units TPU1 and TPU2, pull-down transistor units TPD1 and TPD2, and first transistor T1.

Q node charge and discharge unit (T5-1, T5-2, T5-3), QB node charge and discharge unit (T2-1, T2-2, T3-1, T3-2), pull-up transistor unit (TPU1, TPU2), pull-down The transistor units TPD1 and TPD2 and the first transistor T1 are composed of enhancement mode or depletion mode TFTs. The enhancement mode and depletion mode TFTs have a gate, a source and a drain electrode. The third embodiment also assumes that the TFTs are n-type, so the drain / source electrode is referred to as the first electrode / second electrode.

The n-th stage according to the third embodiment of the present invention is the same as the first embodiment except for the configuration and connection relationship of the Q-node charge / discharge units T5-1, T5-2, and T5-3. Therefore, only portions different from those of the first embodiment will be described in order to prevent duplication of description.

Q-node charging and discharging units T5-1, T5-2, and T5-3 include 5-1 transistors T5-1, 5-2 transistors T5-2, and 5-3 transistors T5-3. It consists of.

The 5-1 transistor T5-1 has a gate electrode connected to the X-1 clock signal terminal CLK [X-1] and is connected to the first output terminal Vg [n-1] of the n-1 stage. The first electrode is connected and the second electrode is connected to the first electrode of the 5-2 transistor T5-2. The gate electrode of the 5-2 transistor T5-2 is connected to the X-1 clock signal terminal CLK [X-1] and the first electrode of the second electrode of the 5-1 transistor T5-1. The second electrode is connected to the Q node Q. In the fifth-3 transistor T5-3, a gate electrode is connected to the X clock signal terminal CLK [X], and a first electrode is connected to the second output terminal Vc [n] of the nth stage. The second electrode is connected to the first electrode of the -2 transistor T5-2. The fifth-3 transistor T5-3 is connected to the Xth clock signal terminal CLK [X] together with the first transistor T1.

The 5-1 and 5-2 transistors T5-1 and T5-2 are simultaneously turned on and off in response to the X-1 clock signal. Accordingly, the 5-1 and 5-2 transistors T5-1 and T5-2 charge the Q node Q to the voltage at the first output terminal of the n-1 stage in response to the X-1 clock signal. Thereafter, the Q node Q is discharged to the voltage at the first output terminal of the n-th stage in response to the X-th clock signal.

The 5-3 transistor T5-3 is turned on and off simultaneously with the first transistor T1 in response to the X clock signal terminal CLK [X]. Accordingly, the fifth to third transistors T5-3 are turned off after maintaining the state of charge of the Q node Q at the voltage of the second output terminal Vc [n] of the nth stage, and are then turned off through the 5-1 and fifth. The transistors T5-1 and T5-2 remain turned off. That is, the 5-3 transistor T5-3 prevents the voltage of the Q node Q from being discharged through the 5-1 transistor T5-1 during the output period of the nth stage, thereby improving stability of the operation. Play a role.

In the third embodiment, like the first embodiment, after the first and second output terminals Vg [n] and Vc [n] are output during the charging period of the Q node Q, the Q node Q is performed. Is discharged, and the pull-up transistors TPU1 and TPU2 are kept turned off.

After the first and second output terminals Vg [n] and Vc [n] are output during the charging period of the QB node QB, the QB node QB is discharged and the pull-down transistor unit TPD1, TPD2) will remain turned off.

According to the above configuration, the shift register of FIG. 10 may configure stages to have a form as shown in FIG. 2. Since the third embodiment is also based on the first embodiment, even if the shift register is configured as the depletion mode TFT, it is possible to perform normal output.

<Fourth Embodiment>

11 is a circuit diagram of the n-th stage according to the fourth embodiment.

As illustrated in FIG. 11, the n-th stage according to the fourth embodiment of the present invention includes Q node charging and discharging units (T5-1, T5-2, and T5-3) and QB node charging and discharging units (T2-1 and T2-). 2, T3-1 and T3-2, pull-up transistor units TPU1 and TPU2, pull-down transistor units TPD1 and TPD2, a first transistor T1, and a fourth transistor T4.

Q node charge and discharge unit (T5-1, T5-2, T5-3), QB node charge and discharge unit (T2-1, T2-2, T3-1, T3-2), pull-up transistor unit (TPU1, TPU2), pull-down The transistor units TPD1 and TPD2, the first transistor T1 and the fourth transistor T4 are configured with enhancement mode or depletion mode TFTs. The enhancement mode and depletion mode TFTs have a gate, a source and a drain electrode. The fourth embodiment also uses TFTs as n-type (n-type) as an example, so the drain / source electrode is referred to as the first electrode / second electrode.

The n-th stage according to the fourth embodiment of the present invention is the same as the first embodiment except for the configuration and connection relationship between the Q-node charging and discharging units T5-1, T5-2, and T5-3 and the fourth transistor T4. same. Therefore, only portions different from those of the first embodiment will be described in order to prevent duplication of description.

Q-node charging and discharging units T5-1, T5-2, and T5-3 include 5-1 transistors T5-1, 5-2 transistors T5-2, and 5-3 transistors T5-3. It consists of.

The 5-1 transistor T5-1 has a gate electrode connected to the X-1 clock signal terminal CLK [X-1] or the second output terminal Vc [n-1] of the n-1 stage. The first electrode is connected to the first output terminal Vg [n-1] or the high potential voltage terminal VDD of the n-1 stage, and the second electrode is connected to the first electrode of the 5-2 transistor T5-2. Is connected. The 5-2 transistor T5-2 has a gate electrode connected to the X-1 clock signal terminal CLK [X-1] or the second output terminal Vc [n-1] of the n-1 stage. The first electrode is connected to the second electrode of the 5-1 transistor T5-1 and the second electrode is connected to the Q node Q. In the fifth-3 transistor T5-3, a gate electrode is connected to the X clock signal terminal CLK [X], and a first electrode is connected to the second output terminal Vc [n] of the nth stage. The second electrode is connected to the first electrode of the -2 transistor T5-2. The fifth-3 transistor T5-3 is connected to the Xth clock signal terminal CLK [X] together with the first transistor T1.

The fourth transistor T4 has a gate electrode connected to the second output terminal Vc [n + 1] of the n + 1th stage, and the second electrode and the Q node Q of the 5-2 transistor T5-2. The first electrode is connected to the second electrode, and the second electrode is connected to the first low potential voltage terminal VGL1. The fourth transistor T4 discharges the Q node Q to the first low potential voltage in response to the voltage of the second output terminal of the n + 1th stage.

The 5-1 and 5-2 transistors T5-1 and T5-2 are simultaneously turned on and off in response to the X-1 clock signal or the voltage of the second output terminal of the n-1th stage. Accordingly, the 5-1 and 5-2 transistors T5-1 and T5-2 correspond to the X-1 clock signal or the voltage at the second output terminal of the n-1th stage to correspond to the first voltage of the n-1th stage. The Q node Q is charged with the output terminal voltage or the high potential voltage, and then the Q node is applied to the first output terminal voltage of the n-1 stage in response to the X-1 clock signal or the voltage of the second output terminal of the n-1 stage. Q) is discharged. That is, the 5-1 and 5-2 transistors T5-1 and T5-2 are the Q nodes Q at the first output terminal Vg [n-1] voltage or the high potential voltage of the n-1 stage. To reset / set

On the other hand, when the first electrode of the 5-1 transistor T5-1 is connected to the high potential voltage terminal VDD, the Q node Q is charged by the high potential voltage. However, since the fourth transistor T4 is turned on by the voltage of the second output terminal of the n + 1th stage, the Q node Q maintains the discharge state after the output. That is, the fourth transistor T4 resets the Q node Q to the voltage of the second output terminal of the n + 1th stage.

The 5-3 transistor T5-3 is turned on and off simultaneously with the first transistor T1 in response to the X clock signal terminal CLK [X]. Accordingly, the fifth to third transistors T5-3 are turned off after maintaining the state of charge of the Q node Q at the voltage of the second output terminal Vc [n] of the nth stage, and are then turned off through the 5-1 and fifth. The transistors T5-1 and T5-2 remain turned off.

In the fourth embodiment, as in the first embodiment, the first and second output terminals Vg [n] and Vc [n] are output during the charging period of the Q node Q, and then the Q node Q is performed. Is discharged, and the pull-up transistors TPU1 and TPU2 are kept turned off.

After the first and second output terminals Vg [n] and Vc [n] are output during the charging period of the QB node QB, the QB node QB is discharged and the pull-down transistor unit TPD1, TPD2) will remain turned off.

According to the above configuration, the shift register of FIG. 11 may configure stages to have a shape as shown in FIG. 3. Since the fourth embodiment is also based on the first embodiment, even if the shift register is configured as the depletion mode TFT, it is possible to perform normal output.

In addition, according to the above configuration, two output terminals Vg [n] and Vc [n] are used, and an output voltage of the first output terminal Vg [n] is used as a gate signal for driving the subpixel. On the other hand, the output voltage of the second output terminal Vc [n] is used as a driving signal for driving the shift register.

Meanwhile, the QB node charge / discharge units T2-1, T2-2, T3-1, and T3-2 of the shift registers according to the first to fourth embodiments described above may be configured by simplifying the circuit as follows.

12 is a circuit diagram illustrating a QB node charge and discharge unit according to a modified example.

As shown in FIG. 12A, the QB node charge / discharge units T2-1, T2-2, T3-1, and T3-2 of the first to fourth embodiments use the QB node QB using four transistors. Charge / discharge). On the other hand, as shown in Figure 12 (b), the QB node charge and discharge unit (T2, T3) according to the modified example charges and discharges the QB node (QB) using two transistors.

The QB node charge / discharge units T2 and T3 are composed of a second transistor T2 and a third transistor T3. In the second transistor T2, the gate electrode and the first electrode are connected to the high potential voltage terminal VDD, and the second electrode is connected to the first electrode and the QB node QB of the third transistor T3. The third transistor T3 has a gate electrode connected to the Q node Q, a first electrode connected to the second electrode and the QB node QB of the second transistor T2, and a first or second low potential voltage terminal. The second electrode is connected to (VGL1 or VGL2).

In the modified example, the QB node charge / discharge units T2 and T3 also charge the QB node QB to the high potential voltage terminal VDD at a frame period corresponding to the charge / discharge state of the Q node Q, or the first or second low potential. The function of discharging to the voltage terminal VGL1 or VGL2 is the same. The QB node charge / discharge units T2 and T3 of the modified example as described above have an advantage of reducing the manufacturing cost by simplifying the circuit.

Meanwhile, in the shift register circuits according to the above-described embodiments, the QB node QB consists of only one node, and the QB node QB consists of two nodes and alternately drives a frame period by adding a transistor accordingly. It may be implemented.

The shift register according to the above-described embodiments has an n-type TFT of negative threshold voltage and a p-type of positive threshold voltage as well as a TFT in enhancement mode. It can be applied to TFT. In addition, the above-described embodiments may be configured in other forms by appropriately combining circuits so as to improve and improve the output characteristics of the shift register.

As described above, the present invention is configured such that the voltage (Vgs) between the gate sources of the TFTs becomes negative even when the depletion mode TFTs as well as the enhancement mode TFTs are applied, and the output characteristics are improved by improving the turn-on / off operation characteristics of the TFTs (output There is an effect of providing a display device including a gate driver capable of solving a problem such as no occurrence.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

10: Display panel 11: Timing controller
12: data driver 13, 14: gate driver
T1: first transistor T2: second transistor
T3: third transistor T4: fourth transistor
T2-1, T2-2, T3-1, T3-2: QB node charging / discharging part
T5: Q-node charging / discharging part or fifth transistor
T5-1, T5-2, T5-3: Q node charging / discharging part
TPU1, TPU2: pull-up transistor section
TPD1, TPD2: pulldown transistor section

Claims (11)

Display panel; And
A shift register connected to the display panel and configured to output clock signals, and a shift register configured to shift gate output pulses in response to the clock signals, and an nth stage of the stages
A pull-up transistor unit including a first pull-up transistor for outputting an X-th clock signal to an output terminal of the n-th stage in response to the potential of the Q node;
A pull-down transistor section including a first pull-down transistor for outputting a first low potential voltage to an output terminal of the n-th stage in response to a potential of a QB node;
Q node charging and discharging unit for charging and discharging the Q node,
A QB node charging and discharging unit for charging the QB node and discharging at a second low potential voltage lower than the first low potential voltage;
And a first transistor configured to switch a current path between the Q node and an output terminal of the nth stage in response to the X clock signal. The method of claim 1,
The Q node charging and discharging unit
After charging the Q node with the output terminal voltage of the n-1 stage in response to the X-1 clock signal, the Q node is discharged with the output terminal voltage of the n-1 stage in response to the X-1 clock signal. Let's
The QB node charge and discharge unit
After discharging the QB node to the second low potential voltage lower than the first low potential voltage in response to the potential of the Q node, the QB node to the high potential voltage in response to the potential and high potential voltage of the Q node. Display device characterized in that the charging. The method of claim 1,
The pull-up transistor unit includes a second pull-up transistor that outputs the X-th clock signal to the second output terminal of the n-th stage in response to the potential of the Q node.
The pull-down transistor unit includes a second pull-down transistor for outputting the second low potential voltage to the second output terminal of the n-th stage in response to the potential of the QB node.
And the first transistor forms a potential of the Q node at a potential of a second output terminal of the nth stage in response to the X clock signal. The method according to claim 1 or 3,
The QB node charge and discharge unit
A second transistor having a gate electrode and a first electrode connected to the high potential voltage terminal;
A display device comprising a third transistor having a gate electrode connected to the Q node, a second electrode of the second transistor, a first electrode connected to the QB node, and a second electrode connected to a first or second low potential voltage terminal Device. The method according to claim 1 or 3,
The QB node charge and discharge unit
A 2-1 transistor having a gate electrode and a first electrode connected to a high potential voltage terminal;
A 2-2 transistor having a gate electrode connected to the second electrode of the 2-1 transistor and a first electrode connected to the high potential voltage terminal;
A 3-1 transistor having a gate electrode connected to the Q node, a first electrode connected to a second electrode of the 2-1 transistor, and a second electrode connected to a first low potential voltage terminal;
A gate electrode connected to the Q node, a second electrode of the second-2 transistor, a third electrode connected to the QB node, and a second electrode connected to a second low potential voltage terminal; Display. The method of claim 3,
The n-th stage
And a fourth transistor configured to discharge the Q node to the first low potential voltage in response to the voltage of the second output terminal of the n + 1th stage. The method according to claim 6,
The Q node charging and discharging unit
The gate electrode is connected to the X-1 clock signal terminal or the second output terminal of the n-1th stage, and the first electrode is connected to the first output terminal or the high potential voltage terminal of the n-1 stage, and the Q node and the first node And a fifth transistor having a second electrode connected to the first electrode of the four transistors. The method of claim 3,
The Q node charging and discharging unit
A 5-1 transistor having a gate electrode connected to the X-1 clock signal terminal and a first electrode connected to the first output terminal of the n-1 stage;
A 5-2 transistor having a gate electrode connected to the X-1 clock signal terminal, a first electrode connected to a second electrode of the 5-1 transistor, and a second electrode connected to the Q node;
A fifth-3 transistor connected to a gate electrode of the X-clock signal terminal, a first electrode of the second output terminal of the nth stage, and a second electrode of the second electrode of the fifth electrode of the fifth transistor; Display. The method according to claim 6,
The Q node charging and discharging unit
A 5-1 transistor having a gate electrode connected to the X-1 clock signal terminal or a second output terminal of the n-1 stage and a first electrode connected to the first output terminal or the high potential voltage terminal of the n-1 stage;
A gate electrode is connected to the second output terminal of the X-1 clock signal terminal or the n-1 stage, a first electrode is connected to the second electrode of the 5-1 transistor, and a second electrode is connected to the Q node. 5-2 transistor,
A fifth-3 transistor connected to a gate electrode of the X-clock signal terminal, a first electrode of the second output terminal of the nth stage, and a second electrode of the second electrode of the fifth electrode of the fifth transistor; Display. 3. The method of claim 2,
The logic low voltage of the clock signals
And a voltage between the first low potential voltage and the second low potential voltage. The method of claim 3,
The pull-up transistor unit
A first pull-up transistor having a gate electrode connected to the Q node, a first electrode connected to an X clock signal terminal, and a second electrode connected to a first output terminal of the nth stage;
A second pull-up transistor having a gate electrode connected to the Q node, a first electrode connected to the X clock signal terminal, and a second electrode connected to a second output terminal of the nth stage;
The pull-down transistor unit
A first pull-down transistor having a gate electrode connected to the QB node, a first electrode connected to a first output terminal of the nth stage, and a second electrode connected to a first low potential voltage terminal;
And a second pull-down transistor having a gate electrode connected to the QB node, a first electrode connected to a second output terminal of the nth stage, and a second electrode connected to a second low potential voltage terminal.

Images