KR102514723B1 - Display Device - Google Patents

Abstract

The display device of the present invention includes a pixel array, a shift register, and a gate low voltage controller. Data lines and gate lines are defined in the pixel array, and pixels are arranged in a matrix form. The shift register includes stages connected in cascade, and sequentially supplies gate pulses swinging between a gate high voltage and a gate low voltage to the gate lines. The gate low voltage controller lowers the gate low voltage when the leakage current of the stage exceeds a predetermined level. The n-th stage includes a pull-up transistor, a pull-down transistor, a start controller, and a QB node discharge controller. The pull-up transistor charges the output terminal in response to the voltage of the Q node and outputs an nth gate pulse. The pull-down transistor discharges the output stage to a gate low voltage in response to the voltage at the QB node. The start controller precharges the Q node in response to a start pulse or a gate pulse other than the nth gate pulse.

Description

Display Device {Display Device}

The present invention relates to a display device.

In the display device, data lines and gate lines are arranged to be orthogonal, and pixels are arranged in a matrix form. Video data voltages to be displayed are supplied to the data lines, and gate pulses are sequentially supplied to the gate lines. The video data voltage is supplied to the pixels of the display line to which the gate pulse is supplied, and video data is displayed while all the display lines are sequentially scanned by the gate pulse.

A gate driver for supplying gate pulses to gate lines of a display device usually includes a plurality of gate integrated circuits (hereinafter referred to as “ICs”). Since each gate drive IC must sequentially output gate pulses, it basically includes a shift register, and may include circuits and output buffers for adjusting the output voltage of the shift register according to the driving characteristics of the display panel.

A gate driver generating a gate pulse, which is a scan signal, in a display device may be implemented in the form of a gate-in-panel (Gate II Paiel, hereinafter referred to as GIP) consisting of a combination of thin film transistors in a bezel area, which is a non-display area, of a display panel. The GIP type gate driver includes stages corresponding to the number of gate lines, and each stage outputs gate pulses to corresponding gate lines on a one-to-one basis.

In the thin film transistor included in the shift register, a transistor characteristic curve is negatively shifted over time, so leakage current increases. When the leakage current of a specific thin film transistor increases, the transistors operate for an undesirable period, causing stress in the transistor to increase and heat generation to increase.

In order to solve the above problems, the present invention is to provide a display device capable of improving problems caused by leakage current of transistors belonging to shift registers.

As a means for solving the above problems, the display device of the present invention includes a pixel array, a shift register, and a gate low voltage controller. Data lines and gate lines are defined in the pixel array, and pixels are arranged in a matrix form. The shift register includes stages connected in cascade, and sequentially supplies gate pulses swinging between a gate high voltage and a gate low voltage to the gate lines. The gate low voltage controller lowers the gate low voltage when the leakage current of the stage exceeds a predetermined level. The n-th stage includes a pull-up transistor, a pull-down transistor, a start controller, and a QB node discharge controller. The pull-up transistor charges the output terminal in response to the voltage of the Q node and outputs an nth gate pulse. The pull-down transistor discharges the output stage to a gate low voltage in response to the voltage at the QB node. The start controller precharges the Q node in response to a start pulse or a gate pulse other than the nth gate pulse.

According to the present invention, the voltage level of the gate low voltage of the gate pulse is lowered according to the amount of leakage current of the stage. As a result, the voltage level of the gate electrode of the start control unit receiving the gate pulse as a carry signal is lowered, thereby reducing the leakage current of the start control unit. If the amount of leakage current of the start control unit is reduced, it is possible to prevent the Q node from being precharged during an unwanted period, and as a result, it is possible to improve the problem of heat generation caused by the operation of transistors for a long time due to the precharging of the Q node.

1 is a view showing a display device according to the present invention.
2 is a diagram showing a shift register according to the first embodiment.
3 is a diagram showing a stage according to the first embodiment.
4 is a timing diagram showing inputs and outputs of shift registers.
5 is a flowchart illustrating the operation of the gate low voltage controller according to the present invention.
6 is a block diagram showing the configuration of a gate low voltage controller according to the present invention.
7 is a diagram explaining an increase in leakage current due to a shift in a transistor characteristic curve.
8 is a view showing a shift register according to the second embodiment.
9 is a diagram showing a stage according to a second embodiment.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings, focusing on the liquid crystal display device. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. The names of the components used in the following description are selected in consideration of the ease of writing the specification, and may differ from the names of actual products.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention. Referring to FIG. 1 , the display device of the present invention includes a display panel 100 , a timing controller 110 , a data driver 120 , and scan drivers 130 and 150 .

The display panel 100 includes a pixel array 100A in which data lines DL and gate lines GL are defined and pixels are disposed, and a non-display area in which various signal lines or pads are formed outside the pixel array 100A. (100B). The display panel 100 may use a liquid crystal display (LCD), an organic light emitting diode display (OLED), an electrophoretic display (EPD), or the like.

The timing controller 110 receives timing signals such as a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and a dot clock (DLCK) through an LVDS or TMDS interface receiving circuit connected to the video board. is input. The timing controller 110 includes a data timing control signal (DDC) for controlling the operation timing of the data driver 120 and a gate timing control signal (for controlling the operation timing of the scan driver 130 and 140) based on the input timing signal. GDC) is created.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (Polarity, POL), and a source output enable signal (Source Output Enable, SOE). includes The source start pulse SSP controls shift start timing of the source drive ICs 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data within the source drive ICs 120 based on a rising or falling edge.

The scan timing control signal includes a start pulse (VST) and a gate clock (CLK). The start pulse VST is input to the shift register 130 to control the shift start timing. The gate clock CLK is input to the shift register 130 after level shifting through the level shifter 150.

The data driver 120 includes a plurality of source drive ICs (Integrated Circuits). The source drive ICs receive digital video data (RGB) and a source timing control signal (DDC) from the timing controller 110 . The source drive ICs generate data voltages by converting digital video data RGB into gamma voltages in response to the source timing control signal DDC, and transmit the data voltages through the data lines DL of the display panel 100. supply

The scan driving units 130 and 150 include a level shifter 150 and a shift register unit 130 . The shift register unit 130 is formed in the non-display area 100B of the display panel 100 using a Gate In Panel (GIP) method.

The level shifter 150 is formed on a printed circuit board (not shown) connected to the display panel 100 in the form of an IC. The level shifter 150 levels shifts the clock signals CLK and the start signal VST under the control of the timing controller 110 and supplies them to the shift register unit 130 .

The shift register unit 130 is formed by a combination of a plurality of thin film transistors (hereinafter referred to as TFTs) in the non-display area 100B of the display panel 100 by a GIP method. The shift register unit 130 outputs a gate pulse corresponding to the clock signals CLK and the start pulse VST.

The gate low voltage controller 200 adjusts the gate low voltage VGL_M according to the amount of leakage current. As a result, acceleration of deterioration of the transistors included in the shift register 130 due to leakage current can be reduced.

2 is a diagram showing stages of shift registers according to the first embodiment.

Referring to FIGS. 1 and 2 , the shift register 130 according to the present invention includes first to nth stages (ST1 to STn, where n is a natural number greater than or equal to 2). 2 shows the [n−3]th stage STG[n−3] and the nth stage STGn.

In the following description, "front stage" refers to a stage positioned above a standard stage. For example, based on the kth (k is a natural number of 1<k<n) stage STk, the previous stage is any one of the first stage ST1 to the k−1th stage ST(k−1). instruct "Later stage" refers to a stage positioned below a standard stage. For example, based on the k(1<k<n)th stage STk, the next stage indicates any one of the k+1th stage ST(k+1) to the nth stage.

Each stage STG of the shift register 130 sequentially outputs gate pulses Gout[1] to Gout[n]. For example, the [n-3]th stage STG[n-3] outputs the [n-3]th gate pulse Gout[n-3], and the nth stage STGn outputs the nth gate pulse ( Gout[n]). To this end, each stage STG receives one gate clock from among sequentially delayed gate clocks CLK. Gate clocks may be implemented with 6 or more phases to ensure sufficient charging time when driven at a high speed of 240Hz or higher. The [n−3]th gate pulse Gout[n−3] is applied to the [n−3]th gate line and serves as a carry signal transmitted to the nth stage. 2 shows that the carry signal input to the nth stage STGn is the [n−3]th gate pulse Gout[n−3], but the carry signal is not limited thereto.

FIG. 3 is a diagram showing the configuration of the stage shown in FIG. 2, and FIG. 4 is a diagram showing timing and output signals of driving signals input to the stage shown in FIG.

1 to 4, the stage STG of the shift register 130 includes a pull-up transistor (Tpu), a pull-down transistor (Tpd), and a node control circuit (NCON). include

The pull-up transistor Tpu includes a gate electrode connected to the Q node, a drain electrode connected to the input terminal of the gate clock CLK, and a source electrode connected to the output terminal Nout.

The pull-down transistor Tpd includes a gate electrode connected to the QB node, a drain electrode connected to the output terminal Nout, and a source electrode connected to the gate low voltage VGL_M input terminal.

The node control circuit NCON is for controlling the voltages of the Q node and the QB node, and includes a start controller T1, a Q node discharge controller T6, a QB node discharge controller T5, and a QB node charge controller T2 and T3. , T4).

The start control unit T1 has a gate electrode connected to the start pulse (VST) input terminal or the [n-3] gate pulse (Gout[n-3]) input terminal, a drain electrode connected to the high potential voltage (VDD) input terminal, and Q It includes a source electrode connected to the node.

The QB node discharge controller T5 includes a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to a low potential voltage (VGL) input terminal.

The Q node discharge controller T6 includes a gate electrode connected to the input terminal of the next signal NEXT, a drain electrode connected to the Q node, and a source electrode connected to the input terminal of the low potential voltage VGL.

The QB node charging control units T2 , T3 , and T4 include second to fourth transistors T2 , T3 , and T4 . The gate electrode and drain electrode of the second transistor T2 are connected to the high potential voltage input terminal. The third transistor T3 includes a gate electrode connected to the Q node, a drain electrode connected to the source electrode of the second transistor T2, and a source electrode connected to the low potential voltage (VGL) input terminal. The fourth transistor T4 includes a gate electrode connected to the drain electrode of the third transistor T3, a drain electrode connected to the drain electrode of the second transistor T2, and a source electrode connected to the QB node.

The start controller T1 pre-charges the Q node in response to the start pulse VST or the [n−3] gate pulse Gout[n−3].

When the gate clock CLK is input to the drain electrode of the pull-up transistor Tpu while the Q node is pre-charged, the Q node bootstraps according to the voltage rise of the drain electrode of the pull-up transistor Tpu. As the Q node is bootstrapping, the potential difference between the gate and the source of the pull-up transistor Tpu increases and the pull-up transistor Tpu is turned on. Eventually, the pull-up transistor Tpu charges the output terminal Nout using the gate clock CLK. The output terminal Nout is connected to the gate line GL, and a gate pulse Gout is applied to the gate line GL from the output terminal Nout.

After the gate clock CLK is inverted to a low level, the gate electrode of the Q node discharge controller T6 receives the next stage signal NEXT. The Q node discharge controller T6 is turned on in response to the next stage signal NEXT, and as a result, the voltage of the Q node is discharged to the low potential voltage VGL.

In FIG. 4, since the Q node is maintained at a high level during the period “t0 to t2”, the QB node discharge controller T5 is turned on, and as a result, the gate electrode of the pull-down transistor Tpd has a gate low voltage VGL_M is maintained as That is, the QB node discharge controller T5 suppresses the operation of the pull-down transistor Tpd when the Q node is at a high level.

As shown in FIG. 4, in a normal driving state, the voltage of the Q node is maintained at a low potential voltage except for the “t0 to t1” period in which the start pulse (VST) is input and the “t1_t2” period in which the gate clock (CLK) is input, The QB node discharge control unit T5 does not operate.

In the QB node discharge control unit T5 according to the first embodiment, a source electrode is connected to the gate low voltage VGL_M, and the gate low voltage VGL_M varies according to the amount of leakage current of the stage STG. The gate low voltage VGL_M is controlled by the gate low voltage controller 200 to prevent the QB node discharge controller T5 from malfunctioning.

Hereinafter, the operation of the gate low voltage controller 200 will be described with reference to FIGS. 5 and 6 .

5 is a flowchart illustrating the operation of the gate low voltage controller according to the present invention, and FIG. 6 is a block diagram showing the configuration of the gate low voltage controller.

Referring to FIGS. 1 to 6 , the gate low voltage controller 200 senses the leakage current of the stage STG. In particular, the current measurement unit 210 of the gate low voltage controller 200 may measure the leakage current of the start controller T1. The leakage current of the start control unit T1 may be measured based on the amount of input line current of the low potential voltage (VGL) (S501).

The comparator 220 of the gate low voltage control unit 200 determines whether the current amount of the input line of the low potential voltage VGL reaches a preset reference value or more. Since the amount of current of the low potential voltage VGL is proportional to the amount of leakage current of the start controller T1, the amount of leakage current of the start controller T1 can be estimated based on the amount of current of the low potential voltage VGL (S503).

The gate low voltage controller 200 maintains the gate low voltage (VGL_M) and outputs it to the stage STG when the amount of current is equal to or less than the reference value (S505 and S507).

On the other hand, the voltage controller 230 of the gate low voltage controller 200 adjusts the gate low voltage VGL_M when the amount of current is greater than or equal to the reference value. The voltage level of the initial gate low voltage VGL_M may be set to be the same as that of the low potential voltage VGL.

The transistor characteristic curve of the start controller T1 may be negatively shifted due to deterioration or stress. As shown in FIG. 7, when the characteristic curve of the transistor is negatively shifted from the second graph (②) to the first graph (①), the amount of leakage current at the low potential voltage (VGL) increases from “I1” to “I2”.

When the amount of leakage current of the start control unit T1 increases, the QB node discharge control unit T5 may be turned on in addition to the “t0 to t2” period. Accordingly, a current path is formed through the fourth transistor T4 and the QB node discharge controller T5 to the low potential voltage (VGL) input terminal. Since this current path is formed during most of one frame except for the period “t0 to t3”, the fourth transistor T4 and the QB node discharge control unit T5 generate heat for a long time.

The gate low voltage controller 200 lowers the voltage level of the gate low voltage VGL_M when the input line current amount of the low potential voltage VGL is greater than or equal to the reference value. The gate low voltage VGL_M is a low level voltage value of the gate pulse Gout, and the gate pulse Gout also functions as a carry signal input to the next stage STG. That is, when the voltage level of the gate low voltage VGL_M is lowered, the low level voltage of the carry signal input to the start controller T1 of the next stage STG is also lowered. Since the start controller T1 receives a lower voltage except for the period in which the Q node is pre-charged, the voltage level of Vgs of the start controller T1 becomes lower. As a result, the leakage current of the start control unit T1 is reduced during the period excluding the pre-charging period, and the phenomenon of unwanted charging of the Q node is improved.

The gate low voltage control unit 200 may lower the voltage level of the gate low voltage VGL_M in proportion to the amount of change in the current value measured from the input line of the low potential voltage VGL. The amount of current of the input line of the low potential voltage VGL is proportional to the degree of negative shift of the transistor characteristic curve of the start controller T1. The input line current amount of the low potential voltage ( ) and the control amount of the gate low voltage ( ) may be stored as a lookup table based on the pre-calculated result. (S509, S011)

8 is a diagram showing a shift register according to the second embodiment, and FIG. 9 is a diagram showing stages of the shift register shown in FIG. 8 . Hereinafter, in the description of the second embodiment, detailed descriptions of the same components as those of the previous embodiment will be omitted.

Referring to FIGS. 8 and 9 , the shift register 130 according to the present invention includes first to nth stages (ST1 to STn, where n is a natural number greater than or equal to 2). 2 shows the [n−3]th stage STG[n−3] and the nth stage STGn.

Each stage STG of the shift register 130 sequentially outputs gate pulses Gout[1] to Gout[n]. For example, the [n-3]th stage STG[n-3] outputs the [n-3]th gate pulse Gout[n-3], and the nth stage STGn outputs the nth gate pulse ( Gout[n]).

The stage STG of the shift register 130 includes first and second pull-up transistors Tpu1 and Tpu2, first and second pull-down transistors Tpd1 and Tpd2, and a node control circuit NCON.

The first pull-up transistor Tpu1 includes a gate electrode connected to the Q node, a drain electrode connected to the input terminal of the gate clock CLK, and a source electrode connected to the first output terminal Nout. The first pull-up transistor Tpu1 includes a gate electrode connected to the Q node, a drain electrode connected to the input terminal of the gate clock CLK, and a source electrode connected to the second output terminal Nout2.

The first pull-down transistor Tpd1 includes a gate electrode connected to the QB node, a drain electrode connected to the first output terminal Nout1, and a source electrode connected to the low potential voltage (VGL) input terminal. The second pull-down transistor Tpd2 includes a gate electrode connected to the QB node, a drain electrode connected to the second output terminal Nout2, and a source electrode connected to the gate low voltage VGL_M input terminal.

The node control circuit (NCON) is for controlling the voltages of the Q node and the QB node, and includes a start control unit T1, a QB node discharge control unit T5, a Q node discharge control unit T6, and a QB node charge control unit T2 and T3. , T4).

The start control unit T1 has a gate electrode connected to the start pulse (VST) input terminal or the [n-3] gate pulse (Gout[n-3]) input terminal, a drain electrode connected to the high potential voltage (VDD) input terminal, and Q It includes a source electrode connected to the node.

The QB node discharge controller T5 includes a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to a low potential voltage (VGL) input terminal.

The Q node discharge controller T6 includes a gate electrode connected to the input terminal of the next signal NEXT, a drain electrode connected to the Q node, and a source electrode connected to the input terminal of the low potential voltage VGL.

The QB node charging controllers T2, T3, and T4 include second to fourth transistors. The gate electrode and drain electrode of the second transistor T2 are connected to the high potential voltage input terminal. The third transistor T3 includes a gate electrode connected to the Q node, a drain electrode connected to the source electrode of the second transistor T2, and a source electrode connected to the low potential voltage (VGL) input terminal. The fourth transistor T4 includes a gate electrode connected to the drain electrode of the third transistor T3, a drain electrode connected to the drain electrode of the second transistor T2, and a source electrode connected to the QB node.

The driving signal input to the stage of the second embodiment shown in FIGS. 8 and 9 may be the same as the driving signal shown in FIG. 4 as in the first embodiment.

The first output terminal Nout1 of the stage according to the second embodiment is connected to the gate line GL, and the second output terminal Nout2 is input as a carry signal to the start controller T1 of the next stage. 8 shows an embodiment in which the carry signal of the [n−3]th stage (STG[n−3]) is input to the nth stage, but the stage to which the carry signal is input is not limited thereto.

The shift register according to the second embodiment separates the output stage for outputting the carry signal and the gate pulse. Then, the gate low voltage (VGL_M) of the second output terminal input as the carry signal of the next stage is adjusted according to the amount of leakage current of the shift register. As a result, the shift register according to the second embodiment can also improve the deterioration of the transistors due to the leakage current.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the above-described technical configuration of the present invention can be changed into other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that this can be implemented. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130, 150: gate driver
200: gate low voltage control unit

Claims (8)

a pixel array in which data lines and gate lines are defined and pixels are arranged in a matrix form;
a shift register comprising stages connected in a dependent manner and sequentially supplying gate pulses swinging between a gate high voltage and a gate low voltage to the gate lines; and
a gate low voltage control unit that lowers the gate low voltage when the leakage current of the stage exceeds a predetermined level;
The nth (n is a natural number) stage is
a pull-up transistor that charges an output terminal in response to the voltage of the Q node and outputs an n-th gate pulse;
a pull-down transistor for discharging the output terminal to the gate low voltage in response to the voltage of the QB node;
A start controller precharging the Q node in response to a start pulse or a gate pulse other than the nth gate pulse;
The gate low voltage controller
A display device that lowers the gate low voltage when the current value of the input line of the low potential voltage is equal to or greater than a preset reference value.
According to claim 1,
The nth stage is
and a QB node discharge controller comprising a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to the input line of the low potential voltage.
According to claim 2,
The nth stage is
A display device further comprising a Q node discharge control unit comprising a gate electrode connected to a downstream signal input terminal, a drain electrode connected to the Q node, and a source electrode connected to a low potential voltage input terminal. According to claim 3,
The nth stage is
a second transistor having a gate electrode and a drain electrode connected to a high potential voltage input terminal;
a third transistor having a gate electrode connected to the Q node, a drain electrode connected to the source electrode of the second transistor, and a source electrode connected to the low potential voltage input terminal; and
A QB charging control unit comprising a fourth transistor including a gate electrode connected to the drain electrode of the third transistor, a drain electrode connected to the drain electrode of the second transistor, and a source electrode connected to the QB node,
The QB charging controller charges the QB node during a period in which the Q node is not charged.
According to claim 1,
The pull-up transistor is connected to a gate clock input terminal and the output terminal,
The pull-down transistor is connected to the output terminal and the gate low voltage input terminal,
The gate pulse output from the output terminal is input to the gate electrode of the start controller of any one of the subsequent stages. According to claim 2,
An initial voltage of the gate low voltage is set equal to the low potential voltage. a pixel array in which data lines and gate lines are defined and pixels are arranged in a matrix form;
a shift register comprising stages connected in a dependent manner and sequentially supplying gate pulses swinging between a gate high voltage and a gate low voltage to the gate lines; and
a gate low voltage control unit that lowers the gate low voltage when the leakage current of the stage exceeds a predetermined level;
The nth (n is a natural number) stage is
a first pull-up transistor that charges the first output terminal in response to the voltage of the Q node and outputs an n-th gate pulse;
a first pull-down transistor for discharging the first output terminal to a low potential voltage in response to a voltage of a QB node;
a second pull-up transistor configured to charge a second output terminal in response to the voltage of the Q node and output an n-th carry signal;
a second pull-down transistor for discharging the second output terminal to the gate low voltage in response to the voltage of the QB node;
A start control unit precharging the Q node in response to a start pulse or a carry signal other than the n-th carry signal;
The gate low voltage controller
A display device that lowers the gate low voltage when a current value in the input line of the low potential voltage is equal to or greater than a preset reference value. delete

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