KR102426176B1 - Display Device - Google Patents

Abstract

A display device according to the present invention includes a timing controller for outputting a reference signal, a level shifter, and a shift register. The level shifter outputs the first high potential voltage or the second high potential voltage during the high level section of the reference signal and outputs the low potential voltage during the low level section of the reference signal. The shift register increases the voltage of the output terminal connected to the gate line in response to the QB node voltage, and corresponds to the first QB node charged with the first high potential voltage or the second QB node charged with the second high potential voltage. Discharge the output stage. The level shifter prevents the output terminal from floating during the image display period by fixing the reference signal to a high level during the image display period and outputting it.

Description

Display Device

The present invention relates to a display device.

In the display device, data lines and gate lines are arranged to be perpendicular to each other, and pixels are arranged in a matrix form. A video data voltage to be displayed is supplied to the data lines, and a gate pulse is sequentially supplied to the gate lines. A video data voltage is supplied to pixels of a display line to which a gate pulse is supplied, and video data is displayed while all display lines are sequentially scanned by the gate pulse.

A gate driving circuit for supplying gate pulses to the gate lines of a flat panel display generally includes a plurality of gate integrated circuits (hereinafter, referred to as "ICs"). Since each gate drive IC has to sequentially output gate pulses, it basically includes a shift register, and may include circuits and output buffers for adjusting an output voltage of the shift register according to driving characteristics of the display panel.

In the display device, the shift register that generates the gate pulse, which is the scan signal, is sometimes implemented in the form of a gate-in-panel (GIP) formed by a combination of thin film transistors in a bezel region that is a non-display region of a display panel. The GIP-type shift register includes stages corresponding to the number of gate lines, and each stage outputs gate pulses to corresponding gate lines on a one-to-one basis. An output terminal of each stage is connected to a gate line, and a gate pulse is provided to the gate line according to a voltage level of the output terminal. That is, the voltage level of the output terminal should be a high level voltage only during the period in which the gate pulse is output, and a period in which the output terminal is floated may occur during the driving period of the stage. Since the voltage level of the output stage is unstable in the floating section, a gate pulse is outputted to the gate line at an undesired timing, and an abnormal image is sometimes displayed.

In order to solve the above problems, the present invention relates to a display device capable of preventing a gate pulse from being output at an undesired timing.

As a means for solving the above problems, the display device according to the present invention includes a timing controller for outputting a reference signal, a level shifter, and a shift register. The level shifter outputs the first high potential voltage or the second high potential voltage during the high level section of the reference signal and outputs the low potential voltage during the low level section of the reference signal. The shift register increases the voltage of the output terminal connected to the gate line in response to the QB node voltage, and corresponds to the first QB node charged with the first high potential voltage or the second QB node charged with the second high potential voltage. Discharge the output stage. The level shifter prevents the output terminal from floating during the image display period by fixing the reference signal to a high level and outputting the reference signal except for a period in which the voltage of the output terminal rises within the image display period.

According to the present invention, since the first and second pull-down transistors are alternately driven to discharge the output terminal of the shift register to which the gate pulse is output, the stress applied to the pull-down transistor can be reduced compared to using one pull-down transistor.

In particular, since the present invention provides a high potential voltage to the first QB node and the second QB node for controlling the operation of the first and second pull-down transistors other than the period for outputting the gate pulse within the image display period, the image display period It is possible to prevent the output stage from floating inside. When the output stage is floating, the voltage state is unstable and a gate pulse can be provided from the output stage to the gate line. However, since the present invention prevents the output stage from floating during the initial period in the power-on sequence, it is It is possible to prevent the pixels from emitting light by outputting a non-existent gate pulse. Accordingly, it is possible to prevent the display quality from being deteriorated due to abnormal light emission during the image display period.

1 is a diagram showing the configuration of a display device according to the present invention.
2 is a block diagram showing the configuration of a level shifter according to the present invention.
3 is a diagram illustrating display timing in a display device;
FIG. 4 is a diagram illustrating the reference signal mask shown in FIG. 2;
5 is a timing diagram showing the input and output of the level shifter.
6 is a diagram illustrating an input and an output of a high potential voltage generator;
7 is a view showing a shift register according to the present invention.
Fig. 8 is a diagram showing a stage of a shift register;
9 is a diagram illustrating voltage changes of first and second QB nodes;

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of the ease of writing the specification, and may be different from the component names of the actual product.

1 is a view showing a display device according to an embodiment of the present invention.

Referring to FIG. 1 , the display device of the present invention includes a display panel 100 , a timing controller 110 , a data driver 120 , and gate drivers 130 and 140 .

The display panel 100 includes a display area 100A in which the pixels P are formed and a non-display area 100B in which various signal lines or pads are formed outside the display area 100A. The display area 100A includes a plurality of pixels P, and displays an image based on a gradation displayed by each pixel P. A plurality of pixels P are arranged in a matrix form on each of the horizontal lines. Each of the pixels P is formed in a region where the data line DL and the gate line GL orthogonal to each other cross each other. The gate line GL includes first to mth (m is a natural number) gate lines GL1 to GLm.

Each pixel P has a pixel circuit PC operating in response to a data signal DATA supplied in response to a scan signal supplied through the switching element SW connected to the gate line GL and the data line DL. includes The pixel circuit PC and the switching element SW may be implemented in different forms depending on the type of the display panel.

The timing controller 110 receives the timing of the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the data enable signal (Data Enable, DE), the main clock (MCLK) from the host computer through the LVDS or TMDS interface receiving circuit. signal is input. The timing controller 110 generates timing control signals for controlling operation timings of the data driving circuit and the gate driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the gate driving circuit, and a data timing control signal for controlling the operation timing of the data driver 120 and the polarity of the data voltage.

The scan timing control signal includes a start signal VST, a gate clock CLK, and a reference signal EO. The start signal VST is input to the shift register 130 to control the shift start timing. The gate clock CLK is input to the shift register 140 after being level-shifted through the level shifter 130 . The reference signal EO includes an initial section and an operation section. The initial period of the reference signal EO is from the time of the first falling edge of the voltage level to the time of the first falling edge in the power-on sequence, and the operation period is from the time of the first falling edge to the moment of power-off.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). The source start pulse SSP controls shift start timing of the source drive ICs 120 . The source sampling clock SSC is a clock signal that controls the sampling timing of data in the data driver 120 based on a rising or falling edge.

The data driver 120 receives digital video data RGB from the timing controller 110 . The data driver 120 converts the digital video data RGB into a gamma compensation voltage in response to a source timing control signal from the timing controller 110 to generate a data voltage, and synchronizes the data voltage with the gate pulse. supplied to the lines DL.

The gate drivers 130 and 140 include a level shifter 130 and a shift register 140 connected between the timing controller 110 and the gate lines of the display panel 100 .

The level shifter 130 converts the transistor-transistor-logic (TTL) logic level voltages of the odd and even gate clocks CLK_O and CLK_E input from the timing controller 110 to a gate high voltage VGH and a gate low voltage VGL. ) to level shift. The level shifter 130 divides the operation period of the reference signal EO into a first output period and a second output period based on the time when the voltage level is changed. The level shifter 130 outputs the first discharge control signal during the first output period and outputs the second discharge control signal during the second output period. In addition, the level shifter 130 outputs a preset first discharge control signal during the initial period of the reference signal.

The shift register 140 includes stages that sequentially output a carry signal and a gate pulse Gout by shifting the start pulse VST according to the odd and even gate clocks CLK_0 and CLK_E.

2 is a view of a level shifter according to the present invention.

2, the level shifter 130 according to the present invention includes a reference signal mask 201, a logic control unit 210, a first output control unit 231, first and second odd transistors T1_O, T2_O, and a second output control unit 241 and first and second even transistors T1_E and T2_E.

As shown in FIG. 6 , the reference signal EO includes output periods To and Te and a rest period Td. The output period To, Te and the idle period Td may be determined by dividing the voltage level of the reference signal EO. Hereinafter, a description will be made based on an embodiment in which the high-level section of the reference signal EO is set as the output sections To and Te, and the low-level section is set as the idle section Td.

The level shifter 130 outputs the first high potential voltage VGH_O or the second high potential voltage VGH_E during the output period To and Te of the reference signal EO. For example, the level shifter 130 outputs the first high potential voltage VGH_O during the first output period To, and outputs the second high potential voltage VGH_E during the second output period Te. The first output section To and the second output section Te are alternated.

The reference signal mask 201 separates the image display period AT and the vertical blank period VT, and allows the reference signal EO to always maintain a high level during the image display period AT.

The image display period AT and the vertical blank period VT divided by the reference signal mask 201 may be based on the VESA standard. Referring to FIG. 3 , the vertical blank period (VB) based on the display timing of the Video Electronic Standards Association (VESA) standard is as follows.

The data enable signal DE is synchronized with the data of the input image. One pulse period of the data enable signal DE is one horizontal time, and a high logic period of the data enable signal DE indicates one line data input timing. One horizontal period is a time required to write data to pixels of one line in the display panel 100 .

The data enable signal DE and data of the input image are input during the image display period AT and are not input during the vertical blank time VB. The image display period AT is a time required to display data of one frame in all pixels of the display unit 100A on which an image is displayed on the display panel 100 . One frame period is a time required to display one frame data on the display panel 100 and is the sum of one image display period AT and one vertical blank period VB.

As can be seen from the data enable signal DE, data of the input image is not received by the display device during the vertical blank period. The vertical blank period VB includes a vertical sync time (VS), a vertical front porch (FP), and a vertical back porch (BP). The vertical sync time (VS) is the time from the falling edge to the rising edge of Vsync, and represents the start (or end) timing of one screen. The vertical front porch FP is the time from the falling edge of the last DE indicating the last line data timing of one frame data to the start of the vertical blank time VB. The vertical back porch BP is the time from the end of the vertical blank time VB to the rising edge of the first DE indicating the first line data timing of one frame data.

The reference signal mask 201 may distinguish the image display period AT and the vertical blank period VT based on the presence or absence of the clock signal.

4 is a circuit diagram illustrating a reference signal mask 201 .

Referring to FIG. 4 , the reference signal mask 201 includes a first OR element OR1 and a second OR element OR2 .

The first OR element OR1 receives the first to i-th gate clocks GCLK1 to GCLKi and outputs the first mask signal EO_M1 when at least one gate clock GCLK is at a high level. The gate clock GCLK is provided to the shift register 140 and is a signal that determines the output timing of the gate pulse. That is, as shown in FIG. 5 , the gate clock GCLK is output during the image display period AT and is not output during the vertical blank period VT. In other words, the first OR element OR1 outputs the first mask signal EO_M1 during the image display period AT and does not output the first mask signal EO_M1 during the vertical blank period VT.

The second OR element OR2 receives the reference signal EO and the outputs of the first OR element OR1 , and outputs the second mask signal EO_M2 when the first mask signal EO_M1 is input. Alternatively, when the first mask signal EO_M1 is not input, the reference signal EO is output. That is, the second OR element OR2 outputs the second mask signal EO_M2 during the image display period AT and outputs the reference signal EO during the vertical blank period VT.

The logic controller 210 receives the output of the reference signal mask 201 and outputs the first control signal Z_O and the second control signal Z_E. The first control signal Z_O is a binary signal and serves as a reference for setting the first output section. The second control signal Z_E is a binary signal and serves as a reference for setting the second output section. [Table 1] below is a table showing an embodiment in which the logic controller 210 outputs the first control signal Z_O and the second control signal Z_E based on the reference signal EO.

EO=L EO=H EO=L EO=H Z_O VGL VGL VGL VGH Z_E VGL VGH VGL VGL

As shown in Table 1, when the reference signal EO is at the low level, the logic controller 210 outputs the first control signal Z_O and the second control signal Z_E of the low level. When the reference signal EO is the high level, the logic controller 210 outputs the voltage level of the first control signal Z_O or the second control signal Z_E as the high level. A section in which the first control signal Z_O and the second control signal Z_E have a high level does not overlap. For example, the high level first control signal Z_O and the high level second control signal Z_E may be alternately output.

6 is a diagram illustrating inputs and outputs of the first and second high potential voltage generators 230 and 240 .

Referring to FIG. 6 , the first high potential voltage generator 230 receives the first control signal Z_O and outputs the first high potential voltage VGH_O. The first high potential voltage generator 230 includes a first output controller 231 , a first odd transistor T1_O, and a second odd transistor T2_O. The drain electrode of the first odd transistor T1_O is connected to the high potential voltage VGH input terminal, the source electrode is connected to the first high potential output terminal Nh1 , and the gate electrode is the first of the first output control unit 231 . It receives the odd output control signal SW1_O. The drain electrode of the second odd transistor T2_O is connected to the first high potential output terminal Nh1 , the source electrode is connected to the low potential voltage input terminal VSS, and the gate electrode is the second of the first output control unit 231 . It receives the odd output control signal SW1_O.

The first output control unit 231 outputs a first odd output control signal SW1_O for turning on the first odd transistor T1_O in a section in which the first control signal Z_O is at a high level. As a result, the first odd transistor T1_O outputs the first high potential voltage VGH_O in the first output period To. In addition, the first output control unit 231 outputs a second odd output control signal SW2_O for turning on the second odd transistor T2_O in a section in which the first control signal Z_O is at a low level.

The second high potential voltage generator 240 receives the second control signal Z_E and outputs a second high potential voltage VGH_E. The second high potential voltage generator 240 includes a second output controller 241 , a first even transistor T1_E, and a second even transistor T2_E. The drain electrode of the first even transistor T1_E is connected to the input terminal of the first high potential voltage VGH_O, the source electrode is connected to the second high potential output terminal Nh2, and the gate electrode of the second output control unit 241 is connected to the The first even output control signal SW1_E is received. The drain electrode of the second even transistor T2_E is connected to the second high potential output terminal Nh2 , the source electrode is connected to the low potential voltage input terminal VSS, and the gate electrode is connected to the second output terminal of the second output control unit 241 . The even output control signal SW2_E is input.

The second output control unit 241 outputs a first even output control signal SW1_E for turning on the first even transistor T1_E in a section in which the second control signal Z_E is at a high level. As a result, the first even transistor T1_E outputs the second high potential voltage VGH_E in the second output period Te. In addition, the second output control unit 241 outputs a second even output control signal SW2_E for turning on the second even transistor T2_E in a section in which the second control signal Z_E is at a low level.

7 is a view showing a shift register according to the present invention.

Referring to FIG. 7 , the shift register 140 according to the present invention includes first to mth stages STG1 to STGm that are sequentially connected. In the following description, the term "front stage" refers to being located above the stage as a reference. For example, based on the i-th stage STGi, the previous stage indicates any one of the first stage STG1 to the (i-1)-th stage STG[i-1]. The “rear stage” refers to being located below the stage as a reference. For example, with respect to the i-th stage STGi, the rear stage indicates any one of the (i+1)-th stage STG[i+1] to the m-th stage.

The ith (i is a natural number greater than or equal to 5 and less than or equal to m) stage STGi outputs an ith gate pulse Gouti using sequentially delayed gate clocks CLK.

The first stage STG1 starts an operation in response to the start signal VST. The i-th stages (i is a natural number greater than or equal to 2 and less than or equal to n) STG[i] start operation in response to the (i-1)-th gate pulse Gout[i-1]. The start signal of each stage is not limited to the embodiment shown in FIG. 7 .

FIG. 8 is a block diagram showing the configuration of the stage i (i is a natural number where 2<i<m) in FIG. 2 .

Referring to FIG. 8 , the i-th stage STG[i] includes a Q node controller QC, first and second QB node controllers QBC1 and QBC2, a pull-up transistor Tpu, and first and second pull-down transistors. (Tpd1, Tpd2).

The Q node Q controls the operation of the pull-up transistor Tpu, and the first QB node QB1 and the second QB node QB2 control the operation of the pull-down transistor Tpd.

A gate electrode of the pull-up transistor Tpu is connected to the Q node Q, a first electrode is connected to an input terminal of the i-th gate clock CLKi, and a second electrode is connected to an output terminal Nout.

A gate electrode of the first pull-down transistor Tpd1 is connected to a first QB node QB1 , a first electrode is connected to an output terminal Nout, and a second electrode is connected to an input terminal of the low potential voltage VSS. The gate electrode of the second pull-down transistor Tpd2 is connected to the second QB node QB2 , the first electrode is connected to the output terminal Nout, and the second electrode is connected to the low potential voltage source VSS.

The Q node controller QC charges the Q node Q to operate the pull-up transistor Tpu. The Q node controller QC charges the Q node before the pull-up transistor Tpu receives the i-th gate clock CLKi, so that the Q node Q operates according to the high-level voltage of the i-th gate clock CLKi. Controls bootstrapping. Also, the Q node controller QC may discharge the Q node Q in each low-level voltage section of the i-th gate clock CLKi.

The first QB node controller QBC1 charges the first QB node QB1 to the first high potential voltage VGH_O as shown in FIG. 9 . The first QB node controller QBC1 discharges the first QB node QB1 during the scan period Ts in which the gate pulse is output through the output terminal Nout in each frame.

The second QB node controller QBC2 charges the second QB node QB2 to the second QB node QB2 to the second high potential voltage VGH_E. The second QB node controller QBC2 discharges the second QB node QB2 during the scan period Ts in which the gate pulse is output through the output terminal Nout in each frame.

That is, as shown in FIG. 9 , during the first output period To, the first QB node QB1 is charged with the first high potential voltage VGH_O, and during the second output period Te, the second QB node ( QB2) is charged to the second high potential voltage VGH_E. As a result, the first pull-down transistor Tpd1 is turned on during the first output period To, and the second pull-down transistor Tpd2 is turned on during the second output period Te. As such, since the first pull-down transistor Tpd1 and the second pull-down transistor Tpd2 are driven alternately, they are less affected by stress. If only one pull-down transistor is used to discharge the output stage, the pull-down transistor maintains the turn-on state for a very long time, so the characteristic changes due to stress. On the other hand, in the present invention, since the first pull-down transistor Tpd1 and the second pull-down transistor Tpd2 are driven alternately, the turn-on time is reduced by half compared to when a single pull-down transistor is used. As a result, the first pull-down transistor Tpd1 and the second pull-down transistor Tpd2 may reduce the effect of stress by half.

The logic controller 210 of the level shifter 130 determines the voltage levels of the first and second control signals Z_O and Z_E based on the falling edge (or falling rising) of the reference signal EO. And, as shown in [Table 1], when the reference signal EO is at the low level, the first and second control signals Z_O and Z_E are both at the low level. When both the first and second control signals Z_O and Z_E are at low levels, since the level shifter does not output both the first high potential voltage VGH_O and the second high potential voltage VGH_E, the first QB node ( QB1) and the second QB node QB2 are both in a state that cannot be charged. That is, in the idle period in which the level shifter 130 changes the outputs of the first high potential voltage VGH_O and the second high potential voltage VGH_E, the first QB node QB1 and the second QB node QB2 are low. Maintain the potential voltage state. In a normal operation, the idle period exists in the vertical blank period VT in which no image is displayed. In addition, since the reference signal maintains a high level in the image display period AT, the level shifter 130 outputs the first high potential voltage VGH_O or the second high potential voltage VGH_E.

However, there are cases in which the reference signal EO input to the level shifter 130 cannot maintain a high level due to noise such as static electricity. That is, when the voltage of the reference signal EO drops to a low level within the image display period AT, the level shifter 130 cannot output the first high potential voltage VGH_O or the second high potential voltage VGH_E. , as a result, both the first pull-down transistor Tpd1 and the second pull-down transistor Tpd2 of the shift register 140 do not operate. When both the first and second pull-down transistors Tpd1 and Tpd2 do not operate, the output terminal Nout is in a floating state. Since the voltage level is unstable when the output terminal Nout is in the floating state, the gate pulse Gout may be output to the gate line through the output terminal Nout in an undesired period. As a result, the pixels may emit light abnormally, which may deteriorate display quality.

According to the present invention, since the level shifter 130 prevents the low potential voltage from being output in the image display period AT, it is possible to prevent the output terminal Nout from floating during the image display period AT. That is, according to the present invention, the voltage of the output terminal Nout is provided to the gate line in an unwanted period in the image display period AT to prevent the pixels P from emitting light in an abnormal period.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: data driver 130: level shifter
140: shift register QBC: QB node control unit
QB: Q node control unit 210: logic control unit
230 and 240: first and second high potential voltage generators
231, 241: first and second output control unit

Claims (6)

a timing controller for outputting a reference signal;
A logic control unit receiving an output of a reference signal mask and outputting a first control signal and a second control signal, a first high potential voltage generator receiving the first control signal and outputting a first high potential voltage, and the second a level shifter comprising a second high potential voltage generator receiving a control signal and outputting a second high potential voltage, and outputting the first high potential voltage or the second high potential voltage during a high level period of the reference signal; and
The voltage of the output terminal connected to the gate line is increased in response to the QB node voltage, and in response to the first QB node charged with the first high potential voltage or the second QB node charged with the second high potential voltage, the including a shift register for discharging the output stage;
The level shifter
A display in which the first high potential voltage or the second high potential voltage is output during the video display period by fixing the reference signal to a high level except for a period in which the voltage of the output terminal rises within an image display period Device. The method of claim 1,
The level shifter is
and a period in which any one of the gate clocks for determining the voltage rise timing of the output terminal is input is set as the image display period. 3. The method of claim 2,
The level shifter is
a first OR element receiving a gate clock and outputting a first mask signal when any one of the gate clocks is input; and
a second OR element receiving the output of the first OR element and the reference signal, and outputting a second mask signal of a high level at all times when the first mask signal is input;
Display for outputting the first high potential voltage or the second high potential voltage when the output of the second OR element is a high potential voltage, and outputting a low potential voltage when the output of the second OR element is at a low level Device. 4. The method of claim 3,
The level shifter is
and a logic control unit for determining a section in which the output of the second OR element is a low level as an idle section, and determining a high-level section divided by the idle section as an output section,
The logic control unit
setting the odd-th output section as a first output section, and outputting a first control signal of a high level during the first output section,
A display device configured to set the even-th output section as a second output section to output a second control signal having a high level during the second output section. 5. The method of claim 4,
The logic controller
A display device for determining the idle period in a vertical blank period during which no image is displayed. 5. The method of claim 4,
The shift register is
a pull-up transistor including a gate electrode connected to the QB node, a first electrode receiving a gate clock, and a second electrode connected to the output terminal;
a first pull-down transistor including a gate electrode connected to the first QB node, a first electrode connected to the output terminal, and a second electrode connected to a low potential voltage input terminal;
a second pull-down transistor including a gate electrode connected to the second QB node, a first electrode connected to the output terminal, and a second electrode connected to a low potential voltage input terminal;
a first QB node control unit providing the first high potential voltage to the first QB node during the first output period, and discharging the first QB node in a period in which the voltage of the output terminal rises; and
and a second QB node controller that provides the second high potential voltage to the second QB node during the second output period, and discharges the second QB node during a period in which the voltage of the output terminal increases.

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