KR102334428B1 - Display Device and Driving Method therof - Google Patents

Abstract

A display device of the present invention includes a display panel including a gate line and a shift register for outputting a gate pulse provided to the gate line. The shift register includes a node control circuit, a first output unit, and a second output unit. The node control circuit includes a Q node and a QB node. The first output unit receives the odd gate clock swinging between the first low potential voltage and the high level voltage, and generates odd gate pulses in response to potentials of the Q node and the QB node. The second output unit receives the even gate clock swinging between the second low potential voltage and the high level voltage, which is a voltage level lower than the first low potential voltage, and generates an even gate pulse in response to the potentials of the Q node and the QB node. and a second output unit.

Description

Display device and driving method thereof

The present invention relates to a display device and a driving method thereof.

In the display device, data lines and gate lines are arranged to be perpendicular to each other, and pixels are arranged in a matrix form. A video data voltage to be displayed is supplied to the data lines, and a gate pulse is sequentially supplied to the gate lines. A video data voltage is supplied to pixels of a display line to which a gate pulse is supplied, and video data is displayed while all display lines are sequentially scanned by the gate pulse.

A gate driving circuit for supplying gate pulses to the gate lines of a flat panel display generally includes a plurality of gate integrated circuits (hereinafter referred to as "ICs"). Since each gate drive IC has to sequentially output gate pulses, it basically includes a shift register, and may include circuits and output buffers for adjusting an output voltage of the shift register according to driving characteristics of the display panel.

In the display device, the gate driver generating a gate pulse, which is a scan signal, is sometimes implemented in the form of a gate-in-panel (GIP) formed by a combination of thin film transistors in a bezel region that is a non-display region of a display panel. The GIP type gate driver includes stages corresponding to the number of gate lines, and each stage outputs a gate pulse to a corresponding gate line on a one-to-one basis. Therefore, the bezel area increases by using the GIP structure because as many stages as the number of gate lines are required.

In order to solve the above problems, the present invention is to provide a display device capable of reducing a bezel area.

As a means for solving the above problems, the display device of the present invention includes a display panel including a gate line and a shift register for outputting a gate pulse provided to the gate line. The shift register includes a node control circuit, a first output unit, and a second output unit. The node control circuit includes a Q node and a QB node. The first output unit receives the odd gate clock swinging between the first low potential voltage and the high level voltage, and generates odd gate pulses in response to potentials of the Q node and the QB node. The second output unit receives the even gate clock swinging between the second low potential voltage and the high level voltage, which is a voltage level lower than the first low potential voltage, and generates an even gate pulse in response to the potentials of the Q node and the QB node. and a second output unit.

In the display device of the present invention, since the stages of the shift register each output a pair of gate pulses, the number of stages can be reduced. In particular, according to the present invention, the timing at which the even gate clock is polled can be prevented from being delayed by differentiating the low potential voltages of the odd gate clock and the even gate clock input to the stage. Accordingly, the present invention can improve the horizontal dim phenomenon that occurs when the polling time of the even gate clock is delayed.

1 is a diagram showing the configuration of a display device according to the present invention.
2 is a diagram illustrating a shift register according to an embodiment;
3 is a diagram illustrating a stage of a shift register according to an embodiment;
4 is a diagram illustrating embodiments of an output unit;
Fig. 5 is a waveform diagram showing input and output signals of a stage;
6 is a view for explaining the cause of the horizontal dim phenomenon occurs.
7 is a view showing an input signal of a stage according to the second embodiment;
Fig. 8 is a view showing a display device according to a second embodiment;

Hereinafter, preferred embodiments according to the present invention will be described in detail with a focus on a liquid crystal display device with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. The names of components used in the following description are selected in consideration of the ease of writing the specification, and may be different from the names of the actual products.

1 is a block diagram showing a display device according to an embodiment of the present invention. Referring to FIG. 1 , the display device of the present invention includes a display panel 100 , a timing controller 110 , a data driving circuit, and gate driving circuits 130 and 140 .

The display panel 100 includes a display area 100A in which sub-pixels are formed and a non-display area 100B in which various signal lines or pads are formed outside the display area 100A. The display area 100A includes a plurality of pixels P, and displays an image based on a gray level displayed by each pixel P. A plurality of pixels P are arranged in a matrix form on each of the horizontal lines. Each of the pixels P is formed in a region where the data line DL and the gate line GL orthogonal to each other cross each other. The gate line GL includes first to m-th (m is a natural number) odd gate lines GL_O1 to GL_Om and first to m-th even gate lines GL_E1 to GL_Em. The ith (i is a natural number equal to or less than m) odd gate line GL_Oi and ith even gate line GL_Ei are arranged adjacent to each other.

Each pixel P has a pixel circuit PC operating in response to the data signal DATA supplied in response to the scan signal supplied through the switching element SW connected to the gate line GL and the data line DL. includes The pixel circuit PC and the switching element SW may be implemented in different forms depending on the type of the display panel.

The timing controller 110 receives the timing of the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the data enable signal (Data Enable, DE), the main clock (MCLK) from the host computer through the LVDS or TMDS interface receiving circuit. signal is input. The timing controller 110 generates timing control signals for controlling operation timings of the data driving circuit and the gate driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the gate driving circuit, and a data timing control signal for controlling the operation timing of the source drive ICs 120 and the polarity of the data voltage.

The scan timing control signal includes a gate start pulse VST, odd and even gate clocks CLK_O and CLK_E, a rear end signal NEXT, and the like. The gate start pulse VST is input to the shift register 130 to control the shift start timing. The odd and even gate clocks CLK_O and CLK_E are level-shifted through the level shifter 150 and then input to the shift register 130 . The downstream signal NEXT initializes each node of the shift register 140 after the shift register 140 outputs a pair of odd gate pulses Gout_O and even gate pulses Gout_E.

The data timing control signal is a source start pulse (Source Start Pulse, SSP), a source sampling clock (SSC), a polarity control signal (Polarity, POL), and a source output enable signal (Source Output Enable, SOE), etc. includes The source start pulse SSP controls shift start timing of the source drive ICs 120 . The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 120 based on a rising or falling edge.

The data driving circuit includes a plurality of source drive ICs 120 . Each source drive IC 120 receives digital video data RGB from the timing controller 110 . The source drive IC 120 converts digital video data RGB into a gamma compensation voltage in response to a source timing control signal from the timing controller 110 to generate a data voltage, and synchronizes the data voltage with the gate pulse. It is supplied to data lines of the display panel 100 .

The gate driving circuit includes a level shifter 130 and a shift register 140 connected between the timing controller 110 and the gate lines of the display panel 100 .

The level shifter 130 converts the transistor-transistor-logic (TTL) logic level voltages of the odd and even gate clocks CLK_O and CLK_E input from the timing controller 110 to a gate high voltage VGH and a gate low voltage VGL. ) to level shift.

The shift register 140 shifts the start pulse VST to match the odd and even gate clocks CLK_0 and CLK_E, and includes stages that sequentially output a carry signal and a gate pulse Gout.

The gate driving circuit may be formed on the lower substrate of the display panel 100 in a GIP (Gate In Panel) method. In the GIP method, the level shifter 150 may be mounted on the PCB 140 , and the shift register 130 may be formed on the lower substrate of the display panel 100 .

2 is a view showing the shift register 140 according to the present invention.

Referring to FIG. 2 , the gate shift register 140 according to the present invention includes first to m-th stages ST1 to STm that are sequentially connected. The ith stage STi outputs an ith odd gate pulse Gout_Oi and an ith even gate pulse Gout_Ei. As described above, in the shift register 140 of the present invention, since each stage outputs a pair of gate pulses, only half of the stages are used compared to the total number of gate lines GL. The shift register 140 may be formed outside the display area 100A of the display panel 100 as shown in FIG. 1 . That is, since the number of shift registers 140 formed in the so-called bezel area of the display panel 100 can be reduced by half, the bezel area can be reduced.

The gate pulse may be applied to the gate lines of the display device and used as a carry signal transmitted to the previous stage and the subsequent stage.

In the following description, the term "front stage" refers to being located above the stage as a reference. For example, with respect to the i-th stage STi, the previous stage indicates any one of the first stage ST1 to the (i-1)-th stage ST[i-1). The “rear stage” refers to being located below the stage as a reference. For example, with respect to the i-th stage STi, the subsequent stage indicates any one of the (i+1)-th stage ST[i+1] to the m-th stage.

3 is a block diagram illustrating the configuration of the stage i (i is a natural number where 2 < i < n) in FIG. 2 , and FIG. 4 is a diagram illustrating an embodiment of the output unit 133 shown in FIG. 3 .

3 and 4 , the i-th stage STi includes a node control circuit NCON and an output unit 133 .

The node control circuit NCON receives the gate timing control signal to control the Q node Q and the QB node QB. The potential of the Q node Q controls the operation of the pull-up transistors Tpu_O and Tpu_E of the output unit 133 , and the potential of the QB node QB is the potential of the pull-down transistors Tpd_O and Tpd_E of the output unit 133 . to control The node control circuit NCON receives a start pulse VST, a post-end signal NEXT, and a high potential voltage VDD to control the Q node Q and the QB node QB. The start pulse VST controls the start of the operation of the stage ST, and the downstream signal NEXT controls the end of the operation of the stage ST. The node control circuit NCON controls the potentials of the Q node Q and the QB node QB by controlling the start pulse VST and the downstream signal NEXT, and the odd gate clock input to the output unit 133 (CLK_O) and the even gate clock (CLK_E) are output as odd gate pulses Gout_O and even gate pulses Gout_E, respectively. The node control circuit NCON may initialize each node using the low potential voltage VSS. In this case, as the low potential voltage VSS, a gate low voltage may be used, or a voltage lower than the gate low voltage may be used to improve a short circuit in a circuit.

The output unit 133 includes first and second output units 135 and 137 . The first output unit 135 outputs an odd gate pulse Gout_O, and the second output unit 137 outputs an even gate pulse Gout_E.

The first output unit 135 includes a first pull-up transistor Tpu_O and a first pull-down transistor Tpd_O. The gate electrode of the first pull-up transistor Tpu_O is connected to the Q node Q, the first electrode is connected to the odd gate clock CLK_O, and the second electrode is connected to the odd output terminal no_O. The gate electrode of the first pull-down transistor Tpd_O is connected to the QB node QB, the first electrode is connected to the odd output terminal no_O, and the second electrode is connected to the low potential voltage source VSS.

The first pull-up transistor Tpu_O outputs the odd gate clock CLK_O received through the first electrode as an odd gate pulse Gout in response to the high level voltage of the Q node Q. The first pull-down transistor Tpd_O discharges the voltage of the odd output terminal no_O to the low potential voltage VSS in response to the high level voltage of the QB node QB.

The second output unit 137 includes a second pull-up transistor Tpu_E and a second pull-down transistor Tpd_E. The gate electrode of the second pull-up transistor Tpu_E is connected to the Q node Q, the first electrode is connected to the even gate clock CLK_E, and the second electrode is connected to the low potential voltage source VSS. The gate electrode of the second pull-down transistor Tpd_E is connected to the QB node QB, the first electrode is connected to the even output terminal no_E, and the second electrode is connected to the low potential voltage source VSS.

The second pull-up transistor Tpu_E outputs the even gate clock CLK_E received through the first electrode as an even gate pulse Gout_E in response to the high level voltage of the Q node Q. The second pull-down transistor Tpd_E discharges the voltage of the even output terminal no_E to the low potential voltage VSS in response to the high level voltage of the QB node QB.

5 is a diagram illustrating a waveform for driving a shift register according to the present invention and an output waveform of the node control circuit according thereto. The driving method of the present invention will be described with reference to FIG. 5 as follows.

During the first period t1 , the node control circuit NCON receives the start pulse VST and charges the Q node Q.

During the second period t2 , the first pull-up transistor Tpu_O of the first output unit 135 receives the odd gate clock CLK_O, and the second pull-up transistor Tpu_E of the second output unit 137 is An even gate clock (CLK_O) is received. Since the second period t2 corresponds to the output period of the odd gate pulse Gout_O, it is set to one horizontal period or more, for example, it is set to a period of two or more horizontal periods for overlap driving of the gate pulse. can be The odd gate clock CLK_O swings between the first low potential voltage VSS1 and the high level voltage. The first low potential voltage VSS1 may use the gate low voltage VGL, and the high level voltage may use the gate high voltage VGH. The even gate clock CLK_E swings between the second low potential voltage VSS2 and the high level voltage. The second low potential voltage VSS2 may use a voltage lower than the first low potential voltage VSS1 , and the high level voltage may use the gate high voltage VGH.

The voltage level of the first electrode of the first pull-up transistor Tpu_O is increased by the odd gate clock CLK_O, and the gate electrode of the first pull-up transistor Tpu_O is bootstrapped ( bootstrap). As described above, when the gate-source potential reaches the threshold voltage Vth while the gate electrode of the first pull-up transistor Tpu_O is bootstrapped, the first pull-up transistor Tpu_O is turned on. As the first pull-up transistor Tpu_O is turned on, it outputs the odd gate clock CLK_O provided through the first electrode as an odd gate pulse Gout_O.

The voltage level of the first electrode of the second pull-up transistor Tpu_E is increased by the even gate clock CLK_E, and the gate electrode of the second pull-up transistor Tpu_E is bootstrapped according to the increase of the voltage level of the first electrode. . As such, when the gate-source potential reaches the threshold voltage Vth while the gate electrode of the second pull-up transistor Tpu_E is bootstrapped, the second pull-up transistor Tpu_E is turned on. As the second pull-up transistor Tpu_E is turned on, it outputs the even gate clock CLK_E received through the first electrode as an even gate pulse Gout_E.

At the end of the second period t2 , the odd gate clock CLK_O is inverted to a low potential, and accordingly, the first output unit 135 does not output the odd gate pulse Gout_O. As the first pull-up transistor Tpu_O discharges the potential of the odd output terminal no_O, the potential of the bootstrapped gate electrode decreases. Accordingly, the potential of the Q node Q connected to the gate electrode of the first pull-up transistor Tpu_O also decreases from 'V1' to 'V2'.

During the third period t3, the even gate clock CLK_E maintains a high level voltage to output the even gate pulse Gout_E following the second period t2. Since the third period is a period for scanning the even gate line GL_E using the even gate pulse Gout_E, it may be set to one horizontal period.

At the end of the third period t3 , the even gate clock CLK_E is inverted to a low potential, and the second output unit 137 does not output the even gate pulse Gout_E. And as the second pull-up transistor Tpu_E discharges the potential of the even output terminal no_E, the potential of the gate electrode decreases. As the gate potential of the second pull-up transistor Tpu_E decreases, the potential of the Q node Q connected to the gate electrode of the second pull-up transistor Tpu_E also decreases from 'V2' to 'V3'.

After a predetermined transition period has elapsed so that the third period t3 ends and the even gate pulse Gout_E is completely discharged, the back-end signal NEXT is provided to the node control circuit NCON during the fourth period t4 to provide the Q node ( Q) and QB node (QB) are initialized.

The timing at which the voltage levels of the odd gate clock CLK_O and the even gate clock CLK_E are inverted from the high level to the low level determines the falling timing of the gate pulse. That is, as the voltage level of the odd gate clock CLK_O and the even gate clock CLK_E is inverted from the high level to the low level is delayed, the falling time of the gate pulse is delayed. The timing at which the voltage level of the gate clock is inverted is inversely proportional to the gate-source potential of the pull-up transistor. In other words, the greater the gate-source potential difference of the pull-up transistor, the faster the gate clock is inverted from the high level to the low level. That is, as the gate-source potentials of the first and second pull-up transistors increase, the odd and even gate pulses Gout_O and Gout_E fall earlier.

The shift register 140 of the present invention uses the second low potential voltage VSS2 of the even gate clock CLK_E as a voltage lower than the first low potential voltage VSS1 of the odd gate clock CLK_O. Accordingly, since the shift register 140 can speed up the even gate clock CLK_E's polling time, it prevents the even gate clock CLK_E's polling time from being delayed from that of the odd gate clock (CLK_O).

A method in which the shift register 140 according to the present invention synchronizes the polling timing of the odd gate pulse Gout_O and the polling timing of the even gate pulse Gout_E is as follows.

The odd gate clock CLK_O is inverted from the high level voltage to the low level voltage at the end of the second period t2 . In this case, the potential of the Q node Q corresponds to the first voltage level V1. That is, the potential of the gate electrode of the first pull-up transistor Tpu_O at the moment when the odd gate clock CLK_O is polled is the first voltage level V1, and the potential of the second electrode serving as the source electrode is the odd gate clock CLK_O. It corresponds to the high-level potential of The voltage of the second electrode of the first pull-up transistor Tpu_O becomes the first low potential voltage VSS1 as the voltage level of the odd gate clock CLK_O is inverted.

In contrast, the even gate clock CLK_E is inverted from the high level voltage to the low level voltage at the end of the third period t3 . At this time, the potential of the Q node Q corresponds to the second voltage level V2. That is, the potential of the gate electrode of the second pull-up transistor Tpu_E at the moment when the even gate clock CLK_E is polled corresponds to the high level potential of the even gate clock CLK_E. The voltage of the second electrode of the second pull-up transistor Tpu_E becomes the second low potential voltage VSS2 as the voltage level of the even gate clock CLK_E is inverted.

As such, the gate electrode voltage of the second pull-up transistor Tpu_E at the moment when the even gate clock CLK_E is polled is higher than the gate electrode voltage of the first pull-up transistor Tpu_O at the moment the odd gate clock CLK_O is polled. lowers In the present invention, the voltage level of the second low potential voltage VSS2 of the even gate clock CLK_E is to compensate for the decrease in the potential difference between the gate electrode and the source electrode due to the decrease in the gate electrode voltage level of the second pull-up transistor Tpu_O. is lower than the voltage level of the first low potential voltage VSS1. At this time, the voltage level of the second low potential voltage VSS is the difference between the first low potential voltage VSS1 and the second low potential voltage VSS2 is the difference between the first voltage level VSS1 and the second voltage level VSS2 set to correspond to

As described above, the present invention compensates for the lowering of the voltage level between the gate-source electrode of the second pull-up transistor Tpu_O, thereby preventing the delay of the falling timing of the even gate clock CLK_E.

The shift register 140 of the present invention may prevent the odd gate clock CLK_O and the even gate clock CLK_E from having different polling times, thereby improving the occurrence of a horizontal dim phenomenon between adjacent horizontal lines. Looking at this:

As shown in FIG. 6 , it takes a certain time until the data voltage Vdata provided to the pixel P is saturated. If the odd gate pulse Gout_O and the even gate pulse Gout_E are polled before the data voltage Vdata is saturated, the data charging time by each gate pulse is different. For example, as shown in the figure, if the falling times of the odd gate pulse Gout_O and the even gate pulse Gout_E are different by 'Δtf', the pixel receiving the odd gate pulse Gout_O and the even gate pulse Gout_E The data voltage charge amount is different for the pixels receiving 'ΔV1'. As a result, a luminance difference equal to the voltage difference of 'ΔV1' is displayed between the pixels on the odd horizontal line and the pixels on the even horizontal line. Such a luminance difference eventually causes a horizontal dim phenomenon between adjacent horizontal lines.

However, since the shift register 140 according to the present invention can prevent the delay of the polling timing of the even gate pulse Gout_E, the polling timing between the odd gate pulse Gout_O and the even gate pulse Gout_E is different. can be prevented Accordingly, it is possible to prevent a horizontal dim phenomenon from occurring due to a difference in the polling timing between the odd gate pulses Gout_O and the even gate pulses Gout_E.

7 is a diagram illustrating a waveform of a gate clock according to the second embodiment. In the second embodiment, a detailed description of a configuration substantially the same as that of the above-described embodiment will be omitted.

Referring to FIG. 7 , the odd gate clock CLK_O swings between the first low potential voltage VSS and the gate high voltage VGH. And the first even gate clock CLK_E swings between the second low potential voltage VSS2 and the gate high voltage VGH, and the second even gate clock CLK_E is the third low potential voltage VSS3 and the gate high voltage. Swings between voltages (VGH). The third low potential voltage VSS3 is set to a voltage level lower than the voltage level of the second low potential voltage VSS2.

The first even gate clock CLK_1E is provided to the first panel block PB1 , and the second even gate clock CLK_2E is provided to the second panel block PB2 . The first panel block PB1 is a horizontal line group located close to the source drive IC 120 , and the second panel block PB2 is a horizontal line group located far from the source drive IC 120 . The number of horizontal lines included in each of the first and second panel blocks PB1 and PB2 may not be the same.

The even gate clock CLK_E is delayed due to the panel load toward the lower end of the panel. Accordingly, the delay in the polling time of the even gate clock CLK_E becomes severe as it goes toward the lower part of the panel.

In the second embodiment, the second even gate clock CLK_2E provided to the second panel block PB2 is higher than the second low potential voltage VSS2 of the first even gate clock CLK_1E provided to the first panel block PB1. ), the third low potential voltage VSS3 is set low to improve the occurrence of a large deviation in the polling timing toward the lower end of the panel.

Of course, in the second embodiment described with reference to FIGS. 7 and 8 , the number of panel blocks and the low potential voltage of each even gate clock CLK_E may be variously changed.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130: level shifter
140: shift register

Claims (10)

a display panel including a gate line; and
a shift register for outputting a gate pulse provided to the gate line;
The shift register is
a node control circuit including a Q node and a QB node;
an odd pull-up transistor having a gate electrode connected to the Q node, a first electrode receiving an odd gate clock, and a second electrode connected to an odd output terminal; and an odd pull-down transistor having a gate electrode connected to the QB node, a first electrode connected to a low potential voltage source, and a second electrode connected to the odd output terminal, receiving the odd gate clock input to receive the Q node and QB node a first output unit for generating odd gate pulses in response to the potential of ; and
an even pull-up transistor having a gate electrode connected to the Q node, a first electrode receiving an even gate clock, and a second electrode connected to an even output terminal; and an even pull-down transistor having a gate electrode connected to the QB node, a first electrode connected to a low potential voltage source, and a second electrode connected to the even output terminal. a second output unit for generating an even gate pulse in response to an electric potential;
The odd gate clock swings between a first low potential voltage and a high level voltage,
The even gate clock swings between a second low potential voltage that is a voltage level lower than the first low potential voltage and the high level voltage.
delete The method of claim 1,
The node control circuit is
The Q node and the QB node are charged using a high potential voltage,
A display device for discharging the Q node and the QB node using the second low potential voltage.
The method of claim 1,
The high level voltage includes a gate high voltage,
The first low potential voltage includes a gate low voltage,
The second low potential voltage is lower than the gate low voltage.
The method of claim 1,
The gate lines include first to mth (m is a natural number) odd gate lines and first to mth even gate lines, and the shift register includes first to mth shift resistors,
The first even gate clock input to the second output unit of the first to i-th (i is a natural number less than or equal to m) shift register swings between the second low potential voltage and the high level voltage,
The second even gate clock input to the second output unit of the (i+1)th to mth shift registers swings between the third low potential voltage lower than the voltage level of the second low potential voltage and the high level voltage. display device.
delete a first step of charging the Q node of the shift register;
a second step of outputting an odd gate pulse by inputting an odd gate clock of a high level voltage to a first output unit of the shift register;
a third step of inputting an even gate clock of a high level voltage to a second output unit of the shift register and outputting an even gate pulse;
a fourth step of discharging the odd gate clock of the high level voltage to a first low potential voltage; and
a fifth step of discharging the even gate clock of the high level voltage to a second low potential voltage of a voltage level lower than the first low potential voltage;
The first output unit,
an odd pull-up transistor having a gate electrode connected to the Q node, a first electrode receiving the odd gate clock, and a second electrode connected to an odd output terminal; and
an odd pull-down transistor having a gate electrode connected to the QB node, a first electrode connected to a low potential voltage source, and a second electrode connected to the odd output terminal,
The second output unit,
an even pull-up transistor having a gate electrode connected to the Q node, a first electrode receiving the even gate clock, and a second electrode connected to an even output terminal; and
and an even pull-down transistor having a gate electrode connected to the QB node, a first electrode connected to a low potential voltage source, and a second electrode connected to the even output terminal.
8. The method of claim 7,
In the second step, the Q node is bootstrapped to a first voltage level,
When the Q node is reduced to a second voltage level in the fourth step,
The fifth step is
and setting a third low potential voltage level so that the voltage difference between the second low potential voltage and the third low potential voltage corresponds to the voltage difference between the first voltage level and the second voltage level.
a display panel including a gate line; and
a shift register for outputting a gate pulse provided to the gate line;
The shift register is
a node control circuit including a Q node and a QB node;
a first output unit receiving an odd gate clock swinging between a first low potential voltage and a high level voltage, and generating an odd gate pulse in response to potentials of the Q node and the QB node; and
a second low potential voltage, which is a voltage level lower than the first low potential voltage, which receives an even gate clock swinging between the high level voltage, and generates an even gate pulse in response to potentials of the Q node and QB node 2 comprising an output;
The gate lines include first to mth (m is a natural number) odd gate lines and first to mth even gate lines, and the shift register includes first to mth shift resistors,
The even gate clock input to the second output unit of the first to i-th (i is a natural number less than or equal to m) shift register swings between the second low potential voltage and the high level voltage,
The even gate clock input to the second output unit of at least one of the (i+1)-th to the m-th shift register is the high voltage at a third low potential voltage lower than the voltage level of the second low potential voltage. A display device that swings between level voltages. delete

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