KR102476465B1 - Gate Driving Circuit and Organic Light Emitting Display having the Same - Google Patents

Abstract

A display device according to the present invention includes a display panel and a gate driving circuit. A plurality of gate lines are disposed on the display panel to supply a gate pulse to each of the pixels. The gate driving circuit is composed of a plurality of stages that are dependently connected to each other, and the stages respectively supply gate pulses to a pair of gate lines among the gate lines. A pair of gate pulses output from one stage do not overlap with each other.

Description

Gate driving circuit and organic light emitting display including the same {Gate Driving Circuit and Organic Light Emitting Display Having the Same}

The present invention relates to a gate driving circuit capable of improving a voltage deviation of a gate pulse while reducing a bezel, and an organic light emitting display device including the same.

A flat panel display (FPD) is widely used in portable computers such as laptop computers and tablets as well as desktop computer monitors and mobile phone terminals due to advantages of miniaturization and light weight. Currently, various types of display devices, such as curved displays, flexible displays, rollable displays, and wearable displays, as well as flat panel displays are being developed. have. These display devices are liquid crystal displays {Liquid Crystal Display; LCD), Plasma Display Panel (PDP), Field Emission Display; FED), Organic Light Emitting Diode Display (OLED), and Quantum Dot Display (QD).

The pixels of the display device are driven by receiving a data voltage synchronized with the gate pulse. A gate driving circuit that generates a gate pulse may be implemented in the form of a gate-in-panel (hereinafter referred to as GIP) consisting of a combination of thin film transistors in a bezel area, which is a non-display area, of a display panel. Recently, in order to reduce a bezel, a method for reducing the size of a GIP-type gate driving circuit has been sought.

An organic light emitting display device according to the present specification is to provide a gate driving circuit capable of reducing a bezel and an organic light emitting display device including the gate driving circuit.

A display device according to the present invention includes a display panel and a gate driving circuit. A plurality of gate lines are disposed on the display panel to supply a gate pulse to each of the pixels. The gate driving circuit is composed of a plurality of stages that are dependently connected to each other, and the stages respectively supply gate pulses to a pair of gate lines among the gate lines. A pair of gate pulses output from one stage do not overlap with each other.

Since the gate driving circuit according to the present invention generates a pair of gate pulses using one stage, the bezel in which the gate driving circuit is disposed can be reduced.

In particular, the gate driving circuit according to the present invention can improve a voltage deviation between gate pulses even in a display device in which overlap driving is performed.

1 is a diagram showing the configuration of a display device according to the present invention.
2 is a diagram showing stages of a gate driving circuit according to the present invention.
3 is a diagram showing a stage according to the first embodiment.
FIG. 4 is a diagram illustrating driving signals of the gate driving circuit shown in FIG. 3 .
5 is a diagram showing a stage according to a comparative example.
FIG. 6 is a diagram illustrating driving signals of the gate driving circuit shown in FIG. 5 .
7 is a diagram showing a stage according to a second embodiment.
FIG. 8 is a diagram illustrating driving signals of the gate driving circuit shown in FIG. 7 .

Advantages and features of this specification, and methods of achieving them, will become clear with reference to embodiments described below in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments make the disclosure of this specification complete, and the common knowledge in the technical field to which this specification belongs. It is provided to fully inform the owner of the scope of the invention, and this specification is only defined by the scope of the claims.

Switch elements in the gate driving circuit of the present specification may be implemented as n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors. Although n-type transistors are exemplified in the following embodiments, the present specification is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in an n-type MOSFET, the direction of current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. The source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on the applied voltage. The invention is not limited by the sources and drains of the transistors in the following embodiments.

1 is a view showing a display device according to an embodiment of the present invention.

Referring to FIG. 1 , the display device of the present invention includes a display panel 100 , a timing controller 110 , a data driving circuit 120 , and gate driving circuits 130 and 140 .

The display panel 100 includes a display portion 100A on which pixels P are disposed to display an image and a non-display portion 100B on which a gate driving circuit 140 is disposed and does not display an image.

The display unit 100A includes a plurality of pixels P, and displays an image based on a gray level displayed by each pixel P. The pixels P are arranged along the first to nth pixel lines HL1 to HLn. Each pixel P is connected to a data line DL arranged along a column line and connected to a gate line GL arranged along a pixel line HL.

The timing controller 110 receives timing signals such as a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (Data Enable, DE), and a main clock (MCLK) from a host system (not shown). . The timing controller 110 generates timing control signals for controlling operation timings of the data driving circuit 120 and the gate driving circuits 130 and 140 based on timing signals received from the host system. The timing control signals include a scan timing control signal for controlling the operation timing of the gate driving circuits 130 and 140 and a data timing control signal for controlling the operation timing of the data driving circuit 120 and the polarity of the data voltage.

The scan timing control signal includes a start signal VST and a gate clock CLK. The start signal VST is input to the shift register 130 to control shift start timing. The gate clock (CLK) is input to the shift register 130 after level shifting through the level shifter 130.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). The source start pulse SSP controls shift start timing of the source drive ICs 120 . The source sampling clock SSC is a gate clock that controls sampling timing of data within the source drive ICs 120 based on a rising or falling edge.

The data driving circuit 120 receives digital video data RGB from the timing controller 110 . The data driving circuit 120 generates a data voltage by converting digital video data in response to a source timing control signal from the timing controller 110, and synchronizes the data voltage with the gate pulse of the data line of the display panel 100. (DL).

The gate driving circuit includes a level shifter 130 and a shift register 140 connected between the timing controller 110 and the gate lines of the display panel 100 .

The level shifter 130 level-shifts the transistor-transistor-logic (TTL) logic level voltage of the gate clock CLK input from the timing controller 110 .

The shift register 140 is composed of stages that sequentially output a carry signal and a gate pulse Gout by shifting the start signal VST according to the gate clock CLK. The shift register 140 may be formed on a lower substrate of the display panel 100 in a Gate In Panel (GIP) method.

2 is a diagram showing stages of a shift register according to the present invention.

Referring to FIG. 2, the kth (k is a natural number less than n) stage STGk according to the present invention satisfies the kth gate pulse Gout_k and the (k+i)th (i is k+i≤n condition). 2 or more natural numbers) outputs the gate pulse (Gout(k+i)).

The kth stage STGk includes a node control unit NCON[k], a pre-buffer unit BUF[k], and a post-buffer unit BUF[k+i].

The node controller NCON[k] controls voltages of the Q node and the QB node. The node control unit NCON[k] includes a start control unit T1, an inverter INV, and a reset unit T2.

The start controller T1 precharges the Q node in response to the start signal VST. The inverter INV controls the voltages of the Q node and the QB node to have voltage levels opposite to each other. That is, the inverter INV controls the voltage of the QB node to the turn-off voltage level when the Q node is at the turn-on voltage level, and controls the voltage at the Q node to the turn-off voltage level when the QB node is at the turn-on voltage level. controlled by level. The reset unit T2 discharges the Q node to the low potential voltage VSS in response to the next stage signal NEXT[k].

The pre-buffer unit BUF[k] outputs the kth gate pulse Gout[k], and the post buffer unit BUF[k+i] outputs the (k+i)th gate pulse Gout[k+i]. ]).

The pre-buffer unit BUF[k] includes a pre-pull-up transistor Tpu[k] and a pre-pull-down transistor Tpd[k]. The pre-pull-up transistor Tpu[k] includes a gate electrode connected to the Q node, a drain electrode receiving a free gate clock CLK[1], and a source electrode connected to the pre-output terminal Nout[k]. . The pre-pull-up transistor Tpu[k] charges the pre-output terminal Nout[k] using the gate clock CLK1 applied to the drain electrode in a state where the Q node is precharged. The pre-pull-down transistor Tpd[k] includes a gate electrode connected to the QB node, a drain electrode connected to the pre-output terminal Nout[k], and a source electrode connected to the input terminal of the low potential voltage VSS. The pre-pull-down transistor Tpd[k] discharges the voltage of the pre-output terminal Nout[k] to the low potential voltage VSS in response to the voltage of the QB node.

The post buffer unit BUF[k+i] includes a post pull-up transistor Tpu[k+i] and a post-pull-down transistor Tpd[k+i]. The post pull-up transistor (Tpu[k+i]) has a gate electrode connected to the Q node, a drain electrode receiving a post gate clock (CLK[1+i]), and a post output terminal (Nout[k+i]). It includes a source electrode that becomes The post pull-up transistor (Tpu[k+i]) uses the post gate clock (CLK[1+i]) applied to the drain electrode in a state where the Q node is precharged to generate the post output terminal (Nout[k+i]). to charge The post pull-down transistor (Tpd[k+i]) has a gate electrode connected to the QB node, a drain electrode connected to the post output terminal (Nout[k+i]), and a source electrode connected to the input terminal of the low potential voltage (VSS). includes The post pull-down transistor Tpd[k+i] discharges the voltage of the post output terminal Nout[k+i] to the low potential voltage VSS in response to the voltage of the QB node.

Since the kth stage of the present invention outputs a pair of gate pulses, the size of the shift register 140 can be reduced. That is, when the number of gate lines GL is n (where n is an even natural number), the shift register 140 is applied to the first to nth pixel lines HL1 to HLn using n/2 stages. The arranged pixels P may be driven.

3 is a diagram showing first and second stages according to the first embodiment.

Referring to FIG. 3 , the first stage according to the first embodiment includes a first node controller NCON and first and third buffer units BUF1 and BUF3. The first buffer unit BUF1 includes a first pull-up transistor Tpu1 and a first pull-down transistor Tpd1, and the third buffer unit BUF3 includes a third pull-up transistor Tpu3 and a third pull-down transistor Tpd3. includes The second stage includes a second node controller NCON2 and second and fourth buffer units BUF2 and BUF4. The second buffer unit BUF2 includes a second pull-up transistor Tpu2 and a second pull-down transistor Tpd2, and the fourth buffer unit BUF4 includes a fourth pull-up transistor Tpu4 and a fourth pull-down transistor Tpd4. includes

The pre-pull-up transistor Tpu[k] of the first stage corresponds to the first pull-up transistor Tpu1, and the pre-pull-down transistor Tpd[k] corresponds to the first pull-down transistor Tpd1. The post pull-up transistor Tpu[k+i] of the first stage corresponds to the third pull-up transistor Tpu3, and the post-pull-down transistor Tpd[k+i] corresponds to the third pull-down transistor Tpd3. The pre output terminal Nout[k] of the first stage corresponds to the first output terminal Nout1, and the post output terminal Nout[k+i] corresponds to the third output terminal Nout3.

The pre-pull-up transistor Tpu[k] of the second stage corresponds to the second pull-up transistor Tpu2, and the pre-pull-down transistor Tpd[k] corresponds to the second pull-down transistor Tpd2. The post pull-up transistor Tpu[k+i] of the second stage corresponds to the fourth pull-up transistor Tpu4, and the post-pull-down transistor Tpd[k+i] corresponds to the fourth pull-down transistor Tpd4. The pre output terminal Nout[k] of the second stage corresponds to the second output terminal Nout2, and the post output terminal Nout[k+i] corresponds to the fourth output terminal Nout4.

4 is a diagram showing the timing of signals driving the first stage.

Referring to FIGS. 3 and 4 , the operation of the first stage is as follows.

At the first timing t1, the first node controller NCON1 receives the start pulse VST and precharges the Q node. At the first timing t1, the voltage of the Q node becomes the precharge voltage Vp.

At the second timing t2, the first pull-up transistor Tpu1 receives the first gate clock CLK1 through the drain electrode and charges the Q node. The voltage of the drain electrode of the first pull-up transistor Tpu1 rises due to the first gate clock CLK1, and as a result, the Q node is bootstrapping. The Q node rises from the precharge voltage Vp to the first bootstrapping voltage Vb1, and the first output terminal Nout1 outputs the first gate pulse Gout1.

At the third timing t3, the first gate clock CLK1 becomes a low potential voltage, and the third gate clock CLK3 is applied to the drain electrode of the third pull-up transistor Tpu2. At the third timing t3 , bootstrapping by the first pull-up transistor Tpu1 does not occur because the first gate clock CLK1 has a low potential voltage. In the Q node, bootstrapping occurs only by the third gate clock CLK3 at the drain electrode of the third pull-up transistor Tpu2, and as a result, the Q node maintains the first bootstrapping voltage Vb1. The third pull-up transistor Tpu3 charges the third output terminal Nout3 using the third gate clock CLK3, and as a result, the third gate pulse Gout3 is output.

At the fourth timing t4, the voltage of the third gate clock CLK3 becomes the low potential voltage, and the voltage of the third output terminal Nout3 is also discharged to the low potential voltage VSS.

As described above, the first buffer unit BUF1 of the first stage according to the present invention receives the first gate clock CLK1, and the third buffer unit BUF3 receives the third gate clock CLK3. Since the first gate clock CLK1 and the third gate clock CLK3 do not overlap each other, the bootstrapping period of the first buffer unit BUF1 and the bootstrapping period of the third buffer unit BUF3 do not overlap. don't As a result, even when the first pull-up transistor Tpu1 and the third pull-up transistor Tpu3 are driven by sharing the Q node, the voltage of the third gate pulse Gout3 output from the third pull-up transistor Tpu3 is It is not affected by the bootstrapping voltage of the Q node by the pull-up transistor Tpu1.

A look at the first embodiment together with a comparative example is as follows.

FIG. 5 is a diagram showing stages of shift registers according to a comparative example, and FIG. 6 is a diagram showing the timing of gate clocks applied to the stages shown in FIG. 5 .

Referring to FIGS. 5 and 6 , the stage according to the comparison example precharges the Q node at a first timing t1 using the start signal VST applied to the node control unit NCON. As a result, at the first timing t1, the voltage of the Q node becomes the precharge voltage Vp.

At the second timing t2, the first pull-up transistor Tpu1 receives the first gate clock CLK1 through the drain electrode and charges the Q node. The voltage of the drain electrode of the first pull-up transistor Tpu1 rises due to the first gate clock CLK1, and as a result, the Q node is bootstrapping. The Q node rises from the precharge voltage Vp to the first bootstrapping voltage Vb1, and the first output terminal Nout1 outputs the first gate pulse Gout1.

At the third timing t3, the first gate clock CLK1 becomes a low potential voltage, and the third gate clock CLK3 is applied to the drain electrode of the second pull-up transistor Tpu2. As a result, the voltage of the Q node, which was the first bootstrapping voltage Vb1, becomes the second bootstrapping voltage Vb2 while being bootstrapped again. The second pull-up transistor Tpu2 charges the second output terminal Nout2 using the second gate clock CLK2, and as a result, the second gate pulse Gout2 is output.

At the fourth timing t4, the voltage of the first gate clock CLK1 becomes a low potential voltage, and the first output terminal Nout1 becomes a low potential voltage VSS. At the fourth timing t4, since the Q node is not affected by bootstrapping by the first pull-up transistor Tpu1, the voltage of the Q node is lowered to the first bootstrapping voltage Vb1.

At the fifth timing t5, the voltage of the second gate clock CLK2 becomes the low potential voltage, and the second output terminal Nout2 becomes the low potential voltage VSS.

As described above, the Q node of the stage according to the comparison example is bootstrapped by the second gate clock CLK2 in a state where it is bootstrapped by the first gate clock CLK1. The first gate pulse Gout1 is the source voltage of the first pull-up transistor Tpu1 whose gate voltage is the first bootstrapping voltage Vb1, and the second gate pulse Gout2 is the source voltage of the first pull-up transistor Tpu1 whose gate voltage is the second bootstrapping voltage Vb2. ) is the source voltage of the second pull-up transistor Tpu2. Since the second bootstrapping voltage Vb2 is higher than the first bootstrapping voltage Vb1, the initial voltage of the second gate pulse Gout2 is higher than the initial voltage of the first gate pulse Gout1. That is, since the delay of the second gate pulse Gout2 is reduced compared to the first gate pulse Gout1, the pixel P of the second pixel line HL2 receiving the second gate pulse Gout2 Compared to the pixels P of the first pixel line HL1 to which the first gate pulse Gout1 is applied, the charging time of the data voltage is increased. As a result, even though the pixels P of the second pixel line HL2 and the pixels P of the first pixel line HL1 are supplied with the same data voltage, luminance deviation may occur.

In contrast, in the stage according to the first embodiment of the present invention, the first and third gate clocks CLK1 and CLK3 respectively applied to the first and third pull-up transistors Tpu1 and Tpu3 sharing the Q node are do not overlap each other Therefore, since the bootstrapping period of the first buffer unit BUF1 and the bootstrapping period of the third buffer unit BUF3 do not overlap, the third gate pulse Gout3 output from the third pull-up transistor Tpu3 The voltage of is not affected by the bootstrapping voltage of the Q node by the first pull-up transistor Tpu1. As a result, the output voltages of the first gate pulse (Gout1) and the third gate pulse (Gout3) output in the first stage become equal, and the data voltage charging period of the pixels ( ) does not vary.

7 is a diagram showing first to third stages according to the second embodiment.

Referring to FIG. 7 , the first stage according to the first embodiment includes a first node controller NCON1 and first and fourth buffer units BUF1 and BUF4. The first buffer unit BUF1 includes a first pull-up transistor Tpu1 and a first pull-down transistor Tpd1, and the fourth buffer unit BUF4 includes a fourth pull-up transistor Tpu4 and a fourth pull-down transistor Tpd4. includes The second stage includes a second node controller NCON2 and second and fifth buffer units BUF2 and BUF5. The second buffer unit BUF2 includes a second pull-up transistor Tpu2 and a second pull-down transistor Tpd2, and the fifth buffer unit BUF5 includes a fifth pull-up transistor Tpu5 and a fifth pull-down transistor Tpd5. includes

The first stage according to the second embodiment includes a first node control unit NCON1 and first and fourth output units BUF1 and BUF4. The second stage includes a second node control unit NCON2 and second and fifth output units BUF2 and BUF5. The third stage includes a third node controller NCON, a third output unit BUF3, and a sixth output unit (not shown). The first stage outputs first and fourth gate pulses Gout1 and Gout4. The second stage outputs the second and fifth gate pulses Gout2 and Gout5, and the third stage outputs the third gate pulse Gout3 and the sixth gate pulse (not shown).

The pre-pull-up transistor Tpu[k] of the first stage corresponds to the first pull-up transistor Tpu1, and the pre-pull-down transistor Tpd[k] corresponds to the first pull-down transistor Tpd1. The post pull-up transistor Tpu[k+i] of the first stage corresponds to the fourth pull-up transistor Tpu4, and the post-pull-down transistor Tpd[k+i] corresponds to the fourth pull-down transistor Tpd4. The pre output terminal Nout[k] of the first stage corresponds to the first output terminal Nout1, and the post output terminal Nout[k+i] corresponds to the fourth output terminal Nout4.

8 is a diagram showing timing of signals driving the first stage. Referring to FIGS. 2, 7 and 8, the operation of the first stage is as follows.

At the first timing t1, the node control unit receives the start pulse VST and precharges the Q node. At the first timing t1, the voltage of the Q node becomes the precharge voltage Vp.

At the second timing t2, the first pull-up transistor Tpu1 receives the first gate clock CLK1 and charges the Q node. The voltage of the drain electrode of the first pull-up transistor Tpu1 rises due to the first gate clock CLK1, and as a result, the Q node is bootstrapping. The Q node rises from the precharge voltage Vp to the first bootstrapping voltage Vb1, and the first output terminal Nout1 outputs the first gate pulse Gout1.

At the third timing t3, the first gate clock CLK1 becomes a low potential voltage. As a result, bootstrapping by the first pull-up transistor Tpu1 does not occur, and the voltage of the Q node is lowered to the precharge voltage Vp.

At a fourth timing t4, the fourth gate clock CLK4 is applied to the drain electrode of the fourth pull-up transistor Tpu4, and the Q node rises again to the first bootstrapping voltage Vb1. The fourth pull-up transistor Tpu4 charges the fourth output terminal Nout4 using the fourth gate clock CLK4, and as a result, the fourth gate pulse Gout4 is output.

At the fifth timing t5, the voltage of the fourth gate clock CLK4 becomes a low potential voltage, and the voltage of the fourth output terminal Nout4 is discharged to the low potential voltage VSS.

As described above, the first pull-up transistor Tpu1 and the fourth pull-up transistor Tpu4 belonging to the stage according to the second embodiment output gate pulses using gate clocks that do not overlap with each other. Therefore, even when the first pull-up transistor Tpu1 and the fourth pull-up transistor Tpu4 are driven by sharing the Q node, the voltage of the 34th gate pulse output from the fourth pull-up transistor Tpu4 is the first pull-up transistor. It is not affected by the bootstrapping voltage of the Q node by (Tpu1).

Through the above description, those skilled in the art will know that various changes and modifications are possible without departing from the technical spirit of the present specification. Therefore, the technical scope of the present specification is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100: display panel 110: timing controller
120: data driving circuit 130, 140: gate driving circuit
NCON: Node Control

Claims (9)

a display panel on which a plurality of gate lines for supplying gate pulses to each of the pixels are disposed; and
It consists of a plurality of stages that are dependently connected to each other, and the stages include gate driving circuits respectively supplying gate pulses to a pair of gate lines among the gate lines;
The pair of gate pulses output by the stage do not overlap with each other,
The gate driving circuit,
a kth buffer unit outputting a kth gate pulse synchronized with a kth gate clock (k is a natural number) in response to the voltage of the Q node of the kth stage; and
and a k+i th buffer unit outputting a k+i th gate pulse synchronized with a k+i th gate clock (j is a natural number greater than or equal to 3) in response to the voltage of the Q node of the k th stage. According to claim 1,
Among the stages, the kth stage is
a node controller controlling a voltage of the Q node of the kth stage;
a pre-buffer unit outputting the k th gate pulse according to the voltage of the Q node of the k th stage; and
a post buffer unit outputting the (k+i)th gate pulse in response to the voltage of the Q node of the kth stage;
The kth gate pulse and the (k+i)th gate pulse do not overlap each other. According to claim 2,
The pre-buffer unit may include: a gate electrode connected to the Q node of the kth stage and a drain electrode receiving the kth gate clock; and a pre-pull-up transistor comprising a source electrode connected to the kth output terminal;
The post buffer unit may include a gate electrode connected to the Q node of the kth stage and a drain electrode receiving a (k+i)th gate clock; and a post pull-up transistor comprising a source electrode connected to the (k+i)th output terminal;
The output period of the first gate clock and the output period of the (k+i)th gate clock do not overlap each other. According to claim 3,
Among the stages, the (k+1)th stage outputs the (k+1)th gate pulse during the output period of the k+1th gate clock;
The k-th gate clock and the k+1-th gate clock overlap at least a portion of each other. According to claim 3,
The pre-buffer unit further includes a pre-pull-down transistor including a gate electrode connected to the QB node of the kth stage, a drain electrode connected to the kth output terminal, and a source electrode connected to a low potential voltage input terminal;
The post buffer unit includes a post pull-up transistor including a gate electrode connected to the QB node of the kth stage, a drain electrode connected to the (k+i)th output terminal, and a source electrode connected to the input terminal of the low potential voltage. A display device containing more. delete delete delete The method of claim 2, wherein the node control unit,
a first transistor having one end connected to a high potential voltage and the other end connected to the Q node of the kth stage to charge the Q node of the kth stage according to a start signal input to a gate electrode;
an inverter controlling voltages of the Q node of the k th stage and the QB node of the k th stage to have voltage levels opposite to each other; and
and a second transistor for discharging the Q node of the k-th stage to a low potential voltage in response to a signal at the next stage.

Images