KR102542874B1 - Display Device - Google Patents

Abstract

A display device according to the present invention includes a pixel array in which data lines and gate lines are defined and pixels are arranged in a matrix form, and a shift register for sequentially supplying gate pulses to the gate lines using stages connected in a subordinate manner. includes At least one of the stages includes a pull-up transistor for charging the output terminal in response to the voltage of the Q node, a pull-down transistor for discharging the output terminal to a first low potential voltage in response to the voltage of the QB node, and a Q node in response to the voltage of the QB node. A first Q node discharge control transistor for discharging the voltage of to a second low potential voltage, and a first QB node for discharging the QB node to a third low potential voltage in response to a first reset signal applied during the vertical blank period. It contains a control transistor. The second low potential voltage is set lower than the first low potential voltage and higher than the third low potential voltage.

Description

Display Device {Display Device}

The present invention relates to a display device.

In the display device, data lines and gate lines are arranged to be orthogonal, and pixels are arranged in a matrix form. Video data voltages to be displayed are supplied to the data lines, and gate pulses are sequentially supplied to the gate lines. The video data voltage is supplied to the pixels of the display line to which the gate pulse is supplied, and video data is displayed while all the display lines are sequentially scanned by the gate pulse.

A gate driver for supplying gate pulses to gate lines of a display device usually includes a plurality of gate integrated circuits (hereinafter referred to as “ICs”). Since each gate drive IC must sequentially output gate pulses, it basically includes a shift register, and may include circuits and output buffers for adjusting the output voltage of the shift register according to the driving characteristics of the display panel.

A gate driver generating a gate pulse, which is a scan signal, in a display device may be implemented in a gate-in-panel (GIP) form composed of a combination of thin film transistors in a bezel area, which is a non-display area, of a display panel. The GIP type gate driver includes stages corresponding to the number of gate lines, and each stage outputs gate pulses to corresponding gate lines on a one-to-one basis.

The characteristic curves of the transistors of the stages may shift due to deterioration. Transistors with severe deterioration do not operate properly, resulting in unstable output of gate pulses.

An object of the present invention is to provide a display device capable of improving deterioration of transistors arranged in shift registers.

As a means for solving the above problems, the display device according to the present invention applies gate pulses to the gate lines by using a pixel array in which data lines and gate lines are defined and pixels are arranged in a matrix form, and stages connected in a dependent manner. It includes a shift register that feeds sequentially. At least one of the stages includes a pull-up transistor for charging the output terminal in response to the voltage of the Q node, a pull-down transistor for discharging the output terminal to a first low potential voltage in response to the voltage of the QB node, and a Q node in response to the voltage of the QB node. A first Q node discharge control transistor for discharging the voltage of to a second low potential voltage, and a first QB node for discharging the QB node to a third low potential voltage in response to a first reset signal applied during the vertical blank period. It contains a control transistor. The second low potential voltage is set lower than the first low potential voltage and higher than the third low potential voltage.

According to the present invention, “Vgs” values of a plurality of transistors, which may seriously deteriorate, are maintained to be negative biased during the vertical blank period. As a result, it is possible to prevent the threshold voltages of the transistors from shifting due to deterioration. In particular, according to the present invention, the first to third low potential voltages having different voltage levels may be applied to the stages so that the “Vgs” values of the plurality of transistors become negative biases.

1 is a view showing a display device according to the present invention.
2 is a diagram showing a shift register according to the present invention.
FIG. 3 is a diagram illustrating the stage shown in FIG. 2 .
4 is a timing diagram showing inputs and outputs of a shift register.
5 is a diagram for explaining a frame period.
6 to 8 are diagrams showing voltages applied to respective electrodes of main transistors during a vertical blank period.
9 is a diagram showing voltage changes of a Q node and a QB node of a stage;
10 is a diagram explaining a threshold voltage shift phenomenon due to a deterioration phenomenon of a transistor.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings, focusing on the liquid crystal display device. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. The names of the components used in the following description are selected in consideration of the ease of writing the specification, and may differ from the names of actual products.

Switch elements in the gate driving circuit of the present invention may be implemented as n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structured transistors. Although n-type transistors are illustrated in the following embodiments, it should be noted that the present invention is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in an n-type MOSFET, the direction of the current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on the applied voltage. The invention should not be limited by the sources and drains of the transistors in the following embodiments.

Also, in this specification, turn-on voltage refers to the operating voltage of a transistor. Since the present specification describes an n-type transistor as an example, a high potential voltage is defined as a turn-on voltage.

1 is a diagram illustrating a display device according to an exemplary embodiment of the present invention. Referring to FIG. 1 , the display device of the present invention includes a display panel 100 , a timing controller 110 , a data driver 120 , gate drivers 130 and 140 , and the like.

The display panel 100 includes a pixel array 100A in which data lines DL and gate lines GL are defined and pixels are disposed, and a non-display area in which various signal lines or pads are formed outside the pixel array 100A. (100B). The display panel 100 may use a liquid crystal display (LCD), an organic light emitting diode display (OLED), an electrophoretic display (EPD), or the like.

The timing controller 110 receives timing signals such as a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and a dot clock (DLCK) through an LVDS or TMDS interface receiving circuit connected to the video board. is input. The timing controller 110 includes a data timing control signal (DDC) for controlling the operation timing of the data driver 120 and a gate timing control signal (for controlling the operation timing of the scan driver 130 and 140) based on the input timing signal. GDC) is created.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (Polarity, POL), and a source output enable signal (Source Output Enable, SOE). includes The source start pulse SSP controls shift start timing of the data driver 120 . The source sampling clock SSC is a clock signal that controls data sampling timing in the data driver 120 based on a rising or falling edge.

The scan timing control signal includes a start pulse (VST) and a gate clock (CLK). The start pulse VST is input to the shift register 140 to control shift start timing. The gate clock CLK is level shifted through the level shifter 130 and then input to the shift register 140.

The data driver 120 receives digital video data RGB and a source timing control signal DDC from the timing controller 110 . The data driver 120 generates a data voltage by converting the digital video data RGB into a gamma voltage in response to the source timing control signal DDC, and converts the data voltage to the data lines DL of the display panel 100. supplied through

The gate drivers 130 and 140 include a level shifter 130 and a shift register 140 .

The level shifter 130 is formed on the printed circuit board 105 connected to the display panel 100 in the form of an IC. The level shifter 130 levels shifts the clock signals CLK and the start signal VST under the control of the timing controller 110 and supplies them to the shift register 140 .

2 is a diagram showing a shift register according to the present invention.

Referring to FIG. 2 , the shift register 140 sequentially outputs gate pulses Gout corresponding to the gate clocks CLK and the start pulse VST. The shift register 140 includes a plurality of stages STG connected to each other dependently. Although FIG. 2 shows the shift register 140 including n stages STG corresponding to n gate lines, the number of stages STG is not limited thereto. For example, the stage may include a dummy stage generating a carry signal or a next-end signal NEXT. In the following description, "front stage" refers to a stage positioned above a standard stage. For example, based on the ith (i is a natural number greater than 5 and less than n) stage STGi, the previous stage is any one of the first stage STG1 to the i−1th stage STG(i−1). instruct "Later stage" refers to a stage positioned below a standard stage. For example, based on the i(1<i<n)th stage STGi, the next stage indicates any one of the [i+1]th stage STG(i+1) to the nth stage.

Each stage STG of the shift register 140 sequentially outputs gate pulses Gout[1] to Gout[n]. For example, the ith stage STGi outputs the ith gate pulse Gouti, and the nth stage STGn outputs the nth gate pulse Gout[n]. To this end, each stage STG receives one gate clock from among sequentially delayed gate clocks CLK.

The [i-4]th gate pulse Gout[i-4] is applied to the [i-4]th gate line and serves as a carry signal transmitted to the i-th stage STGi. The [i+4]th gate pulse (Gout[i+4]) is applied to the [i+4]th gate line and serves as a subsequent signal (NEXT) applied to the ith stage (STGi). The carry signal and the subsequent signal NEXT shown in FIG. 2 are applied to an embodiment in which the phase of the gate clock CLK is 8 and the gate pulse Gout is output for 4 horizontal cycles H, and the carry signal and the subsequent signal (NEXT) may vary according to the phase of the gate clock.

Each stage STG receives a driving signal through signal wires. In particular, the stages STG are connected to signal wires for receiving the first to third low potential voltages VGL1 , VGL2 , and VGL3 . The voltage levels of the first to third low potential voltages VGL1 , VGL2 , and VGL3 are set to satisfy the condition “VGL1>VGL2>VGL3”.

FIG. 3 is a diagram showing the configuration of the stage shown in FIG. 2, and FIG. 4 is a diagram showing timing and output signals of driving signals input to the stage shown in FIG.

1 to 4, the i-th stage STGi of the shift register 140 includes a pull-up transistor (Tpu), a pull-down transistor (Tpd), and a start controller T1. and a number of transistors.

The pull-up transistor Tpu includes a gate electrode connected to the Q node, a drain electrode connected to the input terminal of the gate clock CLK, and a source electrode connected to the output terminal Nout.

The pull-down transistor Tpd includes a gate electrode connected to the QB node, a drain electrode connected to the output terminal Nout, and a source electrode connected to the gate low voltage input terminal.

The start controller T1 may include a transistor including a gate electrode and a drain electrode connected to the start pulse input terminal VST_P and a source electrode connected to the Q node. The start pulse input terminal VST_P receives any one of the first to fourth start pulses VST1 to VST4 or a carry signal. The start pulse input terminals VST_P of the first to fourth stages STG1 to STG4 receive the first to fourth start pulses VST1 to VST4, respectively, and the start input terminal VST_P of the i stage STGi. receives the [i-4]th gate pulse (Gout[i-4]), which is a carry signal.

The second transistor T2 includes a gate electrode connected to the second reset signal DRST input line, a drain electrode connected to the high potential voltage VDD input line, and a source electrode connected to the QB node. The second transistor T2 charges the QB node in response to the second reset signal DRST.

The third transistor T3 includes a gate electrode receiving a gate clock bar signal, a drain electrode connected to a high potential voltage (VDD) input terminal, and a source electrode connected to the QA node. The gate clock bar signal means a gate clock that is in opposite phase to the gate clock applied to the drain electrode of the pull-up transistor Tpu. For example, in a shift register using an 8-phase gate clock, the gate clock bar signal of the ith stage STGi refers to the [i−4]th gate clock CLK[i−4]. The third transistor T3 charges the QA node in response to the [i−4]th gate clock CLK[i−4].

The fourth transistor T4 includes a gate electrode connected to the QA node, a drain electrode connected to a high potential voltage (VDD) input line, and a source electrode connected to the QB node. The fourth transistor T4 charges the QB node when the QA node is charged.

The fifth transistor T5 includes a gate electrode connected to the Q node, a drain electrode connected to the QA node, and a source electrode connected to the third low potential voltage VGL3 input line. The fifth transistor T5 forms a current path between the QA node and the third low potential voltage VGL3 input line when the Q node is charged.

The sixth transistor T6 includes a gate electrode connected to the first reset signal BRST input line, a drain electrode connected to the QA node, and a source electrode connected to the third low potential voltage VGL3 input line. The sixth transistor T6 discharges the QA node to the second low potential voltage VGL2 in response to the first reset signal BRST.

The first Q node control transistor T7 includes a gate electrode connected to the QB node, a drain electrode connected to the Q node, and a source electrode connected to the second low potential voltage VGL2 input line. The first Q node control transistor T7 discharges the QB node to the second low potential voltage VGL2 when the Q node is charged.

The eighth transistor T8 includes a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to the second low potential voltage VGL2 input line. The eighth transistor T8 discharges the Q node to the second low potential voltage VGL2 when the QB node is charged. In this specification, the eighth transistor T8 may also be referred to as a second QB node discharge control transistor.

The second Q node control transistor T9 includes a gate electrode connected to the first reset signal BRST input line, a drain electrode connected to the QB node, and a source electrode connected to the second low potential voltage VGL2 input line. do. The second Q node control transistor T9 discharges the QB node to the second low potential voltage VGL2 in response to the first reset signal BRST.

The output control transistor T10 includes a gate electrode connected to the first reset signal input line BRST_L, a drain electrode connected to the output terminal Nout, and a source electrode connected to the first low potential voltage VGL1 input line. . The output terminal control transistor T10 discharges the output terminal Nout to the first low potential voltage VGL1 in response to the first reset signal BRST.

The third Q node discharge control transistor T11 includes a gate electrode connected to the next stage signal input terminal NEXT_P, a drain electrode connected to the Q node, and a source electrode connected to the second low potential voltage VGL2 input line. The third Q node discharge control transistor T11 discharges the voltage of the Q node to the second low potential voltage VGL2 in response to the next stage signal NEXT.

The QB node control transistor T12 includes a gate electrode receiving the first reset signal BRST, a drain electrode connected to the QB node, and a source electrode connected to the third low potential voltage VGL3 input line. The QB node control transistor T12 discharges the output terminal Nout to the third low potential voltage VGL3 in response to the first reset signal BRST.

The operation of the stages during one frame is as follows. The frame period is divided into an active period (AT) and a vertical blank period (VB). As shown in FIG. 5 , the active period (AT) and the vertical blank period (VB) may be defined based on the Video Electronic Standards Association (VESA) standard.

The active period AT is a period required to display one frame of data on all pixels of the display area 100A where an image is displayed on the display panel 100 .

The vertical blank period VB includes a vertical sync time (VS), a vertical front porch (FP), and a vertical back porch (BP). The vertical sync time (VS) is the time from the falling edge of Vsync to the rising edge, and represents the start (or end) timing of one screen. The Vertical Front Porch (FP) is the time from the falling edge of the last DE indicating the data timing of the last line of 1 frame data to the start of the Vertical Blank Time (VB). The vertical back porch (BP) is the time from the end of the vertical blank time (VB) to the rising edge of the first DE indicating the first line data timing of one frame data.

In the initial section of the kth frame (k is a natural number), the second reset signal DRST is applied to each of the stages STG. The second transistor T2 charges the QB node in response to the second reset signal DRST, and the first Q node control transistor T7 discharges the Q node in response to the second reset signal DRST.

After the second reset signal DRST ends, the first to fourth start signals VST1 , VST2 , VST3 , and VST4 are applied to the first to fourth stages STG, respectively.

The start controller T1 of the first to fourth stages pre-charges the Q node in response to the start pulse VST.

When the gate clock CLK is input to the drain electrode of the pull-up transistor Tpu while the Q node is pre-charged, the Q node is bootstrapping as the drain electrode voltage of the pull-up transistor Tpu increases. As the Q node is bootstrapping, the potential difference between the gate and the source of the pull-up transistor Tpu increases, and eventually, when the voltage difference between the gate and the source reaches the threshold voltage, the pull-up transistor Tpu is turned on. The turned-on pull-up transistor Tpu charges the output terminal Nout using the gate clock CLK. The output terminal Nout of the i-th stage STGi is connected to the i-th gate line GLi, and the gate pulse Gouti is applied to the i-th gate line GLi.

After the gate clock CLK is inverted to a low level, the gate electrode of the third Q node discharge control transistor T11 receives the downstream signal NEXT. The third Q node discharge control transistor T11 is turned on in response to the post signal NEXT, and as a result, the voltage of the Q node is discharged to the second low potential voltage VGL2.

During the active period, the third transistor T3 charges the QA node in response to the [i−4]th gate clock CLK[i−4]. That is, the QA node maintains the high potential voltage VDD during a period in which the ith gate clock CLKi is not input. The fourth transistor T4 charges the QB node in response to the QA node. The ith gate clock CLKi refers to the gate clock CLK applied to the drain electrode of the pull-up transistor Tpu to determine the output timing of the gate pulse output from the ith stage STGi.

The fifth transistor T5 suppresses the operation of the fourth transistor T4 during a period in which the Q node is charged. That is, the fifth transistor T5 discharges the QA node to the third low potential voltage VGL3 while the start pulse VST and the ith gate clock CLKi are input, so that the fourth transistor T4 does not operate. Avoid.

During the vertical blank period VB after the active period AT ends, the first reset signal BRST is applied to each of the stages STG.

The sixth transistor T6 discharges the QA node in response to the first reset signal BRST. As a result, the fourth transistor T4 remains turned off. Since the fourth transistor T4 is turned on for a long time during the active period AT, it receives a lot of stress. Since the fourth transistor T4 does not have to operate during the vertical blank period VB, the sixth transistor T6 discharges the QA node during the vertical blank period VB so that the fourth transistor T4 does not operate. do.

The second Q node control transistor T9, the output control transistor T10, and the QB node control transistor T12 are turned on in response to the first reset signal BRST. The second Q node control transistor T9 is turned on to discharge the Q node to the second low potential voltage VGL2. The output terminal control transistor T10 is turned on to discharge the output terminal Nout to the first low potential voltage VGL1. The first QB node control transistor T12 is turned on to discharge the QB node to the third low potential voltage VGL3.

As described above, the first reset signal BRST applied during the vertical blank period VB turns on the second Q node control transistor T9, the output control transistor T10, and the QB node control transistor T12. . In particular, the second Q node transistor T9, the output control transistor T10, and the QB node control transistor T12 discharge the Q node, the output terminal Nout, and the QB node to different low potential voltages, respectively. In other words, during the vertical blank period VB, low potential voltages having different voltage levels are applied to the Q node, the output terminal Nout, and the QB node.

As a result, during the vertical blank period VB, the voltage levels of the respective electrodes of the first Q node control transistor T7, the pull-up transistor Tpu, and the pull-down transistor Tpd become as shown in FIGS. 6 to 8 .

Referring to FIG. 6, during the vertical blank period VB, the gate electrode of the first Q node control transistor T7 becomes the voltage level of the third low potential voltage VGL3, and the source and drain electrodes of the second low potential voltage VGL3. It becomes the voltage level of the potential voltage VGL2. As a result, “Vgs” of the first Q node control transistor T7 becomes a value obtained by subtracting the second low potential voltage VGL2 from the third low potential voltage VGL3. Since the third low potential voltage VGL3 has a lower voltage level than the second low potential voltage VGL2 , “Vgs” of the first Q node control transistor T7 becomes a negative bias smaller than zero.

Referring to FIG. 7 , during the vertical blank period VB, the gate electrode of the pull-down transistor Tpd becomes the voltage level of the third low potential voltage VGL3, and the source and drain electrodes of the pull-down transistor Tpd become the voltage level of the first low potential voltage VGL1. ) becomes the voltage level of As a result, “Vgs” of the pull-down transistor Tpd becomes a value obtained by subtracting the first low potential voltage VGL1 from the third low potential voltage VGL3. Since the third low potential voltage VGL3 has a lower voltage level than the first low potential voltage VGL1, “Vgs” of the pull-down transistor Tpd becomes a negative bias smaller than zero.

Referring to FIG. 8 , during the vertical blank period VB, the gate electrode of the pull-up transistor Tpu becomes the voltage level of the second low potential voltage VGL2, and the source and drain electrodes have the first low potential voltage VGL1. ) becomes the voltage level of As a result, “Vgs” of the pull-up transistor Tpu becomes a value obtained by subtracting the first low potential voltage VGL1 from the second low potential voltage VGL2. Since the second low potential voltage VGL2 has a lower voltage level than the first low potential voltage VGL1 , “Vgs” of the pull-up transistor Tpu becomes a negative bias smaller than zero.

As a result, during the vertical blank period VB, the first Q node control transistor T7, the pull-up transistor Tpu, and the pull-down transistor Tpd all have low potential voltages.

In the active period (AT), as shown in FIG. 9 , the QB node maintains a high potential voltage except for a period in which the Q node is pre-charged or bootstrapped. As a result, since the first Q node control transistor T7 and the pull-down transistor Tpd, the gate electrode of which is connected to the QB node, maintains a turned-on state for a long time during the active period AT, the threshold voltage deviation due to deterioration is reduced. A shift phenomenon occurs.

10 is a diagram explaining a phenomenon in which voltage-current characteristic curves of transistors are shifted due to deterioration.

As shown in FIG. 10, the voltage-current characteristic curves of the first Q node control transistor T7 and the pull-down transistor Tpd having the form of the first graph gr1 are shifted to the second graph gr2 due to deterioration. . As a result, even if the gate-source voltage of the first Q node control transistor T7 and the pull-down transistor Tpd is applied at the initially set voltage level of the threshold voltage Vth, they cannot be turned on. Therefore, since the first Q node control transistor T7 and the pull-down transistor Tpd do not operate properly, a gate pulse may be output in an unwanted section.

The stages of the shift register according to the present invention apply different low potential voltages to the QB node and the Q node during the vertical blank period (VB) so that the “Vgs” value of the first Q node control transistor T7 and the pull-down transistor Tpd is increased. All can be negative biased. In addition, since a low potential voltage different from that of the QB node and Q is applied to the output terminal Nout during the vertical blank period VB, “Vgs” of the pull-up transistor Tpu also becomes a negative bias.

As such, the present invention applies a low potential voltage level of different voltage level to the main node during the vertical blank period to apply a negative bias to the first Q node control transistor T7, the pull-up transistor Tpu, and the pull-down transistor Tpd. can be authorized. As a result, deterioration of the first Q node control transistor T7, the pull-up transistor Tpu, and the pull-down transistor Tpd can be improved.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the above-described technical configuration of the present invention can be changed into other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that this can be implemented. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130, 140: gate driver

Claims (8)

a pixel array in which data lines and gate lines are defined and pixels are arranged in a matrix form; and
A shift register sequentially supplying gate pulses to the gate lines using stages connected in cascade;
At least one of the stages
a pull-up transistor that charges the output terminal in response to the voltage of the Q node;
a pull-down transistor for discharging the output terminal to a first low potential voltage in response to the voltage of the QB node;
a first Q node discharge control transistor for discharging the voltage of the Q node to a second low potential voltage in response to the voltage of the QB node; and
A first QB node discharge control transistor for discharging the QB node to a third low potential voltage in response to a first reset signal applied during a vertical blank period;
The second low potential voltage is lower than the first low potential voltage and higher than the third low potential voltage;
At least one of the stages includes: a second Q node discharge control transistor including a gate electrode receiving the first reset signal, a drain electrode connected to the Q node, and a source electrode receiving the second low potential voltage Including more,
During the vertical blank period, the drain electrode and the source electrode of the first Q node discharge control transistor receive the second low potential voltage through different current paths. According to claim 1,
The first reset signal maintains a turn-off voltage during an active period in which image data is written in the pixel array. delete According to claim 1,
At least one of the stages
and an output terminal discharge control transistor including a gate electrode receiving the first reset signal, a drain electrode connected to the output terminal, and a source electrode receiving the first low potential voltage. According to claim 1,
The stage outputting the ith (i is a natural number) gate pulse
a start controller precharging the Q node in response to a start pulse or a gate pulse other than the i-th gate pulse; and
and a third Q node discharge control transistor for discharging the Q node to the second low potential voltage in response to a post signal applied when the i th gate pulse ends. According to claim 1,
and a second QB node discharge control transistor including a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode receiving the second low potential voltage. According to claim 4,
The first to third low potential voltages are negative biases. According to claim 1,
The pull-up transistor charges the output terminal using a gate clock applied to a drain electrode,
wherein the gate clock alternately outputs a high potential voltage and the second low potential voltage during an active period and maintains the first low potential voltage during the vertical blank period.

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