CN110675798B - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
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- CN110675798B CN110675798B CN201910916929.1A CN201910916929A CN110675798B CN 110675798 B CN110675798 B CN 110675798B CN 201910916929 A CN201910916929 A CN 201910916929A CN 110675798 B CN110675798 B CN 110675798B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
Abstract
The application provides a GOA circuit and display panel through increase eighth transistor and ninth transistor in the pull-down maintenance module to can be through eighth transistor and ninth transistor with the pull-down of first node to lower electric potential, and then improve the stability of GOA circuit.
Description
Technical Field
The application relates to the technical field of display, in particular to a GOA circuit and a display panel.
Background
The Gate Driver on Array (GOA) technology integrates a Gate Driver circuit on an Array substrate of a display panel, so that a Gate Driver integrated circuit part can be omitted, and the product cost can be reduced from two aspects of material cost and manufacturing process.
In the conventional GOA circuit, after outputting the horizontal scanning signal of the current stage of the GOA unit, the horizontal scanning signal needs to be maintained at a low level for a certain period of time. However, since the transistor is operated for a long time, the electrical property of the transistor is easily damaged, thereby causing the GOA circuit to be unable to operate normally.
Disclosure of Invention
The embodiment of the application provides a GOA circuit and display panel, can solve current GOA circuit because the transistor works for a long time, the electrical property of transistor receives destruction easily to lead to the technical problem that GOA circuit can not normally work.
In a first aspect, the present application provides a GOA circuit, including: the multistage GOA unit that cascades, each grade GOA unit all includes: the device comprises an input module, a first output module, a second output module, a pull-down module and a pull-down maintaining module;
the input module is connected with a previous-stage signal and a first voltage signal and is electrically connected to a first node, and the input module is used for pulling up the potential of the first node to the potential of the first voltage signal under the control of the previous-stage signal;
the first output module is connected with a clock signal and is electrically connected with the first node, and the first output module outputs a current-level transmission signal according to the clock signal under the control of the potential of the first node;
the second output module is connected to the clock signal and electrically connected to a second node, and the second output module is used for outputting a scanning signal according to the clock signal under the potential control of the second node;
the pull-down module is connected to a next-stage signal and a second voltage signal and is electrically connected to a first node, and the pull-down module is used for pulling down the potential of the first node to the potential of the second voltage signal under the control of the next-stage signal;
the pull-down maintaining module is connected to a first voltage signal, a third voltage signal and a power signal and is electrically connected to the first node, the current-stage transmission signal and the scanning signal, and the pull-down maintaining module is used for maintaining the current-stage transmission signal and the scanning signal to the potential of the third signal according to the first voltage signal, the third voltage signal, the power signal and the potential of the first node.
In the GOA circuit provided by the present application, the input module includes a first transistor;
the gate of the first transistor is electrically connected to the previous-stage transmission signal, the source of the first transistor is electrically connected to the first voltage signal, and the drain of the first transistor is electrically connected to the first node.
In the GOA circuit provided by the present application, the first output module includes a second transistor;
the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the current-stage transmission signal, and the drain of the second transistor is electrically connected to the clock signal.
In the GOA circuit provided in the present application, the second output module includes a third transistor and a bootstrap capacitor;
a gate of the third transistor is electrically connected to the second node, a source of the third transistor is electrically connected to the scan signal, and a drain of the third transistor is electrically connected to the clock signal;
a first end of the bootstrap capacitor is electrically connected to the second node, and a second end of the bootstrap capacitor is electrically connected to the source of the third transistor.
In the GOA circuit provided by the present application, the pull-down module includes a fourth transistor;
a gate of the fourth transistor is electrically connected to the next-stage transmission signal, a source of the fourth transistor is electrically connected to the first node, and a drain of the fourth transistor is electrically connected to the second voltage signal.
In the GOA circuit provided by the present application, the pull-down sustain module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor;
a gate of the fifth transistor is electrically connected to a third node, a source of the fifth transistor is electrically connected to the second voltage signal, and a drain of the fifth transistor is electrically connected to the third node;
a gate of the sixth transistor is electrically connected to a fourth node, a source of the sixth transistor is electrically connected to the second voltage signal, and a drain of the sixth transistor is electrically connected to the source of the second transistor;
a gate of the seventh transistor is electrically connected to the fourth node, a source of the seventh transistor is electrically connected to the third voltage signal, and a drain of the seventh transistor is electrically connected to the source of the third transistor;
a gate of the eighth transistor is electrically connected to the first voltage signal, a source of the eighth transistor is electrically connected to the first voltage signal, and a drain of the eighth transistor is electrically connected to a third node;
a gate of the ninth transistor is electrically connected to the first node, a source of the ninth transistor is electrically connected to the power signal, and a drain of the ninth transistor is electrically connected to the third node.
In the GOA circuit provided by the present application, the first voltage signal is a constant voltage high level signal.
In the GOA circuit provided by the present application, the second voltage signal and the third voltage signal are both constant-voltage low-level signals.
In the GOA circuit provided by the present application, a potential of the third voltage signal is greater than a potential of the second voltage signal.
In a second aspect, the present application provides a display panel including the GOA circuit of any of the examples of the present application.
The application provides a GOA circuit and display panel through increase eighth transistor and ninth transistor in the pull-down maintenance module to can be through eighth transistor and ninth transistor with the pull-down of first node to lower electric potential, and then improve the stability of GOA circuit.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic circuit diagram of a GOA unit in a GOA circuit according to an embodiment of the present disclosure;
fig. 3 is a timing diagram of a signal of a GOA unit in the GOA circuit according to the embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, to distinguish two poles of a transistor except for a gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. The form in the drawing provides that the middle end of the switching transistor is a grid, the signal input end is a source, and the output end is a drain. In addition, the transistors adopted in the embodiment of the application are all N-type transistors or P-type transistors, wherein the N-type transistors are switched on when the grid electrodes are at a high level and switched off when the grid electrodes are at a low level; the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure.
As shown in fig. 1, the GOA circuit 10 provided in the embodiment of the present application includes multiple cascaded GOA units 20. Each grade of GOA unit is used for outputting a scanning signal and a grade of transmission signal. When the GOA circuit 10 is in operation, the first GOA unit 20 receives the start signal STV, and then the second GOA unit 20, the third GOA unit 20, … …, and the last GOA unit 20 are activated according to the secondary transmission.
Further, referring to fig. 2, fig. 2 is a circuit schematic diagram of a GOA unit in a GOA circuit according to an embodiment of the present disclosure. As shown in fig. 2, the GOA unit 20 includes: an input module 101, a first output module 102, a second output module 103, a pull-down module 104, and a pull-down maintaining module 105.
The input module 101 is connected to the previous stage C (n-1) and the first voltage signal H, and is electrically connected to the first node a, and the input module 101 is configured to pull up a potential of the first node a to a potential of the first voltage signal H under the control of the previous stage signal C (n-1).
The first output module 102 is connected to the clock signal CK and electrically connected to the first node a, and the first output module 102 outputs the current-stage signal c (n) according to the clock signal CK under the control of the potential of the first node a.
The second output module 103 is connected to the clock signal and electrically connected to the second node b, and the second output module 103 is configured to output the scan signal S according to the clock signal CK under the control of the potential of the second node b.
The pull-down module 104 is connected to the next-stage transmission signal C (n +1) and the second voltage signal L, and is electrically connected to the first node a, and the pull-down module 104 is configured to pull down the potential of the first node a to the potential of the second voltage signal L under the control of the next-stage transmission signal C (n + 1);
the pull-down maintaining module 105 is connected to the first voltage signal H, the third voltage signal D and the power signal E, and electrically connected to the first node a, the current level transmission signal c (n) and the scan signal S, and the pull-down maintaining module 105 is configured to maintain the potentials of the current level transmission signal c (n) and the scan signal S to the potential of the third voltage signal D according to the potentials of the first voltage signal H, the third voltage signal D, the power signal E and the first node a
In some embodiments, the input module 101 includes a first transistor T1. The gate of the first transistor T1 is electrically connected to the previous-stage transmission signal C (n-1), the source of the first transistor T1 is electrically connected to the first voltage signal H, and the drain of the first transistor T1 is electrically connected to the first node a.
In some embodiments, the first output module 102 includes a second transistor T2. The gate of the second transistor T2 is electrically connected to the first node a, the source of the second transistor T2 is electrically connected to the current-stage transmission signal c (n), and the drain of the second transistor T2 is electrically connected to the clock signal CK.
In some embodiments, the second output module 103 includes a third transistor T3 and a bootstrap capacitor C. The gate of the third transistor T3 is electrically connected to the second node b, the source of the third transistor T3 is electrically connected to the scan signal S, and the drain of the third transistor T3 is electrically connected to the clock signal CK. The first end of the bootstrap capacitor C is electrically connected to the second node b, and the second end of the bootstrap capacitor C is electrically connected to the source of the third transistor T3.
In some embodiments, the pull-down module 104 includes a fourth transistor T4. The gate of the fourth transistor T4 is electrically connected to the next-stage transmission signal C (n +1), the source of the fourth transistor T4 is electrically connected to the first node a, and the drain of the fourth transistor T4 is electrically connected to the second voltage signal L.
In some embodiments, the pull-down sustain module includes a fifth transistor T5T, a sixth transistor T6, a seventh transistor T7, an eighth transistor, and a ninth transistor.
The gate of the fifth transistor T5 is electrically connected to the third node c, the source of the fifth transistor T5 is electrically connected to the second voltage signal L, and the drain of the fifth transistor T5 is electrically connected to the first node a. The gate of the sixth transistor T6 is electrically connected to the fourth node d, the source of the sixth transistor T6 is electrically connected to the second voltage signal L, and the drain of the sixth transistor T6 is electrically connected to the source of the second transistor T2. The gate of the seventh transistor T7 is electrically connected to the fourth node D, the source of the seventh transistor T7 is electrically connected to the third voltage signal D, and the drain of the seventh transistor T7 is electrically connected to the source of the third transistor T3. The gate of the eighth transistor T8 is electrically connected to the first voltage signal H, the source of the eighth transistor T8 is electrically connected to the first voltage signal H, and the drain of the eighth transistor T8 is electrically connected to the third node c. The gate of the ninth transistor T9 is electrically connected to the first node a, the source of the ninth transistor T9 is electrically connected to the power signal E, and the drain of the ninth transistor T9 is electrically connected to the third node c. The power supply signal E is used not only as a signal source of the ninth transistor T9 but also as a switching source of the pixel circuit in the display region.
Further, in the GOA circuit provided in this application, the first voltage signal H is a constant voltage high level signal, the second voltage signal L and the third voltage signal D are both constant voltage low level signals, and the potential of the third voltage signal D is greater than the potential of the second voltage signal L.
Specifically, please refer to fig. 2 and fig. 3, which are timing diagrams of a GOA unit in the GOA circuit according to the embodiment of the present disclosure. When the previous-stage transmission signal C (n-1) is at a high level, the next-stage transmission signal C (n +1) is at a low level, and the clock signal CK is at a low level, the first transistor T1 is turned on, the first voltage signal H is transmitted to the first node a through the first transistor T1, and since the potential of the first node a is pulled up to the potential of the first voltage signal, the second transistor T2 is turned on, and the stage transmission signal C (n) is output according to the clock signal CK. Meanwhile, the third transistor T3 is turned on, and outputs the scan signal S according to the clock signal CK, and at this time, the stage transmission signal c (n) and the scan signal S are both at a low level.
Subsequently, the previous stage breakdown signal C (n-1) is converted to the low level, the first transistor T1 is turned off, the potential of the first node a maintains a higher potential through the bootstrap capacitor C, meanwhile, the potential of the clock signal CK is converted to the high level, the clock signal CK charges the bootstrap capacitor C through the third transistor T3, so that the potential of the first node a reaches a higher potential, and the present stage transmission signal C (n) and the scan signal S are also converted to the high level.
Then, when the next-stage pass signal C (n +1) goes high, the fourth transistor T4 is turned on, and the second voltage signal L pulls the potential of the first node a low.
Finally, as the potential of the first node a is changed to the low potential, the second transistor T2 is turned off, the third transistor T3 is turned off, and the ninth transistor T9 is turned off, so that the potential of the third node c and the potential of the fourth node d are pulled up to the potential of the first voltage signal H. Meanwhile, the fourth transistor T4 is turned on, so that the second voltage signal L maintains the potential of the first node a, and further maintains the potentials of the stage-level transmission signal c (n) and the scanning signal S.
It should be noted that, when the potential of the scan signal S is at a low level, the power signal E is raised to a high level, and at this time, the voltage of the ninth transistor T9 is 0, so that the leakage current of the ninth transistor T9 is reduced, thereby reducing the power consumption of the GOA circuit.
In the present application, by adding the eighth transistor T8 and the ninth transistor T9 to the pull-down maintaining module 105, the first node a can be pulled down to a lower potential through the eighth transistor T8 and the ninth transistor T9, thereby improving the stability of the GOA circuit.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 4, the display panel includes a display area 100 and a GOA circuit 200 integrally disposed on an edge of the display area 100; the structure and principle of the GOA circuit 200 are similar to those of the GOA circuit 10, and are not described herein again.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A GOA circuit, comprising: the multistage GOA unit that cascades, each grade GOA unit all includes: the device comprises an input module, a first output module, a second output module, a pull-down module and a pull-down maintaining module;
the input module is connected with a previous-stage signal and a first voltage signal and is electrically connected to a first node, and the input module is used for pulling up the potential of the first node to the potential of the first voltage signal under the control of the previous-stage signal;
the first output module is connected with a clock signal and is electrically connected with the first node, and the first output module outputs a current-level transmission signal according to the clock signal under the potential control of the first node;
the second output module is connected to the clock signal and electrically connected to a second node, and the second output module is used for outputting a scanning signal according to the clock signal under the potential control of the second node;
the pull-down module is connected to a next-stage signal and a second voltage signal and is electrically connected to a first node, and the pull-down module is used for pulling down the potential of the first node to the potential of the second voltage signal under the control of the next-stage signal;
the pull-down maintaining module is connected to a first voltage signal, a third voltage signal and a power signal and is electrically connected to the first node, the current-stage transmission signal and the scanning signal, and the pull-down maintaining module is used for maintaining the potentials of the current-stage transmission signal and the scanning signal to the potential of the third voltage signal according to the potentials of the first voltage signal, the third voltage signal, the power signal and the first node;
the pull-down maintaining module comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;
a gate of the fifth transistor is electrically connected to a third node, a source of the fifth transistor is electrically connected to the second voltage signal, and a drain of the fifth transistor is electrically connected to the first node;
a gate of the sixth transistor is electrically connected to a fourth node, a source of the sixth transistor is electrically connected to the second voltage signal, and a drain of the sixth transistor is electrically connected to the first output module;
a gate of the seventh transistor is electrically connected to the fourth node, a source of the seventh transistor is electrically connected to the third voltage signal, and a drain of the seventh transistor is electrically connected to the second output module;
a gate of the eighth transistor is electrically connected to the first voltage signal, a source of the eighth transistor is electrically connected to the first voltage signal, and a drain of the eighth transistor is electrically connected to a third node;
a gate of the ninth transistor is electrically connected to the first node, a source of the ninth transistor is electrically connected to the power signal, and a drain of the ninth transistor is electrically connected to the third node.
2. The GOA circuit of claim 1, wherein the input module comprises a first transistor;
the gate of the first transistor is electrically connected to the previous-stage transmission signal, the source of the first transistor is electrically connected to the first voltage signal, and the drain of the first transistor is electrically connected to the first node.
3. The GOA circuit of claim 2, wherein the first output module comprises a second transistor;
the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the current-stage transmission signal, the source of the second transistor is electrically connected to the drain of the sixth transistor, and the drain of the second transistor is electrically connected to the clock signal.
4. The GOA circuit of claim 3, wherein the second output module comprises a third transistor and a bootstrap capacitor;
a gate of the third transistor is electrically connected to the second node, a source of the third transistor is electrically connected to the scan signal, a source of the third transistor is electrically connected to a drain of the seventh transistor, and a drain of the third transistor is electrically connected to the clock signal;
a first end of the bootstrap capacitor is electrically connected to the second node, and a second end of the bootstrap capacitor is electrically connected to the source of the third transistor.
5. The GOA circuit of claim 4, wherein the pull-down module comprises a fourth transistor;
a gate of the fourth transistor is electrically connected to the next-stage transmission signal, a source of the fourth transistor is electrically connected to the first node, and a drain of the fourth transistor is electrically connected to the second voltage signal.
6. The GOA circuit of claim 1, wherein the first voltage signal is a constant voltage high signal.
7. The GOA circuit of claim 1, wherein the second and third voltage signals are both constant voltage low level signals.
8. The GOA circuit of claim 7, wherein the third voltage signal is greater in potential than the second voltage signal.
9. A display panel comprising the GOA circuit of any one of claims 1-8.
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| CN201910916929.1A CN110675798B (en) | 2019-09-26 | 2019-09-26 | GOA circuit and display panel |
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| CN201910916929.1A CN110675798B (en) | 2019-09-26 | 2019-09-26 | GOA circuit and display panel |
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| CN110675798B true CN110675798B (en) | 2022-07-12 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016074395A1 (en) * | 2014-11-12 | 2016-05-19 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit and driving method therefor, and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104464656B (en) * | 2014-11-03 | 2017-02-15 | 深圳市华星光电技术有限公司 | GOA circuit based on low-temperature polycrystalline silicon semiconductor film transistor |
| CN104851403B (en) * | 2015-06-01 | 2017-04-05 | 深圳市华星光电技术有限公司 | The GOA circuits of based oxide semiconductor thin film transistor (TFT) |
| KR102542874B1 (en) * | 2016-10-18 | 2023-06-14 | 엘지디스플레이 주식회사 | Display Device |
| CN106782395B (en) * | 2016-12-30 | 2019-02-26 | 深圳市华星光电技术有限公司 | The driving method and driving device of GOA circuit |
| CN106601206B (en) * | 2016-12-30 | 2019-01-11 | 深圳市华星光电技术有限公司 | GOA gate driving circuit and liquid crystal display device |
| CN108962171B (en) * | 2018-07-27 | 2020-02-18 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and liquid crystal display device with same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016074395A1 (en) * | 2014-11-12 | 2016-05-19 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit and driving method therefor, and display panel |
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