CN107799087B - GOA circuit and display device - Google Patents

GOA circuit and display device Download PDF

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CN107799087B
CN107799087B CN201711200160.0A CN201711200160A CN107799087B CN 107799087 B CN107799087 B CN 107799087B CN 201711200160 A CN201711200160 A CN 201711200160A CN 107799087 B CN107799087 B CN 107799087B
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coupled
transistor
circuit
signal input
gate
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CN107799087A (en
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陈帅
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TCL Huaxing Photoelectric Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The invention discloses a GOA circuit and a display device. The GOA circuit comprises a plurality of GOA sub-circuits which are arranged in a cascade mode, wherein each GOA sub-circuit comprises a pull-up control circuit, a pull-up circuit, a level transmission circuit, a pull-down maintaining circuit, a voltage stabilizing circuit and a bootstrap capacitor; the pull-up circuit, the level pass circuit and the pull-up control circuit are coupled to the first common point, the bootstrap capacitor is coupled between the first common point and the scanning signal output end, the pull-down circuit is coupled to the first common point, the scanning signal output end and the reference low potential signal input end, and the pull-down maintaining circuit is coupled to the first common point, the scanning signal output end and the reference low potential signal input end; the voltage stabilizing circuit is coupled with the reference low potential signal input end. By adding the voltage stabilizing circuit, the reference low potential signal is stably output, and the stability and reliability of the GOA circuit are improved.

Description

GOA circuit and display device
Technical Field
The invention relates to the technical field of display, in particular to a GOA circuit and a display device.
Background
The scanning lines and the data lines in the liquid crystal panel are arranged in a grid shape, so that a plurality of parasitic capacitances exist between the scanning lines and the data lines, and the existence of the parasitic capacitances can cause the potentials of the data lines and the scanning lines to influence each other.
For liquid crystal panels with different driving modes, the capacitive coupling effect of the data lines on the scanning lines is always the most serious, that is, the capacitive coupling effect of all the data lines on the scanning lines is in the same direction at a certain moment, the potentials of the scanning lines will have certain ripples, and the existence of the ripples will affect the stability of the liquid crystal panel, so that the stability of the voltage of the scanning lines is very important for solving the capacitive coupling effect.
Disclosure of Invention
The invention mainly solves the problem of providing a GOA circuit and a display device, and the GOA circuit and the display device are provided with a voltage stabilizing circuit, so that when the potential of an output reference low-potential signal changes due to parasitic capacitance, the potential of the output reference low-potential signal is adjusted, the output reference low-potential signal is more stable, and the stability and the reliability of the GOA circuit are improved.
The technical scheme adopted by the invention is that the GOA circuit comprises a plurality of cascaded GOA sub-circuits, each GOA sub-circuit comprises a pull-up control circuit, a pull-up circuit, a stage transmission circuit, a pull-down maintaining circuit and a bootstrap capacitor, the pull-up circuit comprises a first clock signal input end, a first grid control signal input end and a scanning signal output end (G)N) The stage circuit comprises a second clock signal input terminal and a second gate control signalInput terminal and stage signal output terminal (ST)N) The pull-up control circuit is coupled to the first and second gate control signal inputs at a first common point (Q)N) The bootstrap capacitor is coupled to the first common point (Q)N) And a scanning signal output terminal (G)N) A pull-down circuit coupled to the first common point (Q)N) And a scanning signal output terminal (G)N) And a reference low potential signal input terminal (VSS), a pull-down maintaining circuit coupled to the first common node (Q)N) And a scanning signal output terminal (G)N) And a reference low potential signal input terminal (VSS); each grade of GOA sub-circuit further comprises a voltage stabilizing circuit which is coupled with the reference low potential signal input end (VSS) and used for pulling down the potential of the reference low potential signal input end (VSS) when the potential of the reference low potential signal input end (VSS) is raised.
The invention solves the technical problem, and the technical scheme adopted by the invention is a display device which comprises the GOA circuit.
Through the scheme, the invention has the beneficial effects that: the GOA circuit provided by the invention comprises a plurality of GOA sub-circuits which are arranged in a cascade mode, wherein each GOA sub-circuit comprises a pull-up control circuit, a pull-up circuit, a level transmission circuit, a pull-down maintaining circuit and a bootstrap capacitor; the pull-up circuit, the level pass circuit and the pull-up control circuit are coupled to the first common point, the bootstrap capacitor is coupled between the first common point and the scanning signal output end, the pull-down circuit is coupled to the first common point, the scanning signal output end and the reference low potential signal input end, and the pull-down maintaining circuit is coupled to the first common point, the scanning signal output end and the reference low potential signal input end; each GOA sub-circuit further comprises a voltage stabilizing circuit which is coupled with the reference low-potential signal input end and used for pulling down the potential of the reference low-potential signal input end when the potential of the reference low-potential signal input end is raised. Through the mode, the voltage stabilizing circuit is added, so that when the potential of the output reference low-potential signal changes due to parasitic capacitance, the potential of the output reference low-potential signal is adjusted, the output reference low-potential signal is more stable, and the stability and reliability of the GOA circuit are improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a GOA sub-circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a GOA sub-circuit according to an embodiment of the present invention;
fig. 4 is a signal timing diagram of a GOA sub-circuit according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a GOA sub-circuit according to another embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
GOA, namely gatedriver array, refers to the fabrication of gate driver circuits on an array substrate.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present invention, where the GOA circuit includes a plurality of cascaded GOA sub-circuits.
Fig. 1 illustrates an example of a cascade of N-1, N, and N +1 stages of GOA sub-circuits. Wherein, STNFor output of GOA sub-circuit of Nth stageStep-by-step signal, GNCK is a clock signal for the scanning signal output by the N-th GOA sub-circuit.
When the Nth-level GOA sub-circuit works, the scanning signal G output by the Nth-level GOA sub-circuitNA high potential for turning on the transistor switch of each pixel in a row in the panel and charging the pixel electrode in each pixel by a data signal; the Nth-level signal is used for controlling the work of the (N + 1) th-level GOA sub-circuit; when the N + 1-level GOA sub-circuit works, the scanning signal output by the N + 1-level GOA sub-circuit is at a high potential, and the scanning signal output by the N-level GOA sub-circuit is at a low potential.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a GOA sub-circuit according to an embodiment of the present invention, where the GOA sub-circuit includes a pull-up control circuit 11, a pull-up circuit 12, a pass-level circuit 13, a pull-down circuit 14, a pull-down holding circuit 15, and a bootstrap capacitor 16.
The pull-up circuit 12 includes a first clock signal input terminal, a first gate control signal input terminal, and a scan signal output terminal GN. Wherein, the first clock signal input terminal inputs clock signal, the scanning signal output terminal GNAnd outputting a scanning signal. The scan signal is used for driving one scan line, and when the scan signal is at a high potential, the transistor is controlled to be turned on, so that pixels in one row are charged.
The stage circuit 13 includes a second clock signal input terminal, a second gate control signal input terminal, and a stage signal output terminal STN. Wherein the second clock signal input terminal inputs the clock signal, and the stage signal output terminal STNThe output stage is used for outputting a signal and mainly controlling the opening and closing of a next-stage GOA sub-circuit.
The first clock signal input terminal and the second clock signal input terminal may input the same clock signal, specifically, may input a high frequency clock signal.
The pull-up control circuit 11 and the first and second gate control signal input terminals are coupled to a first common point QNThe pull-up control circuit 11 is used for the first common point Q during scanningNAnd (4) pre-charging.
The bootstrap capacitor 16 is coupled to the first common node QNAnd a scanning signal output terminal GNThe main function of the bootstrap capacitor 16 is to provide a scan signal output terminal GNPull-up and maintain the first common point Q during the period of outputting high potentialNThe potential of (2).
The pull-down circuit 14 is coupled to the first common point QNAnd a scanning signal output terminal GNAnd a pull-down circuit 14 having a main function of outputting a scan signal G with reference to a low potential signal input terminal VSSNPulling down the first common point Q after outputting the high potential signalNAnd a scanning signal output terminal GNTo the reference low potential VSS.
The pull-down maintaining circuit 15 is coupled to the first common node QNAnd a scanning signal output terminal GNAnd a pull-down holding circuit 15 mainly functioning as a scan signal output terminal G with reference to a low potential signal input terminal VSSNControlling the first common point Q after outputting a high potential signalNAnd a scanning signal output terminal GNIs maintained at the reference low potential.
Each grade of the GOA sub-circuit further includes a voltage stabilizing circuit 17, coupled to the reference low potential signal input terminal VSS, for pulling down the potential of the reference low potential signal input terminal VSS when the potential of the reference low potential signal input terminal VSS is raised.
For example, in one clock cycle, the pull-up control circuit 11 will set the first common point QNLifting to 4.5V; the pull-up circuit 12 outputs the scanning signalNThe potential is increased from the low potential of-3V to the high potential of 4V; the level transmission circuit 13 transmits the high level of the current GOA sub-circuit to the next level GOA sub-circuit; the bootstrap capacitor 16 is at a first common point QNCharging at high point, discharging at next clock period, and connecting the first common point QNThe potential rises; the pull-down circuit 14 connects the first common point QNAnd a scanning signal output terminal GNTo a reference low potential of-3V, the first common point Q in the next clock cycleNAnd a scanning signal output terminal GNThe potential of (2) is a low potential; the pull-down maintaining circuit 15 maintains the first common point Q after the current periodNAnd a scanning signal outputTerminal GNIs maintained at-3V.
Different from the prior art, the GOA circuit disclosed in this embodiment includes a plurality of cascaded GOA sub-circuits, each of which includes a pull-up control circuit, a pull-up circuit, a pass-down circuit, a pull-down sustain circuit, and a bootstrap capacitor; the pull-up circuit, the level pass circuit and the pull-up control circuit are coupled to the first common point, the bootstrap capacitor is coupled between the first common point and the scanning signal output end, the pull-down circuit is coupled to the first common point, the scanning signal output end and the reference low potential signal input end, and the pull-down maintaining circuit is coupled to the first common point, the scanning signal output end and the reference low potential signal input end; each GOA sub-circuit further comprises a voltage stabilizing circuit which is coupled with the reference low-potential signal input end and used for pulling down the potential of the reference low-potential signal input end when the potential of the reference low-potential signal input end is raised. Through the mode, the voltage stabilizing circuit is added, so that when the potential of the output reference low-potential signal changes due to parasitic capacitance, the potential of the output reference low-potential signal is adjusted, the output reference low-potential signal is more stable, and the stability and reliability of the GOA circuit are improved.
Referring to fig. 3, fig. 3 is a schematic circuit connection diagram of a GOA sub-circuit according to an embodiment of the present invention, where the GOA circuit includes a plurality of GOA sub-circuits arranged in a cascade, and each of the GOA sub-circuits includes a pull-up control circuit 21, a pull-up circuit 22, a pass-through circuit 23, a pull-down circuit 24, a pull-down maintaining circuit 25, a bootstrap capacitor 26, and a voltage stabilizing circuit 27.
The connection structure of each circuit is described in detail below, and it is understood that the transistor may be a Thin Film Transistor (TFT) including a gate (G), a source (S), and a drain (G), and in the following embodiments, an N-type transistor is taken as an example, and in other embodiments, a P-type transistor is also possible. In addition, the source and drain of the transistor may be switched.
The pull-up control circuit 21 comprises a first transistor T1 having a gate coupled to the stage signal output terminal ST of the previous GOA sub-circuitN-1A source electrode thereof is coupled with the scanning output signal output of the previous GOA sub-circuitTerminal GN-1The drain is coupled to the first common point QN。
The pull-up circuit 22 includes a fourth transistor T4 having a gate coupled to the first common point QNA source coupled to the first clock signal input terminal, and a drain coupled to the scan signal output terminal GN。
The pass stage 23 comprises a fifth transistor T5 having a gate coupled to the first common point QNA source electrode thereof is coupled to the second clock signal input terminal, and a drain electrode thereof is coupled to the stage signal output terminal STN。
Optionally, in this embodiment, the first clock signal input terminal and the second clock signal input terminal are the same port, and the input signals are both the first clock signal. It is understood that the first clock signal may be a high frequency clock signal, and in this embodiment, two sets of clocks may be used to drive the GOA circuit, that is, the first clock signal is input to the first clock signal input terminal and the second clock signal input terminal of the nth stage GOA sub-circuit, the second clock signal is input to the first clock signal input terminal and the second clock signal input terminal of the N +1 th stage GOA sub-circuit, and the first clock signal is input to the first clock signal input terminal and the second clock signal input terminal of the N +2 th stage GOA sub-circuit, so as to alternate.
The first clock signal and the second clock signal are two groups of clock signals with opposite waveforms, and the duty ratio of the two groups of clock signals is 50%.
The pull-down circuit 24 includes a sixth transistor T6 and a seventh transistor T7; wherein, the gate of the sixth transistor T6 is coupled to the scan output signal output terminal G of the next GOA sub-circuitN+1The source of which is coupled to the scan output signal output terminal GNThe drain electrode of the transistor is coupled with a reference low potential signal input end VSS; the gate of the seventh transistor T7 is coupled to the scan output signal output terminal G of the next GOA sub-circuitN+1The source of which is coupled to a first common point QNAnd a drain coupled to a reference low signal input terminal VSS.
The pull-down maintaining circuit 25 includes a first pull-down maintaining circuit 251 and a second pull-down maintaining circuit 252, the first pull-down maintaining circuit 251 and the second pull-down maintaining circuit 252 are arranged at the output end G of the scan signalNIs at a state of nonDriving time, alternately setting the first common point QNAnd a scanning signal output terminal GNIs pulled down to a low potential. Of course, in other embodiments, a pull-down holding circuit may be used to maintain the first common point QNAnd a scanning signal output terminal GNLow potential of (c).
The first pull-down sustain circuit 251 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.
Wherein, the gate and the source of the eighth transistor T8 are coupled to the third clock signal LC1, and the drain thereof is coupled to the source of the ninth transistor T9 and the gate of the tenth transistor T10. The gate of the ninth transistor T9 is coupled to the first common point QNAnd a drain coupled to a reference low signal input terminal VSS. A source of the tenth transistor T10 is coupled to the third clock signal LC1, and a drain thereof is coupled to a source of the eleventh transistor T11 and a gate of the twelfth transistor T12. The gate of the eleventh transistor T11 is coupled to the first common point QNThe drain of the transistor is coupled to a reference low level signal input terminal VSS. A source of the twelfth transistor T12 is coupled to the scan output signal output terminal GNThe drain of the transistor is coupled to a reference low level signal input terminal VSS. A thirteenth transistor T13 having a gate coupled to the gate of the twelfth transistor T12 and a source coupled to the first common point QNThe drain of the transistor is coupled to a reference low level signal input terminal VSS.
The second pull-down maintaining circuit 252 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19.
The gate and the source of the fourteenth transistor T14 are coupled to the fourth clock signal LC2, and the drain of the fourteenth transistor T14 is coupled to the source of the fifteenth transistor T15 and the gate of the sixteenth transistor T16. The gate of the fifteenth transistor T15 is coupled to the first common node QNAnd a drain coupled to a reference low signal input terminal VSS. A source of the sixteenth transistor T16 is coupled to the fourth clock signal LC2, and a drain thereof is coupled to a source of the seventeenth transistor T17 and a gate of the eighteenth transistor T18; seventeenth transistor T17) Is coupled to a first common point QNThe drain of the transistor is coupled to a reference low level signal input terminal VSS. A source of the eighteenth transistor T18 is coupled to the scan output signal output terminal GNThe drain of the transistor is coupled to a reference low level signal input terminal VSS. A nineteenth transistor T19 has a gate coupled to the gate of the eighteenth transistor T18 and a source coupled to the first common point QNThe drain of the transistor is coupled to a reference low level signal input terminal VSS.
The bootstrap capacitor 26 is coupled to the first common node QNAnd a scanning signal output terminal GNIn the meantime.
The voltage stabilizing circuit 27 includes a second transistor T2 having a gate and a drain coupled to the reference low potential signal input terminal VSS, and a source coupled to the gate of the first transistor T1.
Specifically, referring to fig. 4, fig. 4 is a signal timing diagram of the GOA sub-circuit of an embodiment of the GOA circuit, in which the first clock signal CK1 and the second clock signal CK2 are two sets of high frequency clock signals with opposite waveforms, and the duty ratio thereof is 50%. The third clock signal LC1 and the fourth clock signal LC2 are two sets of low frequency clock signals with opposite waveforms. The reference low potential signal VSS is a dc low voltage source.
Taking the nth-stage GOA sub-circuit as an example, the first clock signal is input to the first clock signal input terminal and the second clock signal input terminal of the nth-stage GOA sub-circuit.
In the first clock period, the stage signal ST outputted by the previous stage GOA sub-circuitN-1At high level, the first transistor T1 is turned on, due to the scan signal G outputted from the previous GOA sub-circuit inputted from the source of the transistor T1N-1Is high potential so that the first common point QNIs raised, the fourth transistor T4 and the fifth transistor T5 are turned on; at this time, since the first clock signal is at a low potential, the stage signal output terminal STNOutput stage signal and scanning output signal output end GNThe output scanning signals are all low potential.
In the second clock period, the stage signal ST output by the previous stage GOA sub-circuitN-1At a low potential, the first transistor T1 is turned off and the first common point QNPotential ofAnd is kept at the high potential, the fourth transistor T4 and the fifth transistor T5 are still turned on. At this time, the first clock signal is high, and therefore, the stage signal output terminal STNOutput stage signal and scanning signal output terminal GNThe output scanning signals are all high potential. At this stage, the scanning signal output terminal GNThe output scanning signal is at a high potential, so that the scanning line corresponding to the GOA sub-circuit of the current stage is charged, a row of pixels corresponding to the scanning line of the current stage is turned on, and the row of pixels is lighted.
Meanwhile, at this stage, the output terminal G is scannedNThe output scanning signal is high potential, and the first common point Q is connected under the action of a bootstrap capacitorNIs further raised, the turn-on of the fourth transistor T4 and the fifth transistor T5 and the stage signal output terminal ST are ensuredNAnd a scan output signal output terminal GNCan normally output high potential signals.
In the third clock cycle, the first clock signal is at low potential, and the stage signal output terminal STNAnd a scan output signal output terminal GNAnd outputting a low potential signal.
In addition, at this stage, the output end G of the scanning output signal of the next-stage GOA sub-circuitN+1Outputs a high signal to turn on the sixth transistor T6 and the seventh transistor T7, directly connects the first common node QNAnd a scan output signal output terminal GNConnected to a reference low potential signal input VSS, i.e. a first common point QNAnd a scan output signal output terminal GNIs pulled down to the reference low potential.
Due to the first common point QNIs pulled low, the ninth transistor T9 and the eleventh transistor T11 are turned off. At this time, the third clock signal LC1 is at a high level, the eighth transistor T8 is turned on, the gate of the tenth transistor T10 becomes a high level, the tenth transistor T10 is turned on, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the first common point Q is further turned onNAnd a scan output signal output terminal GNIs connected to the reference low potential signal input terminal VSS to maintain the first common point QNAnd a scan output signal output terminal GNIs at the reference low potential.
Of course, if the fourth clock signal LC2 is high and the third clock signal LC1 is low, the second pull-down maintaining circuit 252 is used to maintain the first common node QNAnd a scan output signal output terminal GNThe operation principle of the reference low potential is similar to that of the first pull-down holding circuit, and is not described herein again.
In the present embodiment, the gate of the second transistor T2 is coupled to the reference low potential signal input terminal VSS, and the source is coupled to the stage signal output terminal ST of the previous stageN-1The stage signal output terminal ST of the previous stageN-1When the voltage is low, the voltage is equal to the voltage of the reference low-potential signal input terminal VSS, that is, the gate-source voltage Vgs of the second transistor T2 is equal to 0, and the second transistor T2 is turned off. When the GOA circuit is affected by the coupling of the register capacitor of the scan line or the data line, the potential of the reference low-potential signal input terminal VSS may be raised, i.e., the gate-source voltage Vgs > 0 of the second transistor T2, and when the potential of the reference low-potential signal input terminal VSS is raised to a certain extent, the gate-source voltage Vgs > Vth of the second transistor T2 (the turn-on threshold voltage of the second transistor T2), the second transistor T2 is turned on, so that the stage signal output terminal ST of the previous stage is turned onN-1A stage signal ST connected to a reference low potential signal input terminal VSSN-1The low potential of the reference low potential signal input terminal VSS is transferred to the reference low potential signal input terminal VSS through the second transistor T2, thereby pulling down the potential of the reference low potential signal input terminal VSS and having a certain voltage stabilizing effect on the reference low potential signal input terminal VSS.
For example, the stage signal ST outputted by the previous GOA sub-circuitN-1The high potential of the reference low potential signal is 28V, the low potential is-6V, and the reference low potential signal VSS is-6V; current stage transmission signal STN-1When the voltage is high 28V and the reference low-potential signal VSS is-6V, the gate-source voltage Vgs of the second transistor T2 is-34V, and the second transistor T2 is in an off state; current stage transmission signal STN-1When the voltage is low-6V and the reference low-potential signal VSS is-6V, the gate-source voltage Vgs of the second transistor T2 is 0, and the gate-source voltage of the second transistor T2 is still in an off state, so that the reference low-potential signal VSS is not affectedStage transmission signal STN-1The high signal of (2) causes the GOA sub-circuit to be abnormally opened. When the data line is coupled to the scan line in the forward direction, the reference low-potential signal VSS is pulled high to be higher than-6V, and the gate-source voltage Vgs of the second transistor T2 is generated>0, the second transistor T2 is in an on state, the stage pass signal STN-1The low potential of the first transistor T2 is transmitted to the reference low potential signal VSS through the second transistor T2, so that a certain voltage stabilizing effect is achieved, and the larger the capacitive coupling effect is, the larger Vgs is, the larger the on-state current of the second transistor T2 is, and the more obvious the voltage stabilizing effect is. When the data line is coupled to the scan line in a negative capacitance manner, the reference low-potential signal VSS is pulled down to be lower than-6V, but the gate-source voltage Vgs is determined by the characteristics of the second transistor T2<0, the second transistor T2 is in the off state and does not affect the stability of the circuit.
Different from the prior art, in the GOA circuit disclosed in this embodiment, a transistor is added to the level signaling signal input terminal and the reference low potential signal input terminal, the gate and the drain of the transistor are coupled to the reference low potential signal input terminal, and the source of the transistor is coupled to the level signaling signal input terminal, so that when the low potential signal at the reference low potential signal input terminal is raised due to the coupling effect of the scan line and the data line, the low potential of the reference low potential signal can be stabilized, and the GOA circuit can normally operate.
Referring to fig. 5, fig. 5 is a schematic circuit connection diagram of a GOA sub-circuit according to another embodiment of the present invention, where the GOA circuit includes a plurality of GOA sub-circuits arranged in cascade, each of the plurality of GOA sub-circuits includes a pull-up control circuit 31, a pull-up circuit 32, a pass circuit 33, a pull-down circuit 34, a pull-down maintaining circuit 35, and a bootstrap capacitor 36, and each of the plurality of GOA sub-circuits is similar in structure to the above-mentioned GOA sub-circuit, except that a voltage stabilizing circuit 37 includes a third transistor T3 and a controller 371.
The third transistor T3 has a source coupled to the gate of the first transistor T1 and a drain coupled to the reference low signal input terminal VSS.
And a controller coupled to the reference low potential signal input terminal VSS and the gate of the third transistor T3, for detecting the voltage at the reference low potential signal input terminal VSS, and inputting a high potential signal to the gate of the third transistor T3 when the voltage at the reference low potential signal input terminal VSS is higher than a set voltage threshold, so as to turn on the third transistor T3.
For example, when the voltage at the reference low potential signal input terminal is-5.5V, the stage signal STN-1The voltage is-6V, the set voltage threshold is-6V, the controller outputs a high voltage of 3V to the gate of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 is 8.5V, the third transistor T3 is turned on, and the stage transfer signal ST is assertedN-1The voltage is transmitted to the reference low potential signal input end, and the voltage at the reference low potential signal input end is pulled down.
It is understood that the circuit principle of the present embodiment is similar to that of the above embodiments, and is not described herein again.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention, which includes a display area 100 and a GOA circuit 200 integrally disposed on an edge of the display area; the structure and principle of the GOA circuit 200 are similar to those of the above-mentioned GOA circuit, and are not described herein again.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (7)

1. A GOA circuit comprises a plurality of GOA sub-circuits which are arranged in a cascade mode, each GOA sub-circuit comprises a pull-up control circuit, a pull-up circuit, a cascade pass circuit, a pull-down maintaining circuit and a bootstrap capacitor,
the pull-up circuit comprises a first clock signal input terminal, a first gate control signal input terminal, and a scan signal output terminal (G)N) The stage circuit comprises a second clock signal input terminal, a second gate control signal input terminal, and a stage signal output terminal (ST)N) A pull-up control circuit and a first gate control signal input terminalThe second gate control signal input terminal is coupled to the first common point (Q)N) The bootstrap capacitor is coupled to the first common point (Q)N) And a scanning signal output terminal (G)N) A pull-down circuit coupled to the first common point (Q)N) And a scanning signal output terminal (G)N) And a reference low potential signal input terminal (VSS), a pull-down maintaining circuit coupled to the first common node (Q)N) And a scanning signal output terminal (G)N) And a reference low potential signal input terminal (VSS);
each GOA sub-circuit also comprises a voltage stabilizing circuit which is coupled with the reference low potential signal input end (VSS) and used for pulling down the potential of the reference low potential signal input end (VSS) when the potential of the reference low potential signal input end (VSS) is raised;
the pull-up control circuit comprises a first transistor (T1) with a gate coupled to a stage signal output terminal (ST) of a previous GOA sub-circuitN-1) A source electrode thereof is coupled with a scanning output signal output end (G) of the previous GOA sub-circuitN-1) The drain is coupled to a first common point (Q)N)；
The voltage stabilizing circuit comprises a third transistor (T3) and a controller, wherein the source electrode of the third transistor (T3) is coupled with the grid electrode of the first transistor (T1), and the drain electrode of the third transistor is coupled with a reference low potential signal input end (VSS); the controller is coupled to the reference low potential signal input terminal (VSS) and the gate of the third transistor (T3), and is configured to detect a voltage at the reference low potential signal input terminal (VSS), and input a high potential signal to the gate of the third transistor (T3) when the voltage at the reference low potential signal input terminal (VSS) is higher than a set voltage threshold, so as to turn on the third transistor (T3).
2. GOA circuit according to claim 1,
the pull-up circuit includes a fourth transistor (T4) having a gate coupled to the first common point (Q)N) A source coupled to the first clock signal input terminal, a drain coupled to the scan signal output terminal (G)N)。
3. GOA circuit according to claim 1,
the cascade circuit comprises a fifth transistor (T5) having a gate coupled to the first common node (Q)N) A source terminal coupled to the second clock signal input terminal, and a drain terminal coupled to the stage signal output terminal (ST)N)。
4. GOA circuit according to claim 1,
the pull-down circuit includes a sixth transistor (T6) and a seventh transistor (T7);
wherein, the gate of the sixth transistor (T6) is coupled to the scan output signal output terminal (G) of the next GOA sub-circuitN+1) The source of which is coupled to the scan output signal output terminal (G)N) A drain thereof is coupled to a reference low potential signal input terminal (VSS); the gate of the seventh transistor (T7) is coupled to the scan output signal output terminal (G) of the GOA sub-circuit of the next stageN+1) With its source coupled to a first common point (Q)N) And a drain coupled to a reference low signal input terminal (VSS).
5. GOA circuit according to claim 1,
the pull-down maintaining circuit comprises a first pull-down maintaining circuit and a second pull-down maintaining circuit, which are arranged at the output end of the scanning signal (G)N) In the non-driving time, the first common point (Q) is alternately setN) And a scanning signal output terminal (G)N) Is pulled down to a low potential.
6. GOA circuit according to claim 5,
the first pull-down sustain circuit includes an eighth transistor (T8), a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (T11), a twelfth transistor (T12), and a thirteenth transistor (T13);
the gate and source of the eighth transistor (T8) are coupled to the third clock signal (LC1), and the drain thereof is coupled to the source of the ninth transistor (T9) and the gate of the tenth transistor (T10);
the gate of the ninth transistor (T9) is coupled to the first common point (Q)N) The drain of which is coupled to a referenceA low potential signal input terminal (VSS);
a source of the tenth transistor (T10) is coupled to the third clock signal (LC1), and a drain thereof is coupled to a source of the eleventh transistor (T11) and a gate of the twelfth transistor (T12);
the gate of the eleventh transistor (T11) is coupled to the first common point (Q)N) A drain thereof is coupled to a reference low potential signal input terminal (VSS);
a source of the twelfth transistor (T12) is coupled to the scan output signal output terminal (G)N) A drain thereof is coupled to a reference low potential signal input terminal (VSS);
a thirteenth transistor (T13) having its gate coupled to the gate of the twelfth transistor (T12) and its source coupled to the first common node (Q)N) A drain thereof is coupled to a reference low potential signal input terminal (VSS);
the second pull-down sustain circuit includes a fourteenth transistor (T14), a fifteenth transistor (T15), a sixteenth transistor (T16), a seventeenth transistor (T17), an eighteenth transistor (T18), and a nineteenth transistor (T19);
a gate and a source of the fourteenth transistor (T14) are coupled to the fourth clock signal (LC2), and a drain thereof is coupled to a source of the fifteenth transistor (T15) and a gate of the sixteenth transistor (T16);
the gate of the fifteenth transistor (T15) is coupled to the first common node (Q)N) A drain thereof is coupled to a reference low potential signal input terminal (VSS);
a source of the sixteenth transistor (T16) is coupled to the fourth clock signal (LC2), and a drain thereof is coupled to the source of the seventeenth transistor (T17) and the gate of the eighteenth transistor (T18);
the gate of the seventeenth transistor (T17) is coupled to the first common node (Q)N) A drain thereof is coupled to a reference low potential signal input terminal (VSS);
a source of the eighteenth transistor (T18) is coupled to the scan output signal output terminal (G)N) A drain thereof is coupled to a reference low potential signal input terminal (VSS);
the nineteenth transistor (T19) has a gate coupled to the gate of the eighteenth transistor (T18), a source coupled to the first common point (QN), and a drain coupled to the reference low potential signal input terminal (VSS).
7. A display device comprising a GOA circuit according to any one of claims 1-6.
CN201711200160.0A 2017-11-24 2017-11-24 GOA circuit and display device Active CN107799087B (en)

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