TWI699740B - Sequential pulse generator - Google Patents

Abstract

A sequential pulse generator includes an input circuit, a regulator circuit, a pull-up circuit and a pull-down circuit. The input circuit is coupled to a first voltage source, a second voltage source and a node. The input circuit is configured to receive a first input signal or a second input signal and determine the voltage of the node according to the first input signal or the second input signal. The regulator circuit is coupled to the node, the first voltage source and the second voltage source. The regulator circuit is configured to receive the voltage of the node or the second input signal and maintain the voltage of the output terminal according to the voltage of the node or the second input signal. The pull-up circuit is coupled to the node, the third voltage and the output terminal. The pull-up circuit is configured to receive the voltage of the node and output the voltage of the third voltage source to the output terminal according to the voltage of the node. The pull-down circuit is coupled to the output and the second voltage. The pull-down circuit is configured to receive the second input signal and output the voltage of the second voltage source to the output terminal according to the second input signal.

Description

Pulse wave generating circuit

This disclosure relates to a pulse wave generating circuit, particularly a pulse wave generating circuit for outputting a wide pulse wave.

The light sensing circuit in the display panel needs a long enough pulse signal to detect whether the light source is input or not. However, the shift register circuit in the traditional gate driver cannot output a driving signal with a long pulse width, which leads to display The light sensing circuit in the panel does not have enough time to operate, so the gate driver needs to be designed for how to output a pulse signal of sufficient width and stability.

In an embodiment of the present disclosure, a pulse wave generating circuit includes an input circuit, a voltage stabilizing circuit, a pull-up circuit, and a pull-down circuit. The input circuit is coupled to the first voltage source, the second voltage source, and the node. The input circuit receives the first input signal or the second input signal, and determines the voltage of the node according to the first input signal or the second input signal. The voltage stabilizing circuit is coupled to the node, the first voltage source and the second voltage source. The voltage stabilizing circuit is used to receive the voltage of the node or the second input signal, and maintain the output terminal according to the voltage of the node or the second input signal The voltage. The pull-up circuit is coupled to the node, the third voltage source and the output terminal. The pull-up circuit receives the voltage of the node. The pull-up circuit outputs the voltage of the third voltage source to the output terminal according to the voltage of the node. The pull-down circuit is coupled to the output terminal and the second voltage source. The pull-down circuit receives the second input signal. The pull-down circuit outputs the voltage of the second voltage source to the output terminal according to the second input signal.

In summary, the pulse wave generating circuit can output the voltage of the second voltage source or the third voltage source to the output terminal according to the first input signal or the second input signal, and maintain the voltage at the output terminal by the voltage stabilizing circuit.

100‧‧‧Display Panel

110‧‧‧Timing control circuit

120‧‧‧Gate Driver

122‧‧‧Shift temporary storage circuit

124‧‧‧Shift temporary storage circuit

126‧‧‧Pulse wave generating circuit

126a‧‧‧Input circuit

126b‧‧‧Regulator circuit

126c‧‧‧Pull-up circuit

126d‧‧‧Pull-down circuit

130‧‧‧Source Driver

140‧‧‧Image display area

142‧‧‧display pixel

CK, XCK‧‧‧clock signal

TC1, TC2‧‧‧signal line

GL1, GL2, GL3, GLN, GLM‧‧‧Scan lines

SL1, SL2, SL3, SLK‧‧‧Data line

T1~T12、TS1~TS7‧‧‧Transistor

VH, VGH, VDD, VDDH, U2D‧‧‧High voltage

VGL, VSS, D2U‧‧‧Low voltage

△V‧‧‧Voltage

C1, C2, C3‧‧‧Capacitor

TM1, TP1‧‧‧Enter time

TM2, TP2‧‧‧Enable time

TM3, TP3‧‧‧Pull-down time

TP4‧‧‧Reset time

G1[N-1]‧‧‧The first input signal of the upper level

G1[N+1]‧‧‧The first input signal of the next level

G1[N]‧‧‧First input signal

G2[N]‧‧‧Second input signal

Q1[N], Q2[N]‧‧‧node

S[N]‧‧‧Output signal

FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure.

FIG. 2 shows a block diagram of a gate driver according to an embodiment of the present disclosure.

FIG. 3 shows a diagram of a shift register circuit according to an embodiment of the present disclosure. FIG. 4 shows a signal timing diagram corresponding to the shift register circuit of FIG. 3.

FIG. 5 shows a circuit diagram of pulse wave generation according to an embodiment of the present disclosure.

FIG. 6 shows a signal timing diagram corresponding to the pulse wave generating circuit in FIG. 5.

FIG. 7 is a schematic diagram illustrating the operation of the pulse wave generating circuit in the input time interval according to an embodiment of the present disclosure.

Figure 8 shows a pulse wave generating electricity according to an embodiment of the present disclosure Schematic diagram of the operation in the enabling time interval.

FIG. 9 is a schematic diagram of the operation of the pulse generation circuit in the pull-down time interval according to an embodiment of the disclosure.

FIG. 10 is a schematic diagram illustrating the operation of the pulse wave generating circuit in the reset time interval according to an embodiment of the present disclosure.

The terms "include", "have" and so on used in this article are all open terms, meaning "including but not limited to". In addition, the “and/or” used in this article includes any one of one or more of the related listed items and all combinations thereof.

In this text, when an element is referred to as "connected" or "coupled", it can be referred to as "electrical connection" or "electrical coupling." "Link" or "coupling" can also be used to indicate the coordinated operation or interaction between two or more components. In addition, although terms such as "first", "second", ... are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless the context clearly indicates, the terms do not specifically refer to or imply the order or sequence, nor are they used to limit the present disclosure.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure. As shown in FIG. 1, the display panel 100 includes a timing control circuit 110, a gate driver 120, a source driver 130 and an image display area 140. The image display area 140 is formed by interlacing multiple scan lines GL1~GLN and multiple data lines SL1~SLN, and includes a plurality of display pixels 142. Here, the number N is taken as an example for illustration. The number of N can be based on actual conditions. The size of the applied panel is adjusted. The timing control circuit 110 is coupled to the gate driver 120 and the source driver 130, and controls the timing of circuit operations of the gate driver 120 and the source driver 130 by sending timing control signals through the signal line TC1 and the signal line TC2. The gate driver 120 outputs gate driving signals to the image display area 140 to the corresponding display pixels 124 through the M scan lines GL1 ˜GLM. The source driver 130 outputs source driving signals to the image display area 140 to the corresponding display pixels 124 through the K data lines SL1 ˜SLK. In one embodiment, the display panel 100 is a screen with a resolution of 1920x1080, M is 1080, and K is 1920.

Please refer to FIG. 2. FIG. 2 is a block diagram of a gate driver according to an embodiment of the present disclosure. The gate driver 120 includes a shift register circuit 122, a shift register circuit 124, and a pulse wave generating circuit 126. As shown in Figure 2, the shift register circuit 122 and the shift register circuit 124 are used to generate the first input signal G1[N] and the second input signal G2[N] to the pulse wave generating circuit 126, and the pulse wave is generated The circuit 126 receives the first input signal G1[N] and the second input signal G2[N] and generates an output signal S[N]. It should be noted that although the block diagram of the gate driver 120 in Figure 2 only shows one set of circuits, the actual application is not limited to one. The gate driver 120 in this disclosure uses numbers G1[N], G2[N] And S[N] are denoted as the Nth shift register circuit 122, shift register circuit 124, and pulse generation circuit 126. Actually, a plurality of shift register circuits 122, shift register circuits 124 and pulse generation circuit can be used. The wave generating circuit 126 implements the document of the present disclosure, the number of which can be adjusted according to actual applications. N is a value greater than or equal to 1 and less than or equal to M, and is a positive integer. In the foregoing embodiment, N is between 1 and 1080 Any value of. The following details the shift register circuit 122. The internal circuit structure of the shift register circuit 124 and the pulse wave generation circuit 126.

Please refer to FIG. 3, which is a circuit diagram of a shift register according to an embodiment of the present disclosure. The shift register circuit 122 includes transistors TS1~TS7, high voltage U2D, low voltage D2U, the first input signal G1[N-1] of the previous stage, the first input signal G1[N+1] of the next stage, and the node Q1[ N], clock signal CK, clock signal XCK, capacitor C1, capacitor C2, low voltage VSS, and first input signal G1[N]. The transistors TS1~TS7 all include a first terminal, a second terminal and a control terminal. The first terminal of the transistor TS1 is used to receive the high voltage U2D, and the second terminal of the transistor TS1 is coupled to the second terminal and the node of the transistor TS2 Q1[N], the control terminal of the transistor TS1 is used to receive the first input signal G1[N-1] of the upper stage, and conduct the high voltage U2D to the node Q1 according to the first input signal G1[N-1] of the upper stage [ N]. The first terminal of the transistor TS2 is used to receive the low voltage D2U, the second terminal of the transistor TS2 is coupled to the second terminal of the transistor TS1 and the node Q1[N], and the control terminal of the transistor TS2 is used to receive the next first stage Input signal G1[N+1], and turn on the low voltage D2U to the node Q1[N] according to the first input signal G1[N+1] of the next stage. The first terminal of the transistor TS3 is used to receive the clock signal CK, the second terminal of the transistor TS3 is coupled to the output terminal, the control terminal of the transistor TS3 is coupled to the capacitor C2 and the node Q1[N], the control terminal of the transistor TS3 It is used to receive the voltage of the node Q1[N] and turn on the clock signal CK to the output terminal according to the voltage of Q1[N]. The first terminal of the transistor TS4 is coupled to the output terminal, and the second terminal of the transistor TS4 is coupled to the voltage source VSS. The control terminal of the transistor TS4 is used to receive the clock signal XCK, and according to the clock signal XCK, the voltage source VSS The voltage is conducted to the output terminal. The first end of transistor TS5 is coupled to capacitor C1, The control terminal of the transistor TS6 and the control terminal of the transistor TS7, the second terminal of the transistor TS5 is coupled to the voltage source VSS, the control terminal of the transistor TS5 is used to receive the voltage of the node Q1[N], and according to the node Q1[N ] The voltage of the voltage source VSS is conducted to the capacitor C1, the control terminal of the transistor TS6, and the control terminal of the transistor TS7. The first terminal of the transistor TS6 is coupled to the node Q1[N], the second terminal of the transistor TS6 is coupled to the voltage source VSS, and the control terminal of the transistor TS6 is coupled to the capacitor C1 and the first terminal of the transistor TS5. The first terminal of the transistor TS7 is coupled to the capacitor C2, the output terminal and the first terminal of the transistor TS4, the second terminal of the transistor TS7 is coupled to the voltage source VSS, and the control terminal of the transistor TS7 is coupled to the capacitor C1 and the transistor TS5 The first terminal and the control terminal of transistor TS6. The operation mode of the shift register circuit 122 at each time will be described in detail below.

Please refer to FIG. 3 and FIG. 4 at the same time. FIG. 4 shows a signal timing diagram corresponding to the shift register circuit of FIG. 3. The shift register circuit 122 operates in the input time TM1, the enable time TM2, and the pull-down time TM3 as shown in FIG. 4, where VDD and VGH represent high voltages, and VSS and VGL represent low voltages. When the shift register circuit 122 inputs the time TM1, the clock signal CK is a low voltage VSS, the clock signal XCK is a high voltage VDD, and the first input signal G1[N-1] of the previous stage is a high voltage VDD. Transistor TS1 is turned on, turning high voltage U2D to node Q1[N] to increase the voltage of node Q1[N]. Transistor TS3 is turned on due to the rise in voltage of node Q1[N], turning on the voltage of clock signal CK to At the output end, since the clock signal CK is a low voltage VSS and the clock signal XCK is a high voltage VDD, the first input signal G1[N] is a low voltage VSS. The voltage rise of node Q1[N] turns on transistor TS5, and turns on low voltage VSS to transistor TS6 and transistor TS7. The control terminal turns off the transistor TS6 and the transistor TS7 to maintain the voltage of the node Q1[N].

At the enable time TM2 of the shift register circuit 122, the clock signal CK is a high voltage VDD, the clock signal XCK is a low voltage VSS, and the first input signal G1[N-1] of the previous stage is a low voltage VSS. At this time, the first input signal G1[N] outputs a high voltage VGH close to the high voltage VDD because the clock signal CK is a high voltage VDD, and the clock signal XCK is a low voltage VSS so that the transistor TS4 is turned off and the first input signal G1 [N] can maintain a high voltage. The voltage of node Q1[N] is pulled up to a high voltage VDD+△V due to capacitor C2. The high voltage of node Q1[N] keeps transistor TS5 conducting while transistor TS6 and transistor TS7 remains off, and the first input signal G1[N] can be maintained at the high voltage VGH due to the off of transistors TS4, TS6 and TS7.

During the pull-down time TM3 of the shift register circuit 122, the clock signal CK is a low voltage VSS, the clock signal XCK is a high voltage VDD, and the next-stage first input signal G1[N+1] is a high voltage VDD. Transistor TS2 turns on to turn on low voltage D2U to node Q1[N], causing the voltage of node Q1[N] to drop. Transistor TS3 and transistor TS5 are turned off due to the drop in voltage of node Q1[N]. The clock signal XCK is The high voltage VDD turns on the transistor TS4 and turns on the low voltage VSS to the output terminal. The first input signal G1[N] is the low voltage VGL.

A plurality of shift register circuits 122 can be connected in series to achieve the effect of outputting a plurality of pulse waves in sequence. The circuit structure and operation mode of the shift register circuit 124 and the shift register circuit 122 are the same, which will not be repeated here. The pulse signal generated by the shift register circuit 122 is marked as the first input signal G1[N]. The pulse signal generated by the storage circuit 124 is labeled as the second input signal G2[N], and is sent to the pulse generation circuit 126, as shown in FIG.

Please refer to FIG. 5. FIG. 5 is a diagram of a pulse wave generating circuit according to an embodiment of the present disclosure. The pulse wave generating circuit 126 includes an input circuit 126a, a voltage stabilizing circuit 126b, a pull-up circuit 126c, and a pull-down circuit 126d. The input circuit 126a includes transistors T1 to T4. The transistors T1 to T4 all include a first terminal, a second terminal and a control terminal. The first terminal of the transistor T1 receives the high voltage VDDH, and the second terminal of the transistor T1 is coupled to the node Q2[N], the control terminal of the transistor T1 is used to receive the first input signal G1[N]. The first end of the transistor T2 is coupled to the second end of the transistor T1, and the control end of the transistor T2 is used to receive the second input signal G2[N]. The first terminal of the transistor T3 is used to receive the high voltage VDDH, the second terminal of the transistor T3 is coupled to the second terminal of the transistor T2, and the control terminal of the transistor T3 is coupled to the second terminal of the transistor T1 and the transistor T2 The first end and node Q2[N]. The first end of the transistor T4 is coupled to the second end of the transistor T2 and the second end of the transistor T3, the second end of the transistor T4 is used to receive the low voltage VSS, and the control end of the transistor T4 is coupled to the transistor T2 The control terminal of the transistor T4 is used to receive the second input signal G2[N]. The input circuit 126a is used to receive the first input signal G1[N] or the second input signal G2[N], and determine the node Q2[N] according to the first input signal G1[N] or the second input signal G2[N] Voltage.

The voltage stabilizing circuit 126b includes transistors T7 to T12, and the transistors T7 to T12 all include a first terminal, a second terminal, and a control terminal. The first end of the transistor T7 is coupled to the control end of the transistor T7 for receiving the second input signal G2[N]. The first end of the transistor T8 is coupled to the second end of the transistor T7, and the transistor The second terminal of the body T8 is used to receive the low voltage VSS, and the control terminal of the transistor T8 is coupled to the node Q2[N] for receiving the voltage of the node Q2[N]. The first end of the transistor T9 is coupled to the node Q2[N], and the control end of the transistor T9 is coupled to the second end of the transistor T7 and the first end of the transistor T8. The first end of the transistor T10 is coupled to the second end of the transistor T9, the second end of the transistor T10 is coupled to the low voltage VSS, and the control end of the transistor T10 is coupled to the second end of the transistor T7 and the second end of the transistor T8. The first terminal and the control terminal of the transistor T9. The first end of the transistor T11 is coupled to the output end, the second end of the transistor T11 is coupled to the second end of the transistor T9 and the first end of the transistor T10, and the control end of the transistor T11 is coupled to the first end of the transistor T7. Two terminals, the first terminal of the transistor T8, the control terminal of the transistor T9 and the control terminal of the transistor T10. The first end of the transistor T12 is coupled to the high voltage VDDH, the second end of the transistor T12 is coupled to the second end of the transistor T9, the first end of the transistor T10 and the second end of the transistor T11, the second end of the transistor T12 The control terminal is coupled to the node Q2[N] for receiving the voltage of the node Q2[N]. The voltage stabilizing circuit 126b maintains the output signal S[N] according to the voltage of the node Q2[N].

The pull-up circuit 126c includes a transistor T5, a node Q2[N] and a capacitor C1. The transistor T5 includes a first terminal, a second terminal and a control terminal. The first terminal of the transistor T5 is coupled to the high voltage VDD, the second terminal of the transistor T5 is coupled to the output terminal, and the control terminal of the transistor T5 is coupled to the node Q2 [N]. The capacitor C1 is coupled to the node Q2[N], the control terminal and the output terminal of the transistor T5. The pull-up circuit 126c outputs the high voltage VDD to the output terminal according to the voltage of the node Q2[N].

The pull-down circuit 126d includes a transistor T6. The transistor T6 includes a first terminal, a second terminal and a control terminal. The first terminal of the transistor T6 is coupled to the output terminal and the second terminal of the transistor T5. The second terminal of the transistor T6 Coupling low voltage VSS, the control terminal of the transistor T6 is used to receive the second input signal G2[N]. The pull-down circuit 126d outputs the low voltage VSS to the output terminal according to the second input signal G2[N].

In the above-mentioned embodiment, the pulse wave generating circuit 126 uses transistors T1 to T12 as switching elements, but this disclosure is not limited to this. In other embodiments, the pulse wave generating circuit 126 can also adopt other same functions. Those skilled in the art can understand how to replace the above-mentioned switching elements, and different switching elements are within the scope of this disclosure.

It should be noted that the implementation of the devices and components in the shift register circuit 122 and the pulse generation circuit 126 are not limited to those disclosed in the above-mentioned embodiments, and the connection relationship is not limited to the above-mentioned embodiments. The connection methods and implementation methods that enable the shift register circuit 122 and the pulse wave generation circuit 126 to implement the following technical content can be applied to this case.

Please refer to FIG. 6, which shows a signal timing diagram corresponding to the pulse wave generating circuit of FIG. 5. The pulse wave generating circuit 126 operates in the input time TP1, the enable time TP2, the pull-down time TP3, and the reset time TP4 as shown in FIG. 6. In this embodiment, VGH and VDD are used to indicate high voltage, and VSS Indicates low voltage. For example, VDDH is 25 volts, VDD is 15 volts, VH is VDDH-VTH (the threshold voltage of transistor T1), and VSS is -10 volts. The operation mode of the pulse wave generating circuit 126 at each time will be described in detail below.

Please refer to FIG. 6 and FIG. 7 at the same time. FIG. 7 is a schematic diagram illustrating the operation of the pulse wave generating circuit in the input time interval according to an embodiment of the present disclosure. The arrow in Figure 7 indicates the direction in which the circuit is turned on, and the cross indicates the transistor is off. Figures 8 to 10 have the same labels and will not be repeated here. At the input time TP1, the first input signal G1[N] is the high voltage VGH, and the second input signal G2[N] is the low voltage VGL. The control terminal of the transistor T1 receives the first input signal G1[N], so the transistor T1 will be turned on, turning on the high voltage VDDH to the node Q2[N], making the node Q2[N] a high voltage. The high voltage of the node Q2[N] charges the capacitor C3, and the transistor T5 is turned on because of the node Q2[N], and the high voltage VDD is turned on to the output terminal. At this time, the output signal S[N] is a high voltage, as shown in Figure 6. Shown. At this time, since the second input signal G2[N] is at a low voltage, the transistor T2 and the transistor T4 are turned off, and the high voltage of the node Q2[N] turns on the transistor T3, and the high voltage VDDH is conducted to the transistor T2 and The second terminal (eg, the source) of the transistor T4 reduces the voltage difference V _GS (gate-to-source voltages) between the control terminal and the second terminal of the transistor T2 and the transistor T4. Since the leakage current of the transistor is proportional to the V _GS voltage, the stacked structure of the transistors T2~T4 is used to control the V _{GS of} the transistor T2 and the transistor T4 in the stacked structure to make the leakage current of the transistor T2 and the transistor T4 Decrease, thus improving the leakage of node Q2[N] to transistor T2 and transistor T4.

The second input signal G2[N] is a low voltage, which turns off the transistor T7, and the high voltage of the node Q2[N] turns on the transistor T8, and conducts the low voltage VSS to the transistors T9, T10, and T11. On the control side, turn off transistor T9, transistor T10, and transistor T11. The high voltage of the node Q2[N] turns on the transistor T12, which is similar to the operation of the transistor T2, the transistor T3 and the transistor T4, using the stacked structure of the transistor T9, the transistor T10 and the transistor T12, the transistor T12 The high voltage VDDH is conducted to the second ends of the transistor T9 and the transistor T10, so that the V _{GS of the} transistor T9 and the transistor T10 is reduced, and the leakage of the node Q2[N] to the transistor T9 and the transistor T10 is restricted.

Please refer to FIG. 6 and FIG. 8 at the same time. FIG. 8 is a schematic diagram illustrating the operation of the pulse wave generating circuit in the enabling time interval according to an embodiment of the present disclosure. At the enabling time TP2, the first input signal G1[N] is at a low voltage, so that the transistor T1 is turned off. The second input signal G2[N] is the same low voltage as at the input time TP1, so that the transistor T2, the transistor T4, the transistor T6, and the transistor T7 are turned off. The node Q2[N] is a high voltage to turn on the transistor T3, the transistor T8, and the transistor T12. Similarly, the stacked structure formed by the transistor T2, the transistor T3 and the transistor T4 reduces the V _GS of the transistor T2 and the transistor T4 to limit the leakage current of the transistor T2 and the transistor T4 and improve the pulse generation circuit 126 At the enable time TP2, the leakage status of the node Q2[N] to the path of the transistor T2 and the transistor T4. Similarly, the stacked structure formed by the transistor T9, the transistor T10 and the transistor T12 reduces the V _GS of the transistor T9 and the transistor T10 to limit the leakage current of the transistor T9 and the transistor T10, and to improve the node Q2[N] For the leakage status of the transistor T9 and the transistor T10 path. When the node Q2[N] is maintained at a high voltage, the transistor T12 will conduct the high voltage VDDH to the second terminal of the transistor T11, reduce the V _GS of the transistor T11, limit the leakage current of the transistor T11, and make the output signal When S[N] is maintained at a high voltage, it limits the leakage of the voltage to the transistor T11 and achieves the effect of continuously outputting a high voltage.

Please refer to FIG. 6 and FIG. 9 at the same time. FIG. 9 shows the operation of the pulse wave generating circuit in the pull-down time interval according to an embodiment of the present disclosure. Make a schematic diagram. During the pull-down time TP3, the first input signal G1[N] is a low voltage, and the second input signal G2[N] is a high voltage. The first input signal G1[N] is a low voltage to turn off the transistor T1, and the second input signal G2[N] is a high voltage to turn on the transistor T2, the transistor T4, the transistor T6, and the transistor T7. The voltage of the node Q2[N] becomes close to the low voltage VSS because the transistor T2, the transistor T4, the transistor T9, and the transistor T10 are turned on. At this time, the transistor T5, the transistor T8, and the transistor T12 are turned off. The transistor T5 is turned off and the transistor T6 is turned on, so that the voltage of the output signal S[N] drops to close to the low voltage VSS.

Please refer to FIG. 10, which is a schematic diagram illustrating the operation of the pulse wave generating circuit in the reset time interval according to an embodiment of the present disclosure. At the reset time TP4, all transistors are turned off, and the output signal S[N] is maintained at the low voltage VSS for a period of time due to the parasitic capacitance (not shown) of the output terminal.

Referring to the pulse wave generating circuit 126 in the embodiment of FIG. 5, the level of the node Q2[N] in this embodiment is the first input signal G1[N] generated by the two shift register circuits 122 and 124 And the second input signal G2[N], and because of the transistor stack structure in the pulse generating circuit 126, the level of the node Q2[N] can be prevented from dropping due to leakage current, so the output signal S[ N] is high potential.

In summary, the pulse wave generating circuit has different operation modes according to different input signals. During the enabling time, the voltage is maintained by the overlapping structure of the voltage stabilizing circuit, so that the output terminal of the pulse wave generating circuit can maintain a high output for a long time. Potential, prolong the operation time of the circuit, and use multiple paths to discharge during the pull-down time, reducing the time for the output signal to fall.

Those skilled in the art should understand that in each embodiment, Each circuit unit can be implemented by various types of digital or analog circuits, and can also be implemented by different integrated circuit chips. Each component can also be integrated into a single integrated circuit chip. The foregoing is only an example, and the present disclosure is not limited to this. Electronic components such as resistors, capacitors, diodes, transistor switches, etc., can be made of various appropriate components. For example, the transistors T1~T12 can be selected according to the needs of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Bipolar Junction Transistor (BJT) or various other types. Type of transistor implementation.

Although the content of this disclosure has been disclosed in the above manner, it is not used to limit the content of this disclosure. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection of the content shall be subject to the scope of the attached patent application.

126‧‧‧Pulse wave generating circuit

126a‧‧‧Input circuit

120b‧‧‧Regulating circuit

126c‧‧‧Pull-up circuit

126d‧‧‧Pull-down circuit

T1~T12‧‧‧Transistor

VSS, VDD, VDDH‧‧‧High voltage

C3‧‧‧Capacitor

G1[N]‧‧‧First input signal

G2[N]‧‧‧Second input signal

Q2[N]‧‧‧Node

S[N]‧‧‧Output signal

Claims (12)

A pulse wave generating circuit includes: an input circuit coupled to a first voltage source, a second voltage source and a node, the input circuit is used to receive a first input signal or a second input signal, and according to the The first input signal or the second input signal determines the voltage of the node; a voltage stabilizing circuit is coupled to the node, the first voltage source and the second voltage source, and the voltage stabilizing circuit is used to receive the voltage or The second input signal maintains the voltage of an output terminal according to the voltage of the node or the second input signal; a pull-up circuit is coupled to the node, a third voltage source and the output terminal, and the pull-up circuit is used for Receiving the voltage of the node, the pull-up circuit outputs the voltage of the third voltage source to the output terminal according to the voltage of the node; and a pull-down circuit coupled to the output terminal and the second voltage source, the pull-down circuit For receiving the second input signal, the pull-down circuit outputs the voltage of the second voltage source to the output terminal according to the second input signal; wherein the input circuit includes: a first transistor including a first terminal , A second terminal and a control terminal, the first terminal of the first transistor is coupled to the first voltage source, the second terminal of the first transistor is coupled to the node, the first transistor of the first transistor The control terminal is coupled to the first input signal, the first transistor is selectively turned on according to the first input signal; a second transistor includes a first terminal, a second terminal and a control Terminal, the first terminal of the second transistor is coupled to the second terminal of the first transistor and the node, the control terminal of the second transistor is coupled to the second input signal, the second transistor Selectively conduction according to the second input signal; a third transistor including a first terminal, a second terminal and a control terminal, the first terminal of the third transistor is coupled to the first voltage source, The second end of the third transistor is coupled to the second end of the second transistor, and the control end of the third transistor is coupled to the second end of the first transistor, the second transistor The first terminal and the node, the third transistor is selectively turned on according to the voltage of the node; and a fourth transistor including a first terminal, a second terminal and a control terminal, the fourth transistor The first end of the crystal is coupled to the second end of the third transistor, the second end of the fourth transistor is coupled to the second voltage source, and the control end of the fourth transistor is coupled to the first Two input signals, the fourth transistor is selectively turned on according to the second input signal. The pulse wave generating circuit according to claim 1, wherein the voltage stabilizing circuit comprises: a fifth transistor including a first terminal, a second terminal and a control terminal, the first terminal of the fifth transistor Coupled to the control terminal of the fifth transistor, the first terminal and the control terminal of the fifth transistor are used for receiving the second input signal, and the fifth transistor is selectively turned on according to the second input signal ; A sixth transistor, including a first end, a second end and a control end, the first end of the sixth transistor is coupled to the second of the fifth transistor Terminal, the second terminal of the sixth transistor is coupled to the second voltage source, the control terminal of the sixth transistor is coupled to the node, and the sixth transistor is selectively turned on according to the voltage of the node; A seventh transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the seventh transistor is coupled to the node, and the control terminal of the seventh transistor is coupled to the fifth transistor The second end of the sixth transistor and the first end of the sixth transistor; an eighth transistor includes a first end, a second end and a control end, the first end of the eighth transistor is coupled to The second end of the seventh transistor, the second end of the eighth transistor is coupled to the second voltage source, the control end of the eighth transistor is coupled to the control end of the seventh transistor, The second end of the fifth transistor and the first end of the sixth transistor; a ninth transistor includes a first end, a second end and a control end, the ninth transistor The first end is coupled to the output end, the second end of the ninth transistor is coupled to the second end of the seventh transistor and the first end of the eighth transistor, the control of the ninth transistor The terminal is coupled to the second terminal of the fifth transistor, the first terminal of the sixth transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor; a tenth transistor , Including a first terminal, a second terminal and a control terminal, the first terminal of the tenth transistor is coupled to the second terminal of the seventh transistor and the first terminal of the eighth transistor, The second terminal of the tenth transistor is coupled to the first voltage source, the control terminal of the tenth transistor is coupled to the node, and the tenth transistor is selectively turned on according to the voltage of the node. The pulse wave generating circuit according to claim 1, wherein the pull-up circuit comprises: a fifth transistor including a first terminal, a second terminal and a control terminal, the first terminal of the fifth transistor Coupled to a third voltage source, the second terminal of the fifth transistor is coupled to the output terminal, the control of the fifth transistor is coupled to the node, and the fifth transistor is selectively turned on according to the voltage of the node A capacitor includes a first terminal and a second terminal, the first terminal of the capacitor is coupled to the node, and the second terminal of the capacitor is coupled to the output terminal. The pulse wave generating circuit according to claim 1, wherein the pull-down circuit includes: a fifth transistor including a first terminal, a second terminal and a control terminal, and the first terminal of the fifth transistor is coupled Connected to the output terminal, the second terminal of the fifth transistor is coupled to the second voltage source, the control terminal of the fifth transistor is used to receive the second input signal, and the fifth transistor is based on the second voltage source The input signal is selectively turned on. The pulse wave generating circuit according to claim 1, wherein the pulse wave generating circuit outputs the voltage of the second voltage source or the voltage of the third voltage source to the output according to the first input signal or the second input signal end. The pulse wave generating circuit according to claim 1, wherein the The pulse wave generating circuit operates in an operation mode, which includes a first input time, a consistent energy time, a pull-down time, and a reset time. The pulse wave generating circuit according to claim 6, wherein the pulse wave generating circuit outputs a high voltage during the enabling time interval. The pulse wave generating circuit according to claim 6, wherein the pulse wave generating circuit outputs a low voltage during the pull-down time interval. The pulse wave generating circuit according to claim 6, wherein the voltage stabilizing circuit maintains the voltage of the node at a high voltage during the enabling time interval. A pulse wave generating circuit includes: an input circuit coupled to a first voltage source, a second voltage source and a node, the input circuit is used to receive a first input signal or a second input signal, and according to the The first input signal or the second input signal determines the voltage of the node; a voltage stabilizing circuit is coupled to the node, the first voltage source and the second voltage source, and the voltage stabilizing circuit is used to receive the voltage or The second input signal maintains the voltage of an output terminal according to the voltage of the node or the second input signal; a pull-up circuit is coupled to the node, a third voltage source and the output terminal, and the pull-up circuit is used for Receive the voltage of the node, the pull-up circuit according to The voltage of the node outputs the voltage of the third voltage source to the output terminal; and a pull-down circuit, coupled to the output terminal and the second voltage source, the pull-down circuit for receiving the second input signal, the pull-down circuit The circuit outputs the voltage of the second voltage source to the output terminal according to the second input signal; wherein the voltage stabilizing circuit includes: a first transistor including a first terminal, a second terminal and a control terminal, The first end of the first transistor is coupled to the control end of the first transistor, and the first end and the control end of the first transistor are used for receiving the second input signal, the first transistor Selectively conduction according to the second input signal; a second transistor, including a first terminal, a second terminal and a control terminal, the first terminal of the second transistor is coupled to the first transistor The second terminal, the second terminal of the second transistor is coupled to the second voltage source, the control terminal of the second transistor is coupled to the node, and the second transistor is selectively based on the voltage of the node On; a third transistor, including a first end, a second end and a control end, the first end of the third transistor is coupled to the node, the control end of the third transistor is coupled to the first The second end of a transistor and the first end of the second transistor; a fourth transistor including a first end, a second end and a control end, the first end of the fourth transistor Terminal is coupled to the second terminal of the third transistor, the second terminal of the fourth transistor is coupled to the second voltage source, and the control terminal of the fourth transistor is coupled to the third transistor Control end, the first The second end of the transistor and the first end of the second transistor; a fifth transistor including a first end, a second end and a control end, the first end of the fifth transistor Coupled to the output terminal, the second terminal of the fifth transistor is coupled to the second terminal of the third transistor and the first terminal of the fourth transistor, and the control terminal of the fifth transistor is coupled to The second end of the first transistor, the first end of the second transistor, the control end of the third transistor, and the control end of the fourth transistor; and a sixth transistor including A first end, a second end and a control end, the first end of the sixth transistor is coupled to the second end of the third transistor and the first end of the fourth transistor, the first end The second end of the six transistors is coupled to the first voltage source, the control end of the sixth transistor is coupled to the node, and the sixth transistor is selectively turned on according to the voltage of the node. The pulse wave generating circuit according to claim 10, wherein the pull-up circuit includes: a seventh transistor including a first terminal, a second terminal and a control terminal, the first terminal of the seventh transistor Coupled to a third voltage source, the second terminal of the seventh transistor is coupled to the output terminal, the control of the seventh transistor is coupled to the node, and the seventh transistor is selectively turned on according to the voltage of the node A capacitor includes a first terminal and a second terminal, the first terminal of the capacitor is coupled to the node, and the second terminal of the capacitor is coupled to the output terminal. The pulse wave generating circuit according to claim 10, wherein The pull-down circuit includes: a seventh transistor including a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor is coupled to the output terminal, and the second terminal of the seventh transistor The two ends are coupled to the second voltage source, the control end of the seventh transistor is used for receiving the second input signal, and the seventh transistor is selectively turned on according to the second input signal.

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