CN106504721A

CN106504721A - A kind of shift register, its driving method, gate driver circuit and display device

Info

Publication number: CN106504721A
Application number: CN201710008054.6A
Authority: CN
Inventors: 韩明夫; 商广良; 韩承佑; 金志河; 姚星; 郑皓亮; 袁丽君; 王志冲
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2017-01-05
Filing date: 2017-01-05
Publication date: 2017-03-15
Anticipated expiration: 2037-01-05
Also published as: CN106504721B

Abstract

The invention discloses a kind of shift register, its driving method, gate driver circuit and display device, including：Input module, voltage coupling module, threshold voltage writing module, the first output module and the second output module；Wherein, by cooperating for aforementioned four module, the voltage of Section Point can be compensated, to ensure after the effective impulse signal of shift register output drive signal, the current potential of first node can be made in the stable state of invalid current potential, so as to reduce the output noise of drive signal output end, and then can avoid showing exception occur.

Description

A kind of shift register, its driving method, gate driver circuit and display device

Technical field

The present invention relates to display technology field, more particularly to a kind of shift register, its driving method, gate driver circuit And display device.

Background technology

With developing rapidly for Display Technique, direction of the display floater increasingly towards high integration and low cost is developed. Wherein, array base palte row drives (Gate Driver on Array, GOA) technology by thin film transistor (TFT) (Thin Film Transistor, TFT) gate switch circuit is integrated on the array base palte of display floater and the scanning of display floater driven with being formed Dynamic, such that it is able to saving binding (Bonding) region of grid integrated circuits (Integrated Circuit, IC) and being fanned out to (Fan-out) wiring space in region, not only can reduce product cost, Er Qieke in terms of material cost and preparation technology two So that display floater accomplishes both sides symmetrically and the design for aesthetic of narrow frame；Also, this integrated technique may be omitted with grid and sweep The Bonding techniques in line direction are retouched, so as to improve production capacity and yield.

General gate driver circuit is made up of the shift register of multiple cascades, by shift register realities at different levels Now successively to each row grid line input scanning signal on display floater.At present, in shift register by the scanning signal of high potential Output after the completion of, shift register then enters the electronegative potential maintenance stage, specially：The current potential of pull-down node is high potential, defeated Go out pull-down transistor, under the control of the signal of pull-down node, the reference signal of electronegative potential is supplied to drive signal output end, with Drive signal output is made in the state of electronegative potential；Node pull-down transistor is under the control of the signal of pull-down node by low electricity The reference signal of position is supplied to pull-up node, makes pull-up node be changed into electronegative potential, makes state of the pull-up node in electronegative potential, with Reduce the output noise of drive signal output end.But in electronegative potential maintenance stage, the threshold voltage meeting of node pull-down transistor Positive excursion, causes node pull-down transistor fully open, in some instances it may even be possible to node pull-down transistor can be caused to end, so as to Cause the holding electronegative potential that pull-up node can not be stable, and then cause the drive signal output end of shift register to export generation and make an uproar Sound, in some instances it may even be possible to can cause to show exception occur.

Content of the invention

A kind of shift register, its driving method, gate driver circuit and display device is embodiments provided, is used To solve to keep stage, the holding electronegative potential that pull-up node can not be stable in electronegative potential in prior art, and then displacement is caused to be posted The drive signal output end output of storage produces noise, in some instances it may even be possible to can cause to show abnormal problem occur.

Therefore, a kind of shift register is embodiments provided, including：Input module, voltage coupling module, threshold value Voltage writing module, the first output module and the second output module；Wherein,

The input module is connected with input signal end, the first reference signal end, first node and Section Point respectively； The input module is used for, under the control at the input signal end, the signal at the input signal end is supplied to described first The signal at the first reference signal end is supplied to the Section Point under the control at the input signal end by node；

The voltage coupling module is connected with the first clock signal terminal and the Section Point respectively；The voltage coupling Module is used for, when the Section Point is in floating, keeping between the Section Point and first clock signal terminal Voltage difference stable；

The threshold voltage writing module respectively with the first reset signal end, the first reference signal end, described first Node and the Section Point are connected；The threshold voltage writing module is used under the control at the first reset signal end The first node and the Section Point is turned on, and is referred to described first under the control of the signal of the Section Point The signal of signal end is supplied to the first node；

First output module respectively with first clock signal terminal, the first node and the shift LD The drive signal output end of device is connected；First output module is used for will be described under the control of the signal of the first node The signal of the first clock signal terminal is supplied to the drive signal output end, and is in floating in the first node When, keep the voltage difference between the first node and the drive signal output end stable；

Second output module respectively with second clock signal end, the second reference signal end, the Section Point and The drive signal output end is connected；Second output module is used for will be described under the control of the signal of the Section Point The signal at the second reference signal end is supplied to the drive signal output end, and under the control of the second clock signal end The signal at the second reference signal end is supplied to the drive signal output end.

Preferably, in above-mentioned shift register provided in an embodiment of the present invention, the voltage coupling module includes：First Electric capacity；Wherein,

The first end of first electric capacity is connected with the Section Point, the second end and the first clock signal terminal phase Even.

Preferably, in above-mentioned shift register provided in an embodiment of the present invention, the threshold voltage writing module includes： First switch transistor AND gate second switch transistor；Wherein,

The grid of the first switch transistor is connected with the first reset signal end, source electrode and the first node phase Even, drain electrode is connected with the Section Point；

The grid of the second switch transistor is connected with the Section Point, source electrode and the first reference signal end phase Even, drain electrode is connected with the first node.

Preferably, in above-mentioned shift register provided in an embodiment of the present invention, the input module includes：3rd switch The 4th switching transistor of transistor AND gate；Wherein,

The grid of the 3rd switching transistor is connected with the input signal end with drain electrode, source electrode and the first segment Point is connected；

The grid of the 4th switching transistor is connected with the input signal end, source electrode and the first reference signal end It is connected, drain electrode is connected with the Section Point.

Preferably, in above-mentioned shift register provided in an embodiment of the present invention, first output module includes：5th Switching transistor and the second electric capacity；Wherein,

The grid of the 5th switching transistor is connected with the first node, source electrode and the first clock signal terminal phase Even, drain electrode is connected with the drive signal output end；

The first end of second electric capacity is connected with the first node, the second end and the drive signal output end phase Even.

Preferably, in above-mentioned shift register provided in an embodiment of the present invention, second output module includes：6th Switching transistor and the 7th switching transistor；Wherein,

The grid of the 6th switching transistor is connected with the Section Point, source electrode and the second reference signal end phase Even, drain electrode is connected with the drive signal output end；

The grid of the 7th switching transistor is connected with the second clock signal end, and source electrode and the described second reference are believed Number end be connected, drain electrode be connected with the drive signal output end.

Preferably, in above-mentioned shift register provided in an embodiment of the present invention, also include：Current potential stable module；Wherein,

The current potential stable module is believed with the second reset signal end, the second reference signal end and the driving respectively Number output end is connected；The current potential stable module is used for described second under the control at the second reset signal end with reference to letter Number end signal be supplied to the drive signal output end.

Preferably, in above-mentioned shift register provided in an embodiment of the present invention, the current potential stable module includes：8th Switching transistor；Wherein,

The grid of the 8th switching transistor is connected with the second reset signal end, and source electrode and the described second reference are believed Number end be connected, drain electrode be connected with the drive signal output end.

Correspondingly, the embodiment of the present invention additionally provides a kind of gate driver circuit, including the N number of embodiment of the present invention for cascading Any of the above-described kind of shift register for providing；Wherein, N is the integer more than or equal to 4；

The input signal end of the 1st grade of shift register is connected with the first frame trigger end；

The input signal end of the 2nd grade of shift register is connected with the second frame trigger end；

The input signal end of n-th grade of shift register drive signal output end phase respectively with the n-th -2 grades shift registers Even；

First reset signal end of the n-th -2 grades shift registers is defeated with the drive signal of (n+1)th grade of shift register respectively Go out end to be connected；Wherein, n is the integer more than or equal to 3 and less than or equal to N-1.

Correspondingly, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned provided in an embodiment of the present invention A kind of gate driver circuit.

Correspondingly, the embodiment of the present invention additionally provides a kind of any of the above-described kind of shift register provided in an embodiment of the present invention Driving method, including：First stage, second stage, phase III, fourth stage, the 5th stage and the 6th stage；Its In,

In the first stage, the input module is under the control at the input signal end by the input signal end Signal is supplied to the first node, under the control at the input signal end provides the signal at the first reference signal end Give the Section Point；First output module is under the control of the signal of the first node by first clock signal The signal at end is supplied to the drive signal output end；Second output module is under the control of the second clock signal end The signal at the second reference signal end is supplied to the drive signal output end；

In the second stage, first output module is under the control of the signal of the first node by described first The signal of clock signal terminal is supplied to the drive signal output end, and when the first node is in floating, protects The voltage difference that holds between the first node and the drive signal output end is stable；The input module is in the input signal The signal at the first reference signal end is supplied to the Section Point under the control at end；

In the phase III, first output module is under the control of the signal of the first node by described first The signal of clock signal terminal is supplied to the drive signal output end, and when the first node is in floating, protects The voltage difference that holds between the first node and the drive signal output end is stable；The voltage coupling module is described second When node is in floating, keep the voltage difference between the Section Point and first clock signal terminal stable；

In the fourth stage, the threshold voltage writing module turns on institute under the control at the first reset signal end First node and the Section Point is stated, and by the first reference signal end under the control of the signal of the Section Point Signal be supplied to the first node；Second output module is under the control of the second clock signal end by described The signal at two reference signal ends is supplied to the drive signal output end；

In the 5th stage, the voltage coupling module keeps described when the Section Point is in floating Voltage difference between Section Point and first clock signal terminal is stable；Second output module is in the Section Point The signal at the second reference signal end is supplied to the drive signal output end under the control of signal；The threshold voltage is write Enter module, under the control of the signal of the Section Point, the signal at the first reference signal end is supplied to the first segment Point；

In the 6th stage, the voltage coupling module keeps described when the Section Point is in floating Voltage difference between Section Point and first clock signal terminal is stable；Second output module is believed in the second clock Number end control under the signal at the second reference signal end is supplied to the drive signal output end.

The present invention has the beneficial effect that：

Shift register provided in an embodiment of the present invention, its driving method, gate driver circuit and display device, including： Input module, voltage coupling module, threshold voltage writing module, the first output module and the second output module；Wherein, it is input into Module is used for, under the control at input signal end, the signal at input signal end is supplied to first node, in the control at input signal end The signal at the first reference signal end is supplied to Section Point under system；Voltage coupling module is used for being in suspension joint shape in Section Point During state, keep the voltage difference between Section Point and the first clock signal terminal stable；Threshold voltage writing module is used for first Conducting first node and Section Point under the control at reset signal end, and join first under the control of the signal of Section Point The signal for examining signal end is supplied to first node；When first output module is used for first under the control of the signal of first node The signal of clock signal end is supplied to drive signal output end, and when first node is in floating, keeps first node Stable with the voltage difference between drive signal output end；Second output module is used for the under the control of the signal of Section Point The signal at two reference signal ends is supplied to drive signal output end, and refers to second under the control of second clock signal end The signal of signal end is supplied to drive signal output end.Therefore, it can cooperating by aforementioned four module, can compensate The voltage of Section Point, to ensure, after the effective impulse signal of shift register output drive signal, to make first segment Stable state of the current potential of point in invalid current potential, so as to reduce the output noise of drive signal output end, and then can avoid Show exception occur.

Description of the drawings

Fig. 1 a are one of structural representation of shift register provided in an embodiment of the present invention；

Fig. 1 b are the two of the structural representation of shift register provided in an embodiment of the present invention；

Fig. 2 a are the concrete structure schematic diagram of the shift register shown in Fig. 1 a；

Fig. 2 b are the concrete structure schematic diagram of the shift register shown in Fig. 1 b；

Fig. 3 a are the input and output sequential chart of the shift register shown in Fig. 2 a；

Fig. 3 b are the input and output sequential chart of the shift register shown in Fig. 2 b；

Fig. 4 a are one of analogue simulation schematic diagram of shift register shown in Fig. 2 b；

Fig. 4 b are the two of the analogue simulation schematic diagram of the shift register shown in Fig. 2 b；

Fig. 5 is the flow chart of the driving method of shift register provided in an embodiment of the present invention；

Fig. 6 is the structural representation of gate driver circuit provided in an embodiment of the present invention.

Specific embodiment

In order that the purpose of the present invention, technical scheme and advantage are clearer, below in conjunction with the accompanying drawings, to the embodiment of the present invention The specific embodiment of the shift register of offer, its driving method, gate driver circuit and display device is carried out in detail Bright.It should be appreciated that preferred embodiment disclosed below is merely to illustrate and explains the present invention, it is not intended to limit the present invention. And in the case where not conflicting, the feature in embodiment and embodiment in the application can be mutually combined.

A kind of shift register is embodiments provided, as illustrated in figs. ia and ib, including：Input module 1, voltage Coupling module 2, threshold voltage writing module 3, the first output module 4 and the second output module 5；Wherein,

Input module 1 respectively with input signal end Input, the first reference signal end VSS1, first node A and second section Point B is connected；Input module 1 is used for, under the control of input signal end Input, the signal of input signal end Input is supplied to the The signal of the first reference signal end VSS1 is supplied to Section Point B under the control of input signal end Input by one node A；

Voltage coupling module 2 is connected with the first clock signal terminal CLK and Section Point B respectively；Voltage coupling module 2 is used Stablize in the voltage difference between Section Point B and the first clock signal terminal CLK when Section Point B is in floating, is kept；

Threshold voltage writing module 3 respectively with the first reset signal end RST1, the first reference signal end VSS1, first node A and Section Point B is connected；Threshold voltage writing module 3 is used for turning on first under the control of the first reset signal end RST1 Node A and Section Point B, and the signal of the first reference signal end VSS1 is provided under the control of the signal of Section Point B Give first node A；

First output module 4 is believed with the driving of the first clock signal terminal CLK, first node A and shift register respectively Number output end Output is connected；First output module 4 is used for the first clock signal terminal under the control of the signal of first node A The signal of CLK is supplied to drive signal output end Output, and when first node A is in floating, keeps first segment Voltage difference between point A and drive signal output end Output is stable；

Second output module 5 respectively with second clock signal end CLKB, the second reference signal end VSS2, Section Point B with And drive signal output end Output is connected；Second output module 5 is used for joining second under the control of the signal of Section Point B The signal for examining signal end VSS2 is supplied to drive signal output end Output, and under the control of second clock signal end CLKB The signal of the second reference signal end VSS2 is supplied to drive signal output end Output.

Above-mentioned shift register provided in an embodiment of the present invention, including：Input module, voltage coupling module, threshold voltage Writing module, the first output module and the second output module；Wherein, input module is used for inciting somebody to action under the control at input signal end The signal at input signal end is supplied to first node, under the control at input signal end provides the signal at the first reference signal end Give Section Point；Voltage coupling module is used for, when Section Point is in floating, keeping Section Point and the first clock letter Voltage difference between number end is stable；Threshold voltage writing module is used for turning on first node under the control at the first reset signal end With Section Point, and the signal at the first reference signal end is supplied to first node under the control of the signal of Section Point； First output module is used for, under the control of the signal of first node, the signal of the first clock signal terminal is supplied to drive signal Output end, and when first node is in floating, keep the voltage difference between first node and drive signal output end Stable；Second output module is used for, under the control of the signal of Section Point, the signal at the second reference signal end is supplied to driving Signal output part, and it is defeated that the signal at the second reference signal end is supplied to drive signal under the control of second clock signal end Go out end.Therefore, above-mentioned shift register provided in an embodiment of the present invention cooperating by aforementioned four module, can compensate The voltage of Section Point, to ensure, after the effective impulse signal of shift register output drive signal, to make first segment Stable state of the current potential of point in invalid current potential, so as to reduce the output noise of drive signal output end, and then can avoid Show exception occur.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, in the effective of input signal end When pulse signal is high potential, the voltage amplitude of the effective impulse signal at input signal end, the voltage amplitude of the first clock signal And the voltage amplitude of second clock signal can be with equal.Certainly, the voltage amplitude of the effective impulse signal at input signal end, Can also be at least two unequal in the voltage amplitude of the voltage amplitude of the first clock signal and second clock signal.In reality In application, the voltage amplitude of the effective impulse signal at input signal end, the voltage amplitude of the signal of the first clock signal terminal and The voltage amplitude of the signal of second clock signal end needs to design determination according to practical situations, is not limited thereto.

Further, after the effective impulse signal that drive signal output end Output exports scanning signal is completed, it is Be further ensured that drive signal output end Output current potential can in time with input signal end Input effective impulse signal Current potential conversely, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Figure 1 b, also including：Current potential stable mode Block 6；Wherein,

Current potential stable module 6 respectively with the second reset signal end RST2, the second reference signal end VSS2 and drive signal Output end Output is connected；Current potential stable module 6 is used for the second reference signal under the control of the second reset signal end RST2 The signal of end VSS2 is supplied to drive signal output end Output.

With reference to specific embodiment, the present invention is described in detail.It should be noted that in the present embodiment be in order to The present invention is preferably explained, but does not limit the present invention.

Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 a and Fig. 2 b Shown, threshold voltage writing module 3 can specifically include：First switch transistor M1 and second switch transistor M2；Wherein,

The grid of first switch transistor M1 is connected with the first reset signal end RST1, and source electrode is connected with first node A, leakage Pole is connected with Section Point B；

The grid of second switch transistor M2 is connected with Section Point B, and source electrode is connected with the first reference signal end VSS1, leakage Pole is connected with first node A.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, at the first reset signal end When effective impulse signal is high potential, first switch transistor can be N-type switching transistor；Or, in the first reset signal When the effective impulse signal at end is electronegative potential, first switch transistor can be p-type switching transistor, be not limited thereto.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the Input at input signal end When effective impulse signal is high potential, as shown in Figure 2 a and 2 b, first switch transistor M1 and second switch transistor M2 can Think N-type switching transistor.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, first switch transistor is When in the conduction state under the control at one reset signal end, first node and Section Point is turned on.Second switch transistor is When in the conduction state under the control of the signal of two nodes, the signal at the first reference signal end is supplied to first node.

The above is only the concrete structure for illustrating threshold voltage writing module in shift register, in the specific implementation, The concrete structure of threshold voltage writing module is not limited to said structure provided in an embodiment of the present invention, can also be art technology Other structures knowable to personnel, are not limited thereto.

Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 a and Fig. 2 b Shown, voltage coupling module 2 can specifically include：First electric capacity C1；Wherein,

The first end of the first electric capacity C1 is connected with Section Point B, and the second end is connected with the first clock signal terminal CLK.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, suspension joint is in Section Point During state, due to the boot strap of the first electric capacity, the voltage difference at the first electric capacity two ends can be kept stable, that is, keep Section Point Stable with the voltage difference between the first clock signal terminal.

The above is only the concrete structure for illustrating voltage coupling module in shift register, in the specific implementation, voltage The concrete structure of coupling module is not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that Other structures, be not limited thereto.

Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 a and Fig. 2 b Shown, input module 1 can specifically include：3rd switching transistor M3 and the 4th switching transistor M4；Wherein,

The grid of the 3rd switching transistor M3 is connected with input signal end Input with drain electrode, source electrode and first node A phases Even；

The grid of the 4th switching transistor M4 is connected with input signal end Input, source electrode and the first reference signal end VSS1 It is connected, drain electrode is connected with Section Point B

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the Input at input signal end When effective impulse signal is high potential, as shown in Figure 2 a and 2 b, the 3rd switching transistor M3 and the 4th switching transistor M4 can Think N-type switching transistor.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 4th switching transistor is defeated Enter, under the control of signal end, the signal at the first reference signal end is supplied to Section Point.3rd switching transistor is in input signal The signal at input signal end is supplied to first node under the control at end；Wherein, in actual applications, due to the 3rd switch crystal The grid of pipe is connected with input signal end with drain electrode, and the voltage of the grid of the 3rd switching transistor is effective with input signal end The voltage amplitude V of pulse signal_InputEqual, between the grid and its source electrode of the 3rd switching transistor gate source voltage V_gs (M3) more than the threshold voltage V of the 3rd switching transistor_th(M3), i.e. V_gs(M3)>V_th(M3) when, the 3rd switching transistor could be located First node is supplied in conducting state and by the signal at input signal end, until the voltage V in first node_A=V_Input-V_th (M3), when, the 3rd switching transistor can just be ended.

The above is only the concrete structure for illustrating input module in shift register, in the specific implementation, input module Concrete structure be not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot Structure, is not limited thereto.

Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 a and Fig. 2 b Shown, the first output module 4 can specifically include：5th switching transistor M5 and the second electric capacity C2；Wherein,

The grid of the 5th switching transistor M5 is connected with first node A, and source electrode is connected with the first clock signal terminal CLK, leakage Pole is connected with drive signal output end Output；

The first end of the second electric capacity C2 is connected with first node A, and the second end is connected with drive signal output end Output.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the Input at input signal end When effective impulse signal is high potential, as shown in Figure 2 a and 2 b, the 5th switching transistor can be N-type switching transistor.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 5th switching transistor is When in the conduction state under the control of the signal of one node, the signal of the first clock signal terminal is supplied to drive signal output End.When first node is in floating, due to the boot strap of the second electric capacity, the voltage at the second electric capacity two ends can be kept Difference is stable, that is, keep the voltage difference between first node and drive signal output end stable.

The above is only the concrete structure for illustrating the first output module in shift register, in the specific implementation, first The concrete structure of output module is not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that Other structures, be not limited thereto.

Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 a and Fig. 2 b Shown, the second output module 5 can specifically include：6th switching transistor M6 and the 7th switching transistor M7；Wherein,

The grid of the 6th switching transistor M6 is connected with Section Point B, and source electrode is connected with the second reference signal end VSS2, leakage Pole is connected with drive signal output end Output；

The grid of the 7th switching transistor M7 is connected with second clock signal end CLKB, source electrode and the second reference signal end VSS2 is connected, and drain electrode is connected with drive signal output end Output.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the Input at input signal end When effective impulse signal is high potential, as shown in Figure 2 a and 2 b, the 6th switching transistor M6 and the 7th switching transistor M7 can Think N-type switching transistor.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 6th switching transistor is When in the conduction state under the control of the signal of two nodes, the signal at the second reference signal end is supplied to drive signal output End.When 7th switching transistor is in the conduction state under the control of second clock signal end, by the letter at the second reference signal end Number it is supplied to drive signal output end.

The above is only the concrete structure for illustrating the second output module in shift register, in the specific implementation, second The concrete structure of output module is not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that Other structures, be not limited thereto.

Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Figure 2 b, Current potential stable module 6 can specifically include：8th switching transistor M8；Wherein,

The grid of the 8th switching transistor M8 is connected with the second reset signal end RST2, source electrode and the second reference signal end VSS2 is connected, and drain electrode is connected with drive signal output end Output.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, at the second reset signal end When effective impulse signal is high potential, the 8th switching transistor can be N-type switching transistor；Or, in the second reset signal When the effective impulse signal at end is electronegative potential, the 8th switching transistor can be p-type switching transistor, be not limited thereto.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the Input at input signal end When effective impulse signal is high potential, as shown in Figure 2 b, the 8th switching transistor can be N-type switching transistor.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 8th switching transistor is When in the conduction state under the control at two reset signal ends, the signal at the second reference signal end is supplied to drive signal output End.

The above is only the concrete structure for illustrating current potential stable module in shift register, in the specific implementation, current potential The concrete structure of stable module is not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that Other structures, be not limited thereto.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, in the effective of input signal end When pulse signal is high potential, the current potential at the first reference signal end is electronegative potential, and the current potential at the second reference signal end is electronegative potential. Wherein, voltage of the voltage at the first reference signal end more than or equal to the second reference signal end.Electricity at the first reference signal end When pressure is more than the voltage at the second reference signal end, can prevent shift register from leaking electricity.In actual applications, the first reference signal The voltage at the voltage at end and the second reference signal end needs to design determination according to practical situations, is not limited thereto.

Further, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, first with reference to letter Number end with the second reference signal end be same signal end.The voltage at such first reference signal end is equal to the second reference signal end Voltage.And also the setting of holding wire can be further reduced, simplify preparation technology.

It is preferred that in order to simplify preparation technology, in the specific implementation, in above-mentioned shift LD provided in an embodiment of the present invention In device, as shown in Figure 2 a and 2 b, all switching transistors can be N-type switching transistor, be not limited thereto.

Further, in the specific implementation, N-type switching transistor is turned under high potential effect, under electronegative potential effect Cut-off；P-type switching transistor is ended under high potential effect, turns under electronegative potential effect.

It should be noted that the switching transistor that mentions in the above embodiment of the present invention can be amorphous silicon film transistor (a-Si TFT), or metal oxide semiconductor field effect tube (MOS, Metal Oxide Scmiconductor), This is not construed as limiting.In being embodied as, the source electrode of these transistors and drain electrode according to transistor types and input signal not With its function can be exchanged, and here does not do concrete differentiation.

The course of work of above-mentioned shift register provided in an embodiment of the present invention is made to retouch with reference to circuit timing diagram State.Wherein, by taking the voltage that the voltage at the first reference signal end is equal to the second reference signal end as an example.Represent with 1 in described below High potential signal, 0 represents low-potential signal, and wherein, 1 and 0 represents its logic level, merely to preferably explaining that the present invention is real The course of work of the above-mentioned shift register of example offer is provided, rather than is applied to the grid of each switching transistor in the specific implementation On current potential.

Embodiment one,

Its course of work is described by taking the structure of the shift register shown in Fig. 2 a as an example, wherein, shown in Fig. 2 a Shift register in, all switching transistors are N-type switching transistor, and each N-type switching transistor is under high potential effect Conducting, ends under electronegative potential effect；The current potential of the first reference signal end VSS1 be electronegative potential, corresponding input and output sequential chart As shown in Figure 3 a, specifically, choose first stage T1 in input and output sequential chart as shown in Figure 3 a, second stage T2, the Three stage T3, fourth stage T4, six stages of the 5th stage T5 and the 6th stage T6.

T1 in the first stage, Input=1, RST1=0, CLK=0, CLKB=1.

Due to Input=1, therefore the 3rd switching transistor M3 is both turned on the 4th switching transistor M4.Open due to the 3rd Close transistor M3 conducting and the signal of the input signal end Input of high potential is supplied to first node A, and open due to the 3rd The grid for closing transistor M3 is connected with input signal end Input with drain electrode, and the electricity of the grid of the 3rd switching transistor M3 Pressure and the voltage V of input signal end Input_InputEqual, between the grid and its source electrode of the 3rd switching transistor M3 grid source Voltage V_gs(M3) more than the threshold voltage V of the 3rd switching transistor M3_th(M3), i.e. V_gs(M3)>V_th(M3) the 3rd switch crystal when Pipe M3 is in the conduction state and the signal of input signal end Input is supplied to first node A, until first node A is in height Voltage V during current potential_A=V_Input-V_th(M3) when, the 3rd switching transistor M3 can just be ended, so that the current potential of first node A For high potential, and the voltage V of first node A_A=V_Input-V_th(M3).As the current potential of first node A is high potential, therefore the Five switching transistors M5 turn on and the signal of the first clock signal terminal CLK of electronegative potential are supplied to drive signal output end Output, therefore the second electric capacity C2 chargings, the current potential of drive signal output end Output is electronegative potential, i.e. drive signal output end Output exports the drive signal of electronegative potential.As the 4th switching transistor M4 is turned on and the first reference signal end by electronegative potential The signal of VSS1 is supplied to Section Point B, and therefore the current potential of Section Point B is electronegative potential.As the current potential of Section Point B is low Current potential, therefore second switch transistor M2 be turned off with the 6th switching transistor M6.Due to CLKB=1, therefore the 7th switch is brilliant Body pipe M7 is turned on and the signal of the second reference signal end VSS2 of electronegative potential is supplied to drive signal output end Output, enters one Step ensures that the current potential of drive signal output end Output is electronegative potential.Due to RST1=0, therefore first switch transistor M1 cuts Only.

In second stage T2, Input=1, RST1=0, CLK=1, CLKB=0.

Due to Input=1, therefore the 4th switching transistor M4 conducting.Due to the 4th switching transistor M4 turn on and will be low The signal of the first reference signal end VSS1 of current potential is supplied to Section Point B, and therefore the current potential of Section Point B is electronegative potential.By In CLK=1, and the current potential of Section Point B is electronegative potential, and therefore the first electric capacity C1 charges, second switch transistor M2 and the 6th Switching transistor M6 is turned off.Although the grid of the 3rd switching transistor M3 is connected with input signal end Input, due to It is with voltage V that the boot strap of two electric capacity C2 keeps first node A_A=V_Input-V_th(M3) high potential, therefore the 3rd switchs Transistor M3 ends so that first node A is in floating.As the current potential of first node A remains high potential, therefore Five switching transistors M5 turn on and the signal of the first clock signal terminal CLK of high potential are supplied to drive signal output end Output, therefore the current potential of drive signal output end Output is high potential, i.e. the high electricity of drive signal output end Output output The drive signal of position.Due to the boot strap of the second electric capacity C2, in order to keep first node A and drive signal output end Output Between voltage difference stable so that the current potential of first node A is further pulled up, it is ensured that the 5th switching transistor M5 is led completely Logical, the signal of the first clock signal terminal CLK of high potential is supplied to drive signal output end Output.Due to RST1=0, Therefore first switch transistor M1 cut-offs.Due to CLKB=0, therefore the 7th switching transistor M7 cut-off.

In phase III T3, Input=0, RST1=0, CLK=1, CLKB=0.

Due to Input=0, therefore the 3rd switching transistor M3 is turned off with the 4th switching transistor M4, therefore first segment Point A and Section Point B is in floating.As first node A is in floating, as the bootstrapping of the second electric capacity C2 is made Stable with the voltage difference that can keep its two ends, it is with voltage V that therefore can keep first node A_A=V_Input-V_th(M3) High potential.As the current potential of first node A remains high potential, therefore the 5th switching transistor M5 conducting by high potential the The signal of one clock signal terminal CLK is supplied to drive signal output end Output, therefore the electricity of drive signal output end Output Position is the drive signal that high potential, i.e. drive signal output end Output export high potential.As the bootstrapping of the second electric capacity C2 is made With in order to keep the voltage difference between first node A and drive signal output end Output stable so that the electricity of first node A Position is further pulled up, it is ensured that the 5th switching transistor M5 is fully on, by the first clock signal terminal CLK's of high potential Signal is supplied to drive signal output end Output.As the boot strap of the first electric capacity C1 can keep the voltage difference at two ends steady Fixed, therefore the current potential of Section Point B remains electronegative potential.As the current potential of Section Point B is electronegative potential, therefore second switch is brilliant Body pipe M2 is turned off with the 6th switching transistor M6.Due to RST1=0, therefore first switch transistor M1 cut-offs.Due to CLKB =0, therefore the 7th switching transistor M7 cut-off.

In fourth stage T4, Input=0, RST1=1, CLK=0, CLKB=1.

Due to Input=0, therefore the 3rd switching transistor M3 is turned off with the 4th switching transistor M4.Due to RST1= 1, therefore first switch transistor M1 conductings.As first switch transistor M1 is turned on, therefore first node A and Section Point B Conducting so that the current potential of Section Point B is high potential.As the current potential of Section Point B is high potential, therefore second switch crystal The signal of the first reference signal end VSS1 of electronegative potential is simultaneously supplied to first node A, and make second switch brilliant by pipe M2 conductings The grid of body pipe M2 is connected to form diode structure with drain electrode, so that the high potential of first node A is by forming diode junction The second switch transistor M2 of structure is discharged, until the gate source voltage V of second switch transistor M2_gs(M2) second switch is equal to The threshold voltage V of transistor M2_th(M2), i.e. V_gs(M2)=V_th(M2) second switch transistor M2 cut-offs when so that first node A and Section Point B is with voltage V_th(M2) electronegative potential.As the current potential of first node A is electronegative potential, therefore the 5th open Close transistor M5 cut-offs.As the current potential of Section Point B is electronegative potential, therefore second switch transistor M2 and the 6th switchs crystal Pipe M6 is turned off.Due to CLKB=1, the therefore conducting of the 7th switching transistor M7 the second reference signal end VSS2 by electronegative potential Signal be supplied to drive signal output end Output, therefore the current potential of drive signal output end Output be electronegative potential, that is, drive Dynamic signal output part Output exports the drive signal of electronegative potential.As first node A and Section Point B is with voltage V_th (M2) electronegative potential, therefore the voltage difference at the first electric capacity C1 two ends is V_thAnd the voltage difference at the second electric capacity C2 two ends is (M2) V_th(M2).

In the 5th stage T5, Input=0, RST1=0, CLK=1, CLKB=0.

Due to Input=0, therefore the 3rd switching transistor M3 is turned off with the 4th switching transistor M4, therefore first segment Point A and Section Point B is in floating.As Section Point B is in floating, and CLK=1 and the first electric capacity C1 Boot strap, the voltage difference in order to keep its two ends are stable, and therefore the current potential of Section Point B is pulled high to voltage V_th(M2) +V_compHigh potential, therefore the current potential of Section Point B be high potential.As the current potential of Section Point B is high potential, therefore the Two switching transistors M2 are both turned on the 6th switching transistor M6.Due to second switch transistor M2 turn on and by electronegative potential the The signal of one reference signal end VSS1 is supplied to first node A, and therefore first node A is electronegative potential, as first node A is low Current potential, therefore the 5th switching transistor M5 cut-off.As the 6th switching transistor M6 is turned on and by the second of electronegative potential with reference to letter Number end VSS2 signal be supplied to drive signal output end Output, therefore the current potential of drive signal output end Output be low electricity Position, i.e. drive signal output end Output export the drive signal of electronegative potential.Due to RST1=0, therefore first switch transistor M1 ends.Due to CLKB=0, therefore the 7th switching transistor M7 cut-off.

In the 6th stage T6, Input=0, RST1=0, CLK=0, CLKB=1.

Due to Input=0, therefore the 3rd switching transistor M3 is turned off with the 4th switching transistor M4, therefore first segment Point A and Section Point B is in floating.As Section Point B is in floating, and CLK=0 and the first electric capacity C1 Boot strap, the voltage difference in order to keep its two ends are stable, and therefore the current potential of Section Point B is with voltage V_th(M2) low electricity Position, therefore the current potential of Section Point B is electronegative potential, and second switch transistor M2 is turned off with the 6th switching transistor M6.Due to CLKB=1, therefore the 7th switching transistor M7 turn on and the signal of the second reference signal end VSS2 of electronegative potential is supplied to drive Dynamic signal output part Output, therefore the current potential of drive signal output end Output is electronegative potential, i.e. drive signal output end Output exports the drive signal of electronegative potential.Due to RST1=0, therefore first switch transistor M1 cut-offs.

In above-mentioned shift register provided in an embodiment of the present invention, after the 6th stage T6, is repeated always The course of work of five stage T5 and the 6th stage T6, until next frame starts.

Embodiment two,

Its course of work is described by taking the structure of the shift register shown in Fig. 2 b as an example, wherein, shown in Fig. 2 b Shift register in, all switching transistors are N-type switching transistor, and each N-type switching transistor is under high potential effect Conducting, ends under electronegative potential effect；The current potential of the first reference signal end VSS1 be electronegative potential, corresponding input and output sequential chart As shown in Figure 3 b, specifically, choose first stage T1 in input and output sequential chart as shown in Figure 3 b, second stage T2, the Three stage T3, fourth stage T4, six stages of the 5th stage T5 and the 6th stage T6.

T1 in the first stage, Input=1, RST1=0, RST2=0, CLK=0, CLKB=1.Due to RST2=0, therefore 8th switching transistor M8 is ended.Remaining specific work process is identical with the course of work of the first stage T1 in embodiment one, Therefore not to repeat here.

In second stage T2, Input=1, RST1=0, RST2=0, CLK=1, CLKB=0.Due to RST2=0, therefore 8th switching transistor M8 is ended.Remaining specific work process is identical with the course of work of second stage T2 in embodiment one, Therefore not to repeat here.

In phase III T3, Input=0, RST1=0, RST2=0, CLK=1, CLKB=0.Due to RST2=0, therefore 8th switching transistor M8 is ended.Remaining specific work process is identical with the course of work of the phase III T3 in embodiment one, Therefore not to repeat here.

In fourth stage T4, first half time period, Input=0, RST1=1, RST2=0, CLK=0, CLKB=1.Due to RST2=0, therefore the 8th switching transistor M8 cut-off.The work of fourth stage T4 in remaining specific work process and embodiment one Make process identical, therefore not to repeat here.

Later half time period, Input=0, RST1=1, RST2=1, CLK=0, CLKB=1.Due to RST2=1, therefore Eight switching transistors M8 turn on and the signal of the second reference signal end VSS2 of electronegative potential are supplied to drive signal output end Output, is further ensured that the current potential of drive signal output end Output is electronegative potential.Remaining specific work process and embodiment The course of work of fourth stage T4 in is identical, and therefore not to repeat here.

In the 5th stage T5, first half time period, Input=0, RST1=0, RST2=1, CLK=1, CLKB=0.Due to RST2=1, therefore the 8th switching transistor M8 turn on and the signal of the second reference signal end VSS2 of electronegative potential is supplied to drive Dynamic signal output part Output, is further ensured that the current potential of drive signal output end Output is electronegative potential.Remaining specific works Process is identical with the course of work of the 5th stage T5 in embodiment one, and therefore not to repeat here.

Later half time period, Input=0, RST1=0, RST2=0, CLK=1, CLKB=0.Due to RST2=0, therefore Eight switching transistors M8 are ended.Remaining specific work process is identical with the course of work of the 5th stage T5 in embodiment one, This does not repeat.

In the 6th stage T6, Input=0, RST1=0, RST2=0, CLK=0, CLKB=1.Due to RST2=0, therefore 8th switching transistor M8 is ended.Remaining specific work process is identical with the course of work of the 6th stage T6 in embodiment one, Therefore not to repeat here.

In above-mentioned shift register provided in an embodiment of the present invention, after the 6th stage T6, is repeated always The later half time period of five stage T5 and the course of work of the 6th stage T6, until next frame starts.

In above-mentioned shift register provided in an embodiment of the present invention, in fourth stage, due to forming diode structure The threshold voltage vt h (M2) of second switch transistor M2 can be written to Section Point by second switch transistor M2, so as to After 5th stage was driven high the current potential of Section Point by the boot strap of the first electric capacity, the voltage of Section Point is equally drawn High voltage V_compSo that the voltage of Section Point is：V_th(M2)+V_compSo that the Vgs (M2) of second switch transistor M2= V_comp, such that it is able to keep second switch transistor in the conduction state all the time, by the first reference signal end of electronegative potential Signal is supplied to first node, and the current potential for keeping first node is electronegative potential, and then lowers the output of drive signal output end and make an uproar Sound, it is to avoid show abnormal, the exhibit stabilization of raising display device.

In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 4th of its course of work the In stage, voltage V_compMeet formula：Wherein V_CLKThe voltage amplitude of the first clock signal terminal is represented, C1 represents the capacitance of the first electric capacity, Cpd=c1+Cgs (M1)+Cgs (M2)+Cgd (M2)+Cgd (M4)+Cgs (M6)+Cgd (M6), Cgs (M1) represents the parasitic capacitance between the grid and source electrode of first switch transistor, and Cgs (M2) represents second switch Parasitic capacitance between the grid and source electrode of transistor, Cgd (M2) are represented between the grid of second switch transistor and drain electrode Parasitic capacitance, Cgd (M4) represent the parasitic capacitance between the grid of the 4th switching transistor and drain electrode, and Cgs (M6) represents the 6th Parasitic capacitance between the grid and source electrode of switching transistor, Cgd (M6) represent the grid of the 6th switching transistor and drain electrode Between parasitic capacitance.

Below so that the concrete structure of the shift register shown in Fig. 2 b and voltage step size are as 2V as an example, analogue simulation is in work During work, the threshold voltage vt h (M2) of second switch transistor M2 is drifted about to the right the relation of the voltage of corresponding Section Point.The As shown in fig. 4 a, abscissa represents electricity to the simulation results that the threshold voltage vt h (M2) of two switching transistors M2 is drifted about to the right Pressure, ordinate represent electric current.Wherein, S1, S2, S3, S4, S5, S6 and S7 represent the threshold value of second switch transistor M2 respectively Voltage Vth (M2) is drifted about to the right the analogue simulation curve of 0V, 2V, 4V, 6V, 8V, 10V and 12V.Corresponding with S1-S7 in Fig. 4 a First node and the voltage analogue simulation figure of Section Point be that abscissa represents the time shown in Fig. 4 b, ordinate represents electricity Pressure.Wherein, S0 represent second switch transistor M2 threshold voltage vt h (M2) drift about to the right 0V, 2V, 4V, 6V, 8V, 10V and The voltage of first node during 12V.S1 '-S7 ' represent the threshold voltage vt h (M2) of second switch transistor M2 respectively and drift about to the right The voltage of Section Point when 0V, 2V, 4V, 6V, 8V, 10V and 12V.From Fig. 4 a and Fig. 4 b, it can be seen that open with second The increase of the threshold voltage vt h (M2) of transistor M2 is closed, the voltage of Section Point also accordingly can increase, such that it is able to compensate second The drift of the threshold voltage vt h (M2) of switching transistor M2.

Same inventive concept is based on, the embodiment of the present invention additionally provides a kind of any of the above-described kind of displacement of present invention offer and posts The driving method of storage, as shown in figure 5, including：First stage, second stage, the phase III, fourth stage, the 5th stage with And the 6th stage；Wherein,

S501, in the first stage, the signal at input signal end is supplied under the control at input signal end by input module The signal at the first reference signal end is supplied to Section Point under the control at input signal end by first node；First output mould The signal of the first clock signal terminal is supplied to drive signal output end under the control of the signal of first node by block；Second output The signal at the second reference signal end is supplied to drive signal output end under the control of second clock signal end by module；

S502, in second stage, the first output module is under the control of the signal of first node by the first clock signal terminal Signal be supplied to drive signal output end, and when first node is in floating, keeps first node and drive letter Voltage difference between number output end is stable；The signal at the first reference signal end is carried under the control at input signal end by input module Supply Section Point；

S503, in the phase III, the first output module is under the control of the signal of first node by the first clock signal terminal Signal be supplied to drive signal output end, and when first node is in floating, keeps first node and drive letter Voltage difference between number output end is stable；Voltage coupling module Section Point be in floating when, keep Section Point with Voltage difference between first clock signal terminal is stable；

S504, in fourth stage, threshold voltage writing module turns on first node under the control at the first reset signal end With Section Point, and the signal at the first reference signal end is supplied to first node under the control of the signal of Section Point； The signal at the second reference signal end is supplied to drive signal output under the control of second clock signal end by the second output module End；

S505, in the 5th stage, voltage coupling module keeps Section Point and the when Section Point is in floating Voltage difference between one clock signal terminal is stable；Second output module is under the control of the signal of Section Point by second with reference to letter Number end signal be supplied to drive signal output end；Threshold voltage writing module is under the control of the signal of Section Point by first The signal at reference signal end is supplied to first node；

S506, in the 6th stage, voltage coupling module keeps Section Point and the when Section Point is in floating Voltage difference between one clock signal terminal is stable；Second output module is under the control of second clock signal end by second with reference to letter Number end signal be supplied to drive signal output end.

Above-mentioned driving method provided in an embodiment of the present invention, can compensate the voltage of Section Point, to ensure to post in displacement After the effective impulse signal of storage output drive signal, the current potential of first node can be made in the stable shape of invalid current potential State, so as to reduce the output noise of drive signal output end, and then can avoid showing exception occur.

Further, in above-mentioned driving method provided in an embodiment of the present invention, also include current potential in each shift register During stable module,

Fourth stage is specifically included：The first half time period, threshold voltage writing module is under the control at the first reset signal end Conducting first node and Section Point, and the signal at the first reference signal end is provided under the control of the signal of Section Point Give first node；The signal at the second reference signal end is supplied to drive under the control of second clock signal end by the second output module Dynamic signal output part；

Later half time period, threshold voltage writing module turn on first node and second under the control at the first reset signal end Node, and the signal at the first reference signal end is supplied to first node under the control of the signal of Section Point；Second is defeated Go out module, under the control of second clock signal end, the signal at the second reference signal end is supplied to drive signal output end；Current potential The signal at the second reference signal end is supplied to drive signal output end under the control at the second reset signal end by stable module；

5th stage specifically included：First half time period, voltage coupling module are kept when Section Point is in floating Voltage difference between Section Point and the first clock signal terminal is stable；Second output module is under the control of the signal of Section Point The signal at the second reference signal end is supplied to drive signal output end；The signal of threshold voltage writing module in Section Point The signal at the first reference signal end is supplied to first node under control；Control of the current potential stable module at the second reset signal end The lower signal by the second reference signal end is supplied to drive signal output end；

Later half time period, voltage coupling module keep Section Point and when first when Section Point is in floating Voltage difference between clock signal end is stable；Second output module is under the control of the signal of Section Point by the second reference signal end Signal be supplied to drive signal output end；Threshold voltage writing module is referred to first under the control of the signal of Section Point The signal of signal end is supplied to first node.

Same inventive concept is based on, the embodiment of the present invention also provides a kind of gate driver circuit, as shown in fig. 6, including：Level Any of the above-described kind of shift register SR (1) N number of provided in an embodiment of the present invention of connection, SR (2), SR (3) ... SR (n), SR (n- 1)、SR(n+1)；Wherein, N is the integer more than or equal to 4；

The input signal end Input of the 1st grade of shift register SR (1) is connected with the first frame trigger end STV1；

The input signal end Input of the 2nd grade of shift register SR (2) is connected with the second frame trigger end STV2；

The input signal end Input of n-th grade of shift register SR (n) respectively with the n-th -2 grades shift register SR (n-2) Drive signal output end Output is connected；

First reset signal end RST1 of the n-th -2 grades shift register SR (n-2) respectively with (n+1)th grade of shift register SR (n+1) drive signal output end Output is connected；Wherein, n is the integer more than or equal to 3 and less than or equal to N-1.

Further, in the specific implementation, in above-mentioned driving method provided in an embodiment of the present invention, in each shift LD When device also includes current potential stable module, the second reset signal end of the n-th -2 grades shift registers respectively with the n-th+2 grades shift LDs The drive signal output end of device is connected.

Further, in the specific implementation, in above-mentioned driving method provided in an embodiment of the present invention, the first reference signal End is same signal end with the second reference signal end.

Specifically, the concrete structure of each shift register in above-mentioned gate driver circuit is posted with above-mentioned displacement of the invention Storage all same in function and structure, repeats part and repeats no more.The gate driver circuit can apply to LCD In plate, it is also possible to be applied in organic EL display panel, be not limited thereto.

Specifically, in above-mentioned gate driver circuit provided in an embodiment of the present invention, as shown in fig. 6, the displacement of 6k+1 levels The second clock signal end CLKB of the first clock signal terminal CLK and 6k+4 level shift register of register with same clock End is that the first clock end ck1 is connected；First clock signal terminal CLK and 6k+5 level shift LD of 6k+2 level shift registers The second clock signal end CLKB of device is that second clock end ck2 is connected with same clock end；6k+3 level shift registers The second clock signal end CLKB of the first clock signal terminal CLK and 6k+6 level shift register is the 3rd with same clock end Clock end ck3 is connected；The second of first clock signal terminal CLK and 6k+1 level shift register of 6k+4 level shift registers Clock signal terminal CLKB is that the 4th clock end ck4 is connected with same clock end；First clock of 6k+5 level shift registers The second clock signal end CLKB of signal end CLK and 6k+2 level shift register is the 5th clock end with same clock end Ck5 is connected；The second clock letter of the first clock signal terminal CLK and 6k+3 level shift register of 6k+6 level shift registers Number end CLKB with same clock end be the 6th clock end ck6 be connected；Wherein, k is the integer more than or equal to 0.

Same inventive concept is based on, the embodiment of the present invention additionally provides a kind of display device, carries including the embodiment of the present invention For any of the above-described kind of gate driver circuit.The display device can be：Mobile phone, panel computer, television set, display, notes Any product or part with display function such as this computer, DPF, navigator.For other of the display device must not The part that can lack is it will be apparent to an ordinarily skilled person in the art that have, and be will not be described here, also be should not be used as Limitation of the present invention.The enforcement of the display device may refer to the embodiment of above-mentioned shift register, repeats part and no longer goes to live in the household of one's in-laws on getting married State.

Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the present invention to the present invention God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to comprising these changes and modification.

Claims

1. a kind of shift register, it is characterised in that include：Input module, voltage coupling module, threshold voltage writing module, First output module and the second output module；Wherein,

The input module is connected with input signal end, the first reference signal end, first node and Section Point respectively；Described Input module is used for, under the control at the input signal end, the signal at the input signal end is supplied to the first node, The signal at the first reference signal end is supplied to the Section Point under the control at the input signal end；

The voltage coupling module is connected with the first clock signal terminal and the Section Point respectively；The voltage coupling module For when the Section Point is in floating, keeping the electricity between the Section Point and first clock signal terminal Pressure reduction is stable；

The threshold voltage writing module respectively with the first reset signal end, the first reference signal end, the first node And the Section Point is connected；The threshold voltage writing module is used for turning under the control at the first reset signal end The first node and the Section Point, and by first reference signal under the control of the signal of the Section Point The signal at end is supplied to the first node；

First output module respectively with first clock signal terminal, the first node and the shift register Drive signal output end is connected；First output module is used for described first under the control of the signal of the first node The signal of clock signal terminal is supplied to the drive signal output end, and when the first node is in floating, protects The voltage difference that holds between the first node and the drive signal output end is stable；

Second output module respectively with second clock signal end, the second reference signal end, the Section Point and described Drive signal output end is connected；Second output module is used for described second under the control of the signal of the Section Point The signal at reference signal end is supplied to the drive signal output end, and by institute under the control of the second clock signal end The signal for stating the second reference signal end is supplied to the drive signal output end.

2. shift register as claimed in claim 1, it is characterised in that the voltage coupling module includes：First electric capacity；Its In,

The first end of first electric capacity is connected with the Section Point, and the second end is connected with first clock signal terminal.

3. shift register as claimed in claim 1, it is characterised in that the threshold voltage writing module includes：First opens Close transistor AND gate second switch transistor；Wherein,

The grid of the first switch transistor is connected with the first reset signal end, and source electrode is connected with the first node, Drain electrode is connected with the Section Point；

The grid of the second switch transistor is connected with the Section Point, and source electrode is connected with the first reference signal end, Drain electrode is connected with the first node.

4. shift register as claimed in claim 1, it is characterised in that the input module includes：3rd switching transistor With the 4th switching transistor；Wherein,

The grid of the 3rd switching transistor is connected with the input signal end with drain electrode, source electrode and the first node phase Even；

The grid of the 4th switching transistor is connected with the input signal end, source electrode and the first reference signal end phase Even, drain electrode is connected with the Section Point.

5. shift register as claimed in claim 1, it is characterised in that first output module includes：5th switch is brilliant Body pipe and the second electric capacity；Wherein,

The grid of the 5th switching transistor is connected with the first node, and source electrode is connected with first clock signal terminal, Drain electrode is connected with the drive signal output end；

The first end of second electric capacity is connected with the first node, and the second end is connected with the drive signal output end.

6. shift register as claimed in claim 1, it is characterised in that second output module includes：6th switch is brilliant Seven switching transistors of body Guan Yu；Wherein,

The grid of the 6th switching transistor is connected with the Section Point, and source electrode is connected with the second reference signal end, Drain electrode is connected with the drive signal output end；

The grid of the 7th switching transistor is connected with the second clock signal end, source electrode and the second reference signal end It is connected, drain electrode is connected with the drive signal output end.

7. the shift register as described in any one of claim 1-6, it is characterised in that also include：Current potential stable module；Its In,

The current potential stable module is defeated with the second reset signal end, the second reference signal end and the drive signal respectively Go out end to be connected；The current potential stable module is used for the second reference signal end under the control at the second reset signal end Signal be supplied to the drive signal output end.

8. shift register as claimed in claim 7, it is characterised in that the current potential stable module includes：8th switch is brilliant Body pipe；Wherein,

The grid of the 8th switching transistor is connected with the second reset signal end, source electrode and the second reference signal end It is connected, drain electrode is connected with the drive signal output end.

9. a kind of gate driver circuit, it is characterised in that including the N number of displacement as described in any one of claim 1-8 for cascading Register；Wherein, N is the integer more than or equal to 4；

The input signal end of n-th grade of shift register is connected with the drive signal output end of the n-th -2 grades shift registers respectively；

First reset signal end of the n-th -2 grades shift registers drive signal output end respectively with (n+1)th grade of shift register It is connected；Wherein, n is the integer more than or equal to 3 and less than or equal to N-1.

10. a kind of display device, it is characterised in that including gate driver circuit as claimed in claim 9.

11. a kind of driving methods of the shift register as described in any one of claim 1-8, it is characterised in that include：First Stage, second stage, phase III, fourth stage, the 5th stage and the 6th stage；Wherein,

In the first stage, the input module is under the control at the input signal end by the signal at the input signal end The first node is supplied to, the signal at the first reference signal end is supplied to institute under the control at the input signal end State Section Point；First output module is under the control of the signal of the first node by first clock signal terminal Signal is supplied to the drive signal output end；Second output module is under the control of the second clock signal end by institute The signal for stating the second reference signal end is supplied to the drive signal output end；

In the second stage, first output module is under the control of the signal of the first node by first clock The signal of signal end is supplied to the drive signal output end, and when the first node is in floating, keeps institute The voltage difference that states between first node and the drive signal output end is stable；The input module is at the input signal end The signal at the first reference signal end is supplied to the Section Point under control；

In the phase III, first output module is under the control of the signal of the first node by first clock The signal of signal end is supplied to the drive signal output end, and when the first node is in floating, keeps institute The voltage difference that states between first node and the drive signal output end is stable；The voltage coupling module is in the Section Point When being in floating, keep the voltage difference between the Section Point and first clock signal terminal stable；

In the fourth stage, the threshold voltage writing module turns on described under the control at the first reset signal end One node and the Section Point, and by the letter at the first reference signal end under the control of the signal of the Section Point Number it is supplied to the first node；Second output module is joined described second under the control of the second clock signal end The signal for examining signal end is supplied to the drive signal output end；

In the 5th stage, the voltage coupling module keeps described second when the Section Point is in floating Voltage difference between node and first clock signal terminal is stable；Signal of second output module in the Section Point Control under the signal at the second reference signal end is supplied to the drive signal output end；The threshold voltage writes mould The signal at the first reference signal end is supplied to the first node under the control of the signal of the Section Point by block；

In the 6th stage, the voltage coupling module keeps described second when the Section Point is in floating Voltage difference between node and first clock signal terminal is stable；Second output module is in the second clock signal end Control under the signal at the second reference signal end is supplied to the drive signal output end.