CN106782399A - A kind of shift register, its driving method, gate driving circuit and display device - Google Patents

A kind of shift register, its driving method, gate driving circuit and display device Download PDF

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Publication number
CN106782399A
CN106782399A CN201710020028.5A CN201710020028A CN106782399A CN 106782399 A CN106782399 A CN 106782399A CN 201710020028 A CN201710020028 A CN 201710020028A CN 106782399 A CN106782399 A CN 106782399A
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China
Prior art keywords
signal
output
switching transistor
module
section point
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CN201710020028.5A
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Chinese (zh)
Inventor
陈义鹏
玄明花
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to CN201710020028.5A priority Critical patent/CN106782399A/en
Publication of CN106782399A publication Critical patent/CN106782399A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Abstract

The invention discloses a kind of shift register, its driving method, gate driving circuit and display device, including：Input module, the first control module, the second control module, the first output module and the second output module；Wherein it is possible to by the mutual cooperation of above-mentioned five modules, to realize the output of scanning signal by simple structure and less clock signal, so as to simplify preparation technology, reduce production cost.

Description

A kind of shift register, its driving method, gate driving circuit and display device
Technical field
The present invention relates to display technology field, more particularly to a kind of shift register, its driving method, gate driving circuit And display device.
Background technology
With developing rapidly for Display Technique, direction of the display panel increasingly towards high integration and low cost is developed. Wherein, array base palte row drives (Gate Driver on Array, GOA) technology by thin film transistor (TFT) (Thin Film Transistor, TFT) gate switch circuit is integrated on the array base palte of display panel and the scanning of display panel is driven with being formed It is dynamic, such that it is able to saving binding (Bonding) region of grid integrated circuits (Integrated Circuit, IC) and being fanned out to (Fan-out) wiring space in region, not only can reduce product cost, Er Qieke in material cost and the aspect of preparation technology two So that display panel accomplishes symmetrical and narrow frame the design for aesthetic in both sides；Also, this integrated technique may be omitted with grid and sweep The Bonding techniques in line direction are retouched, so as to improve production capacity and yield.
General gate driving circuit is made up of the shift register of multiple cascades, by shift register realities at different levels Now it is input into scanning signal to each row grid line on display panel successively.At present, although can be by being input into more clock signal To realize the output of scanning signal, but the switching transistor of shift registers at different levels is constituted in so causing gate driving circuit Number it is more, and between each switching transistor connect concrete structure it is also more complicated, cause technology difficulty to increase, produce Cost increases, or even due to needing to use more clock cable by the clock signal input of different sequential shift LDs at different levels Device, so as to the aperture opening ratio for causing display panel is reduced so that the display panel does not possess competitiveness.
The content of the invention
The embodiment of the present invention provides a kind of shift register, its driving method, gate driving circuit and display device, is used to Solve that shift register needs in the prior art clock signal is more and baroque problem.
Therefore, a kind of shift register is the embodiment of the invention provides, including：Input module, the first control module, second Control module, the first output module and the second output module；Wherein,
The first end of the input module is connected with input signal end, and the second end is connected with the first clock signal terminal, the 3rd End is connected with first node；The input module is used for the input signal end under the control of first clock signal terminal Signal be supplied to the first node；
The first end of first control module is connected with the first reference signal end, the second end and second clock signal end phase Even, the 3rd end is connected with the first node, and the 4th end is connected with Section Point；First control module is used for described the The signal at the first reference signal end is supplied under two clock signal terminals and the co- controlling of the signal of the Section Point The first node；
The first end of second control module is connected with first clock signal terminal, and the second end and described first refers to Signal end is connected, and the 3rd end is connected with the second reference signal end, the drive signal output end of the 4th end and the shift register It is connected, the 5th end is connected with the Section Point；Second control module is used for the control in first clock signal terminal The lower signal by the second reference signal end is supplied to the Section Point, and in the control of the drive signal output end The lower signal by the first reference signal end is supplied to the Section Point；
The first end of first output module is connected with the first node, the second end and the second clock signal end It is connected, the 3rd end is connected with the drive signal output end；First output module is used in first output module The signal of the second clock signal end is supplied to the drive signal output end, Yi Ji under the control of the signal of first end When the first node is in floating, keep first output module first end and the drive signal output end it Between voltage difference stabilization；
The first end of second output module is connected with the Section Point, the second end and the first reference signal end It is connected, the 3rd end is connected with the drive signal output end；Second output module is used for the signal in the Section Point Control under the signal at the first reference signal end is supplied to the drive signal output end, and in the Section Point During in floating, the voltage difference stabilization between the Section Point and the drive signal output end is kept.
Preferably, in above-mentioned shift register provided in an embodiment of the present invention, first control module includes：First Switching transistor and second switch transistor；Wherein,
The grid of the first switch transistor is connected with the Section Point, the source electrode of the first switch transistor with The first reference signal end is connected, the source electrode phase of the drain electrode of the first switch transistor and the second switch transistor Even；
The grid of the second switch transistor is connected with the second clock signal end, drains and the first node phase Even.
Preferably, in above-mentioned shift register provided in an embodiment of the present invention, second control module includes：3rd Switching transistor and the 4th switching transistor；Wherein,
The grid of the 3rd switching transistor is connected with first clock signal terminal, and source electrode and the described second reference are believed Number end be connected, drain electrode be connected with the Section Point；
The grid of the 4th switching transistor is connected with the drive signal output end, and source electrode and the described first reference are believed Number end be connected, drain electrode be connected with the Section Point.
Preferably, in above-mentioned shift register provided in an embodiment of the present invention, the input module includes：5th switch Transistor；Wherein,
The grid of the 5th switching transistor is connected with first clock signal terminal, source electrode and the first node phase Even, drain electrode is connected with the input signal end.
Preferably, in above-mentioned shift register provided in an embodiment of the present invention, first output module includes：6th Switching transistor and the first electric capacity；Wherein,
The grid of the 6th switching transistor is the first end of first output module, source electrode and the second clock Signal end is connected, and drain electrode is connected with the drive signal output end；
First capacitance connection is between the grid and the drive signal output end of the 6th switching transistor.
Preferably, in above-mentioned shift register provided in an embodiment of the present invention, second output module includes：7th Switching transistor and the second electric capacity；Wherein,
The grid of the 7th switching transistor is connected with the Section Point, source electrode and the first reference signal end phase Even, drain electrode is connected with the drive signal output end；
Second capacitance connection is between the grid and the drive signal output end of the 7th switching transistor.
Preferably, in above-mentioned shift register provided in an embodiment of the present invention, also include：8th switching transistor；
The first node is connected by the 8th switching transistor with the first end of first output module, and The grid of the 8th switching transistor is connected with leakage control signal end, the first end phase of source electrode and first output module Even, drain electrode is connected with the first node.
Correspondingly, the embodiment of the present invention additionally provides a kind of gate driving circuit, including the multiple present invention of cascade is implemented Any of the above-described kind of shift register that example is provided；Wherein,
The input signal end of first order shift register is connected with frame trigger signal end；
In addition to the first order shift register, the input signal end of remaining shift register at different levels respectively with its The drive signal output end of the upper level shift register of connection is connected.
Correspondingly, the embodiment of the present invention additionally provides a kind of display device, including provided in an embodiment of the present invention above-mentioned Gate driving circuit.
Correspondingly, the embodiment of the present invention additionally provides a kind of any of the above-described kind of shift register provided in an embodiment of the present invention Driving method, including：First stage, second stage, phase III and fourth stage；Wherein,
In the first stage, the input module is under the control of first clock signal terminal by the input signal The signal at end is supplied to the first node；Signal of first output module in the first end of first output module The signal of the second clock signal end is supplied to the drive signal output end under control；Second control module is in institute State and the signal at the second reference signal end is supplied to the Section Point under the control of the first clock signal terminal；Described second The signal at the first reference signal end is supplied to the driving by output module under the control of the signal of the Section Point Signal output part；
In the second stage, first output module keeps described when the first node is in floating Voltage difference stabilization between the first end of the first output module and the drive signal output end, and export mould described first The signal of the second clock signal end is supplied to the drive signal output end under the control of the signal of the first end of block；Institute State the second control module and the signal at the first reference signal end is supplied to institute under the control of the drive signal output end State Section Point；
In the phase III, the input module is under the control of first clock signal terminal by the input signal The signal at end is supplied to the first node；Second control module will be described under the control of first clock signal terminal The signal at the second reference signal end is supplied to the Section Point；The signal of second output module in the Section Point The signal at the first reference signal end is supplied to the drive signal output end under control；
In the fourth stage, second output module keeps described when the Section Point is in floating Voltage difference stabilization between Section Point and the drive signal output end, and under the control of signal in the Section Point The signal at the first reference signal end is supplied to the drive signal output end；First control module is described second The signal at the first reference signal end is supplied to institute under clock signal terminal and the co- controlling of the signal of the Section Point State first node.
The present invention has the beneficial effect that：
Shift register provided in an embodiment of the present invention, its driving method, gate driving circuit and display device, including： Input module, the first control module, the second control module, the first output module and the second output module；Wherein, due to input Module is used to that the signal at input signal end to be supplied into first node under the control of the first clock signal terminal；First control module For the signal at the first reference signal end to be supplied under co- controlling of the second clock signal end with the signal of Section Point First node；Second control module is used to be supplied to the signal at the second reference signal end under the control of the first clock signal terminal Section Point, and the signal at the first reference signal end is supplied to Section Point under the control of drive signal output end；The One output module is used to provide the signal of second clock signal end under the control of the signal of the first end of the first output module Drive signal output end is given, and when first node is in floating, is kept the first end of the first output module and is driven Voltage difference stabilization between signal output part；Second output module is used for the first reference under the control of the signal of Section Point The signal of signal end is supplied to drive signal output end, and when Section Point is in floating, keep Section Point with Voltage difference stabilization between drive signal output end.Therefore, above-mentioned shift register provided in an embodiment of the present invention, by above-mentioned Five mutual cooperations of module, can realize the output of scanning signal by simple structure and less clock signal, So as to simplify preparation technology, production cost is reduced.
Brief description of the drawings
Fig. 1 is one of structural representation of shift register provided in an embodiment of the present invention；
Fig. 2 a are the two of the structural representation of shift register provided in an embodiment of the present invention；
Fig. 2 b are the three of the structural representation of shift register provided in an embodiment of the present invention；
Fig. 3 a are one of concrete structure schematic diagram of shift register shown in Fig. 1；
Fig. 3 b are the two of the concrete structure schematic diagram of the shift register shown in Fig. 1；
Fig. 4 a are the concrete structure schematic diagram of the shift register shown in Fig. 2 a；
Fig. 4 b are the concrete structure schematic diagram of the shift register shown in Fig. 2 b；
Fig. 5 a are the circuit timing diagram of the shift register shown in Fig. 3 a and Fig. 4 a；
Fig. 5 b are the circuit timing diagram of the shift register shown in Fig. 3 b and Fig. 4 b；
Fig. 6 is the flow chart of the driving method of shift register provided in an embodiment of the present invention；
Fig. 7 is the structural representation of gate driving circuit provided in an embodiment of the present invention.
Specific embodiment
In order that the purpose of the present invention, technical scheme and advantage are clearer, below in conjunction with the accompanying drawings, to the embodiment of the present invention The specific embodiment of the shift register of offer, its driving method, gate driving circuit and display device is carried out in detail It is bright.It should be appreciated that preferred embodiment disclosed below is merely to illustrate and explain the present invention, it is not intended to limit the present invention. And in the case where not conflicting, the feature in embodiment and embodiment in the application can be mutually combined.
A kind of shift register is the embodiment of the invention provides, as shown in figure 1, including：Input module 1, first controls mould Block 2, the second control module 3, the first output module 4 and the second output module 5；Wherein,
The first end of input module 1 is connected with input signal end Input, the second end is connected with the first clock signal terminal CK1, 3rd end is connected with first node A；Input module 1 is used for input signal end under the control of the first clock signal terminal CK1 The signal of Input is supplied to first node A；
The first end of the first control module 2 is connected with the first reference signal end VDD, the second end and second clock signal end CK2 is connected, and the 3rd end is connected with first node A, and the 4th end is connected with Section Point B；First control module 2 is used at second The signal of the first reference signal end VDD is supplied to first segment under the co- controlling of the signal of clock signal end CK2 and Section Point B Point A；
The first end of the second control module 3 is connected with the first clock signal terminal CK1, the second end and the first reference signal end VDD is connected, and the 3rd end is connected with the second reference signal end VSS, the drive signal output end of the 4th end and shift register Output is connected, and the 5th end is connected with Section Point B；Second control module 3 is used under the control of the first clock signal terminal CK1 The signal of the second reference signal end VSS is supplied to Section Point B, and will under the control of drive signal output end Output The signal of the first reference signal end VDD is supplied to Section Point B；
The first end of the first output module 4 is connected with first node A, and the second end is connected with second clock signal end CK2, the Three ends are connected with drive signal output end Output；First output module 4 is used for the signal of the first end in the first output module 4 Control under the signal of second clock signal end CK2 is supplied to drive signal output end Output, and at first node A When floating, the voltage difference stabilization between the first end and drive signal output end Output of the first output module 4 is kept；
The first end of the second output module 5 is connected with Section Point B, and the second end is connected with the first reference signal end VDD, the Three ends are connected with drive signal output end Output；Second output module 5 is used for the under the control of the signal of Section Point B The signal of one reference signal end VDD is supplied to drive signal output end Output, and is in floating in Section Point B When, keep the voltage difference stabilization between Section Point B and drive signal output end Output.
Above-mentioned shift register provided in an embodiment of the present invention, including：Input module, the first control module, the second control Module, the first output module and the second output module；Wherein, because input module is used for the control in the first clock signal terminal The lower signal by input signal end is supplied to first node；First control module is used in second clock signal end and Section Point Signal co- controlling under the signal at the first reference signal end is supplied to first node；Second control module is used for first The signal at the second reference signal end is supplied to Section Point under the control of clock signal terminal, and in drive signal output end The signal at the first reference signal end is supplied to Section Point under control；First output module is used for the of the first output module The signal of second clock signal end is supplied to drive signal output end under the control of the signal of one end, and at first node When floating, the voltage difference stabilization between the first end and drive signal output end of the first output module is kept；Second is defeated Go out module for the signal at the first reference signal end to be supplied into drive signal output end under the control of the signal of Section Point, And when Section Point is in floating, keep the voltage difference stabilization between Section Point and drive signal output end.Cause This, above-mentioned shift register provided in an embodiment of the present invention, by the mutual cooperation of above-mentioned five modules, can be by simple Structure and less clock signal realize the output of scanning signal, so as to simplify preparation technology, reduce production cost.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, in the effective of input signal end When pulse signal is low potential, the current potential at the first reference signal end is high potential, and the current potential at the second reference signal end is low potential. When the effective impulse signal at input signal end is high potential, the current potential at the first reference signal end is low potential, and second with reference to letter Number end current potential be high potential.
In order to be further ensured that the current potential stabilization of first node A, in the specific implementation, on provided in an embodiment of the present invention State in shift register, as shown in Figure 2 a and 2 b, shift register can also include：8th switching transistor M8；
First node A is connected by the 8th switching transistor M8 with the first end of the first output module 4, and the 8th switch The grid of transistor M8 is connected with leakage control signal end CS, and source electrode is connected with the first end of the first output module 4, drain electrode and the One node A is connected.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, leakage control signal end can be with It is same signal end with the second reference signal end.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Figure 2 a, the 8th switch Transistor M8 can be P-type transistor, and the effective impulse signal of input signal end Input is low potential.Or, such as Fig. 2 b institutes Show, the 8th switching transistor M8 can also be N-type transistor, and the effective impulse signal of input signal end Input is high potential, This is not construed as limiting.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 8th switching transistor is in leakage When in the conduction state under the control at electric control signal end, the signal of first node is supplied to the first of the first output module End.In actual applications, as shown in Figure 2 a, when the 8th switching transistor M8 is P-type transistor, the 8th switching transistor M8 exists Voltage difference V between its grid and its source electrodegs(M8) with its threshold voltage Vth(M8) relation between meets formula：Vgs(M8)< Vth(M8) turned on when.As shown in Figure 2 b, when the 8th switching transistor M8 is N-type transistor, the 8th switching transistor M8 is at it Voltage difference V between grid and its source electrodegs(M8) with its threshold voltage Vth(M8) relation between meets formula：Vgs(M8)>Vth (M8) turned on when.Also, after the 8th switching transistor M8 conductings, the resistance value of its equivalent resistance is smaller, is opened flowing through the 8th Close transistor M8 electric current it is smaller when, the pressure drop at its two ends can be ignored, and can reduce voltage loss.
With reference to specific embodiment, the present invention is described in detail.It should be noted that be in the present embodiment in order to The present invention is preferably explained, but does not limit the present invention.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 3 a to Fig. 4 b Shown, the first control module 2 can specifically include：First switch transistor M1 and second switch transistor M2；Wherein,
The grid of first switch transistor M1 is connected with Section Point B, and the source electrode of first switch transistor M1 and first is joined Examine signal end VDD to be connected, the drain electrode of first switch transistor M1 is connected with the source electrode of second switch transistor M2；
The grid of second switch transistor M2 is connected with second clock signal end CK2, and drain electrode is connected with first node A.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 3 a and Fig. 4 a, the One switching transistor M1 and second switch transistor M2 can be p-type switching transistor, the effective impulse of input signal end Input Signal is low potential.Or, as is shown in figures 3b and 4b, first switch transistor M1 can also be with second switch transistor M2 N-type switching transistor, the effective impulse signal of input signal end Input is high potential, is not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, first switch transistor is When in the conduction state under the control of the signal of two nodes, the signal at the first reference signal end is supplied to second switch transistor Source electrode.When second switch transistor is in the conduction state under the control of second clock signal end, the signal of its source electrode is carried Supply first node.
The above is only the concrete structure for illustrating the first control module in shift register provided in an embodiment of the present invention, In the specific implementation, the concrete structure of the first control module is not limited to said structure provided in an embodiment of the present invention, can also be Skilled person will appreciate that other structures, be not limited thereto.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 3 a to Fig. 4 b Shown, the second control module 3 can specifically include：3rd switching transistor M3 and the 4th switching transistor M4；Wherein,
The grid of the 3rd switching transistor M3 is connected with the first clock signal terminal CK1, source electrode and the second reference signal end VSS It is connected, drain electrode is connected with Section Point B；
The grid of the 4th switching transistor M4 is connected with drive signal output end Output, source electrode and the first reference signal end VDD is connected, and drain electrode is connected with Section Point B.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 3 a and Fig. 4 a, the Three switching transistor M3 and the 4th switching transistor M4 can be p-type switching transistor, the effective impulse of input signal end Input Signal is low potential.Or, as is shown in figures 3b and 4b, the 3rd switching transistor M3 and the 4th switching transistor M4 can also be N-type switching transistor, the effective impulse signal of input signal end Input is high potential, is not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 3rd switching transistor is When in the conduction state under the control of one clock signal terminal, the signal at the second reference signal end is supplied to Section Point.4th When switching transistor is in the conduction state under the control of drive signal output end, the signal at the first reference signal end is supplied to Section Point.
The above is only the concrete structure for illustrating the second control module in shift register provided in an embodiment of the present invention, In the specific implementation, the concrete structure of the second control module is not limited to said structure provided in an embodiment of the present invention, can also be Skilled person will appreciate that other structures, be not limited thereto.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 3 a to Fig. 4 b Shown, input module 1 can specifically include：5th switching transistor M5；Wherein,
The grid of the 5th switching transistor M5 is connected with the first clock signal terminal CK1, and source electrode is connected with first node A, leakage Pole is connected with input signal end Input.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 3 a and Fig. 4 a, the Five switching transistor M5 can be P-type transistor, and the effective impulse signal of input signal end Input is low potential.Or, such as scheme Shown in 3b and Fig. 4 b, the 5th switching transistor M5 can also be N-type transistor, the effective impulse signal of input signal end Input It is high potential, is not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 5th switching transistor is When in the conduction state under the control of one clock signal terminal, the signal at input signal end is supplied to first node.
The above is only the concrete structure for illustrating input module in shift register provided in an embodiment of the present invention, in tool When body is implemented, the concrete structure of input module is not limited to said structure provided in an embodiment of the present invention, can also be this area skill Other structures knowable to art personnel, are not limited thereto.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 3 a to Fig. 4 b Shown, the first output module 4 can specifically include：6th switching transistor M6 and the first electric capacity C1；Wherein,
The grid of the 6th switching transistor M6 is the first end of the first output module 4, source electrode and second clock signal end CK2 It is connected, drain electrode is connected with drive signal output end Output；
First electric capacity C1 is connected between the grid of the 6th switching transistor M6 and drive signal output end Output.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 3 a and Fig. 4 a, the Six switching transistor M6 can be P-type transistor, and the effective impulse signal of input signal end Input is low potential.Or, such as scheme Shown in 3b and Fig. 4 b, the 6th switching transistor M6 can also be N-type transistor, the effective impulse signal of input signal end Input It is high potential, is not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 6th switching transistor is When in the conduction state under the control of the signal of the first end of one output module, the signal of second clock signal end is supplied to drive Dynamic signal output part.When the first end of the first output module is in floating, because the boot strap of the first electric capacity can be with The voltage difference stabilization at its two ends is kept, that is, keeps the voltage difference between the first end of the first output module and drive signal output end Stabilization.
The above is only the concrete structure for illustrating the first output module in shift register provided in an embodiment of the present invention, In the specific implementation, the concrete structure of the first output module is not limited to said structure provided in an embodiment of the present invention, can also be Skilled person will appreciate that other structures, be not limited thereto.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 3 a to Fig. 4 b Shown, the second output module 5 can specifically include：7th switching transistor M7 and the second electric capacity C2；Wherein,
The grid of the 7th switching transistor M7 is connected with Section Point B, and source electrode is connected with the first reference signal end VDD, leakage Pole is connected with drive signal output end Output；
Second electric capacity C2 is connected between the grid of the 7th switching transistor M7 and drive signal output end Output.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 3 a and Fig. 4 a, the Seven switching transistor M7 can be P-type transistor, and the effective impulse signal of input signal end Input is low potential.Or, such as scheme Shown in 3b and Fig. 4 b, the 7th switching transistor M7 can also be N-type transistor, the effective impulse signal of input signal end Input It is high potential, is not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 7th switching transistor is When in the conduction state under the control of the signal of two nodes, it is supplied to drive signal to export the signal at the first reference signal end End.When Section Point is in floating, the voltage difference stabilization at its two ends can be kept due to the boot strap of the second electric capacity, Keep the voltage difference stabilization between Section Point and drive signal output end.
The above is only the concrete structure for illustrating the second output module in shift register provided in an embodiment of the present invention, In the specific implementation, the concrete structure of the second output module is not limited to said structure provided in an embodiment of the present invention, can also be Skilled person will appreciate that other structures, be not limited thereto.
It is preferred that in order to simplify preparation technology, in the specific implementation, in above-mentioned shift LD provided in an embodiment of the present invention In device, as shown in Fig. 3 a and Fig. 4 a, all switching transistors can be p-type switching transistor；Or, such as Fig. 3 b and Fig. 3 b institutes Show, all switching transistors can be N-type switching transistor, be not limited thereto.
Further, in the specific implementation, p-type switching transistor is ended under high potential effect, under low potential effect Conducting；N-type switching transistor is turned under high potential effect, is ended under low potential effect.
It should be noted that the switching transistor mentioned in the above embodiment of the present invention can be thin film transistor (TFT) (TFT, Thin Film Transistor), or metal oxide semiconductor field effect tube (MOS, Metal Oxide Scmiconductor), it is not limited thereto.In specific implementation, the source electrode of these transistors and drain electrode are according to transistor types And the difference of input signal, its function can exchange, and not do specific differentiation herein.
The course of work of above-mentioned shift register provided in an embodiment of the present invention is made to retouch with reference to circuit timing diagram State.High potential signal is represented with 1 in described below, 0 represents low-potential signal.Wherein, 1 and 0 represent its logic level, be only for The more preferable course of work for explaining above-mentioned shift register provided in an embodiment of the present invention, rather than in the specific implementation applying Current potential on the grid of each switching transistor.
Embodiment one,
Its course of work is described by taking the structure of the shift register shown in Fig. 3 a as an example, wherein shown in Fig. 3 a In shift register, the current potential of the first reference signal end VDD is high potential, and the current potential of the second reference signal end VSS is low potential, Corresponding input and output sequential chart as shown in Figure 5 a, specifically, chooses the T1 ranks in input and output sequential chart as shown in Figure 5 a Section, T2 stages, T3 stages and T4 stage four-stages.
In T1 stages, Input=0, CK1=0, CK2=1.
Due to CK1=0, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 conductings.Because the 5th switch is brilliant Body pipe M5 is turned on and the signal of the input signal end Input of low potential is supplied into first node A, thus first node A electricity Position is low potential.Because the current potential of first node A is low potential, therefore, the 6th switching transistor M6 conductings.Due to the 6th switch Transistor M6 is turned on and the signal of the second clock signal end CK2 of high potential is supplied into drive signal output end Output, because This drive signal output end Output is high potential, and the first electric capacity C1 charges, i.e. drive signal output end Output outputs electricity high The scanning signal of position.Because the 3rd switching transistor M3 is turned on and provides the signal of the second reference signal end VSS of low potential Section Point B is given, therefore the current potential of Section Point B is low potential.Because the current potential of Section Point B is low potential, therefore the 7th Switching transistor M7 is turned on, and the second electric capacity C2 charges.Because the 7th switching transistor M7 is turned on and is referred to the first of high potential The signal of signal end VDD is supplied to drive signal output end Output, therefore drive signal output end Output is high potential, i.e., It is further ensured that drive signal output end Output exports the scanning signal of high potential.
In T2 stages, Input=1, CK1=1, CK2=0.
Due to CK1=1, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 cut-offs, first node A is in floating Connect state.Because first node A is in floating, due to the boot strap of the first electric capacity C1, can keep first node A's Current potential is low potential, therefore the 6th switching transistor M6 is turned on.Turned on due to the 6th switching transistor M6 and by the of low potential The signal of two clock signal terminal CK2 is supplied to drive signal output end Output, therefore drive signal output end Output is low Current potential.Because drive signal output end Output is low potential, due to the boot strap of the first electric capacity C1, in order to keep its two ends Voltage difference stabilization, the current potential of first node A is further dragged down so that the 6th switching transistor M6 is fully on so that What the signal no-voltage of the second clock signal end CK2 of low potential lost is supplied to drive signal output end Output, makes driving Signal output part Output exports the scanning signal of low potential.Because drive signal output end Output is low potential, therefore the Four switching transistor M4 are turned on and the signal of the first reference signal end VDD of high potential are supplied into Section Point B, therefore second The current potential of node B is high potential, so that first switch transistor M1 is turned off with the 7th switching transistor M7.
In T3 stages, Input=1, CK1=0, CK2=1.
Due to CK1=0, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 conductings.Because the 3rd switch is brilliant Body pipe M3 is turned on and the signal of the second reference signal end VSS of low potential is supplied into Section Point B, therefore Section Point B Current potential is low potential.Due to Section Point B current potential be low potential, therefore the 7th switching transistor M7 turn on.Open due to the 7th Close transistor M7 conductings and the signal of the first reference signal end VDD of high potential be supplied to drive signal output end Output, Therefore drive signal output end Output is high potential, and the second electric capacity C2 charges, i.e. drive signal output end Output outputs are high The scanning signal of current potential.Because the 5th switching transistor M5 is turned on and provides the signal of the input signal end Input of high potential First node A is given, therefore the current potential of first node A is high potential, the first electric capacity C1 electric discharges.Because the current potential of first node A is High potential, therefore, the 6th switching transistor M6 cut-offs.
In T4 stages, Input=1, CK1=1, CK2=0.
Due to CK1=1, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 cut-offs, Section Point B is in floating Connect state.Because Section Point B is in floating, due to the boot strap of the second electric capacity C2, can keep Section Point B's Current potential is low potential, therefore first switch transistor M1 and the 7th switching transistor M7 is both turned on.Due to CK2=0, therefore second Switching transistor M2 is turned on, and due to first switch transistor M1 conductings, therefore can be by the first reference signal of high potential Hold the signal of VDD to be supplied to first node A, make the current potential of first node A for high potential, the 6th switching transistor M6 cut-offs.By Turned in the 7th switching transistor M7 and the signal of the first reference signal end VDD of high potential is supplied to drive signal output end Output, therefore drive signal output end Output is high potential, i.e. drive signal output end Output exports sweeping for high potential Retouch signal.
In above-mentioned shift register provided in an embodiment of the present invention, after the T4 stages, the T3 stages are repeated always With the course of work in T4 stages, untill when the current potential of input signal end Input is changed into low potential again.
Shift register in embodiment one only need set two clock signal terminals, and by seven switching transistors with And two mutual cooperations of electric capacity, the output of scanning signal is realized, compared with prior art, simple structure and required clock Signal is less.
In actual applications, the voltage of the first reference signal end signal of high potential is typically set to 7V, by low potential The voltage of the second reference signal end signal be set to -7V, electricity during by the signal high potential of the first clock signal terminal signal end Voltage of pressure when being set to 7V, low potential is set to -7V, and during by the signal high potential of second clock signal end signal end Voltage when voltage is set to 7V, low potential is set to -7V.But in the T2 stages of embodiment one, due to the first electric capacity Boot strap further drags down the current potential of first node, i.e. the current potential of the drain electrode of the 5th switching transistor is further dragged down, And because the grid of the 5th switching transistor is the signal of the first clock signal terminal of high potential, so as to cause the 5th switch brilliant The gate source voltage V of body pipegs(M5) it is larger, consequently, it is possible to cause the leakage current of the 5th switching transistor to increase, and then may shadow Ring the stabilization of the current potential of first node.Therefore, in order that the current potential of first node is more in stable state, by following realities Example is applied to illustrate.
Embodiment two,
With the structure of the shift register shown in Fig. 4 a, and leakage control signal end CS and the second reference signal end VSS To be described to its course of work as a example by same signal end, wherein in the shift register shown in Fig. 4 a, first with reference to letter The current potential of number end VDD is high potential, and the current potential of the second reference signal end VSS is low potential, and corresponding input and output sequential chart is such as Shown in Fig. 5 a, specifically, T1 stages, T2 stages, T3 stages and T4 ranks in selection input and output sequential chart as shown in Figure 5 a Section four-stage.
In T1 stages, Input=0, CK1=0, CK2=1.Due to CS1=0, therefore the 8th switching transistor M8 conductings are simultaneously The signal of the low potential of first node A is supplied to the grid of the 6th switching transistor M6, therefore, the 6th switching transistor M6 leads It is logical.Remaining course of work is essentially identical with the course of work in T1 stages in embodiment one, is not described in detail here.
In T2 stages, Input=1, CK1=1, CK2=0.
Due to CK1=1, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 cut-offs, first node A is in floating Connect state.Because first node A is in floating, therefore the grid of the 6th switching transistor M6 is in floating, due to The boot strap of the first electric capacity C1, can keep the current potential of grid of the 6th switching transistor M6 for low potential, therefore the 6th opens Close transistor M6 conductings.Because the 6th switching transistor M6 is turned on and carries the signal of the second clock signal end CK2 of low potential Supply drive signal output end Output, therefore drive signal output end Output is low potential.Due to drive signal output end Output is low potential, and due to the boot strap of the first electric capacity C1, in order to keep the voltage difference stabilization at its two ends, the 6th switch is brilliant The current potential of the grid of body pipe M6 is further dragged down, and makes the 6th switching transistor M6 fully on, and makes the 8th switch crystal Vgs (the M8) >=V of pipe M8th(M8) end, so that the grid of the 6th switching transistor M6 and the 5th switching transistor M5 Source electrode disconnects, and the current potential of the grid of the 6th switching transistor M6 is influenceed with the leakage current for avoiding the 5th switching transistor M5.By Can make what the signal no-voltage of the second clock signal end CK2 of low potential lost in the 6th fully on switching transistor M6 Drive signal output end Output is supplied to, drive signal output end Output is exported the scanning signal of low potential.Due to driving Dynamic signal output part Output is low potential, therefore the 4th switching transistor M4 conductings and by the first reference signal end of high potential The signal of VDD is supplied to Section Point B, therefore the current potential of Section Point B is high potential so that first switch transistor M1 with 7th switching transistor M7 is turned off.
In T3 stages, Input=1, CK1=0, CK2=1.Due to CS=0, therefore the 8th switching transistor M8 conductings are simultaneously The signal of the high potential of first node A is supplied to the grid of the 6th switching transistor M6, therefore, the 6th switching transistor M6 cuts Only, the first electric capacity C1 electric discharges.Remaining course of work is essentially identical with the course of work in T3 stages in embodiment one, does not make herein in detail State.
In T4 stages, Input=1, CK1=1, CK2=0.Due to CS=0, therefore the 8th switching transistor M8 conductings are simultaneously The signal of the high potential of first node A is supplied to the grid of the 6th switching transistor M6, therefore, the 6th switching transistor M6 cuts Only.Remaining course of work is essentially identical with the course of work in T4 stages in embodiment one, is not described in detail here.
In above-mentioned shift register provided in an embodiment of the present invention, after the T4 stages, the T3 stages are repeated always With the course of work in T4 stages, untill when the current potential of input signal end Input is changed into low potential again.
Embodiment three,
Its course of work is described by taking the structure of the shift register shown in Fig. 3 b as an example, wherein shown in Fig. 3 b In shift register, the current potential of the first reference signal end VDD is low potential, and the current potential of the second reference signal end VSS is high potential, Corresponding input and output sequential chart as shown in Figure 5 b, specifically, chooses the T1 ranks in input and output sequential chart as shown in Figure 5 b Section, T2 stages, T3 stages and T4 stage four-stages.
In T1 stages, Input=1, CK1=1, CK2=0.
Due to CK1=1, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 conductings.Because the 5th switch is brilliant Body pipe M5 is turned on and the signal of the input signal end Input of high potential is supplied into first node A, thus first node A electricity Position is high potential.Because the current potential of first node A is high potential, therefore, the 6th switching transistor M6 conductings.Due to the 6th switch Transistor M6 is turned on and the signal of the second clock signal end CK2 of low potential is supplied into drive signal output end Output, because This drive signal output end Output is low potential, and the first electric capacity C1 charges, i.e. drive signal output end Output exports low electricity The scanning signal of position.Because the 3rd switching transistor M3 is turned on and provides the signal of the second reference signal end VSS of high potential Section Point B is given, therefore the current potential of Section Point B is high potential.Because the current potential of Section Point B is high potential, therefore the 7th Switching transistor M7 is turned on, and the second electric capacity C2 charges.Because the 7th switching transistor M7 is turned on and is referred to the first of low potential The signal of signal end VDD is supplied to drive signal output end Output, therefore drive signal output end Output is low potential, i.e., It is further ensured that drive signal output end Output exports the scanning signal of low potential.
In T2 stages, Input=0, CK1=0, CK2=1.
Due to CK1=0, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 cut-offs, first node A is in floating Connect state.Because first node A is in floating, due to the boot strap of the first electric capacity C1, can keep first node A's Current potential is high potential, therefore the 6th switching transistor M6 is turned on.Turned on due to the 6th switching transistor M6 and by the of high potential It is height that the signal of two clock signal terminal CK2 is supplied to drive signal output end Output, therefore drive signal output end Output Current potential.Because drive signal output end Output is high potential, due to the boot strap of the first electric capacity C1, in order to keep its two ends Voltage difference stabilization, the current potential of first node A is further pulled up so that the 6th switching transistor M6 is fully on so that What the signal no-voltage of the second clock signal end CK2 of high potential lost is supplied to drive signal output end Output, makes driving Signal output part Output exports the scanning signal of high potential.Because drive signal output end Output is high potential, therefore the Four switching transistor M4 are turned on and the signal of the first reference signal end VDD of low potential are supplied into Section Point B, therefore second The current potential of node B is low potential, so that first switch transistor M1 is turned off with the 7th switching transistor M7.
In T3 stages, Input=0, CK1=1, CK2=0.
Due to CK1=1, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 conductings.Because the 3rd switch is brilliant Body pipe M3 is turned on and the signal of the second reference signal end VSS of high potential is supplied into Section Point B, therefore Section Point B Current potential is high potential.Due to Section Point B current potential be high potential, therefore the 7th switching transistor M7 turn on.Open due to the 7th Close transistor M7 conductings and the signal of the first reference signal end VDD of low potential be supplied to drive signal output end Output, Therefore drive signal output end Output is low potential, and the second electric capacity C2 charges, i.e. drive signal output end Output outputs are low The scanning signal of current potential.Because the 5th switching transistor M5 is turned on and provides the signal of the input signal end Input of low potential First node A is given, therefore the current potential of first node A is low potential, the first electric capacity C1 electric discharges.Because the current potential of first node A is Low potential, therefore, the 6th switching transistor M6 cut-offs.
In T4 stages, Input=0, CK1=0, CK2=1.
Due to CK1=0, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 cut-offs, Section Point B is in floating Connect state.Because Section Point B is in floating, due to the boot strap of the second electric capacity C2, can keep Section Point B's Current potential is high potential, therefore first switch transistor M1 and the 7th switching transistor M7 is both turned on.Due to CK2=1, therefore second Switching transistor M2 is turned on, and due to first switch transistor M1 conductings, therefore can be by the first reference signal of low potential Hold the signal of VDD to be supplied to first node A, make the current potential of first node A for low potential, the 6th switching transistor M6 cut-offs.By Turned in the 7th switching transistor M7 and the signal of the first reference signal end VDD of low potential is supplied to drive signal output end Output, therefore drive signal output end Output is low potential, i.e. drive signal output end Output exports sweeping for low potential Retouch signal.
In above-mentioned shift register provided in an embodiment of the present invention, after the T4 stages, the T3 stages are repeated always With the course of work in T4 stages, untill when the current potential of input signal end Input is changed into high potential again.
Shift register in embodiment three only need set two clock signal terminals, and by seven switching transistors with And two mutual cooperations of electric capacity, the output of scanning signal is realized, compared with prior art, simple structure and required clock Signal is less.In order that the current potential of first node is more in stable state, will be illustrated by the following examples.
Example IV,
With the structure of the shift register shown in Fig. 4 b, and leakage control signal end CS and the second reference signal end VSS To be described to its course of work as a example by same signal end, wherein in the shift register shown in Fig. 4 b, first with reference to letter The current potential of number end VDD is low potential, and the current potential of the second reference signal end VSS is high potential, and corresponding input and output sequential chart is such as Shown in Fig. 5 b, specifically, T1 stages, T2 stages, T3 stages and T4 ranks in selection input and output sequential chart as shown in Figure 5 b Section four-stage.
In T1 stages, Input=1, CK1=1, CK2=0.Due to CS1=1, therefore the 8th switching transistor M8 conductings are simultaneously The signal of the high potential of first node A is supplied to the grid of the 6th switching transistor M6, therefore, the 6th switching transistor M6 leads It is logical.Remaining course of work is essentially identical with the course of work in T1 stages in embodiment three, is not described in detail here.
In T2 stages, Input=0, CK1=0, CK2=1.
Due to CK1=0, therefore the 3rd switching transistor M3 and the 5th switching transistor M5 cut-offs, first node A is in floating Connect state.Because first node A is in floating, therefore the grid of the 6th switching transistor M6 is in floating, due to The boot strap of the first electric capacity C1, can keep the current potential of grid of the 6th switching transistor M6 for high potential, therefore the 6th opens Close transistor M6 conductings.Because the 6th switching transistor M6 is turned on and carries the signal of the second clock signal end CK2 of high potential Supply drive signal output end Output, therefore drive signal output end Output is high potential.Due to drive signal output end Output is high potential, and due to the boot strap of the first electric capacity C1, in order to keep the voltage difference stabilization at its two ends, the 6th switch is brilliant The current potential of the grid of body pipe M6 is further pulled up, and makes the 6th switching transistor M6 fully on, and makes the 8th switch crystal Vgs (the M8)≤V of pipe M8th(M8) end, so that the grid of the 6th switching transistor M6 and the 5th switching transistor M5 Source electrode disconnects, and the current potential of the grid of the 6th switching transistor M6 is influenceed with the leakage current for avoiding the 5th switching transistor M5.By Can make what the signal no-voltage of the second clock signal end CK2 of high potential lost in the 6th fully on switching transistor M6 Drive signal output end Output is supplied to, drive signal output end Output is exported the scanning signal of high potential.Due to driving Dynamic signal output part Output is high potential, therefore the 4th switching transistor M4 conductings and by the first reference signal end of low potential The signal of VDD is supplied to Section Point B, therefore the current potential of Section Point B is low potential so that first switch transistor M1 with 7th switching transistor M7 is turned off.
In T3 stages, Input=0, CK1=1, CK2=0.Due to CS=1, therefore the 8th switching transistor M8 conductings are simultaneously The signal of the low potential of first node A is supplied to the grid of the 6th switching transistor M6, therefore, the 6th switching transistor M6 cuts Only, the first electric capacity C1 electric discharges.Remaining course of work is essentially identical with the course of work in T3 stages in embodiment three, does not make herein in detail State.
In T4 stages, Input=0, CK1=0, CK2=1.Due to CS=1, therefore the 8th switching transistor M8 conductings are simultaneously The signal of the low potential of first node A is supplied to the grid of the 6th switching transistor M6, therefore, the 6th switching transistor M6 cuts Only.Remaining course of work is essentially identical with the course of work in T4 stages in embodiment three, is not described in detail here.
In above-mentioned shift register provided in an embodiment of the present invention, after the T4 stages, the T3 stages are repeated always With the course of work in T4 stages, untill when the current potential of input signal end Input is changed into high potential again.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of provided in an embodiment of the present invention any of the above-described kind The driving method of shift register, as shown in fig. 6, including：First stage, second stage, phase III and fourth stage；Its In,
S601, in the first stage, input module carries the signal at input signal end under the control of the first clock signal terminal Supply first node；First output module is under the control of the signal of the first end of the first output module by second clock signal end Signal be supplied to drive signal output end；Second control module is under the control of the first clock signal terminal by the second reference signal The signal at end is supplied to Section Point；Second output module is under the control of the signal of Section Point by the first reference signal end Signal is supplied to drive signal output end；
S602, in second stage, the first output module first node be in floating when, keep the first output module First end and drive signal output end between voltage difference stabilization, and the first output module first end signal control The signal of second clock signal end is supplied to drive signal output end under system；Second control module is in drive signal output end The signal at the first reference signal end is supplied to Section Point under control；
S603, in the phase III, input module carries the signal at input signal end under the control of the first clock signal terminal Supply first node；Be supplied to for the signal at the second reference signal end under the control of the first clock signal terminal by the second control module Section Point；The signal at the first reference signal end is supplied to driving by the second output module under the control of the signal of Section Point Signal output part；
S604, in fourth stage, the second output module Section Point be in floating when, keep Section Point with drive Voltage difference stabilization between dynamic signal output part, and by the letter at the first reference signal end under the control of the signal of Section Point Number it is supplied to drive signal output end；First control module is in second clock signal end and the co- controlling of the signal of Section Point The lower signal by the first reference signal end is supplied to first node.
The driving method of above-mentioned shift register provided in an embodiment of the present invention, can be by simple structure and less Clock signal realize the output of scanning signal, so as to simplify preparation technology, reduce production cost.
Specifically, in the specific implementation, in above-mentioned driving method provided in an embodiment of the present invention, in shift register also During including eight switching transistors, driving method also includes：
In the first stage, that first node is turned under the control at leakage control signal end is defeated with first for the 8th switching transistor Go out the first end of module；
In second stage, the 8th switching transistor first node be in floating when, at leakage control signal end The lower first end for disconnecting first node and the first output module of control；
In the phase III, it is defeated with first that the 8th switching transistor turns on first node under the control at leakage control signal end Go out the first end of module；
In fourth stage, it is defeated with first that the 8th switching transistor turns on first node under the control at leakage control signal end Go out the first end of module.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of gate driving circuit, and (Fig. 7 is with each shifting for such as Fig. 7 As a example by leakage control signal end in bit register and the second reference signal end are same signal end) shown in, including cascade is more Individual any of the above-described kind of shift register SR (1) provided in an embodiment of the present invention, SR (2) ... SR (n-1), SR (n) ... SR (N-1), SR (N) (N number of shift register, 1≤n≤N altogether)；Wherein,
The input signal end Input of first order shift register SR (1) is connected with frame trigger signal end STV；
In addition to first order shift register SR (1), the input signal end Input of remaining shift register SR (n) at different levels The drive signal output end Output of connected upper level shift register SR (n-1) is connected respectively.
Specifically, the concrete structure of each shift register in above-mentioned gate driving circuit is posted with above-mentioned displacement of the invention Storage all same in function and structure, repeats part and repeats no more.The gate driving circuit can apply to LCD In plate, it is also possible to be applied in organic EL display panel, it is not limited thereto.
Specifically, in above-mentioned gate driving circuit provided in an embodiment of the present invention, as shown in fig. 7, shift LD at different levels First reference signal end VDD of device SR (n) is connected with same direct current signal end vdd, and the second of shift registers SR (n) at different levels Reference signal end VSS is connected with same direct current signal end vss.
Specifically, in above-mentioned gate driving circuit provided in an embodiment of the present invention, also include in shift registers at different levels During eight switching transistors, leakage control signal end can be same signal end with the second reference signal end.
Specifically, in above-mentioned gate driving circuit provided in an embodiment of the present invention, as shown in fig. 7,2k-1 grades of displacement First clock signal terminal CK1 of register and 2k grades of second clock signal end CK2 of shift register with same clock end That is the first clock end ck1 is connected；The second clock signal end CK2 of 2k-1 grades of shift register and 2k grades of shift register First clock signal terminal CK1 is that second clock end ck2 is connected with same clock end；Wherein, k is positive integer.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including the embodiment of the present invention is carried The above-mentioned gate driving circuit for supplying.The principle of the display device solve problem is similar to aforementioned shift register, therefore the display The implementation of device may refer to the implementation of aforementioned shift register, repeats part and will not be repeated here.
In the specific implementation, above-mentioned display device provided in an embodiment of the present invention can be：Mobile phone, panel computer, TV Any product or part with display function such as machine, display, notebook computer, DPF, navigator.For the display The essential part of other of device is it will be apparent to an ordinarily skilled person in the art that have, and is not done herein superfluous State, also should not be taken as limiting the invention.
Above-mentioned shift register provided in an embodiment of the present invention, its driving method, gate driving circuit and display device, bag Include：Input module, the first control module, the second control module, the first output module and the second output module；Wherein, due to Input module is used to that the signal at input signal end to be supplied into first node under the control of the first clock signal terminal；First control Module is used to carry the signal at the first reference signal end under co- controlling of the second clock signal end with the signal of Section Point Supply first node；Second control module is used to carry the signal at the second reference signal end under the control of the first clock signal terminal Supply Section Point, and the signal at the first reference signal end is supplied to second section under the control of drive signal output end Point；First output module is used for the signal of second clock signal end under the control of the signal of the first end of the first output module Be supplied to drive signal output end, and when first node is in floating, keep the first end of the first output module with Voltage difference stabilization between drive signal output end；Second output module is used for first under the control of the signal of Section Point The signal at reference signal end is supplied to drive signal output end, and when Section Point is in floating, keeps second section Voltage difference stabilization between point and drive signal output end.Therefore, above-mentioned shift register provided in an embodiment of the present invention, passes through The mutual cooperation of above-mentioned five modules, can realize the defeated of scanning signal by simple structure and less clock signal Go out, so as to simplify preparation technology, reduce production cost.
Obviously, those skilled in the art can carry out various changes and modification without deviating from essence of the invention to the present invention God and scope.So, if these modifications of the invention and modification belong to the scope of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to comprising these changes and modification.

Claims (10)

1. a kind of shift register, it is characterised in that including：Input module, the first control module, the second control module, first Output module and the second output module；Wherein,
The first end of the input module is connected with input signal end, the second end is connected with the first clock signal terminal, the 3rd end with First node is connected；The input module is used for the letter at the input signal end under the control of first clock signal terminal Number it is supplied to the first node；
The first end of first control module is connected with the first reference signal end, and the second end is connected with second clock signal end, 3rd end is connected with the first node, and the 4th end is connected with Section Point；First control module is used for described second The signal at the first reference signal end is supplied to institute under clock signal terminal and the co- controlling of the signal of the Section Point State first node；
The first end of second control module is connected with first clock signal terminal, the second end and first reference signal End is connected, and the 3rd end is connected with the second reference signal end, and the 4th end is connected with the drive signal output end of the shift register, 5th end is connected with the Section Point；Second control module is used for institute under the control of first clock signal terminal The signal for stating the second reference signal end is supplied to the Section Point, and by institute under the control of the drive signal output end The signal for stating the first reference signal end is supplied to the Section Point；
The first end of first output module is connected with the first node, the second end and the second clock signal end phase Even, the 3rd end is connected with the drive signal output end；First output module is used for the of first output module The signal of the second clock signal end is supplied to the drive signal output end under the control of the signal of one end, and in institute When stating first node in floating, keep between the first end and the drive signal output end of first output module Voltage difference stabilization；
The first end of second output module is connected with the Section Point, the second end and the first reference signal end phase Even, the 3rd end is connected with the drive signal output end；Second output module is for the signal in the Section Point The signal at the first reference signal end is supplied to the drive signal output end under control, and at the Section Point When floating, the voltage difference stabilization between the Section Point and the drive signal output end is kept.
2. shift register as claimed in claim 1, it is characterised in that first control module includes：First switch is brilliant Body pipe and second switch transistor；Wherein,
The grid of the first switch transistor is connected with the Section Point, the source electrode of the first switch transistor with it is described First reference signal end is connected, and the drain electrode of the first switch transistor is connected with the source electrode of the second switch transistor；
The grid of the second switch transistor is connected with the second clock signal end, and drain electrode is connected with the first node.
3. shift register as claimed in claim 1, it is characterised in that second control module includes：3rd switch is brilliant The switching transistors of body Guan Yu tetra-；Wherein,
The grid of the 3rd switching transistor is connected with first clock signal terminal, source electrode and the second reference signal end It is connected, drain electrode is connected with the Section Point；
The grid of the 4th switching transistor is connected with the drive signal output end, source electrode and the first reference signal end It is connected, drain electrode is connected with the Section Point.
4. shift register as claimed in claim 1, it is characterised in that the input module includes：5th switching transistor； Wherein,
The grid of the 5th switching transistor is connected with first clock signal terminal, and source electrode is connected with the first node, Drain electrode is connected with the input signal end.
5. shift register as claimed in claim 1, it is characterised in that first output module includes：6th switch is brilliant Body pipe and the first electric capacity；Wherein,
The grid of the 6th switching transistor is the first end of first output module, source electrode and the second clock signal End is connected, and drain electrode is connected with the drive signal output end；
First capacitance connection is between the grid and the drive signal output end of the 6th switching transistor.
6. shift register as claimed in claim 1, it is characterised in that second output module includes：7th switch is brilliant Body pipe and the second electric capacity；Wherein,
The grid of the 7th switching transistor is connected with the Section Point, and source electrode is connected with the first reference signal end, Drain electrode is connected with the drive signal output end；
Second capacitance connection is between the grid and the drive signal output end of the 7th switching transistor.
7. the shift register as described in claim any one of 1-6, it is characterised in that also include：8th switching transistor；
The first node is connected by the 8th switching transistor with the first end of first output module, and described The grid of the 8th switching transistor is connected with leakage control signal end, and source electrode is connected with the first end of first output module, Drain electrode is connected with the first node.
8. a kind of gate driving circuit, it is characterised in that the multiple displacements as described in claim any one of 1-7 including cascade Register；Wherein,
The input signal end of first order shift register is connected with frame trigger signal end；
In addition to the first order shift register, the input signal end of remaining shift register at different levels is connected thereto respectively Upper level shift register drive signal output end be connected.
9. a kind of display device, it is characterised in that including gate driving circuit as claimed in claim 8.
10. the driving method of a kind of shift register as described in claim any one of 1-7, it is characterised in that including：First Stage, second stage, phase III and fourth stage；Wherein,
In the first stage, the input module is under the control of first clock signal terminal by the input signal end Signal is supplied to the first node；Control of first output module in the signal of the first end of first output module The lower signal by the second clock signal end is supplied to the drive signal output end；Second control module is described The signal at the second reference signal end is supplied to the Section Point under the control of one clock signal terminal；Second output The signal at the first reference signal end is supplied to the drive signal by module under the control of the signal of the Section Point Output end；
In the second stage, first output module keeps described first when the first node is in floating Voltage difference stabilization between the first end of output module and the drive signal output end, and in first output module The signal of the second clock signal end is supplied to the drive signal output end under the control of the signal of first end；Described The signal at the first reference signal end is supplied to described by two control modules under the control of the drive signal output end Two nodes；
In the phase III, the input module is under the control of first clock signal terminal by the input signal end Signal is supplied to the first node；Second control module is under the control of first clock signal terminal by described second The signal at reference signal end is supplied to the Section Point；The control of signal of second output module in the Section Point The lower signal by the first reference signal end is supplied to the drive signal output end；
In the fourth stage, second output module keeps described second when the Section Point is in floating Voltage difference stabilization between node and the drive signal output end, and by institute under the control of signal in the Section Point The signal for stating the first reference signal end is supplied to the drive signal output end；First control module is in the second clock The signal at the first reference signal end is supplied to described under signal end and the co- controlling of the signal of the Section Point One node.
CN201710020028.5A 2017-01-11 2017-01-11 A kind of shift register, its driving method, gate driving circuit and display device Pending CN106782399A (en)

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Application publication date: 20170531