CN106504721B

CN106504721B - A kind of shift register, its driving method, gate driving circuit and display device

Info

Publication number: CN106504721B
Application number: CN201710008054.6A
Authority: CN
Inventors: 韩明夫; 商广良; 韩承佑; 金志河; 姚星; 郑皓亮; 袁丽君; 王志冲
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2017-01-05
Filing date: 2017-01-05
Publication date: 2019-01-11
Anticipated expiration: 2037-01-05
Also published as: CN106504721A

Abstract

The invention discloses a kind of shift register, its driving method, gate driving circuit and display devices, comprising: input module, voltage coupling module, threshold voltage writing module, the first output module and the second output module；Wherein, pass through the mutual cooperation of aforementioned four module, the voltage of second node can be compensated, to guarantee after the effective impulse signal of shift register output driving signal, the current potential of first node can be made to be in the stable state of invalid current potential, to reduce the output noise of driving signal output end, and then can be to avoid showing existing exception.

Description

Shifting register, driving method thereof, grid driving circuit and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit, and a display device.

Background

With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. The Array substrate line driving (GOA) technology integrates a Thin Film Transistor (TFT) Gate switch Circuit on an Array substrate of a display panel to form a scan driving of the display panel, so that a wiring space of a binding (binding) region and a Fan-out (Fan-out) region of an Integrated Circuit (IC) can be omitted, and not only can the product cost be reduced in two aspects of material cost and preparation process, but also the display panel can be designed to be symmetrical at two sides and beautiful with a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.

A common gate driving circuit is composed of a plurality of cascaded shift registers, and scan signals are sequentially input to each row of gate lines on a display panel through each stage of shift register. At present, after the shift register finishes outputting the high-potential scan signal, the shift register enters a low-potential maintaining stage, which specifically includes: the pull-down transistor outputs a reference signal of a low potential to the driving signal output end under the control of a signal of the pull-down node so as to enable the driving signal output end to be in a low potential state; the node pull-down transistor provides a reference signal with a low potential to the pull-up node under the control of a signal of the pull-down node, so that the pull-up node becomes the low potential, and the pull-up node is in a low potential state, thereby reducing the output noise of the driving signal output end. However, in the low potential maintaining stage, the threshold voltage of the node pull-down transistor may drift forward, so that the node pull-down transistor may not be completely turned on, or even the node pull-down transistor may be turned off, so that the pull-up node may not stably maintain the low potential, and further, the output of the driving signal output terminal of the shift register may generate noise, or even display may be abnormal.

Disclosure of Invention

Embodiments of the present invention provide a shift register, a driving method thereof, a gate driving circuit and a display device, so as to solve a problem in the prior art that in a low potential holding stage, a pull-up node cannot stably hold a low potential, which may cause noise to be generated at an output of a driving signal output terminal of the shift register, and even may cause display abnormality.

Accordingly, an embodiment of the present invention provides a shift register, including: the device comprises an input module, a voltage coupling module, a threshold voltage writing module, a first output module and a second output module; wherein,

the input module is respectively connected with an input signal end, a first reference signal end, a first node and a second node; the input module is used for providing a signal of the input signal terminal to the first node under the control of the input signal terminal and providing a signal of the first reference signal terminal to the second node under the control of the input signal terminal;

the voltage coupling module is respectively connected with a first clock signal end and the second node; the voltage coupling module is used for keeping the voltage difference between the second node and the first clock signal end stable when the second node is in a floating state;

the threshold voltage writing module is respectively connected with a first reset signal end, the first reference signal end, the first node and the second node; the threshold voltage writing module is used for conducting the first node and the second node under the control of the first reset signal terminal, and providing a signal of the first reference signal terminal to the first node under the control of a signal of the second node;

the first output module is respectively connected with the first clock signal end, the first node and the drive signal output end of the shift register; the first output module is used for providing a signal of the first clock signal end to the driving signal output end under the control of a signal of the first node, and keeping a voltage difference between the first node and the driving signal output end stable when the first node is in a floating state;

the second output module is respectively connected with a second clock signal end, a second reference signal end, the second node and the driving signal output end; the second output module is configured to provide the signal of the second reference signal terminal to the driving signal output terminal under the control of the signal of the second node, and provide the signal of the second reference signal terminal to the driving signal output terminal under the control of the second clock signal terminal.

Preferably, in the shift register provided in the embodiment of the present invention, the voltage coupling module includes: a first capacitor; wherein,

and the first end of the first capacitor is connected with the second node, and the second end of the first capacitor is connected with the first clock signal end.

Preferably, in the shift register provided in the embodiment of the present invention, the threshold voltage writing module includes: a first switching transistor and a second switching transistor; wherein,

the grid electrode of the first switch transistor is connected with the first reset signal end, the source electrode of the first switch transistor is connected with the first node, and the drain electrode of the first switch transistor is connected with the second node;

and the grid electrode of the second switch transistor is connected with the second node, the source electrode of the second switch transistor is connected with the first reference signal end, and the drain electrode of the second switch transistor is connected with the first node.

Preferably, in the shift register provided in the embodiment of the present invention, the input module includes: a third switching transistor and a fourth switching transistor; wherein,

the grid electrode and the drain electrode of the third switching transistor are both connected with the input signal end, and the source electrode of the third switching transistor is connected with the first node;

and the grid electrode of the fourth switching transistor is connected with the input signal end, the source electrode of the fourth switching transistor is connected with the first reference signal end, and the drain electrode of the fourth switching transistor is connected with the second node.

Preferably, in the shift register provided in the embodiment of the present invention, the first output module includes: a fifth switching transistor and a second capacitor; wherein,

a grid electrode of the fifth switching transistor is connected with the first node, a source electrode of the fifth switching transistor is connected with the first clock signal end, and a drain electrode of the fifth switching transistor is connected with the driving signal output end;

and the first end of the second capacitor is connected with the first node, and the second end of the second capacitor is connected with the driving signal output end.

Preferably, in the shift register provided in the embodiment of the present invention, the second output module includes: a sixth switching transistor and a seventh switching transistor; wherein,

a gate of the sixth switching transistor is connected to the second node, a source thereof is connected to the second reference signal terminal, and a drain thereof is connected to the driving signal output terminal;

and the grid electrode of the seventh switching transistor is connected with the second clock signal end, the source electrode of the seventh switching transistor is connected with the second reference signal end, and the drain electrode of the seventh switching transistor is connected with the driving signal output end.

Preferably, in the shift register provided in the embodiment of the present invention, the shift register further includes: a potential stabilization module; wherein,

the potential stabilizing module is respectively connected with a second reset signal end, the second reference signal end and the driving signal output end; the potential stabilizing module is used for providing the signal of the second reference signal end to the driving signal output end under the control of the second reset signal end.

Preferably, in the shift register provided in the embodiment of the present invention, the potential stabilizing module includes: an eighth switching transistor; wherein,

and the grid electrode of the eighth switching transistor is connected with the second reset signal end, the source electrode of the eighth switching transistor is connected with the second reference signal end, and the drain electrode of the eighth switching transistor is connected with the driving signal output end.

Correspondingly, the embodiment of the invention also provides a gate drive circuit, which comprises N cascaded shift registers provided by the embodiment of the invention; wherein N is an integer greater than or equal to 4;

the input signal end of the 1 st-stage shift register is connected with the first frame trigger signal end;

the input signal end of the 2 nd-stage shift register is connected with the second frame trigger signal end;

the input signal end of the nth stage shift register is respectively connected with the driving signal output end of the nth-2 stage shift register;

the first reset signal end of the (n-2) th stage shift register is respectively connected with the driving signal output end of the (n +1) th stage shift register; wherein N is an integer greater than or equal to 3 and less than or equal to N-1.

Correspondingly, the embodiment of the invention also provides a display device which comprises any one of the gate driving circuits provided by the embodiment of the invention.

Correspondingly, an embodiment of the present invention further provides a method for driving any one of the shift registers, which includes: a first stage, a second stage, a third stage, a fourth stage, a fifth stage and a sixth stage; wherein,

in the first phase, the input module provides the signal of the input signal terminal to the first node under the control of the input signal terminal, and provides the signal of the first reference signal terminal to the second node under the control of the input signal terminal; the first output module provides a signal of the first clock signal end to the driving signal output end under the control of the signal of the first node; the second output module provides the signal of the second reference signal end to the driving signal output end under the control of the second clock signal end;

in the second stage, the first output module provides the signal of the first clock signal end to the driving signal output end under the control of the signal of the first node, and keeps the voltage difference between the first node and the driving signal output end stable when the first node is in a floating state; the input module provides the signal of the first reference signal terminal to the second node under the control of the input signal terminal;

in the third phase, the first output module provides the signal of the first clock signal end to the driving signal output end under the control of the signal of the first node, and keeps the voltage difference between the first node and the driving signal output end stable when the first node is in a floating state; when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal end stable;

in the fourth phase, the threshold voltage writing module turns on the first node and the second node under the control of the first reset signal terminal, and provides the signal of the first reference signal terminal to the first node under the control of the signal of the second node; the second output module provides the signal of the second reference signal end to the driving signal output end under the control of the second clock signal end;

in the fifth stage, when the second node is in a floating state, the voltage coupling module keeps a voltage difference between the second node and the first clock signal terminal stable; the second output module provides the signal of the second reference signal end to the driving signal output end under the control of the signal of the second node; the threshold voltage writing module provides a signal of the first reference signal terminal to the first node under the control of a signal of the second node;

in the sixth stage, when the second node is in a floating state, the voltage coupling module keeps a voltage difference between the second node and the first clock signal terminal stable; the second output module provides the signal of the second reference signal end to the driving signal output end under the control of the second clock signal end.

The invention has the following beneficial effects:

the shift register, the driving method thereof, the gate driving circuit and the display device provided by the embodiment of the invention comprise the following steps: the device comprises an input module, a voltage coupling module, a threshold voltage writing module, a first output module and a second output module; the input module is used for providing a signal of an input signal end to a first node under the control of the input signal end and providing a signal of a first reference signal end to a second node under the control of the input signal end; the voltage coupling module is used for keeping the voltage difference between the second node and the first clock signal end stable when the second node is in a floating state; the threshold voltage writing module is used for conducting the first node and the second node under the control of the first reset signal end and providing a signal of the first reference signal end to the first node under the control of a signal of the second node; the first output module is used for providing a signal of a first clock signal end to the driving signal output end under the control of a signal of a first node, and keeping a voltage difference between the first node and the driving signal output end stable when the first node is in a floating state; the second output module is used for providing a signal of a second reference signal end to the driving signal output end under the control of a signal of a second node and providing a signal of the second reference signal end to the driving signal output end under the control of a second clock signal end. Therefore, the voltage of the second node can be compensated through the mutual matching of the four modules, so that the potential of the first node can be in a stable state of an invalid potential after the shift register outputs an effective pulse signal of a driving signal, the output noise of the driving signal output end is reduced, and the display abnormity can be avoided.

Drawings

Fig. 1a is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 1b is a second schematic diagram of a shift register according to an embodiment of the present invention;

FIG. 2a is a schematic diagram of a specific structure of the shift register shown in FIG. 1 a;

FIG. 2b is a schematic diagram of a specific structure of the shift register shown in FIG. 1 b;

FIG. 3a is a timing diagram of the input/output of the shift register shown in FIG. 2 a;

FIG. 3b is a timing diagram of the input and output of the shift register shown in FIG. 2 b;

FIG. 4a is a schematic diagram of an emulation simulation of the shift register shown in FIG. 2 b;

FIG. 4b is a second simulation diagram of the shift register shown in FIG. 2 b;

fig. 5 is a flowchart of a driving method of a shift register according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a shift register, a driving method thereof, a gate driving circuit and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

An embodiment of the present invention provides a shift register, as shown in fig. 1a and 1b, including: the device comprises an input module 1, a voltage coupling module 2, a threshold voltage writing module 3, a first output module 4 and a second output module 5; wherein,

the Input module 1 is respectively connected with an Input signal end Input, a first reference signal end VSS1, a first node A and a second node B; the Input module 1 is configured to provide a signal of an Input signal terminal Input to a first node a under the control of the Input signal terminal Input, and provide a signal of a first reference signal terminal VSS1 to a second node B under the control of the Input signal terminal Input;

the voltage coupling module 2 is respectively connected with a first clock signal end CLK and a second node B; the voltage coupling module 2 is used for keeping the voltage difference between the second node B and the first clock signal end CLK stable when the second node B is in a floating state;

the threshold voltage writing module 3 is respectively connected to the first reset signal terminal RST1, the first reference signal terminal VSS1, the first node a and the second node B; the threshold voltage writing module 3 is used for turning on the first node a and the second node B under the control of the first reset signal terminal RST1, and providing the signal of the first reference signal terminal VSS1 to the first node a under the control of the signal of the second node B;

the first Output module 4 is respectively connected with a first clock signal end CLK, a first node A and a drive signal Output end Output of the shift register; the first Output module 4 is configured to provide a signal of the first clock signal terminal CLK to the driving signal Output terminal Output under the control of a signal of the first node a, and keep a voltage difference between the first node a and the driving signal Output terminal Output stable when the first node a is in a floating state;

the second Output module 5 is respectively connected to the second clock signal terminal CLKB, the second reference signal terminal VSS2, the second node B and the driving signal Output terminal Output; the second Output module 5 is configured to provide a signal of the second reference signal terminal VSS2 to the driving signal Output terminal Output under the control of the signal of the second node B, and to provide a signal of the second reference signal terminal VSS2 to the driving signal Output terminal Output under the control of the second clock signal terminal CLKB.

The shift register provided in the embodiment of the present invention includes: the device comprises an input module, a voltage coupling module, a threshold voltage writing module, a first output module and a second output module; the input module is used for providing a signal of an input signal end to a first node under the control of the input signal end and providing a signal of a first reference signal end to a second node under the control of the input signal end; the voltage coupling module is used for keeping the voltage difference between the second node and the first clock signal end stable when the second node is in a floating state; the threshold voltage writing module is used for conducting the first node and the second node under the control of the first reset signal end and providing a signal of the first reference signal end to the first node under the control of a signal of the second node; the first output module is used for providing a signal of a first clock signal end to the driving signal output end under the control of a signal of a first node, and keeping a voltage difference between the first node and the driving signal output end stable when the first node is in a floating state; the second output module is used for providing a signal of a second reference signal end to the driving signal output end under the control of a signal of a second node and providing a signal of the second reference signal end to the driving signal output end under the control of a second clock signal end. Therefore, the shift register provided in the embodiment of the present invention can compensate the voltage of the second node by the mutual cooperation of the four modules, so as to ensure that the potential of the first node is in a stable state of an invalid potential after the shift register outputs the valid pulse signal of the driving signal, thereby reducing the output noise of the driving signal output end, and further avoiding the display from being abnormal.

In a specific implementation, in the shift register provided in the embodiment of the present invention, when the effective pulse signal at the input signal end is at a high potential, the voltage amplitude of the effective pulse signal at the input signal end, the voltage amplitude of the first clock signal, and the voltage amplitude of the second clock signal may all be equal. Of course, at least two of the voltage amplitude of the effective pulse signal at the input signal end, the voltage amplitude of the first clock signal and the voltage amplitude of the second clock signal may be unequal. In practical applications, the voltage amplitude of the effective pulse signal at the input signal terminal, the voltage amplitude of the signal at the first clock signal terminal, and the voltage amplitude of the signal at the second clock signal terminal need to be designed and determined according to practical application situations, which is not limited herein.

Further, after the driving signal Output end outputs the valid pulse signal of the scan signal, in order to further ensure that the potential of the driving signal Output end can be opposite to the potential of the valid pulse signal of the Input signal end in time, as shown in fig. 1b, in the shift register provided in the embodiment of the present invention, the shift register further includes: a potential stabilization module 6; wherein,

the potential stabilizing module 6 is respectively connected to the second reset signal terminal RST2, the second reference signal terminal VSS2 and the driving signal Output terminal Output; the potential stabilizing module 6 is configured to provide a signal of the second reference signal terminal VSS2 to the driving signal Output terminal Output under the control of the second reset signal terminal RST 2.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a and fig. 2b, the threshold voltage writing module 3 may specifically include: a first switching transistor M1 and a second switching transistor M2; wherein,

the gate of the first switching transistor M1 is connected to the first reset signal terminal RST1, the source is connected to the first node a, and the drain is connected to the second node B;

the second switching transistor M2 has a gate connected to the second node B, a source connected to the first reference signal terminal VSS1, and a drain connected to the first node a.

In a specific implementation, in the shift register provided in the embodiment of the present invention, when the active pulse signal of the first reset signal terminal is at a high potential, the first switch transistor may be an N-type switch transistor; alternatively, when the active pulse signal of the first reset signal terminal is at a low potential, the first switch transistor may be a P-type switch transistor, which is not limited herein.

In a specific implementation, in the shift register provided in the embodiment of the invention, when the active pulse signal of the Input signal terminal is at a high level, as shown in fig. 2a and 2b, the first switching transistor M1 and the second switching transistor M2 may be N-type switching transistors.

In a specific implementation, in the shift register provided in the embodiment of the present invention, when the first switching transistor is in a conducting state under the control of the first reset signal terminal, the first node and the second node are conducted. The second switching transistor supplies a signal of the first reference signal terminal to the first node when being in a conductive state under control of a signal of the second node.

The above is merely an example of the specific structure of the threshold voltage writing module in the shift register, and in the specific implementation, the specific structure of the threshold voltage writing module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a and fig. 2b, the voltage coupling module 2 may specifically include: a first capacitance C1; wherein,

the first capacitor C1 has a first terminal connected to the second node B and a second terminal connected to the first clock signal terminal CLK.

In a specific implementation, in the shift register provided in the embodiment of the present invention, when the second node is in a floating state, due to the bootstrap effect of the first capacitor, a voltage difference between two ends of the first capacitor may be kept stable, that is, a voltage difference between the second node and the first clock signal end is kept stable.

The above is merely an example of the specific structure of the voltage coupling module in the shift register, and in the specific implementation, the specific structure of the voltage coupling module is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a and fig. 2b, the input module 1 may specifically include: a third switching transistor M3 and a fourth switching transistor M4; wherein,

the gate and the drain of the third switching transistor M3 are both connected to the Input signal terminal Input, and the source is connected to the first node a;

a gate of the fourth switching transistor M4 is connected to the Input signal terminal Input, a source thereof is connected to the first reference signal terminal VSS1, and a drain thereof is connected to the second node B

In a specific implementation, in the shift register provided in the embodiment of the invention, when the active pulse signal of the Input signal terminal is at a high level, as shown in fig. 2a and fig. 2b, the third switching transistor M3 and the fourth switching transistor M4 may be N-type switching transistors.

In practical implementation, in the shift register provided in the embodiment of the invention, the fourth switching transistor supplies the signal of the first reference signal terminal to the second node under the control of the input signal terminal. The third switching transistor supplies a signal of the input signal terminal to the first node under the control of the input signal terminal; in practical application, because the grid electrode and the drain electrode of the third switching transistor are both connected with the input signal end, the voltage of the grid electrode of the third switching transistor and the voltage amplitude V of the effective pulse signal of the input signal end_InputIn the third switch crystalGate-source voltage V between gate and source of transistor_gs(M3) is greater than the threshold voltage V of the third switching transistor_th(M3), i.e. V_gs(M3)>V_th(M3) the third switching transistor is turned on and provides the signal from the input signal terminal to the first node until the voltage V at the first node_A＝V_Input-V_th(M3), the third switching transistor is turned off.

The above is merely an example of the specific structure of the input module in the shift register, and in the specific implementation, the specific structure of the input module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a and fig. 2b, the first output module 4 may specifically include: a fifth switching transistor M5 and a second capacitor C2; wherein,

a gate of the fifth switching transistor M5 is connected to the first node a, a source thereof is connected to the first clock signal terminal CLK, and a drain thereof is connected to the driving signal Output terminal Output;

a first terminal of the second capacitor C2 is connected to the first node a, and a second terminal thereof is connected to the driving signal Output terminal Output.

In a specific implementation, in the shift register provided in the embodiment of the present invention, when the active pulse signal of the Input signal terminal is at a high potential, as shown in fig. 2a and 2b, the fifth switching transistor may be an N-type switching transistor.

In a specific implementation, in the shift register provided in the embodiment of the present invention, when the fifth switching transistor is in a conducting state under the control of the signal at the first node, the signal at the first clock signal terminal is provided to the driving signal output terminal. When the first node is in a floating state, the voltage difference between two ends of the second capacitor can be kept stable due to the bootstrap effect of the second capacitor, namely, the voltage difference between the first node and the driving signal output end is kept stable.

The above is merely an example of the specific structure of the first output module in the shift register, and in the specific implementation, the specific structure of the first output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a and fig. 2b, the second output module 5 may specifically include: a sixth switching transistor M6 and a seventh switching transistor M7; wherein,

a gate of the sixth switching transistor M6 is connected to the second node B, a source thereof is connected to the second reference signal terminal VSS2, and a drain thereof is connected to the driving signal Output terminal Output;

the seventh switching transistor M7 has a gate connected to the second clock signal terminal CLKB, a source connected to the second reference signal terminal VSS2, and a drain connected to the driving signal Output terminal Output.

In a specific implementation, in the shift register provided in the embodiment of the invention, when the active pulse signal of the Input signal terminal is at a high level, as shown in fig. 2a and 2b, the sixth switching transistor M6 and the seventh switching transistor M7 may be N-type switching transistors.

In a specific implementation, in the shift register provided in the embodiment of the present invention, when the sixth switching transistor is in a conducting state under the control of the signal at the second node, the signal at the second reference signal terminal is provided to the driving signal output terminal. The seventh switching transistor supplies a signal of the second reference signal terminal to the driving signal output terminal when being in a conductive state under the control of the second clock signal terminal.

The above is merely an example of the specific structure of the second output module in the shift register, and in the specific implementation, the specific structure of the second output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2b, the potential stabilizing module 6 may specifically include: an eighth switching transistor M8; wherein,

the eighth switching transistor M8 has a gate connected to the second reset signal terminal RST2, a source connected to the second reference signal terminal VSS2, and a drain connected to the driving signal Output terminal Output.

In a specific implementation, in the shift register provided in the embodiment of the present invention, when the effective pulse signal at the second reset signal end is a high potential, the eighth switching transistor may be an N-type switching transistor; alternatively, when the active pulse signal of the second reset signal terminal is at a low potential, the eighth switching transistor may be a P-type switching transistor, which is not limited herein.

In a specific implementation, in the shift register provided in the embodiment of the invention, when the active pulse signal of the Input signal terminal is at a high potential, as shown in fig. 2b, the eighth switching transistor may be an N-type switching transistor.

In a specific implementation manner, in the shift register provided in the embodiment of the present invention, when the eighth switching transistor is in a conducting state under the control of the second reset signal terminal, the eighth switching transistor provides a signal of the second reference signal terminal to the driving signal output terminal.

The above is merely an example of the specific structure of the potential stabilizing module in the shift register, and in the specific implementation, the specific structure of the potential stabilizing module is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

In a specific implementation, in the shift register provided in the embodiment of the present invention, when the effective pulse signal at the input signal end is at a high potential, the potential of the first reference signal end is at a low potential, and the potential of the second reference signal end is at a low potential. The voltage of the first reference signal end is larger than or equal to the voltage of the second reference signal end. When the voltage of the first reference signal terminal is greater than the voltage of the second reference signal terminal, the shift register can be prevented from leaking electricity. In practical applications, the voltage of the first reference signal terminal and the voltage of the second reference signal terminal need to be designed and determined according to practical application situations, and are not limited herein.

Further, in a specific implementation, in the shift register provided in the embodiment of the present invention, the first reference signal terminal and the second reference signal terminal are the same signal terminal. Such that the voltage at the first reference signal terminal is equal to the voltage at the second reference signal terminal. And the arrangement of signal lines can be further reduced, and the preparation process is simplified.

Preferably, in order to simplify the manufacturing process, in the shift register provided in the embodiment of the present invention, in the implementation, as shown in fig. 2a and fig. 2b, all the switch transistors may be N-type switch transistors, which is not limited herein.

Furthermore, in specific implementation, the N-type switch transistor is turned on under the action of high potential and is turned off under the action of low potential; the P-type switching transistor is turned off under the action of a high potential and turned on under the action of a low potential.

It should be noted that the switching transistor mentioned in the above embodiments of the present invention may be an amorphous silicon thin film transistor (a-Si TFT), and may also be a Metal Oxide semiconductor field effect transistor (MOS), which is not limited herein. In specific implementation, the functions of the sources and the drains of the transistors can be interchanged according to the types of the transistors and different input signals, and are not particularly distinguished.

The operation of the shift register provided in the embodiment of the present invention is described below with reference to a circuit timing diagram. For example, the voltage of the first reference signal terminal is equal to the voltage of the second reference signal terminal. In the following description, a high potential signal is denoted by 1, and a low potential signal is denoted by 0, where 1 and 0 represent logic potentials thereof, which are provided only for better explaining the operation of the shift register provided by the embodiment of the present invention, and are not potentials applied to the gates of the switching transistors in practical implementation.

The first embodiment,

The operation process of the shift register shown in fig. 2a is described by taking the structure of the shift register as an example, wherein in the shift register shown in fig. 2a, all the switch transistors are N-type switch transistors, and each N-type switch transistor is turned on under the action of a high potential and is turned off under the action of a low potential; the potential of the first reference signal terminal VSS1 is low, and the corresponding input/output timing diagram is shown in fig. 3a, specifically, six stages of the first stage T1, the second stage T2, the third stage T3, the fourth stage T4, the fifth stage T5 and the sixth stage T6 in the input/output timing diagram shown in fig. 3a are selected.

In the first stage T1, Input is 1, RST1 is 0, CLK is 0, and CLKB is 1.

Since Input is equal to 1, the third switching transistor M3 and the fourth switching transistor M4 are both turned on. Since the third switching transistor M3 is turned on and supplies a signal of the Input signal terminal Input of a high potential to the first node a, and since both the gate and the drain of the third switching transistor M3 are connected to the Input signal terminal Input, and the voltage of the gate of the third switching transistor M3 and the voltage V of the Input signal terminal Input_InputEqual, gate-source voltage V between the gate of the third switching transistor M3 and its source_gs(M3) is greater than the threshold voltage V of the third switching transistor M3_th(M3), i.e. V_gs(M3)>V_th(M3) the third switching transistor M3 is in a conducting state and supplies the signal of the Input signal terminal Input to the first node a until the voltage V at which the first node a is at a high potential_A＝V_Input-V_th(M3), the third switching transistor M3 is turned off, so that the voltage at the first node A is high and the voltage V at the first node A is high_A＝V_Input-V_th(M3). Since the potential of the first node A is high, the first node A is connected to the first node BThe fifth switching transistor M5 is turned on and provides the low-level signal of the first clock signal terminal CLK to the driving signal Output terminal Output, so that the second capacitor C2 is charged, and the driving signal Output terminal Output is at a low level, i.e., the driving signal Output terminal Output outputs a low-level driving signal. Since the fourth switching transistor M4 is turned on and provides the low-level signal of the first reference signal terminal VSS1 to the second node B, the potential of the second node B is low. Since the potential of the second node B is low, the second switching transistor M2 and the sixth switching transistor M6 are both turned off. Since CLKB is equal to 1, the seventh switching transistor M7 is turned on and provides the low-level signal of the second reference signal terminal VSS2 to the driving signal Output terminal Output, further ensuring that the driving signal Output terminal Output is at a low level. Since RST1 is 0, first switching transistor M1 is turned off.

In the second stage T2, Input is 1, RST1 is 0, CLK is 1, and CLKB is 0.

Since Input is 1, the fourth switching transistor M4 is turned on. Since the fourth switching transistor M4 is turned on and provides the low-level signal of the first reference signal terminal VSS1 to the second node B, the potential of the second node B is low. Since CLK is equal to 1 and the potential of the second node B is low, the first capacitor C1 is charged, and the second switching transistor M2 and the sixth switching transistor M6 are both turned off. Although the gate of the third switching transistor M3 is connected to the Input signal terminal Input, the first node a is maintained to have the voltage V due to the bootstrap of the second capacitor C2_A＝V_Input-V_th(M3), the third switching transistor M3 is turned off, so that the first node a is in a floating state. Since the potential of the first node a is maintained at the high potential, the fifth switching transistor M5 is turned on and supplies the signal of the first clock signal terminal CLK at the high potential to the driving signal Output terminal Output, and thus the potential of the driving signal Output terminal Output is at the high potential, that is, the driving signal Output terminal Output outputs the driving signal at the high potential. Due to the bootstrap action of the second capacitor C2, in order to keep the voltage difference between the first node a and the driving signal Output terminal stable, the first node is enabledThe potential at the point a is further pulled high, ensuring that the fifth switching transistor M5 is fully turned on to supply the signal of the first clock signal terminal CLK at the high potential to the driving signal Output terminal Output. Since RST1 is 0, first switching transistor M1 is turned off. Since CLKB is 0, the seventh switching transistor M7 is turned off.

In the third stage T3, Input is 0, RST1 is 0, CLK is 1, and CLKB is 0.

Since Input is equal to 0, the third switching transistor M3 and the fourth switching transistor M4 are both turned off, and thus the first node a and the second node B are both in a floating state. Since the first node a is in a floating state, the voltage difference between the two ends of the second capacitor C2 can be kept stable due to the bootstrap effect of the second capacitor C2, and therefore the first node a can be kept at the voltage V_A＝V_Input-V_th(M3). Since the potential of the first node a is maintained at the high potential, the fifth switching transistor M5 is turned on and supplies the signal of the first clock signal terminal CLK at the high potential to the driving signal Output terminal Output, and thus the potential of the driving signal Output terminal Output is at the high potential, that is, the driving signal Output terminal Output outputs the driving signal at the high potential. Due to the bootstrap action of the second capacitor C2, in order to keep the voltage difference between the first node a and the driving signal Output terminal stable, the potential of the first node a is further pulled high, and it is ensured that the fifth switching transistor M5 is fully turned on to provide the signal of the first clock signal terminal CLK with high potential to the driving signal Output terminal Output. The voltage difference between the two terminals can be kept stable due to the bootstrap effect of the first capacitor C1, so that the potential of the second node B is kept low. Since the potential of the second node B is low, the second switching transistor M2 and the sixth switching transistor M6 are both turned off. Since RST1 is 0, first switching transistor M1 is turned off. Since CLKB is 0, the seventh switching transistor M7 is turned off.

In the fourth stage T4, Input is 0, RST1 is 1, CLK is 0, and CLKB is 1.

Since Input is 0, both the third switching transistor M3 and the fourth switching transistor M4 are turned off. Due to RST1 equals 1, so the first switching transistor M1 is turned on. Since the first switching transistor M1 is turned on, the first node a and the second node B are turned on, so that the potential of the second node B is high. Since the potential of the second node B is high, the second switching transistor M2 is turned on and supplies the signal of the first reference signal terminal VSS1 with a low potential to the first node a, and the gate and the drain of the second switching transistor M2 are connected to form a diode structure, so that the high potential of the first node a is discharged through the second switching transistor M2 forming a diode structure until the gate-source voltage V of the second switching transistor M2 is high_gs(M2) is equal to the threshold voltage V of the second switching transistor M2_th(M2), i.e. V_gs(M2)＝V_th(M2) the second switch transistor M2 is turned off, so that the first node A and the second node B both have the voltage V_th(M2) low potential. Since the potential of the first node a is low, the fifth switching transistor M5 is turned off. Since the potential of the second node B is low, the second switching transistor M2 and the sixth switching transistor M6 are both turned off. Since CLKB is equal to 1, the seventh switching transistor M7 is turned on and provides the low-level signal of the second reference signal terminal VSS2 to the driving signal Output terminal Output, so that the driving signal Output terminal Output is at a low level, that is, the driving signal Output terminal Output outputs the low-level driving signal. Since the first node A and the second node B both have the voltage V_th(M2) so that the voltage difference across the first capacitor C1 is V_th(M2) and a voltage difference V between the two ends of the second capacitor C2_th(M2)。

In the fifth stage T5, Input is 0, RST1 is 0, CLK is 1, and CLKB is 0.

Since Input is equal to 0, the third switching transistor M3 and the fourth switching transistor M4 are both turned off, and thus the first node a and the second node B are both in a floating state. Since the second node B is in a floating state and CLK is 1, the voltage difference between the two ends of the second node B is stable due to the bootstrap effect of the first capacitor C1, and therefore the potential of the second node B is pulled high to have the voltage V_th(M2)+V_compSo that the potential of the second node B is high. Since the potential of the second node B is high, the second switching transistor M2 and the sixth switching transistor M6 are both turned on. Since the second switching transistor M2 is turned on and supplies the signal of the first reference signal terminal VSS1, which is low, to the first node a, the first node a is low, and since the first node a is low, the fifth switching transistor M5 is turned off. Since the sixth switching transistor M6 is turned on and provides the low-level signal of the second reference signal terminal VSS2 to the driving signal Output terminal Output, the driving signal Output terminal Output is at a low level, that is, the driving signal Output terminal Output outputs the low-level driving signal. Since RST1 is 0, first switching transistor M1 is turned off. Since CLKB is 0, the seventh switching transistor M7 is turned off.

In the sixth stage T6, Input is 0, RST1 is 0, CLK is 0, and CLKB is 1.

Since Input is equal to 0, the third switching transistor M3 and the fourth switching transistor M4 are both turned off, and thus the first node a and the second node B are both in a floating state. Since the second node B is in a floating state and CLK is 0, and the first capacitor C1 is bootstrapped, the voltage difference between the two ends is kept stable, so the potential of the second node B has a voltage V_th(M2), the potential of the second node B is low, and the second switching transistor M2 and the sixth switching transistor M6 are both turned off. Since CLKB is equal to 1, the seventh switching transistor M7 is turned on and provides the low-level signal of the second reference signal terminal VSS2 to the driving signal Output terminal Output, so that the driving signal Output terminal Output is at a low level, that is, the driving signal Output terminal Output outputs the low-level driving signal. Since RST1 is 0, first switching transistor M1 is turned off.

In the shift register provided in the embodiment of the invention, after the sixth stage T6, the operation processes of the fifth stage T5 and the sixth stage T6 are repeated until the next frame starts.

Example II,

The operation process of the shift register shown in fig. 2b is described by taking the structure of the shift register as an example, wherein in the shift register shown in fig. 2b, all the switch transistors are N-type switch transistors, and each N-type switch transistor is turned on under the action of a high potential and is turned off under the action of a low potential; the potential of the first reference signal terminal VSS1 is low, and the corresponding input/output timing diagram is shown in fig. 3b, specifically, six stages, i.e., the first stage T1, the second stage T2, the third stage T3, the fourth stage T4, the fifth stage T5 and the sixth stage T6, in the input/output timing diagram shown in fig. 3b are selected.

In the first stage T1, Input is 1, RST1 is 0, RST2 is 0, CLK is 0, and CLKB is 1. Since RST2 is 0, eighth switching transistor M8 is turned off. The remaining specific working process is the same as the working process of the first stage T1 in the first embodiment, and is not described herein again.

In the second stage T2, Input is 1, RST1 is 0, RST2 is 0, CLK is 1, and CLKB is 0. Since RST2 is 0, eighth switching transistor M8 is turned off. The remaining specific working process is the same as the working process of the second stage T2 in the first embodiment, and is not described herein again.

In the third stage T3, Input is 0, RST1 is 0, RST2 is 0, CLK is 1, and CLKB is 0. Since RST2 is 0, eighth switching transistor M8 is turned off. The remaining specific working process is the same as the working process of the third stage T3 in the first embodiment, and is not described herein again.

In the fourth stage T4, during the first half period, Input is 0, RST1 is 1, RST2 is 0, CLK is 0, and CLKB is 1. Since RST2 is 0, eighth switching transistor M8 is turned off. The remaining specific working process is the same as the working process of the fourth stage T4 in the first embodiment, and is not described herein again.

In the latter half, Input is 0, RST1 is 1, RST2 is 1, CLK is 0, and CLKB is 1. Since RST2 is equal to 1, the eighth switching transistor M8 is turned on and provides the low-level signal of the second reference signal terminal VSS2 to the driving signal Output terminal Output, which further ensures that the driving signal Output terminal Output is at a low level. The remaining specific working process is the same as the working process of the fourth stage T4 in the first embodiment, and is not described herein again.

In the fifth stage T5, during the first half period, Input is 0, RST1 is 0, RST2 is 1, CLK is 1, and CLKB is 0. Since RST2 is equal to 1, the eighth switching transistor M8 is turned on and provides the low-level signal of the second reference signal terminal VSS2 to the driving signal Output terminal Output, which further ensures that the driving signal Output terminal Output is at a low level. The remaining specific working process is the same as the working process of the fifth stage T5 in the first embodiment, and is not described herein again.

In the latter half, Input is 0, RST1 is 0, RST2 is 0, CLK is 1, and CLKB is 0. Since RST2 is 0, eighth switching transistor M8 is turned off. The remaining specific working process is the same as the working process of the fifth stage T5 in the first embodiment, and is not described herein again.

In the sixth stage T6, Input is 0, RST1 is 0, RST2 is 0, CLK is 0, and CLKB is 1. Since RST2 is 0, eighth switching transistor M8 is turned off. The remaining specific working process is the same as the working process of the sixth stage T6 in the first embodiment, and is not described herein again.

In the shift register provided in the embodiment of the present invention, after the sixth phase T6, the working processes of the second half period of the fifth phase T5 and the sixth phase T6 are repeatedly performed until the next frame starts.

In the shift register provided in the embodiment of the invention, in the fourth stage, since the second switching transistor M2 forming the diode structure can write the threshold voltage Vth (M2) of the second switching transistor M2 into the second node, after the potential of the second node is pulled high by the bootstrap action of the first capacitor in the fifth stage, the voltage of the second node is also pulled high by the voltage V_compSo that the voltage at the second node is: v_th(M2)+V_compSo that Vgs (M2) of the second switching transistor M2 becomes V_compThereby keeping the second switching transistor in a conductive state all the time to lower the potentialThe signal of the first reference signal end is provided for the first node, the potential of the first node is kept to be a low potential, and therefore output noise of the driving signal output end is reduced, abnormal display is avoided, and display stability of the display device is improved.

In practical implementation, in the shift register provided in the embodiment of the present invention, in the fourth stage of the operation process of the shift register, the voltage V is set_compSatisfies the formula:wherein V_CLKRepresenting the voltage amplitude of the first clock signal terminal, c1 represents the capacitance value of the first capacitor, Cpd ═ c1+ Cgs (M1) + Cgs (M2) + Cgd (M2) + Cgd (M4) + Cgs (M6) + Cgd (M6), Cgs (M1) represents the parasitic capacitance between the gate and the source of the first switching transistor, Cgs (M2) represents the parasitic capacitance between the gate and the source of the second switching transistor, Cgd (M2) represents the parasitic capacitance between the gate and the drain of the second switching transistor, Cgd (M4) represents the parasitic capacitance between the gate and the drain of the fourth switching transistor, Cgs (M6) represents the parasitic capacitance between the gate and the source of the sixth switching transistor, and Cgd (M6) represents the parasitic capacitance between the gate and the drain of the sixth switching transistor.

Taking the specific structure of the shift register shown in fig. 2b and the voltage step size of 2V as an example, the relationship that the threshold voltage Vth (M2) of the second switching transistor M2 shifts to the right corresponding to the voltage of the second node during operation is simulated. The simulation result of the shift of the threshold voltage Vth (M2) of the second switching transistor M2 to the right is shown in fig. 4a, where the abscissa represents the voltage and the ordinate represents the current. Here, S1, S2, S3, S4, S5, S6, and S7 represent simulation curves in which the threshold voltage Vth (M2) of the second switching transistor M2 shifts rightward by 0V, 2V, 4V, 6V, 8V, 10V, and 12V, respectively. The simulation graphs of the voltages of the first node and the second node corresponding to S1-S7 in fig. 4a are shown in fig. 4b, wherein the abscissa represents time and the ordinate represents voltage. Wherein S0 represents the voltage of the first node when the threshold voltage Vth (M2) of the second switching transistor M2 shifts 0V, 2V, 4V, 6V, 8V, 10V, and 12V to the right. S1 '-S7' represent voltages of the second node when the threshold voltage Vth (M2) of the second switching transistor M2 shifts rightward by 0V, 2V, 4V, 6V, 8V, 10V, and 12V, respectively. As can be seen from fig. 4a and 4b, as the threshold voltage Vth (M2) of the second switching transistor M2 increases, the voltage of the second node also increases accordingly, so that the drift of the threshold voltage Vth (M2) of the second switching transistor M2 can be compensated.

Based on the same inventive concept, an embodiment of the present invention further provides a driving method of any one of the shift registers provided by the present invention, as shown in fig. 5, including: a first stage, a second stage, a third stage, a fourth stage, a fifth stage and a sixth stage; wherein,

s501, in the first stage, an input module provides a signal of an input signal end to a first node under the control of the input signal end, and provides a signal of a first reference signal end to a second node under the control of the input signal end; the first output module provides a signal of a first clock signal end to the driving signal output end under the control of a signal of a first node; the second output module provides a signal of a second reference signal end to the driving signal output end under the control of a second clock signal end;

s502, in the second stage, the first output module provides the signal of the first clock signal end to the driving signal output end under the control of the signal of the first node, and keeps the voltage difference between the first node and the driving signal output end stable when the first node is in a floating state; the input module provides a signal of the first reference signal end to the second node under the control of the input signal end;

s503, in the third stage, the first output module provides the signal of the first clock signal end to the driving signal output end under the control of the signal of the first node, and keeps the voltage difference between the first node and the driving signal output end stable when the first node is in the floating state; when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal end stable;

s504, in the fourth stage, the threshold voltage writing module conducts the first node and the second node under the control of the first reset signal end, and provides the signal of the first reference signal end to the first node under the control of the signal of the second node; the second output module provides a signal of a second reference signal end to the driving signal output end under the control of a second clock signal end;

s505, in the fifth stage, when the second node is in a floating state, the voltage coupling module keeps a voltage difference between the second node and the first clock signal end stable; the second output module provides a signal of the second reference signal end to the driving signal output end under the control of a signal of a second node; the threshold voltage writing module provides a signal of a first reference signal end to the first node under the control of a signal of the second node;

s506, in the sixth stage, when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal end stable; the second output module provides the signal of the second reference signal end to the driving signal output end under the control of the second clock signal end.

The driving method provided by the embodiment of the invention can compensate the voltage of the second node to ensure that the potential of the first node is in a stable state of an invalid potential after the shift register outputs the effective pulse signal of the driving signal, thereby reducing the output noise of the output end of the driving signal and further avoiding the display from being abnormal.

Further, in the above driving method provided by the embodiment of the present invention, when each shift register further includes a potential stabilizing module,

the fourth stage specifically includes: in the first half time period, the threshold voltage writing module conducts the first node and the second node under the control of the first reset signal terminal, and provides a signal of the first reference signal terminal to the first node under the control of a signal of the second node; the second output module provides a signal of a second reference signal end to the driving signal output end under the control of a second clock signal end;

in the second half period, the threshold voltage writing module conducts the first node and the second node under the control of the first reset signal end, and provides a signal of the first reference signal end to the first node under the control of a signal of the second node; the second output module provides a signal of a second reference signal end to the driving signal output end under the control of a second clock signal end; the potential stabilizing module supplies a signal of a second reference signal end to the driving signal output end under the control of a second reset signal end;

the fifth stage specifically comprises: in the first half time period, when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal end stable; the second output module provides a signal of the second reference signal end to the driving signal output end under the control of a signal of a second node; the threshold voltage writing module provides a signal of a first reference signal end to the first node under the control of a signal of the second node; the potential stabilizing module supplies a signal of a second reference signal end to the driving signal output end under the control of a second reset signal end;

in the second half period, when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal end stable; the second output module provides a signal of the second reference signal end to the driving signal output end under the control of a signal of a second node; the threshold voltage writing module provides a signal of the first reference signal terminal to the first node under the control of a signal of the second node.

Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 6, including: n cascaded shift registers SR (1), SR (2), SR (3) … SR (N), SR (N-1), SR (N +1) provided by the embodiments of the present invention; wherein N is an integer greater than or equal to 4;

an Input signal end Input of the 1 st-stage shift register SR (1) is connected with a first frame trigger signal end STV 1;

an Input signal end Input of the 2 nd-stage shift register SR (2) is connected with a second frame trigger signal end STV 2;

an Input signal end Input of the nth stage shift register SR (n) is respectively connected with a driving signal Output end Output of the n-2 th stage shift register SR (n-2);

the first reset signal end RST1 of the (n-2) th stage shift register SR (n-2) is respectively connected with the driving signal Output end Output of the (n +1) th stage shift register SR (n + 1); wherein N is an integer greater than or equal to 3 and less than or equal to N-1.

Further, in a specific implementation, in the driving method provided in the embodiment of the present invention, when each shift register further includes a potential stabilizing module, the second reset signal terminal of the n-2 th stage shift register is respectively connected to the driving signal output terminal of the n +2 th stage shift register.

Further, in a specific implementation, in the driving method provided in the embodiment of the present invention, the first reference signal terminal and the second reference signal terminal are the same signal terminal.

Specifically, the specific structure of each shift register in the gate driving circuit is the same as that of the shift register of the present invention in function and structure, and repeated descriptions are omitted. The gate driving circuit may be applied to a liquid crystal display panel, and may also be applied to an organic electroluminescent display panel, which is not limited herein.

Specifically, in the gate driving circuit provided in the embodiment of the present invention, as shown in fig. 6, the first clock signal terminal CLK of the 6k +1 th stage shift register and the second clock signal terminal CLKB of the 6k +4 th stage shift register are both connected to the same clock terminal, i.e., the first clock terminal ck 1; the first clock signal end CLK of the 6k +2 th stage shift register and the second clock signal end CLKB of the 6k +5 th stage shift register are both connected with the same clock end, namely a second clock end ck 2; the first clock signal end CLK of the 6k +3 th stage shift register and the second clock signal end CLKB of the 6k +6 th stage shift register are both connected to the same clock end, i.e. the third clock end ck 3; the first clock signal terminal CLK of the 6k +4 th stage shift register and the second clock signal terminal CLKB of the 6k +1 th stage shift register are both connected to the same clock terminal, i.e., the fourth clock terminal ck 4; the first clock signal terminal CLK of the 6k +5 th stage shift register and the second clock signal terminal CLKB of the 6k +2 th stage shift register are both connected to the same clock terminal, i.e., a fifth clock terminal ck 5; the first clock signal end CLK of the 6k +6 th stage shift register and the second clock signal end CLKB of the 6k +3 th stage shift register are both connected to the same clock end, i.e., the sixth clock end ck 6; wherein k is an integer greater than or equal to 0.

Based on the same inventive concept, embodiments of the present invention further provide a display device, including any one of the gate driving circuits provided in embodiments of the present invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention. The implementation of the display device can refer to the above-mentioned embodiments of the shift register, and repeated descriptions are omitted.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A shift register, comprising: the device comprises an input module, a voltage coupling module, a threshold voltage writing module, a first output module and a second output module; wherein,

the input module is respectively connected with an input signal end, a first reference signal end, a first node and a second node; the input module is used for providing a signal of the input signal terminal to the first node under the control of the input signal terminal and providing a first reference signal of the first reference signal terminal to the second node under the control of the input signal terminal;

the threshold voltage writing module is respectively connected with a first reset signal end, the first reference signal end, the first node and the second node; the threshold voltage writing module is used for conducting the first node and the second node under the control of the first reset signal terminal, and providing a first reference signal of the first reference signal terminal to the first node under the control of a signal of the second node;

the second output module is respectively connected with a second clock signal end, a second reference signal end, the second node and the driving signal output end; the second output module is configured to provide a second reference signal of the second reference signal terminal to the driving signal output terminal under the control of the signal of the second node, and provide a second reference signal of the second reference signal terminal to the driving signal output terminal under the control of the second clock signal terminal.

2. The shift register of claim 1, wherein the voltage coupling module comprises: a first capacitor; wherein,

3. The shift register of claim 1, wherein the threshold voltage write module comprises: a first switching transistor and a second switching transistor; wherein,

4. The shift register of claim 1, wherein the input module comprises: a third switching transistor and a fourth switching transistor; wherein,

5. The shift register of claim 1, wherein the first output module comprises: a fifth switching transistor and a second capacitor; wherein,

6. The shift register of claim 1, wherein the second output module comprises: a sixth switching transistor and a seventh switching transistor; wherein,

7. The shift register of any one of claims 1-6, further comprising: a potential stabilization module; wherein,

8. The shift register of claim 7, wherein the potential stabilization module comprises: an eighth switching transistor; wherein,

9. A gate drive circuit comprising a cascade of N shift registers according to any one of claims 1 to 8; wherein N is an integer greater than or equal to 4;

10. A display device comprising the gate driver circuit according to claim 9.

11. A driving method of a shift register according to any one of claims 1 to 8, comprising: a first stage, a second stage, a third stage, a fourth stage, a fifth stage and a sixth stage; wherein,