CN104217693A - Shift register, display device, gate drive circuit and drive method thereof - Google Patents

Shift register, display device, gate drive circuit and drive method thereof Download PDF

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Publication number
CN104217693A
CN104217693A CN201410447285.3A CN201410447285A CN104217693A CN 104217693 A CN104217693 A CN 104217693A CN 201410447285 A CN201410447285 A CN 201410447285A CN 104217693 A CN104217693 A CN 104217693A
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China
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film transistor
tft
thin film
connects
node
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CN201410447285.3A
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Chinese (zh)
Inventor
郝学光
李成
安星俊
柳奉烈
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to CN201410447285.3A priority Critical patent/CN104217693A/en
Publication of CN104217693A publication Critical patent/CN104217693A/en

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Abstract

An embodiment of the invention discloses a shift register, a display device, a gate drive circuit and a drive method thereof and relates to the technical field of display. The shift register can suppress noise and reduce power consumption of the gate drive circuit. The shift register comprises an input module, a first node pull-up module, a first node pull-down module, a second node pull-up module, a second node pull-down module and an output module. The input module is connected with a signal input end and used for inputting signals to a first node which serves as a pull-up node; the first node pull-up module is connected with a first clock signal terminal and used for maintaining voltage of the first node at high level; the first node pull-down module is connected with a low-voltage signal terminal and used for maintaining the voltage of the first node at low level; the second node pull-up module is connected with the output module and used for maintaining voltage of a second node which serves as a pull-down node at high level; the second node pull-down module is connected with the low-voltage signal terminal and used for maintaining the voltage of the second node at low level; and the output module is connected with the first clock signal terminal and used for providing a first clock signal to an output terminal.

Description

Shift register, gate driver circuit and driving method thereof, display device

Technical field

The present invention relates to display field, particularly relate to a kind of shift register, gate driver circuit and driving method thereof, display device.

Background technology

The driver of Thin Film Transistor-LCD comprises gate driver circuit, and particularly, gate driver circuit comprises the shift register of multiple mutual cascade, and every grade of shift register is all connected on corresponding grid line, to export gate drive signal driven grid line.The cascade system of multiple shift register is: when the input end of preceding shift register is connected to the output terminal of upper level shift register, and the output terminal of next stage shift register is connected to the reset terminal when preceding shift register.

In prior art, the every one-level shift register in gate driver circuit has structure as shown in Figure 1.Inventor finds, the power consumption comprising the gate driver circuit of shift register is as shown in Figure 1 higher, easily cause noise, need upper and lower two virtual shift registers normally to work simultaneously, and the signal that virtual shift register arranges difficulty and the gate driver circuit adding the wiring of gate driver circuit exports, thus further increase the power consumption of gate driver circuit.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of shift register, gate driver circuit and driving method thereof, display device, can restraint speckle, and reduces the power consumption of gate driver circuit.

For solving the problems of the technologies described above, embodiments providing a kind of shift register, adopting following technical scheme:

A kind of shift register comprises load module, output module, first node pull-up module, the drop-down module of first node, Section Point pull-up module and the drop-down module of Section Point;

Described load module connection signal input end, for for the first node input signal as pull-up node;

Described first node pull-up model calling first clock signal terminal is high level for maintaining the voltage of described first node;

Described first node drop-down model calling low voltage signal end is low level for maintaining the voltage of described first node;

Output module described in described Section Point pull-up model calling is high level for the voltage maintained for the Section Point as pull-down node;

Low voltage signal end described in the drop-down model calling of described Section Point is low level for maintaining the voltage of described Section Point;

Described output module connects described first clock signal terminal, and the first clock signal is supplied to lead-out terminal.

Described load module comprises the first film transistor and the second thin film transistor (TFT);

The grid of described the first film transistor connects initialize signal input end, and the drain electrode of described the first film transistor connects the first direct current signal input end, and the source electrode of described the first film transistor connects described first node;

The grid of described second thin film transistor (TFT) connects reset signal input end, and the drain electrode of described second thin film transistor (TFT) connects the second direct current signal input end, and the source electrode of described second thin film transistor (TFT) connects described first node.

Described first node pull-up module comprises the first electric capacity, and one end of described first electric capacity connects described first node, and the other end of described first electric capacity connects described output module.

The drop-down module of described first node comprises the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT), the grid of described 3rd thin film transistor (TFT) connects described Section Point, the drain electrode of described 3rd thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 3rd thin film transistor (TFT) connects described first node;

The grid of described 4th thin film transistor (TFT) connects described Section Point, and the drain electrode of described 4th thin film transistor (TFT) connects described Section Point, and the source electrode of described 4th thin film transistor (TFT) connects described low voltage signal end.

Described Section Point pull-up module comprises the second electric capacity and the 5th thin film transistor (TFT);

One end of described second electric capacity connects described output module, and the other end of described second electric capacity connects described low voltage signal end;

The grid of described 5th thin film transistor (TFT) is connected second clock signal end with drain electrode, and the source electrode of described 5th thin film transistor (TFT) connects described Section Point.

The drop-down module of described Section Point comprises the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT);

The grid of described 6th thin film transistor (TFT) connects described pull-up node, and the drain electrode of described 6th thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 6th thin film transistor (TFT) connects the drop-down module of described first node;

The grid of described 7th thin film transistor (TFT) connects described lead-out terminal, and the drain electrode of described 7th thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 7th thin film transistor (TFT) connects the drop-down module of described first node;

The grid of described 8th thin film transistor (TFT) connects described output module, and the drain electrode of described 8th thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 8th thin film transistor (TFT) connects described Section Point.

Described output module comprises the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT);

The grid of described 9th thin film transistor (TFT) connects described Section Point, and the drain electrode of described 9th thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 9th thin film transistor (TFT) connects described first node pull-up module;

The grid of described tenth thin film transistor (TFT) connects described first node, and the drain electrode of described tenth thin film transistor (TFT) connects described first clock signal terminal, and the source electrode of described tenth thin film transistor (TFT) connects described first node pull-up module.

The embodiment of the present invention additionally provides a kind of gate driver circuit, adopts following technical scheme:

This gate driver circuit comprises the shift register multiple as above of mutual cascade, except first order shift register and afterbody shift register, the initialize signal input end of every one-level shift register all connects the lead-out terminal of the upper level shift register of self, the reset signal input end of every one-level shift register cell all connects the lead-out terminal of the next stage shift register of self, the lead-out terminal of every one-level shift register connects self the reset signal input end of upper level shift register and the initialize signal input end of the next stage shift register of self.

Embodiments provide a kind of shift register and gate driver circuit, wherein, shift register comprises: load module, output module, first node pull-up module, the drop-down module of first node, Section Point pull-up module and the drop-down module of Section Point, load module connection signal input end, for for the first node input signal as pull-up node; First node pull-up model calling first clock signal terminal is high level for maintaining the voltage of first node; First node drop-down model calling low voltage signal end is low level for maintaining the voltage of first node; Section Point pull-up model calling output module is high level for the voltage maintained for the Section Point as pull-down node; Section Point drop-down model calling low voltage signal end is low level for maintaining the voltage of Section Point; Output module connects the first clock signal terminal, and the first clock signal is supplied to lead-out terminal.This shift register is discharged to first node by first node drop-down unit before next frame is opened, and effectively avoids the generation of first node place noise, is discharged by output module to lead-out terminal, effectively avoids the generation of lead-out terminal place noise; Meanwhile, the current potential of Section Point can both be drawn high by each high level signal of second clock signal end, greatly reduces the power consumption of gate driver circuit.In addition, because gate driver circuit comprises the shift register multiple as above of mutual cascade, do not need to arrange virtual shift register again, effectively can reduce wiring space, and reduce further the power consumption of gate driver circuit.

In addition, the embodiment of the present invention additionally provides a kind of display device, and this display device comprises above-described gate driver circuit.

In order to solve the problems of the technologies described above further, the embodiment of the present invention additionally provides a kind of driving method of gate driver circuit, adopts following technical scheme:

A kind of driving method of gate driver circuit comprises:

First stage, first direct current signal input end and initialize signal input end export high level, first clock signal terminal, second clock signal end and reset signal input end output low level, the first film transistor turns, first node voltage raises, the first capacitor charging, 6th thin film transistor (TFT) conducting, Section Point current potential is dragged down, the tenth thin film transistor (TFT) conducting, and lead-out terminal current potential is dragged down;

Subordinate phase, described first direct current signal input end and described first clock signal terminal export high level, described initialize signal input end, described second clock signal end and described reset signal input end output low level, described the first film transistor cutoff, the voltage of described first node raises, the tenth thin film transistor (TFT) conducting, and described lead-out terminal exports high level, described 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT) conducting, described Section Point current potential is dragged down;

Phase III, described first direct current signal input end, described second clock signal end and described reset signal input end export high level, described first clock signal terminal and described initialize signal input end output low level, 5th thin film transistor (TFT) conducting, the second capacitor charging, described Section Point current potential is driven high, 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT) conducting, described first node current potential is dragged down, the 9th thin film transistor (TFT) conducting, and described lead-out terminal current potential is dragged down.

Embodiments provide a kind of driving method of gate driver circuit, this driving method comprises first stage as above, subordinate phase and phase III, wherein, before next frame is opened, 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT) conducting, first node is discharged, effectively avoid the generation of first node place noise, second electric capacity makes Section Point be in noble potential, the conducting all the time before next frame starts of 9th thin film transistor (TFT), make lead-out terminal be in electronegative potential, effectively avoid the generation of lead-out terminal place noise; Meanwhile, the current potential of Section Point can both be drawn high by each high level signal of second clock signal end, greatly reduces the power consumption of gate driver circuit.In addition, because gate driver circuit comprises the shift register multiple as above of mutual cascade, do not need to arrange virtual shift register again, effectively can reduce wiring space, and reduce further the power consumption of gate driver circuit.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the schematic diagram of shift register of the prior art;

Fig. 2 is the schematic diagram of the shift register in the embodiment of the present invention;

Fig. 3 is the schematic diagram of the gate driver circuit in the embodiment of the present invention;

Sequential chart when Fig. 4 is the gate driver circuit forward scan in the embodiment of the present invention;

Output waveform figure when Fig. 5 is the gate driver circuit forward scan in the embodiment of the present invention;

Sequential chart when Fig. 6 is the gate driver circuit reverse scan in the embodiment of the present invention;

Output waveform figure when Fig. 7 is the gate driver circuit reverse scan in the embodiment of the present invention.

Description of reference numerals:

1-load module; 2-first node pull-up module; The drop-down module of 3-first node;

4-Section Point pull-up module; The drop-down module of 5-Section Point; 6-output module.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

Embodiment one

Embodiments provide a kind of shift register, can restraint speckle, and reduce the power consumption of gate driver circuit.

As shown in Figure 2, this shift register comprises load module 1, first node pull-up module 2, the drop-down module of first node 3, Section Point pull-up module 4, the drop-down module 5 of Section Point and output module 6.

Particularly, load module 1 connection signal input end, for for the first node PU input signal as pull-up node.Signal input part comprises the first direct current signal input end CN, the second direct current signal input end CNB, initialize signal input end STV_U and reset signal input end Reset.

First node pull-up module 2 connects the first clock signal terminal, is high level for maintaining the voltage of first node PU.

The drop-down module 3 of first node connects low voltage signal end VGL, is low level for maintaining the voltage of first node PU.

Section Point pull-up module 4 connects output module 6, is high level for the voltage maintained for the Section Point PD as pull-down node.

The drop-down module 5 of Section Point connects low voltage signal end VGL, is low level for maintaining the voltage of Section Point PD.

Output module 6 connects the first clock signal terminal CK, and the first clock signal is supplied to lead-out terminal OUT_N.

Exemplarily, as shown in Figure 2, load module 1 comprises the first film transistor M1 and the second thin film transistor (TFT) M2.

Wherein, the grid of the first film transistor M1 connects initialize signal input end STV_U, and the drain electrode of the first film transistor M1 connects the first direct current signal input end CN, and the source electrode of the first film transistor M1 connects first node PU.

The grid of the second thin film transistor (TFT) M2 connects reset signal input end Reset, and the drain electrode of the second thin film transistor (TFT) M2 connects the second direct current signal input end CNB, and the source electrode of the second thin film transistor (TFT) M2 connects first node PU.

First node pull-up module 2 comprises the first electric capacity C1, and one end of the first electric capacity C1 connects first node PU, and the other end of the first electric capacity C1 connects output module 6.

The drop-down module 3 of first node comprises the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4.

Wherein, the grid of the 3rd thin film transistor (TFT) M3 connects Section Point PD, and the drain electrode of the 3rd thin film transistor (TFT) M3 connects low voltage signal end VGL, and the source electrode of the 3rd thin film transistor (TFT) M3 connects first node PU.

The grid of the 4th thin film transistor (TFT) M4 connects Section Point PD, and the drain electrode of the 4th thin film transistor (TFT) M4 connects Section Point PD, and the source electrode of the 4th thin film transistor (TFT) M4 connects low voltage signal end VGL.

Section Point pull-up module 4 comprises the second electric capacity and the 5th thin film transistor (TFT) M5.

Wherein, one end of the second electric capacity connects the other end connection low voltage signal end VGL of output module 6, second electric capacity C2.

The grid of the 5th thin film transistor (TFT) M5 is connected second clock signal end CKB with drain electrode, and the source electrode of the 5th thin film transistor (TFT) M5 connects Section Point PD.

The drop-down module 5 of Section Point comprises the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7 and the 8th thin film transistor (TFT) M8.

Wherein, the grid of the 6th thin film transistor (TFT) M6 connects pull-up node PU, and the drain electrode of the 6th thin film transistor (TFT) M6 connects low voltage signal end VGL, and the source electrode of the 6th thin film transistor (TFT) M6 connects the drop-down module 3 of first node.

The grid of the 7th thin film transistor (TFT) M7 connects lead-out terminal OUT_N, and the drain electrode of the 7th thin film transistor (TFT) M7 connects low voltage signal end VGL, and the source electrode of the 7th thin film transistor (TFT) M7 connects the drop-down module 3 of first node.

The grid of the 8th thin film transistor (TFT) M8 connects the drain electrode connection low voltage signal end VGL of output module the 6, eight thin film transistor (TFT) M8, and the source electrode of the 8th thin film transistor (TFT) M8 connects Section Point PD.

Output module 6 comprises the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10.

Wherein, the grid of the 9th thin film transistor (TFT) M9 connects Section Point PD, and the drain electrode of the 9th thin film transistor (TFT) M9 connects low voltage signal end VGL, and the source electrode of the 9th thin film transistor (TFT) M9 connects first node pull-up module 2.

The grid of the tenth thin film transistor (TFT) M10 connects first node PU, and the drain electrode of the tenth thin film transistor (TFT) M10 connects the first clock signal terminal CK, and the source electrode of the tenth thin film transistor (TFT) M10 connects first node pull-up module 2.

It should be noted that, above-mentioned all thin film transistor (TFT)s are N-type TFT or P-type TFT, and in the embodiment of the present invention, preferred all thin film transistor (TFT)s are N-type TFT.

Embodiments provide a kind of shift register, this shift register comprises: load module, output module, first node pull-up module, the drop-down module of first node, Section Point pull-up module and the drop-down module of Section Point, wherein, load module connection signal input end, for for the first node input signal as pull-up node; First node pull-up model calling first clock signal terminal is high level for maintaining the voltage of first node; First node drop-down model calling low voltage signal end is low level for maintaining the voltage of first node; Section Point pull-up model calling output module is high level for the voltage maintained for the Section Point as pull-down node; Section Point drop-down model calling low voltage signal end is low level for maintaining the voltage of Section Point; Output module connects the first clock signal terminal, and the first clock signal is supplied to lead-out terminal.In this shift register, before next frame is opened, by first node drop-down unit, continuous discharge is carried out to first node, effectively avoid the generation of first node place noise, by output module, continuous discharge is carried out to lead-out terminal, effectively avoid the generation of lead-out terminal place noise; Meanwhile, the current potential of Section Point can both be drawn high by each high level signal of second clock signal, greatly reduces the power consumption of gate driver circuit.

Embodiment two

Embodiments provide a kind of gate driver circuit, can restraint speckle, and reduce the power consumption of gate driver circuit.

As shown in Figure 3, this gate driver circuit comprises the shift register multiple as above of mutual cascade, except first order shift register and afterbody shift register, the initialize signal input end STV_U of every one-level shift register all connects the lead-out terminal of the upper level shift register of self, the reset signal input end of every one-level shift register cell all connects the lead-out terminal OUT_N of the next stage shift register of self, the lead-out terminal OUT_N of every one-level shift register connects the reset signal input end Reset of the upper level shift register of self and the initialize signal input end STV_U of the next stage shift register of self.The gate driver circuit with as above structure can realize bilateral scanning.

Embodiments provide a kind of gate driver circuit, this gate driver circuit comprises multiple shift registers as described in embodiment one of mutual cascade, in this gate driver circuit scanning process, by first node drop-down unit, first node is discharged before next frame is opened, effectively avoid the generation of first node place noise, by output module, lead-out terminal is discharged, effectively avoid the generation of lead-out terminal place noise; Meanwhile, the current potential of Section Point can both be drawn high by each high level signal of second clock signal end, greatly reduces the power consumption of gate driver circuit.In addition, because gate driver circuit comprises the shift register multiple as above of mutual cascade, do not need to arrange virtual shift register again, effectively can reduce wiring space, and reduce further the power consumption of gate driver circuit.

Be described below in conjunction with the driving method of accompanying drawing to the gate driver circuit that the embodiment of the present invention provides, wherein, the circuit of the shift register that gate driver circuit comprises as shown in Figure 3.

It should be noted that, when gate driver circuit scans, all thin film transistor (TFT)s are high level conducting, and low level is ended, and the first clock signal C K is contrary with the phase place of second clock signal CKB.

Particularly, when gate driver circuit forward scan (being scanned up to N level shift register from first order shift register), initialize signal is inputted by the initialize signal input end STV_U of first order shift register, as shown in Figure 4 and Figure 5, first stage S1, first direct current signal input end CN and initialize signal input end STV_U exports high level, first clock signal terminal CK, second clock signal end CKB and reset signal input end Reset output low level, make the first film transistor M1 conducting, first electric capacity C1 is charged, the voltage of first node PU raises, thus make the 6th thin film transistor (TFT) M6 conducting, Section Point PD is discharged by the 6th thin film transistor (TFT) M6, and then the current potential of Section Point PD is dragged down.Meanwhile, the tenth thin film transistor (TFT) M10 conducting, lead-out terminal OUT_N is discharged by the tenth thin film transistor (TFT) M10, and the current potential of lead-out terminal OUT_N is dragged down.

Subordinate phase S2, first direct current signal input end CN and the first clock signal terminal CK exports high level, initialize signal input end STV_U, second clock signal end CKB and reset signal input end Reset output low level, the first film transistor M1 is ended, due to the boot strap of the first electric capacity C1, the voltage of first node PU is made to continue to raise, and then make the tenth thin film transistor (TFT) M10 conducting, the signal that first clock signal terminal CK is exported can, by the tenth thin film transistor (TFT) M10, make lead-out terminal OUT_N export high level.Simultaneously, 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7 and the 8th thin film transistor (TFT) M8 conducting, Section Point PD is discharged by the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7 and the 8th thin film transistor (TFT) M8, and the current potential of Section Point PD is dragged down.

Phase III S3, first direct current signal input end CN, second clock signal end CKB and reset signal input end Reset export high level, first clock signal terminal CK and initialize signal input end STV_U output low level, make the 5th thin film transistor (TFT) M5 conducting, second electric capacity C2 charges, thus the current potential of Section Point PD is drawn high, and then make the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4 conducting, first node PU is discharged by the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4, and the current potential of first node PU is dragged down.Meanwhile, because the current potential of Section Point PD is high, the 9th thin film transistor (TFT) M9 conducting, lead-out terminal OUT_N is discharged by the 9th thin film transistor (TFT) M9, and the current potential of lead-out terminal OUT_N is dragged down.

When gate driver circuit reverse scan (being scanned up to first order shift register from N level shift register), the reset signal input end Reset of N level shift register holds and connects initialize signal input end STV_D, as shown in Figure 6 and Figure 7, first stage S1, second direct current signal input end CNB and initialize signal input end STV_D exports high level, first clock signal terminal CK, second clock signal end CKB and reset signal input end Reset output low level, make the second thin film transistor (TFT) M2 conducting, first electric capacity C1 is charged, the voltage of first node PU raises, thus make the 6th thin film transistor (TFT) M6 conducting, Section Point PD is discharged by the 6th thin film transistor (TFT) M6, and then the current potential of Section Point PD is dragged down.Meanwhile, the tenth thin film transistor (TFT) M10 conducting, lead-out terminal OUT_N is discharged by the tenth thin film transistor (TFT) M10, and the current potential of lead-out terminal OUT_N is dragged down.

Subordinate phase S2, second direct current signal input end CNB and the first clock signal terminal CK exports high level, initialize signal input end STV_D, second clock signal end CKB and reset signal input end Reset output low level, second thin film transistor (TFT) M2 is ended, due to the boot strap of the first electric capacity C1, the voltage of first node PU is made to continue to raise, and then make the tenth thin film transistor (TFT) M10 conducting, the signal that first clock signal terminal CK is exported can, by the tenth thin film transistor (TFT) M10, make lead-out terminal OUT_N export high level.Simultaneously, 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7 and the 8th thin film transistor (TFT) M8 conducting, Section Point PD is discharged by the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7 and the 8th thin film transistor (TFT) M8, and the current potential of Section Point PD is dragged down.

Phase III S3, second direct current signal input end CNB, second clock signal end CKB and reset signal input end Reset export high level, first clock signal terminal CK and initialize signal input end STV_D output low level, make the 5th thin film transistor (TFT) M5 conducting, second electric capacity C2 charges, thus the current potential of Section Point PD is drawn high, and then make the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4 conducting, first node PU is discharged by the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4, and the current potential of first node PU is dragged down.Meanwhile, because the current potential of Section Point PD is high, the 9th thin film transistor (TFT) M9 conducting, lead-out terminal OUT_N is discharged by the 9th thin film transistor (TFT) M9, and the current potential of lead-out terminal OUT_N is dragged down.

In the scanning process of above-mentioned gate driver circuit, no matter when forward scan or reverse scan, before next frame is opened, 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4 conducting, first node PU is discharged, effectively prevent the generation of first node PU place noise, simultaneously, second electric capacity C2 makes Section Point PD be in noble potential, make the 9th thin film transistor (TFT) M9 conducting all the time before next frame starts, lead-out terminal OUT_N is discharged by the 9th thin film transistor (TFT) M9, lead-out terminal OUT_N is made to be in electronegative potential, effectively avoid the generation of lead-out terminal OUT_N place noise.In addition, the current potential of Section Point PD can both be drawn high by each high level signal of second clock signal end CKB, thus greatly reduces the power consumption of gate driver circuit.In addition, because gate driver circuit comprises the shift register multiple as above of mutual cascade, do not need to arrange virtual shift register again, thus effectively can reduce wiring space, and reduce further the power consumption of gate driver circuit.

In addition, the embodiment of the present invention additionally provides a kind of display device, and this display device comprises above-described gate driver circuit.This display device can be: any product or parts with Presentation Function such as liquid crystal panel, panel computer, televisor, display, notebook computer, Electronic Paper, mobile phone, digital album (digital photo frame), navigating instrument.

Through the above description of the embodiments, those skilled in the art can be well understood to the mode that the present invention can add required common hardware by software and realize, and can certainly pass through hardware, but in a lot of situation, the former is better embodiment.Based on such understanding, technical scheme of the present invention can embody with the form of software product the part that prior art contributes in essence in other words, this computer software product is stored in the storage medium that can read, as the floppy disk of computing machine, hard disk or CD etc., comprise some instructions and perform method described in each embodiment of the present invention in order to make a computer equipment (can be personal computer, server, or the network equipment etc.).

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.

Claims (10)

1. a shift register, is characterized in that, comprises load module, output module, first node pull-up module, the drop-down module of first node, Section Point pull-up module and the drop-down module of Section Point;
Described load module connection signal input end, for for the first node input signal as pull-up node;
Described first node pull-up model calling first clock signal terminal is high level for maintaining the voltage of described first node;
Described first node drop-down model calling low voltage signal end is low level for maintaining the voltage of described first node;
Output module described in described Section Point pull-up model calling is high level for the voltage maintained for the Section Point as pull-down node;
Low voltage signal end described in the drop-down model calling of described Section Point is low level for maintaining the voltage of described Section Point;
Described output module connects described first clock signal terminal, and the first clock signal is supplied to lead-out terminal.
2. shift register according to claim 1, is characterized in that,
Described load module comprises the first film transistor and the second thin film transistor (TFT);
The grid of described the first film transistor connects initialize signal input end, and the drain electrode of described the first film transistor connects the first direct current signal input end, and the source electrode of described the first film transistor connects described first node;
The grid of described second thin film transistor (TFT) connects reset signal input end, and the drain electrode of described second thin film transistor (TFT) connects the second direct current signal input end, and the source electrode of described second thin film transistor (TFT) connects described first node.
3. shift register according to claim 1, is characterized in that,
Described first node pull-up module comprises the first electric capacity, and one end of described first electric capacity connects described first node, and the other end of described first electric capacity connects described output module.
4. shift register according to claim 1, is characterized in that,
The drop-down module of described first node comprises the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT), the grid of described 3rd thin film transistor (TFT) connects described Section Point, the drain electrode of described 3rd thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 3rd thin film transistor (TFT) connects described first node;
The grid of described 4th thin film transistor (TFT) connects described Section Point, and the drain electrode of described 4th thin film transistor (TFT) connects described Section Point, and the source electrode of described 4th thin film transistor (TFT) connects described low voltage signal end.
5. shift register according to claim 1, is characterized in that,
Described Section Point pull-up module comprises the second electric capacity and the 5th thin film transistor (TFT);
One end of described second electric capacity connects described output module, and the other end of described second electric capacity connects described low voltage signal end;
The grid of described 5th thin film transistor (TFT) is connected second clock signal end with drain electrode, and the source electrode of described 5th thin film transistor (TFT) connects described Section Point.
6. shift register according to claim 1, is characterized in that,
The drop-down module of described Section Point comprises the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT);
The grid of described 6th thin film transistor (TFT) connects described pull-up node, and the drain electrode of described 6th thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 6th thin film transistor (TFT) connects the drop-down module of described first node;
The grid of described 7th thin film transistor (TFT) connects described lead-out terminal, and the drain electrode of described 7th thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 7th thin film transistor (TFT) connects the drop-down module of described first node;
The grid of described 8th thin film transistor (TFT) connects described output module, and the drain electrode of described 8th thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 8th thin film transistor (TFT) connects described Section Point.
7. shift register according to claim 1, is characterized in that,
Described output module comprises the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT);
The grid of described 9th thin film transistor (TFT) connects described Section Point, and the drain electrode of described 9th thin film transistor (TFT) connects described low voltage signal end, and the source electrode of described 9th thin film transistor (TFT) connects described first node pull-up module;
The grid of described tenth thin film transistor (TFT) connects described first node, and the drain electrode of described tenth thin film transistor (TFT) connects described first clock signal terminal, and the source electrode of described tenth thin film transistor (TFT) connects described first node pull-up module.
8. a gate driver circuit, it is characterized in that, comprise multiple shift registers as described in any one of claim 1-7 of mutual cascade, except first order shift register and afterbody shift register, the initialize signal input end of every one-level shift register all connects the lead-out terminal of the upper level shift register of self, the reset signal input end of every one-level shift register cell all connects the lead-out terminal of the next stage shift register of self, the lead-out terminal of every one-level shift register connects self the reset signal input end of upper level shift register and the initialize signal input end of the next stage shift register of self.
9. a display device, is characterized in that, comprises gate driver circuit as claimed in claim 8.
10. a driving method for gate driver circuit, is characterized in that, comprising:
First stage, first direct current signal input end and initialize signal input end export high level, first clock signal terminal, second clock signal end and reset signal input end output low level, the first film transistor turns, first node voltage raises, the first capacitor charging, 6th thin film transistor (TFT) conducting, Section Point current potential is dragged down, the tenth thin film transistor (TFT) conducting, and lead-out terminal current potential is dragged down;
Subordinate phase, described first direct current signal input end and described first clock signal terminal export high level, described initialize signal input end, described second clock signal end and described reset signal input end output low level, described the first film transistor cutoff, the voltage of described first node raises, the tenth thin film transistor (TFT) conducting, and described lead-out terminal exports high level, described 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT) conducting, described Section Point current potential is dragged down;
Phase III, described first direct current signal input end, described second clock signal end and described reset signal input end export high level, described first clock signal terminal and described initialize signal input end output low level, 5th thin film transistor (TFT) conducting, the second capacitor charging, described Section Point current potential is driven high, 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT) conducting, described first node current potential is dragged down, the 9th thin film transistor (TFT) conducting, and described lead-out terminal current potential is dragged down.
CN201410447285.3A 2014-09-04 2014-09-04 Shift register, display device, gate drive circuit and drive method thereof CN104217693A (en)

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